TW527653B - Self-aligned epitaxial base bipolar transistor and its manufacturing method - Google Patents

Abstract

A kind of self-aligned epitaxial base bipolar transistor and its manufacturing method are disclosed in the present invention. At first, after finishing the device isolation process module, the epitaxial base thin film (silicon or silicon germanium) is grown on the wafer and is followed by depositing a thin silicon dioxide (SiO2) layer. The thin silicon dioxide layer is used for the isolation of the emitter and the extrinsic base; and in addition, it is used to function as an etching stop layer in the following etching polysilicon process. After the deposition of silicon dioxide thin film is completed, a poly-crystal pedestal having an outer insulation spacer is formed on the silicon dioxide thin film. The pedestal is used as a hard mask to complete the manufacture of extrinsic base. The pedestal is covered with a thicker insulation film and is followed by using a planarization process to remove the extra insulation film until the poly-crystal pedestal is exposed. The poly-crystal pedestal is removed by using a selective etching method. After that, the inside spacer is manufactured; and the oxide film below the opening containing the inside spacer is removed. Then, the poly-crystal emitter is formed; and the self-aligned epitaxial base bipolar transistor is completed.

Description

527653

V. Description of the invention (1) [Application field of the invention] Manufacturing method of crystal The self-alignment of the transistor The present invention relates to an epitaxial base bipolar thunder method, and more particularly to an accurate method for manufacturing an epitaxial base. [Background of the invention] Discrimination and the transistor ’s f :: car “southern frequency characteristics of the soil compared with traditional ion implantation diffusion, and self-aligned system can reduce parasitic valley and resistance, so it can greatly improve The performance of the transistor. However, once the growth of the base epitaxial film is completed, the process temperature required after i must be as low as possible (less than 90.00, which currently meets the requirements of self-aligned epitaxy). The methods of base bipolar transistor are more complicated or the process control is not easy. The advantage of the self-aligned process is that it can reduce the misalignment caused by the alignment step of the yellow light process. Therefore, the size of the component can be designed to be relatively small, so that the parasitic valley and resistance of the component are reduced, and the performance of the transistor can be greatly improved (Performance). Therefore, the following related researches on the self-alignment process have been conducted: I. IBM's paper in IEEE (Transactions on electron, V0L, 42 NO · 3, PP469-482), which is to make a high platform in a three-layer structure of LTO / silicon nitride / polysilicon (Poly), using the high platform as a hard type Light (Hard Mask) as the extrinsic base (Extrinsic Base) implants and the periphery of the high-high pressure oxidation of polysilicon (HIP0X a High Pressure Oxidation) process to reduce process temperature. Disadvantages in the art

527653 V. Description of the invention (2) Because HIPOX machine is needed, it is more expensive. 2. US Patent No. 4927774 (British

Telecommunication pic), which uses the silicon nitride platform as a hard mask for extrinsic base implantation and oxidizes the crystal silicon (Si Si 1 icon) outside the platform. , Σ Disadvantages: There is no protection of dioxide in the activation zone, which is easy to cause damage (Damage), and the temperature of the thermal oxidation process is too active. Epi-base Blp〇lar TransiH—

CorpoTat ^ ^ 1 ΓΓΓ-46 ^ N ^ / " η31 SemiC〇ndUCt- The emitter window is defined on the layer structure first = evening / second, fossil evening, three drops to form grooves, and then plated with a, s silicon oxide / Silicon nitride etched polycrystalline stone is removed, and then the stone is used again. The planarization process will remove the crystalline silicon outside the groove-the choice of silicon oxide and silicon dioxide etching will be higher Removed. Then use the same port as a hard mask; pole. The character emitter * is turned on, and then a polycrystalline silicon emitter is produced. The disadvantage of the item $ process is that the manufacturing process is complicated. 4. Another paper of IBMCIEEE 93, RrTM cnrx on SiO 2 / SiO 2/2% TM Μ5) is, first, then the upper layer of silicon dioxide and scion silicon, define the emitter window on the two-layer structure The inner gap of the polycrystalline silicon is made, and the silicon nitride is etched away to form a groove. The electrode window is opened in the groove and plated with non = 〇ly-Inside Spacer), and then the amorphous stone outside the shot groove is removeda =) 'Then use the Hiragaki process to remove the recesses __— to form a high platform, and then use the high platform as the platform; Page 6 527653 — 丨 丨 丨 丨 V. Description of the invention (3) Photomask for exoplasmic base ion cloth The direct annealing to form the polycrystalline spar pole is removed again. The disadvantage of this technique is that the emitter is connected to a yellow light alignment process window (Wlndow). [Objective and Overview of the Invention] The problem of this kind of manufacturing technology, the purpose of the present invention is to provide a self-aligned stupid base bipolar electricity that is easy to control by the father. Sun-day body elements and manufacturing method thereof. The present invention provides a kind of self-aligned epitaxial base electrode with 7C pieces, which includes: a single crystal p-type, a cat-like base layer, a ψ,. pa., soil layer. The relationship and function of each adjacent eight μ pair of inner wall, one outer wall, and one emitter 2 are described below. Single crystal? The semiconductor type ί = forms a secondary collector and a worm crystal collector region, and is used as a collector in the I2S to form on the epitaxial collector region. The inner gap wall is formed, and is jealous of red 22 g to define the hole in the epitaxial base layer. Outer gap wall hole. y and ΓB means that the base layer is attached to the inner gap wall and faces away from the above-mentioned hole / 0 κ is formed in the hole and is in contact with the epitaxial base layer. The invention of the invention provides a self-aligned worm crystal base double carrier electric method. In the SM manufacturing method, first, an epitaxial base film (silicon) is grown in the epitaxial collector region of the component insulation process module. Or a thin layer of silicon dioxide (S102) film on silicon it / mine. In addition to the insulation of the emitter and the exoplasmic base, this dioxide also serves as a stop layer for the 2 1_two complex crystal process ( Etching StOP Layer). 7 After the fossil evening film is plated, an outer surface is made on the stone dioxide evening film. Page 7 527653 V. Description of the invention (4), a compound crystal with an insulating spacer (〇utside Spacer) High platform, use this station (Pedestal) as a hard mask (Har (i Mask) to complete the outer base coat, then cover the thick insulation film, and use the flattening process to add additional insulation film It is removed until the polycrystalline plateau is exposed. At this time, the polycrystalline plateau is removed by selective etching, and then an inner spacer (1 = 1 je Spacer) is produced, and then an oxide film under the opening containing the inner spacer is removed. 'And then grow the polycrystalline silicon emitter, so that self-alignment is completed Crystal base bipolar transistor. The characteristics and implementation of the present invention are described in detail below with reference to the preferred embodiment. [Detailed description of the invention] The present invention uses a sacrificial pedestal (Sacrificial Pedestal) And a pair of inner gap walls and an outer gap wall to achieve self-alignment during the production of epitaxial base double carrier electronic components, and by first completing the Pedestal and the outer gap wall, and using this high platform and The outer gap wall is implanted with the exoplasmic base, and then the planarization process and selective etching method are used to remove the sacrificial high platform, and the inner gap wall process is completed, so that the alignment steps and The size of the opening of the emitter window is reduced. Therefore, in structure, the self-aligned epitaxial base bipolar transistor element of the present invention includes several parts: a single crystal semiconductor substrate including an N + subpole set Sub-collector Regi〇n and Epi-collector; epitaxial base layer formed on the epitaxial collector region; a pair of inner partition walls formed on the epitaxial base Definition The holes in the base layer; between a pair of outer walls, is formed on the epitaxial base layer and paste

Page 8 V. Description of the invention (5) and an emitter layer formed in the hole and in contact with the epitaxial layer based on the inner partition wall and facing away from the hole pole layer. The crystal material is selected from the #crystalline material germanium worm. The material of the outer partition wall is: electricity :: a self-intermediate material or a semiconductor material, which contains an exoplasmic base material. And the premature semiconductor substrate also includes the gallium glaciers on the semiconductor substrate, which are formed on the semiconductor substrate and formed through the self-alignment process of the outer space wall and the outer space. In addition, the stupid base bipolar thunder thunder carrier thunder is P 骋 M P, and the solar heliosphere is an N-P-N type epitaxial base gemstone. If it is N-two stone, the selected substrate can be a? -Type substrate;

ΓΓ plate crystal base bipolar transistor, the selected substrate can be N ^ Λ, in 2 passes, it is designed according to the transistor element structure described above, master: as follows: first step, step, provide a single The first step is to form an epitaxial base layer on a single crystal semiconductor substrate. The first step is to form the epitaxial base layer on the single crystal semiconductor substrate. In three steps, a thin oxide layer is deposited on the epitaxial base layer and the single crystal semiconductor substrate. In the fourth step, an external spacer is formed on the thin oxide layer, and the external spacer is used to define the exogenous base region. In the fifth step, a pair of inner gap walls are formed on the thin oxide layer. The pair of inner gap walls are attached to the outer gap walls and formed in a hole. This hole is the position of the emitter window. In a sixth step, an emitter layer is formed in the hole to be in contact with the epitaxial base layer. ^ For detailed manufacturing process, please refer to the following description: First, please refer to "Figure 1", which is the first step mentioned above, 527653

(Contains the buried layer insulation of the N-layer transistor and forms the second step of growing the epitaxial base on the local isolation technology. This is a single epitaxial base on the silicon crystal and then the area is engraved with the yellow light name In addition to the subsequent etching of polycrystalline silicon, it includes the following pre-steps: 10a, N + layer 10b, and P-layer 10c on silicon wafer 10). Traditional dual-load (ie, secondary collector), collector, collector connection, and inter-component silicon oxide layer (LOCOS) 12a, 12b (or using trench isolation). Then, on the Shixi wafer I electrode film 14 (usually silicon germanium or silicon), that is, the above-mentioned stupid base film 14 has a polycrystalline structure and a crystal structure on the insulating layer. After the growth of the stupid base film 14 is completed, the manufacturing process removes the desired extraneous and intrinsic base film 14. Then, the third step is performed, that is, after the external pattern is completed, a thin oxide layer 16 is plated to provide insulation between the emitter and the exoplasmic base region, and there is still a function as an Etching Stop Layer. The thickness of the oxide layer 16 is about 300 to 500 Angstroms. For the fourth to sixth steps, please refer to "Figures 2 to 6". For the fourth step, please refer to "Figure 2", which is to achieve self-alignment by making a high platform. After the oxide layer 16 is plated, a sacrificial layer is then deposited on the wafer, and a pedestal 18 is defined. The material recommendation is polycrystalline silicon, and then an outer layer is made on the outside of the pedestal " The partition walls 2 0 a, 2 0 b. The material of the outer partition walls 20 a and 20 b may be silicon nitride or silicon dioxide. Then, using this composite structure (height i 8 + outer spacers 20a, 20b) as a hard mask, an exoplasmic base ion implantation process is performed to form exoplasmic base regions 22a, 22b. This composite structure just separates the intrinsic base (epitaxial base film 14) from the exoplasmic base.

Page 10 527653 V. Description of the invention (7) The extreme base (exoplasmic base regions 22a, 22b) region. Among them, the thickness of the high platform is about 4,000 to 6000 angstroms (in); the outer = degree M is about 50,000 to 1 500 angstroms; the width of the high platform W1 is the emitter window = the fifth step is Contains "Figures 3 and 4". Please refer to "Figure 3", which is the pre-step of the fifth step. After the exogenous base entry process is completed, a thick insulating layer is then plated on the silicon wafer, and then a planarization process is performed to remove the additional insulating layer until the plateau 18 ^, and a thick insulating layer 24a is formed. , 2 4b and the plane of the platform 18. Flat = process can use chemical mechanical polishing (CMP) or coated glass (SOG = chemical method (Etching Back). Among them, the material of the insulating layer 24a, 24b can be two = silicon dioxide, borophosphosilicate glass (BPSG ) Or silicon nitride. Then, as shown in "Figure 4", after the planarization process is completed, the thick insulating layers 24a, 24b plus the outer spacers 20a, 20b are hard light, and the sacrificial layer will also be That is, the plateau 18 is selectively removed and stopped at the oxide layer ^. The process of removing the plateau 18 can be processed using a conventional semiconductor process. Next, the inner spacers 26a and 26b are made to form a hole 28. This hole will It is used for emitter window. Among them, the material of the inner spacers 26a, 26b can be dielectric materials such as silicon dioxide, silicon nitride or polycrystalline silicon, and semiconductor materials. So far, the above-mentioned platform 18 is combined with the inner spacers. 26 &, 2⑽external gap wall 208, 2 (^ is the definition of the essential base (] [] ^ 1 ^ 1 ^; ^ 1 ^%) /, an external base and the base The structure of the electrode-emitter junction is the key structure of the self-alignment process. The final sixth step is as shown in Figures 5 and 6. ". Please refer to" page 11 527653

Figure 5 ": After the inner spacers 26a and 26b are completed, the insulation layers 24 & and 24b plus the outer spacers 20a and 20b and the inner spacers 26a and 26b are hard masks to oxidize the exposed thin Layer 16 is removed by etching and a thin oxide layer is left. And 16b, this completes the structure of the emitter window 28a. The oxide layer can be etched by wet etching, so that the epitaxial base film is not damaged. However, the use of the wet-cut method will produce an undercut (jer cut) effect. Therefore, the oxide layers 16a and 16b of Fig. 5 will be concave. At the same time, if the insulation sounds 24a, 2 4b The material is the same as that of the oxide layer 16, and it will be slightly concaved by etching, as shown in "Figure 5". Finally, please refer to "Figure 6", and wait to remove the exposed thin oxide layer 6 After that, the polycrystalline silicon can be plated on the emitter window 28a, and the process module of the polycrystalline silicon 30 can be completed. Then, the contact window and the metallization module are performed, so that the self-aligned epitaxial substrate is completed. Manufacturing process of polar bipolar transistor 0 The inner spacer of the present invention can make the opening of the emitter window smaller than the yellow light limit. [Effect of the invention] IBM in BCTM1 993 Compared with published papers, the previous case is to complete the inside-spacer first, and this case is to complete the outside-spacer first, and the process of the present invention is simpler than the previous case. With US Patent No. 4297774 (British Telecommunications p 1 c.) In comparison, the case Higher process temperature, does not apply to very ambipolar crystal epitaxial substrate, and which is made of high-silicon nitride, while the process of the present invention is a low temperature, and the high material is polycrystalline silicon (Polysi 1 icon).

527653 V. Description of Invention (9) and US Patent No. 6020246 (National Semiconductor

Corporation), the manufacturing process of the present invention is relatively simple, and the case does not have an in-spacer, and the present invention includes an inside-spacer, which can make an emitter tunnel smaller than the limit of the yellow light process. Can make better transistor. Although the present invention is disclosed in the foregoing preferred embodiment as above, autumn is used to limit the present invention. Any person skilled in the relevant arts can make some changes to the scope of the patent protection of this month within the spirit and scope of not equal to ^. It shall be subject to the benefit of this specification, and the inventor shall prevail. Defined by

527653 Figures 1 to 6 show the self-aligned epitaxial machine and bipolar transistor crystals of the present invention, and briefly explain the manufacturing method of the element. [Symbol description] 10 Broken wafer 10a N layer 10b N + layer 10c P -Layer 12a Local silicon oxide layer 12b Local silicon oxide layer 14 Stupid base film 16 Oxide layer 16a Oxide layer 16b Oxide layer 18 Platform 20a Outer spacer 20b Outer spacer 22a Outer base layer 22b Outer base layer 24a Insulation layer 24b Insulation layer 26a Inner spacer 26b Inner spacer 28 Hole 28a Emitter window

Page 14 527653 Brief description of drawings 30 Emitter polycrystalline silicon CMP Chemical-Mechanical Polishing

Polishing) LOCOS local oxidation of Si

Page 15

Claims (1)

527653 A self-aligned epitaxial base bipolar transistor element includes: 1. Said: a crystal field semiconductor substrate on which a sub-collector and a Leiji wooden pole region are first formed for use as A collector, an epitaxial base layer is formed on the epitaxial collector region; a pair of internal spacers are formed on the epitaxial base layer to define a hole in the staggered base layer; ~ An outer gap wall is formed on the epitaxial base layer and the inner gap wall faces away from the hole; and the pair of emitter layers is formed on the hole to be in contact with the epitaxial base layer. • The self-aligned epitaxial base double-battery electric device as described in item 丨 of the patent scope, wherein the epitaxial base double-battery transistor system is an Nϋ-type stupid base double-battery Daughter transistor. 3. The self-aligned epitaxial base bipolar transistor element described in item 1 of the patent scope, wherein the epitaxial base bipolar transistor system is a P-type stupid base bipolar transistor. Transistor. 4. The self-aligned epitaxial base bipolar transistor element according to item 丨 of the scope of the patent application, wherein the material of the epitaxial base layer is selected from silicon epitaxial materials and silicon germanium epitaxial materials. 5 · The self-aligned epitaxial base bipolar transistor device described in item 1 of the scope of patent application, wherein the material forming the pair of inner spacers is selected from a dielectric material and a semiconductor material, and forms the outer gap The material of the wall is eight electric materials. Μ ^ The self-aligned epitaxial base bipolar transistor device as described in item 1 of Shenyan's patent scope, wherein the width of the external spacer is about 50 0 to i 5 0 0 Angstroms. Page 16 527653 • The self-aligned worm crystal base double carrier described in the electric item further includes an exoplasmic base region, which was formed in that year. The two exoplasmic base regions pass through the pair of inner and outer gap walls. Self-aligned and formed separately. 8 · If the scope of patent application is the first! Or the self-aligned stupid base dual carrier device as described in item 7, further comprising a thin oxide layer formed on the worm-crystal base layer for connecting the emitter layer and the extraneous base region insulation. 9. A method for manufacturing a self-aligned epitaxial base bipolar transistor element, comprising the following steps: k for a single positive semiconductor substrate to form a secondary collector and a stupid collector region thereon as a Collecting poles; forming an epitaxial base layer on the single crystal semiconductor substrate; forming an external gap wall on the stupid base layer, the outer bulk wall defining a hole in the stupid base layer;幵 > forming a pair of inner gap walls on both sides of the hole on the worm crystal base layer to further define a second hole, and the pair of gap walls are attached to the outer gap wall; and An emitter layer is formed in the second hole to be in contact with the epitaxial base layer. 10 · The method for manufacturing a self-aligned epitaxial base bipolar transistor device as described in item 9 of the scope of the patent application, further comprising depositing on the epitaxial base layer before forming the external gap wall A thin oxide layer. 11. Manufacture self-aligned epitaxial base as described in the scope of patent application No. 丨 0 Page 17 527653 6. Method of applying for a patent A method for a bipolar transistor device, in which the thickness of the thin oxide layer is about 300 to 500 angstroms. 1 2 As claimed, the method for manufacturing a self-aligned epitaxial base bipolar transistor device described in item 9 of the patent scope, wherein the step of forming the external spacer comprises the following steps: depositing a sacrificial layer; Define an elevated area; form the external gap wall beside the elevated area; deposit an insulating layer on the single crystal semiconductor substrate; planarize the insulating layer to expose the elevated area; and remove the two elevated areas to form the Holes. 1 3 · The method for manufacturing a self-aligned epitaxial base bipolar transistor device as described in item 2 of the patent application scope, wherein after the step of forming the external bulkhead, the method further includes using the platform and the external The partition wall is a hard mask for implanting exoplasmic base ions on the single crystal semiconductor substrate to form an exoplasmic base layer. 1 4 · The method for manufacturing a self-aligned epitaxial base bipolar transistor device as described in item 12 of the scope of patent application, wherein the sacrificial layer is a complex crystal 0 1 5 · As described in the scope of patent application 丨 2 The method for manufacturing a self-aligned epitaxial base bipolar transistor device according to the above item, wherein the thickness of the sacrificial layer is between 4,000 and 600,000 Angstroms (A). 1 6 · The method for manufacturing a self-aligned epitaxial base bipolar transistor device as described in item 2 of the patent application scope, wherein the material of the insulating layer is deposited Page 18 527653 Sixth, the scope of patent application is selected from silicon dioxide, monolithic glass (BPSG) and nitride; 17. The method for manufacturing a self-aligned stupid base bipolar transistor device as described in item 12 of the scope of patent application, wherein the method for planarizing the insulating layer may be selected from the chemical mechanical polishing (CMP) and Coated glass (SOG) Etching Back 1 8 · The method for manufacturing a self-aligned stupid base bipolar transistor device as described in item 9 or 丨 〇 of the patent application scope, wherein After the step of forming the pair of inner gap walls, the method further includes a step of etching the thin oxide layer by a wet etching method. 19 · The method for manufacturing a self-aligned epitaxial base bipolar transistor device as described in item 9 of the scope of patent application, wherein the epitaxial base bipolar transistor system is a PNP type epitaxial base Bipolar transistor. 20. 21 · 22 · 23. The method for manufacturing a self-aligned epitaxial base bipolar transistor device as described in item 9 of the scope of patent application, wherein the epitaxial base bipolar thunder system is an NPN Type epitaxial base bipolar transistor. The method for manufacturing a self-aligned epitaxial base bipolar transistor device as described in item 9 of the scope of patent application, wherein the material of the epitaxial base layer is a self-aligned epitaxial material and a germanium stupid crystal. material. The method for manufacturing a self-aligned epitaxial base dual product transistor device as described in item 9 of the Ming patent scope further includes a foreign substrate = j% formed on the semiconductor substrate. The transmission = Shen 2 gap wall is formed by self-alignment with the outer gap wall. Carrier% patent | & The method for manufacturing a self-aligned epitaxial base bipolar transistor device as described in item 9, wherein the width W2 of the external spacer Page 527 653 Page 20