WO2022179027A1 - 存储器件及其制备方法 - Google Patents

存储器件及其制备方法 Download PDF

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Publication number
WO2022179027A1
WO2022179027A1 PCT/CN2021/103683 CN2021103683W WO2022179027A1 WO 2022179027 A1 WO2022179027 A1 WO 2022179027A1 CN 2021103683 W CN2021103683 W CN 2021103683W WO 2022179027 A1 WO2022179027 A1 WO 2022179027A1
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Prior art keywords
word line
top surface
active
conductive layer
inter
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PCT/CN2021/103683
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English (en)
French (fr)
Inventor
陈涛
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长鑫存储技术有限公司
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Priority to US17/411,094 priority Critical patent/US11854880B2/en
Publication of WO2022179027A1 publication Critical patent/WO2022179027A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

Definitions

  • the present application relates to the field of semiconductor technology, and in particular, to a memory device and a preparation method thereof.
  • the steps of forming the word line structure include: first, after forming the active region (AA region) and the shallow trench isolation structure (STI) on the substrate, etching the word line trench (WL) trench).
  • the second step after depositing a metal tungsten film on the substrate to fill the word line trenches by a CVD process, an etching process is performed to remove the excess metal tungsten film to obtain a word line structure composed of the remaining metal tungsten film.
  • the word line structure obtained by this method has the problem of poor electrical conductivity, which further affects the performance of the memory device.
  • a preparation method of a memory device comprising:
  • a substrate is provided, an insulating structure and a plurality of first active structures are formed on the substrate, and a plurality of first active structures are arranged at intervals in the insulating structure;
  • the conductive layer of the word line is patterned and etched to obtain a plurality of word line structures arranged in parallel and spaced apart and filling grooves between adjacent word line structures.
  • the filling groove includes exposing the top surface of the first active structure part and the insulating structure part at the same time a first filling groove on the top surface;
  • Isolation structures extending along the top surfaces of the exposed insulating structures toward the top surfaces of the word line structures are formed in the first filled trenches.
  • a storage device is manufactured by any one of the above-mentioned preparation methods.
  • a word line conductive layer is formed on a substrate by a physical vapor deposition process, wherein the top surface of the word line conductive layer is higher than the top surface of the first active structure formed on the substrate, and secondly , pattern-etching the conductive layer of the word line to obtain a plurality of word line structures arranged in parallel and spaced apart and a filling groove between adjacent word line structures, the filling groove includes simultaneously exposing the top surface of the first active structure part and the a first filled trench on the top surface of the insulating structure portion; again, a second active structure extending along the exposed top surface of the first active structure toward the top surface of the word line structure is formed in the first filled trench, and in the first filled trench An isolation structure extending along the top surface of the exposed insulating structure toward the top surface of the word line structure is formed in the trench.
  • the word line structure in the memory device of the present application is formed by physical vapor deposition.
  • the word line conductive layer is formed by etching and removing the redundant word line conductive layer after the process.
  • the word line structure does not contain halogen elements and voids, so as to achieve the purpose of improving the conductive performance of the word line structure and the performance of the memory device.
  • FIG. 1 is a schematic flowchart of a method for manufacturing a memory device in an embodiment
  • FIG. 2 is a schematic flowchart of step S102 in an embodiment
  • step S204 is a schematic top view of the memory device after step S204 in one embodiment
  • Figure 4a is a schematic cross-sectional view of the memory device shown in Figure 3 along the AA' direction;
  • Figure 4b is a schematic cross-sectional view of the memory device shown in Figure 3 along the BB' direction;
  • 5a is a schematic cross-sectional view of the memory device along the AA' direction after forming the first active structure in one embodiment
  • Figure 5b is a schematic cross-sectional view of the memory device corresponding to Figure 5a along the BB' direction;
  • FIG. 6 is a schematic flow chart of forming a word line conductive layer on a substrate in an embodiment
  • 7a is a schematic cross-sectional view of the memory device along the AA' direction after the word line conductive layer is formed in one embodiment
  • Figure 7b is a schematic cross-sectional view of the memory device corresponding to Figure 7a along the BB' direction;
  • FIG. 8a is a schematic cross-sectional view of the memory device along the AA' direction after the word line structure is formed in one embodiment
  • Fig. 8b is a schematic cross-sectional view of the memory device corresponding to Fig. 8a along the BB' direction;
  • 9a is a schematic cross-sectional view of the memory device along the AA' direction after the isolation structure is formed in one embodiment
  • Fig. 9b is a schematic cross-sectional view of the memory device corresponding to Fig. 9a along the BB' direction;
  • first doping type becomes the second doping type
  • second doping type can be the first doping type
  • the first doping type and the second doping type are different doping types, for example,
  • the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.
  • Spatial relational terms such as “under”, “below”, “below”, “under”, “above”, “above”, etc., in This may be used to describe the relationship of one element or feature to other elements or features shown in the figures. It should be understood that in addition to the orientation shown in the figures, the spatially relative terms encompass different orientations of the device in use and operation. For example, if the device in the figures is turned over, elements or features described as “below” or “beneath” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary terms “below” and “under” can encompass both an orientation of above and below. In addition, the device may also be otherwise oriented (eg, rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
  • Embodiments of the application are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the application, such that variations in the shapes shown may be contemplated due, for example, to manufacturing techniques and/or tolerances. Accordingly, embodiments of the present application should not be limited to the specific shapes of the regions shown herein, but include shape deviations due, for example, to manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface over which the implantation proceeds. Thus, the regions shown in the figures are schematic in nature and their shapes do not represent the actual shape of a region of a device and do not limit the scope of the invention.
  • word line trenches are etched, and a tungsten metal film is formed by a chemical vapor deposition process, and then a rapid thermal annealing process (RTA) is performed to pattern etching.
  • RTA rapid thermal annealing process
  • a word line structure composed of the remaining tungsten metal film in the word line trench is obtained.
  • the halogen element existing in the word line structure will affect the conductivity of the word line structure, thereby affecting the performance of the memory device.
  • FIG. 1 it is a schematic flowchart of a method for fabricating a memory device in an embodiment.
  • the present application provides a preparation method of a memory device, as shown in FIG. 1 , the preparation method includes:
  • a substrate is provided, an insulating structure and a plurality of first active structures are formed on the substrate, and the plurality of first active structures are arranged at intervals in the insulating structure.
  • a substrate is provided, an insulating structure and a plurality of first active structures are formed on the substrate, and a plurality of first active structures are arranged at intervals in the insulating structure.
  • the first active structure is a silicon active structure
  • the insulating structure is a silicon dioxide structure.
  • the substrate can be undoped single crystal silicon, impurity-doped single crystal silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI), silicon-on-insulator Silicon germanium (SiGeOI) and germanium on insulator (GeOI), etc.
  • SOI silicon-on-insulator
  • SSOI silicon-on-insulator
  • SiGeOI silicon-germanium-on-insulator
  • SiGeOI silicon-on-insulator Silicon germanium
  • GeOI germanium on insulator
  • a physical vapor deposition process is performed to form a word line conductive layer on the substrate, and the top surface of the word line conductive layer is higher than the top surface of the first active structure.
  • a physical vapor deposition process is performed to form a word line conductive layer on the substrate, the word line conductive layer covers the first active structure and the insulating structure, and the top surface of the word line conductive layer is higher than the first active structure and the insulating structure the top surface of the structure.
  • the influence of halogen elements in the process gas on the conductive properties of the word line conductive layer during the formation of the word line conductive layer can be avoided.
  • the conductive layer of the word line is patterned and etched to obtain a plurality of word line structures arranged in parallel and spaced apart and filling grooves between adjacent word line structures.
  • the filling groove includes exposing the top surface of the first active structure part and the insulating structure part at the same time The first fill groove on the top surface. That is, after a mask pattern is formed on the word line conductive layer by a photolithography process, the word line conductive layer (excessive word line conductive layer) that is not covered by the mask pattern is etched and removed by an etching process, so as to be covered by the mask pattern.
  • the word line conductive layer (remaining word line conductive layer) consists of several word line structures arranged in parallel and spaced apart, and filling grooves located between adjacent word line structures, the filling grooves include Between the word line structure and the word line structure on the insulating structure while exposing part of the top surface of the first active structure, part of the top surface of the insulating structure, and the first filling at the junction of the first active structure and the insulating structure groove.
  • a second active structure extending along the exposed top surface of the first active structure to the top surface of the word line structure is formed in the first filled trench, that is, a second active structure with a bottom and exposed first filled trench is formed in the first filled trench
  • a second active structure, the top surface of which is coincident with the active structure, is in contact with the first active structure, and serves as an active region of the memory device.
  • An isolation structure extending from the top surface of the exposed insulating structure to the top surface of the word line structure is formed in the first filled trench, that is, the bottom and the first filled trench are formed in the part of the first filled trench where the second active structure is not formed.
  • the isolation structure in which the top surface of the exposed insulating structure overlaps, and the bottom surface of the isolation structure is in contact with the top surface of the insulating structure at this time.
  • a word line conductive layer is formed on a substrate by a physical vapor deposition process, wherein the top surface of the word line conductive layer is higher than the top surface of the first active structure formed on the substrate, and secondly , pattern-etching the conductive layer of the word line to obtain a plurality of word line structures arranged in parallel and spaced apart and a filling groove between adjacent word line structures, the filling groove includes simultaneously exposing the top surface of the first active structure part and the a first filled trench on the top surface of the insulating structure portion; again, a second active structure extending along the exposed top surface of the first active structure toward the top surface of the word line structure is formed in the first filled trench, and in the first filled trench An isolation structure extending along the top surface of the exposed insulating structure toward the top surface of the word line structure is formed in the trench.
  • the word line structure in the memory device of the present application is formed by physical vapor deposition.
  • the word line conductive layer is formed by etching and removing the redundant word line conductive layer after the process.
  • the word line structure does not contain halogen elements and voids, so as to achieve the purpose of improving the conductive performance of the word line structure and the performance of the memory device.
  • the bottom surface of the word line conductive layer is flush with the top surface of the first active structure. In other embodiments, the bottom surface of the word line conductive layer is higher than the top surface of the first active structure.
  • FIG. 2 it is a schematic flowchart of step S102 in an embodiment.
  • FIG. 3 it is a schematic top view of the memory device after step S204 in one embodiment.
  • FIG. 4a it is a schematic cross-sectional view of the memory device shown in FIG. 3 along the AA' direction.
  • FIG. 4b it is a schematic cross-sectional view of the memory device shown in FIG. 3 along the BB' direction.
  • FIG. 5a it is a schematic cross-sectional view of the memory device along the AA' direction after the first active structure is formed in an embodiment.
  • FIG. 5b it is a schematic cross-sectional view of the memory device corresponding to FIG. 5a along the BB' direction.
  • step S102 includes:
  • the insulating layer is patterned and etched to obtain an insulating structure and a plurality of active trenches arranged at intervals in the insulating structure.
  • the redundant insulating layer on the substrate 102 is removed by patterning and etching to obtain the insulating structure 202 and a plurality of active trenches 204 arranged at intervals in the insulating structure.
  • a mask pattern covering the insulating layer to be retained is formed on the substrate 102, that is, the mask pattern exposes the position where the first active structure is subsequently formed the insulating layer. Then, the insulating layer not covered by the mask pattern is removed by etching to obtain an insulating structure 202 composed of the remaining insulating layer, and a plurality of active trenches 204 arranged at intervals in the insulating structure 202 .
  • an insulating layer of a certain thickness is provided between the bottom of the active trench 204 and the upper surface of the substrate 102 .
  • the active trench 204 is filled to form a first active structure 206 with a top surface higher than the top surface of the insulating structure 202 .
  • a first active structure 206 having a top surface higher than the insulating structure 202 is formed by filling in the active trench 204 .
  • the top surfaces of the first active structure 206 and the insulating structure 202 are flush, or the top surface of the first active structure 206 is lower than the top surface of the insulating structure 202.
  • the active trench 204 exposes the upper surface of the substrate 102, fills the active trench 204, and forms a top surface higher than the insulating structure 202
  • the steps of the first active structure 206 include:
  • An epitaxial process is performed to form a first active structure 206 in the active trench 204, the first active structure 206 is a silicon epitaxial structure, and the first active structure 206 formed by the epitaxial process is a monocrystalline silicon structure, to avoid The problem of lattice mismatch between the first active structure 206 and the substrate 102 is solved.
  • the first active structure may be formed by other methods of forming silicon active structures known to those skilled in the art.
  • FIG. 6 it is a schematic flowchart of forming a word line conductive layer on a substrate in an embodiment.
  • FIG. 7a it is a schematic cross-sectional view of the memory device along the AA' direction after the word line conductive layer is formed in an embodiment.
  • FIG. 7b it is a schematic cross-sectional view of the memory device corresponding to FIG. 7a along the BB' direction.
  • the step of forming the word line conductive layer on the substrate 102 includes:
  • a first inter-gate insulating layer 402 is formed on the substrate 102 , and the first inter-gate insulating layer 402 covers the top surface of the first active structure 206 and the top surface of the insulating structure 202 .
  • a first inter-gate insulating layer 402 is formed on the upper surface of the first active structure 206 , and the first inter-gate insulating layer 402 extends and covers the top surface of the first active structure 206 . on the top surface of insulating structure 202 .
  • the first inter-gate insulating layer 402 includes at least one of a silicon dioxide film and a high-k gate dielectric film, and the first inter-gate insulating layer 402 can be formed by an atomic layer deposition process or other processes.
  • a first conductive layer 404 such as a Ti/TiN metal layer, is formed on the top surface of the first inter-gate insulating layer 402 .
  • a second conductive layer 304 is formed on the top surface of the first conductive layer 404 , and the first inter-gate insulation 402 , the first conductive layer 404 , and the second conductive layer 304 constitute a word line conductive layer.
  • the second conductive layer 304 includes a tungsten conductive layer.
  • a silicon oxide layer is selected for the first inter-gate insulating layer 402
  • a titanium nitride metal layer is selected for the first conductive layer 404
  • a tungsten conductive layer is selected for the second conductive layer 304
  • the second conductive layer 304 is formed on the first conductive layer 404 .
  • the steps are: forming a tungsten conductive layer on the upper surface of the titanium nitride metal layer, and at this time, the titanium nitride metal layer simultaneously serves as an adhesion layer.
  • the lower surface of the second conductive layer 304 is lower than the upper surface of the first active structure 206 .
  • step S306 includes: a first step, forming a second conductive layer material on the first conductive layer 404 .
  • the material of the second conductive layer is planarized to obtain the second conductive layer 304.
  • the material of the second conductive layer is planarized by a chemical grinding process to obtain the first conductive layer composed of the remaining material of the second conductive layer.
  • Two conductive layers 304 are two conductive layers 304 .
  • FIG. 8a it is a schematic cross-sectional view of the memory device along the AA' direction after the word line structure is formed in an embodiment.
  • FIG. 8b it is a schematic cross-sectional view of the memory device corresponding to FIG. 8a along the BB' direction.
  • the step of patterning and etching the word line conductive layer to obtain several word line structures arranged in parallel and spaced apart includes:
  • the second conductive layer 304 , the first conductive layer 404 and the first inter-gate insulating layer 402 are patterned and etched to obtain the characters including the second conductive structure 502 , the first conductive structure 604 and the first inter-gate insulating structure 602 stacked in sequence line structure.
  • a word line mask pattern is formed on the substrate 102, the word line mask pattern covers the second conductive layer 304 to be retained, the second conductive layer 304 to be removed is exposed, and the word line mask is removed by etching
  • the second conductive layer 304 exposed by the pattern, the first conductive layer 404 and the first inter-gate insulating layer 402 located under the second conductive layer 304 are obtained to obtain a second conductive structure 502 (the remaining second conductive layer 304 ),
  • the second conductive structure 502 includes a tungsten conductive structure
  • the first conductive structure 604 includes a titanium nitride structure
  • the first inter-gate insulating structure 602 includes a silicon oxide structure.
  • the step further includes:
  • a third conductive structure 608 and a second inter-gate insulating structure 606 are sequentially formed on the sidewalls of the word line structure; wherein, the extension direction of the third conductive structure 608 and the second inter-gate insulating structure 606 is the same as the extension direction of the word line structure , the heights of the third conductive structure 608 and the second inter-gate insulating structure 606 are both equal to the distance between the bottom surface of the word line structure and the top surface of the word line structure, and the gate word line of the memory device includes the word line structure, the third Conductive structure 608 and second inter-gate insulating structure 606 .
  • the third conductive structure 608 and the second inter-gate insulating structure 606 are sequentially stacked from the word line structure to the filled trench, that is, the distance between the second inter-gate insulating structure 606 and the word line structure is greater than the distance between the third conductive structure 608 and the word line structure distance between.
  • the step of sequentially forming the third conductive structure 608 and the second inter-gate insulating structure 606 on the sidewall of the wordline structure includes: a first step, filling the sidewalls of the wordline structure (that is, filling the trenches on both sides of the wordline structure 502 ) sidewall) to form a third conductive structure 608, wherein the extension direction of the third conductive structure 608 is the same as the extension direction of the word line structure, and the height of the third conductive structure 608 (the third conductive structure 608 is close to the bottom surface of the substrate 102 and The distance between the top surfaces away from the substrate 102 (ie, the distance between the bottom wall of the filled trench and the opening of the filled trench) is equal to the distance between the bottom surface of the word line structure and the top surface of the word line structure.
  • a second inter-gate insulating structure 606 is formed on the side surface of the third conductive structure 608, wherein the extension direction of the second inter-gate insulating structure 606 is the same as that of the word line structure, and the extension direction of the second inter-gate insulating structure 606 is the same as that of the word line structure.
  • the height (the distance between the bottom surface of the second inter-gate insulating structure 606 close to the substrate 102 and the top surface away from the substrate 102, that is, the distance between the bottom wall of the filled trench and the opening of the filled trench) is equal to the bottom of the word line structure The distance between the surface and the top surface of the word line structure.
  • the first inter-gate insulating structure 602 and the second inter-gate insulating structure 606 are made of the same material, for example, both are silicon dioxide gate dielectric layers or high-k gate dielectric layers.
  • the first conductive structure 608 and the third conductive structure 608 are made of the same material, for example, both are titanium nitride metal structures.
  • the third conductive structure 608 includes a titanium nitride structure
  • the second inter-gate insulating structure 606 includes a silicon oxide structure
  • the word line structure includes a buried word line structure
  • the second active structure the isolation structure
  • the top surfaces are all higher than the top surfaces of the word line structures.
  • the first inter-gate insulating structure 602 and the second inter-gate insulating structure 606 together constitute a gate dielectric structure of the memory device.
  • FIG. 9a it is a schematic cross-sectional view of the memory device along the AA' direction after the isolation structure is formed in one embodiment.
  • FIG. 9b it is a schematic cross-sectional view of the memory device corresponding to FIG. 9a along the BB' direction.
  • the filling trench further includes a second filling trench 504 exposing a part of the top surface of the first active structure 206;
  • the second active structure 610 extending along the exposed top surface 508 of the first active structure 206 toward the top surface of the word line structure is formed in the first filled trench 506 and further comprising:
  • the first active structure 206 , the second active structure 610 and the third active structure 612 together constitute an active region of the memory device.
  • the top surfaces of the second active structure 610 and the third active structure 612 are flush.
  • the top surfaces of the second active structure 610, the third active structure 612 and the word line structure are flush.
  • the first active structure 206 , the second active structure 610 and the third active structure 612 are integrated as a silicon active structure, and a memory device is subsequently formed in the second active structure 610
  • the source structure of the transistor is formed, and the drain structure of the transistor in the memory device is formed in the third active structure 612.
  • the memory device includes transistors with a double word line structure and a common drain structure.
  • the third active structure 612 and the second active structure 610 are formed in the same process.
  • the step of forming the third active structure 612 extending along the exposed top surface 512 of the first active structure 206 toward the top surface of the word line structure in the second filled trench 504 includes:
  • An epitaxial process is performed to form a third active structure 612 extending along the exposed top surface of the first active structure 206 toward the top surface of the word line structure in the second filled trench 504 .
  • the second active structures 610 on both sides of the word line structure are used to form source structures and drain structures of transistors in the memory device, respectively.
  • the step of forming a second active structure 610 extending along the exposed top surface of the first active structure 206 toward the top surface of the word line structure in the first filled trench 506 includes:
  • An epitaxial process is performed to form a second active structure 610 extending along the exposed top surface of the first active structure 206 toward the top surface of the word line structure in the first filled trench 506 .
  • the first active structure 206 and the second active structure 610 together constitute an active region of the memory device.
  • the first filling trench 506 is formed along the exposed top surface 510 of the insulating structure 202 toward the top surface 510 .
  • the isolation structure 614 extending from the top surface of the word line structure and the insulating structure 202 together form a shallow trench isolation structure between the active regions.
  • the present application also provides a memory device, which is manufactured by the preparation method described in any one of the above.
  • the present application also provides a storage device, the storage device includes the above storage device.
  • steps in the flowcharts of FIG. 1 , FIG. 2 , and FIG. 6 are displayed in sequence according to the arrows, these steps are not necessarily executed in the sequence indicated by the arrows. Unless explicitly stated herein, the execution of these steps is not strictly limited to the order, and these steps may be performed in other orders. Moreover, at least a part of the steps in FIG. 1 , FIG. 2 , and FIG. 6 may include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but may be executed at different times. Alternatively, the order of execution of the stages is not necessarily sequential, but may be performed alternately or alternately with other steps or at least a portion of the steps or stages in the other steps.

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Abstract

本申请涉及一种存储器件及其制备方法，包括：提供衬底，衬底上形成有绝缘结构及若干个第一有源结构，若干个第一有源结构于绝缘结构内间隔排布；进行物理气相淀积工艺，在衬底上形成字线导电层；图形化刻蚀字线导电层，得到若干条平行间隔排布的字线结构以及位于相邻字线结构之间的填充槽，填充槽包括同时露出第一有源结构部分顶表面和绝缘结构部分顶表面的第一填充槽；在第一填充槽中分别形成沿露出的第一有源结构的顶表面向字线结构的顶表面延伸的第二有源结构、沿露出的绝缘结构的顶表面向字线结构的顶表面延伸的隔离结构。达到提高字线结构导电性能及存储器件的性能的目的。

Description

存储器件及其制备方法
本申请要求于2021年2月25日提交中国专利局，申请号为2021102098964，申请名称为“存储器件及其制备方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体技术领域，特别是涉及一种存储器件及其制备方法。
背景技术
传统的存储器件制备工艺中，形成字线结构的步骤包括：第一步，在衬底上形成有源区(AA区)和浅槽隔离结构(STI)后，蚀刻出字线沟槽(WL trench)。第二步，通过CVD工艺在衬底上淀积形成金属钨薄膜填充字线沟槽后，进行刻蚀工艺去除多余金属钨薄膜，得到由剩余金属钨薄膜构成的字线结构。但是，通过该方法得到的字线结构存在导电性能差，进而影响存储器件性能的问题。
发明内容
基于此，有必要针对上述存储器件中字线结构导电性能差，进而影响存储器件性能的问题，提供一种存储器件及其制备方法。
一种存储器件的制备方法，包括：
提供衬底，衬底上形成有绝缘结构及若干个第一有源结构，若干个第一有源结构于绝缘结构内间隔排布；
进行物理气相淀积工艺，在衬底上形成字线导电层，字线导电层的顶表面高于第一有源结构的顶表面；
图形化刻蚀字线导电层，得到若干条平行间隔排布的字线结构及位于相邻字线结构之间的填充槽，填充槽包括同时露出第一有源结构部分顶表面和绝缘结构部分顶表面的第一填充槽；
在第一填充槽中形成沿露出的第一有源结构的顶表面向字线结构的顶表面延伸的第二有源结构；
在第一填充槽中形成沿露出的绝缘结构的顶表面向字线结构的顶表面延伸的隔离结构。
一种存储器件，是通过上述任一项所述的制备方法制成的。
上述存储器件的制备方法，首先，通过物理气相淀积工艺在衬底上形成字线导电层，其中字线导电层的顶表面高于衬底上形成的第一有源结构的顶表面，其次，图形化刻蚀字线导电层，得到若干条平行间隔排布的字线结构以及位于相邻字线结构之间的填充槽，所述填充槽包括同时露出第一有源结构部分顶表面和绝缘结构部分顶表面的第一填充槽；再次，在第一填充槽中形成沿露出的第一有源结构的顶表面向字线结构的顶表面延伸的第二有源结构，在第一填充槽中形成沿露出的绝缘结构的顶表面向字线结构的顶表面延伸的隔离结构。与先形成包括第一有源结构、第二有源结构的有源区和隔离结构，然后开槽、填充形成字线结构相比，本申请存储器件中的字线结构是通过物理气相淀积工艺形成字线导电层后刻蚀去除多余的字线导电层形成的，该字线结构中不存在卤族元素和空洞，达到提高字线结构导电性能及存储器件的性能的目的。
附图说明
为了更清楚地说明本申请实施例或传统技术中的技术方案，下面将对实施例或传统技 术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为一实施例中存储器件的制备方法的流程示意图；
图2为一实施例中步骤S102的流程示意图；
图3为一实施例中步骤S204之后存储器件的俯视示意图；
图4a为图3所示的存储器件沿AA’方向的剖面示意图；
图4b为图3所示的存储器件沿BB’方向的剖面示意图；
图5a为一实施例中形成第一有源结构后存储器件沿AA’方向的剖面示意图；
图5b为图5a对应的存储器件沿BB’方向的剖面示意图；
图6为一实施例中在衬底上形成字线导电层的流程示意图；
图7a为一实施例中形成字线导电层后存储器件沿AA’方向的剖面示意图；
图7b为图7a对应的存储器件沿BB’方向的剖面示意图；
图8a为一实施例中形成字线结构后存储器件沿AA’方向的剖面示意图；
图8b为图8a对应的存储器件沿BB’方向的剖面示意图；
图9a为一实施例中形成隔离结构后存储器件沿AA’方向的剖面示意图；
图9b为图9a对应的存储器件沿BB’方向的剖面示意图；
附图标记说明：
102-衬底，202-绝缘结构，204-有源沟槽，206-第一有源结构，304-第二导电层，402-第一栅间绝缘层，404-第一导电层，502-第二导电结构，504-第二填充槽，506-第一填充槽，508-第一有源结构顶表面，510-绝缘结构顶表面，512-第一有源结构顶表面，602-第一栅间绝缘结构，604-第一导电结构，606-第二栅间绝缘结构，608-第三导电结构，610-第二有源结构，612-第三有源结构，614-隔离结构。
具体实施方式
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的首选实施例。但是，本申请可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本申请的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本申请。
应当明白，当元件或层被称为“在...上”、“与...相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在...上”、“与...直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层、掺杂类型和/或部分，这些元件、部件、区、层、掺杂类型和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层、掺杂类型或部分与另一个元件、部件、区、层、掺杂类型或部分。因此，在不脱离本发明教导之下，下面讨论的第一元件、部件、区、层、掺杂类型或部分可表示为第二元件、部件、区、层或部分；举例来说，可以将第一掺杂类型成为第二掺杂类型，且类似地，可以将第二掺杂类型成为第一掺杂类型；第一掺杂类型与第二掺杂类型为不同的掺杂类型，譬如，第一掺杂类型可以为P型且第二掺杂类型可以为N型，或第一掺杂类型可以为N型且第二掺杂类型可以为P型。
空间关系术语例如“在...下”、“在...下面”、“下面的”、“在...之下”、“在...之上”、“上面的”等，在这里可以用于描述图中所示的一个元件或特征与其它元件或特征的关系。应当 明白，除了图中所示的取向以外，空间关系术语还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在...下面”和“在...下”可包括上和下两个取向。此外，器件也可以包括另外地取向(譬如，旋转90度或其它取向)，并且在此使用的空间描述语相应地被解释。
在此使用时，单数形式的“一”、“一个”和“所述/该”也可以包括复数形式，除非上下文清楚指出另外的方式。还应明白，当术语“组成”和/或“包括”在该说明书中使用时，可以确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。同时，在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
这里参考作为本申请的理想实施例(和中间结构)的示意图的横截面图来描述申请的实施例，这样可以预期由于例如制造技术和/或容差导致的所示形状的变化。因此，本申请的实施例不应当局限于在此所示的区的特定形状，而是包括由于例如制造技术导致的形状偏差。例如，显示为矩形的注入区在其边缘通常具有圆的或弯曲特征和/或注入浓度梯度，而不是从注入区到非注入区的二元改变。同样，通过注入形成的埋藏区可导致该埋藏区和注入进行时所经过的表面之间的区中的一些注入。因此，图中显示的区实质上是示意性的，它们的形状并不表示器件的区的实际形状，且并不限定本发明的范围。
典型存储器件的制备工艺中，形成有源区和隔离结构后，蚀刻出字线沟槽，通过化学气相淀积工艺形成钨金属薄膜后，然后进行快速热退火工艺(RTA)，图形化刻蚀钨金属薄膜后，得到由字线沟槽中剩余的钨金属薄膜构成的字线结构。此时，字线结构中存在的卤族元素会影响字线结构的导电性，进而影响存储器件的性能。
参见图1，为一实施例中存储器件的制备方法的流程示意图。
为了解决上述问题，本申请提供一种存储器件的制备方法，如图1所示，该制备方法包括：
S102，提供衬底，衬底上形成有绝缘结构及若干个第一有源结构，若干个第一有源结构于绝缘结构内间隔排布。
提供衬底，衬底上形成有绝缘结构及若干个第一有源结构，若干个第一有源结构于绝缘结构内间隔排布，可以理解的是第一有源结构为硅有源结构、绝缘结构为二氧化硅结构。
衬底可以采用未掺杂的单晶硅、掺杂有杂质的单晶硅、绝缘体上硅(SOI)、绝缘体上层叠硅(SSOI)、绝缘体上层叠锗化硅(S-SiGeOI)、绝缘体上锗化硅(SiGeOI)以及绝缘体上锗(GeOI)等。作为示例，在本实施例中，衬底的构成材料选用单晶硅。
S104，进行物理气相淀积工艺，在衬底上形成字线导电层，字线导电层的顶表面高于第一有源结构的顶表面。
进行物理气相淀积工艺，在衬底上形成字线导电层，字线导电层覆盖在第一有源结构和绝缘结构上，且字线导电层的顶表面高于第一有源结构和绝缘结构的顶表面。与化学气相淀积相比，可以避免在形成字线导电层的过程中工艺气体中的卤族元素对字线导电层的导电性能的影响。
S106，刻蚀形成字线结构以及位于相邻字线结构之间的填充槽，所述填充槽包括第一填充槽。
图形化刻蚀字线导电层，得到若干条平行间隔排布的字线结构及位于相邻字线结构之间的填充槽，填充槽包括同时露出第一有源结构部分顶表面和绝缘结构部分顶表面的第一填充槽。即通过光刻工艺在字线导电层上形成掩膜图案后，通过刻蚀工艺刻蚀去除未被掩膜图案覆盖的字线导电层(多余的字线导电层)，得到由掩膜图案覆盖的字线导电层(剩余字线导电层)构成的若干条平行间隔排布的字线结构，以及位于相邻字线结构之间的填充槽，填充槽包括形成于第一有源结构上的字线结构和绝缘结构上的字线结构之间，且同 时暴露出第一有源结构的部分顶表面、绝缘结构的部分顶表面以及第一有源结构和绝缘结构的交界处的第一填充槽。
S108，在第一填充槽中形成沿露出的第一有源结构的顶表面向字线结构的顶表面延伸的第二有源结构。
在第一填充槽中形成沿露出的第一有源结构的顶表面向字线结构的顶表面延伸的第二有源结构，即在第一填充槽中形成底部与第一填充槽露出的第一有源结构的顶表面重合的第二有源结构，该第二有源结构和第一有源结构接触，作为存储器件的有源区。
S110，在第一填充槽中形成沿露出的绝缘结构的顶表面向字线结构的顶表面延伸的隔离结构。
在第一填充槽中形成沿露出的绝缘结构的顶表面向字线结构的顶表面延伸的隔离结构，即在第一填充槽未形成第二有源结构的部分填充形成底部与第一填充槽露出的绝缘结构的顶表面重合的隔离结构，此时隔离结构的底表面和绝缘结构的顶表面接触。
上述存储器件的制备方法，首先，通过物理气相淀积工艺在衬底上形成字线导电层，其中字线导电层的顶表面高于衬底上形成的第一有源结构的顶表面，其次，图形化刻蚀字线导电层，得到若干条平行间隔排布的字线结构以及位于相邻字线结构之间的填充槽，所述填充槽包括同时露出第一有源结构部分顶表面和绝缘结构部分顶表面的第一填充槽；再次，在第一填充槽中形成沿露出的第一有源结构的顶表面向字线结构的顶表面延伸的第二有源结构，在第一填充槽中形成沿露出的绝缘结构的顶表面向字线结构的顶表面延伸的隔离结构。与先形成包括第一有源结构、第二有源结构的有源区和隔离结构，然后开槽、填充形成字线结构相比，本申请存储器件中的字线结构是通过物理气相淀积工艺形成字线导电层后刻蚀去除多余的字线导电层形成的，该字线结构中不存在卤族元素和空洞，达到提高字线结构导电性能及存储器件的性能的目的。
在其中一个实施例中，字线导电层的底表面与第一有源结构的顶表面齐平。在其他实施例中，字线导电层的底表面高于第一有源结构的顶表面。
参见图2，为一实施例中步骤S102的流程示意图。参见图3，为一实施例中步骤S204之后存储器件的俯视示意图。参见图4a，为图3所示的存储器件沿AA’方向的剖面示意图。参见图4b，为图3所示的存储器件沿BB’方向的剖面示意图。参见图5a，为一实施例中形成第一有源结构后存储器件沿AA’方向的剖面示意图。参见图5b，为图5a对应的存储器件沿BB’方向的剖面示意图。
如图2-图5b所示，在其中一个实施例中，位于绝缘结构顶表面部分的字线导电层的底表面低于第一有源结构的顶表面，步骤S102包括：
S202，提供表面形成有绝缘层的衬底。
S204，图形化刻蚀绝缘层，得到绝缘结构及若干个于绝缘结构内间隔排布的有源沟槽。
图形化刻蚀去除衬底102上多余的绝缘层，得到绝缘结构202、以及若干个于绝缘结构内间隔排布的有源沟槽204。
如图4a、图4b所示，具体地，首先，在衬底上102上形成覆盖在需要保留的绝缘层上的掩膜图案，即掩膜图案暴露出后续形成第一有源结构的位置上的绝缘层。然后，刻蚀去除未被掩膜图案覆盖的绝缘层，得到由剩余绝缘层构成的绝缘结构202，以及若干个于绝缘结构202内间隔排布的有源沟槽204。
在其中一个实施例中，有源沟槽204的底部和衬底102的上表面之间具有一定厚度的绝缘层。
S206，填充有源沟槽，形成顶表面高于绝缘结构顶表面的第一有源结构。
填充有源沟槽204，形成顶表面高于绝缘结构202顶表面的第一有源结构206。具体地，在有源沟槽204中填充形成顶表面高于绝缘结构202的第一有源结构206。
在其他实施例中，第一有源结构206和绝缘结构202的顶表面齐平，或者第一有源结 构206的顶表面低于绝缘结构202的顶表面。
如图4a、图4b、图5a、图5b所示，在其中一个实施例中，有源沟槽204露出衬底102的上表面，填充有源沟槽204，形成顶表面高于绝缘结构202的第一有源结构206的步骤包括：
进行外延工艺，在有源沟槽204中形成第一有源结构206，所述第一有源结构206为硅外延结构，通过外延工艺形成的第一有源结构206为单晶硅结构，避免了第一有源结构206与衬底102之间晶格不匹配的问题。
在其中实施例中，可以选用本领域技术人员熟知的其他形成硅有源结构的方式形成第一有源结构。
参见图6，为一实施例中在衬底上形成字线导电层的流程示意图。参见图7a，为一实施例中形成字线导电层后存储器件沿AA’方向的剖面示意图。参见图7b，为图7a对应的存储器件沿BB’方向的剖面示意图。
如图6、图7a、图7b所示，在其中一个实施例中，在衬底102上形成字线导电层的步骤包括：
S302，在衬底上形成第一栅间绝缘层。
在衬底102上形成第一栅间绝缘层402，第一栅间绝缘402覆盖第一有源结构206的顶表面及绝缘结构202的顶表面。具体地，如图7a、图7b所示，在第一有源结构206的上表面形成第一栅间绝缘层402，第一栅间绝缘层402沿第一有源结构206的顶表面延伸覆盖在绝缘结构202的顶表面。本实施例中，第一栅间绝缘层402至少包括二氧化硅薄膜、高k栅介质薄膜中的一种，可以通过原子层淀积工艺或其他工艺形成第一栅间绝缘层402。
S304，在第一栅间绝缘层的顶表面形成第一导电层。
在第一栅间绝缘层402的顶表面形成第一导电层404，例如Ti/TiN金属层。
S306，在第一导电层的顶表面形成第二导电层。
在第一导电层404的顶表面形成第二导电层304，第一栅间绝缘402、第一导电层404、第二导电层304构成字线导电层。
在其中一个实施例中，第二导电层304包括钨导电层。当第一栅间绝缘层402选取氧化硅层，第一导电层404选取氮化钛金属层，第二导电层304选取钨导电层时，在第一导电层404上成第二导电层304的步骤为：在氮化钛金属层的上表面形成钨导电层，此时，氮化钛金属层同时作为粘附层。在本实施例中，第二导电层304的下表面低于第一有源结构206的上表面。
在其中一个实施例中，步骤S306包括：第一步，在第一导电层404上形成第二导电层材料。第二步，对第二导电层材料进行平坦化处理，得到第二导电层304，例如，通过化学研磨工艺对第二导电层材料进行平坦化处理，得到由剩余第二导电层材料构成的第二导电层304。
参见图8a，为一实施例中形成字线结构后存储器件沿AA’方向的剖面示意图。参见图8b，为图8a对应的存储器件沿BB’方向的剖面示意图。
如图8a、图8b所示，在其中一个实施例中，图形化刻蚀字线导电层，得到若干条平行间隔排布的字线结构的步骤包括：
图形化刻蚀第二导电层304、第一导电层404及第一栅间绝缘层402，得到包括依次叠加的第二导电结构502、第一导电结构604、第一栅间绝缘结构602的字线结构。
具体地，在衬底102上形成字线掩膜图案，字线掩膜图案覆盖在需要保留的第二导电层304上，暴露出需要去除的第二导电层304，刻蚀去除字线掩膜图案露出的第二导电层304以及位于第二导电层304下方的第一导电层404、第一栅间绝缘层402，得到包括依次叠加的第二导电结构502(剩余第二导电层304)、第一导电结构604(剩余第一导电层404)、第一栅间绝缘结构602(剩余第一栅间绝缘层402)的字线结构。
在其中一个实施例中，第二导电结构502包括钨导电结构，第一导电结构604包括氮化钛结构，第一栅间绝缘结构602包括氧化硅结构。
在其中一个实施例中，得到包括依次叠加的第二导电结构502、第一导电结构604、第一栅间绝缘结构602的字线结构之后还包括步骤：
在字线结构的侧壁依次形成第三导电结构608和第二栅间绝缘结构606；其中，第三导电结构608和第二栅间绝缘结构606的延伸方向均与字线结构的延伸方向相同，第三导电结构608和第二栅间绝缘结构606的高度均等于字线结构的底表面与字线结构的顶表面之间的距离，存储器件的栅极字线包括字线结构、第三导电结构608和第二栅间绝缘结构606。第三导电结构608和第二栅间绝缘结构606自字线结构向填充槽依次叠加，即第二栅间绝缘结构606与字线结构之间的距离大于第三导电结构608与字线结构之间的距离。
具体地，在字线结构的侧壁依次形成第三导电结构608和第二栅间绝缘结构606的步骤包括：第一步，在字线结构的侧面(即字线结构502两侧填充槽的侧壁)形成第三导电结构608，其中，第三导电结构608的延伸方向与字线结构的延伸方向相同，第三导电结构608的高度(第三导电结构608靠近衬底102的底表面与远离衬底102的顶表面之间的距离即填充槽的底壁与填充槽的开口之间的距离)等于字线结构的底表面与字线结构的顶表面之间的距离。第二步，在第三导电结构608的侧面形成第二栅间绝缘结构606，其中，第二栅间绝缘结构606的延伸方向与字线结构的延伸方向相同，第二栅间绝缘结构606的高度(第二栅间绝缘结构606靠近衬底102的底表面与远离衬底102的顶表面之间的距离即填充槽的底壁与填充槽的开口之间的距离)等于字线结构的底表面与字线结构的顶表面之间的距离。
在其中一个实施例中，第一栅间绝缘结构602和第二栅间绝缘结构606是由相同材料构成的，例如均为二氧化硅栅介质层或高k栅介质层。第一导电结构608和第三导电结构608是由相同材料构成的，例如均为氮化钛金属结构。
在其中一个实施例中，第三导电结构608包括氮化钛结构，第二栅间绝缘结构606包括氧化硅结构，字线结构包括埋入式字线结构，第二有源结构、隔离结构的顶表面均高于字线结构的顶表面。
在其中一个实施例中，第一栅间绝缘结构602和第二栅间绝缘结构606共同构成存储器件的栅介质结构。
参见图9a，为一实施例中形成隔离结构后存储器件沿AA’方向的剖面示意图。参见图9b，为图9a对应的存储器件沿BB’方向的剖面示意图。
如图8a、图9a、图9b所示，在其中一个实施例中，填充槽还包括露出第一有源结构206部分顶表面的第二填充槽504；
在第一填充槽506中形成沿露出的第一有源结构206顶表面508向字线结构顶表面延伸的第二有源结构610的同时还包括：
在第二填充槽504中形成沿露出的第一有源结构206顶表面512向字线结构顶表面延伸的第三有源结构612；
其中，第一有源结构206、第二有源结构610和第三有源结构612共同构成存储器件的有源区。
在其中一个实施例中，第二有源结构610和第三有源结构612的顶表面齐平。
在其中一个实施例中，第二有源结构610、第三有源结构612和字线结构的顶表面齐平。
具体地，如图9a所示，第一有源结构206、第二有源结构610和第三有源结构612作为一个整体的硅有源结构，后续在第二有源结构610中形成存储器件中晶体管的源极结构，在第三有源结构612中形成存储器件中晶体管的漏极结构，该存储器件包括双字线结构、共漏极结构的晶体管。
在其中一个实施例中，第三有源结构612和第二有源结构610是在同一步工艺中形成的。
在其中一个实施例中，在第二填充槽504中形成沿露出的第一有源结构206顶表面512向字线结构顶表面延伸的第三有源结构612的步骤包括：
进行外延工艺，在第二填充槽504中形成沿露出的所述第一有源结构206顶表面向字线结构顶表面延伸的第三有源结构612。
在其中一个实施例中，字线结构两侧的第二有源结构610分别用于形成存储器件中晶体管的源极结构和漏极结构。
在其中一个实施例中，在第一填充槽506中形成沿露出的第一有源结构206顶表面向字线结构顶表面延伸的第二有源结构610的步骤包括：
进行外延工艺，在第一填充槽506中形成沿露出的第一有源结构206顶表面向字线结构顶表面延伸的第二有源结构610。
在其中一个实施例中，第一有源结构206和第二有源结构610共同构成存储器件的有源区，步骤S110中在第一填充槽506中形成沿露出的绝缘结构202顶表面510向字线结构顶表面延伸的隔离结构614和绝缘结构202共同构成有源区之间的浅槽隔离结构。
本申请还提供一种存储器件，是通过上述任一项所述的制备方法制成的。
本申请还提供一种存储设备，所述存储设备包括上述存储器件。
应该理解的是，虽然图1、图2、图6的流程图中的各个步骤按照箭头的指示依次显示，但是这些步骤并不是必然按照箭头指示的顺序依次执行。除非本文中有明确的说明，这些步骤的执行并没有严格的顺序限制，这些步骤可以以其它的顺序执行。而且，图1、图2、图6中的至少一部分步骤可以包括多个步骤或者多个阶段，这些步骤或者阶段并不必然是在同一时刻执行完成，而是可以在不同的时刻执行，这些步骤或者阶段的执行顺序也不必然是依次进行，而是可以与其它步骤或者其它步骤中的步骤或者阶段的至少一部分轮流或者交替地执行。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (15)

  1. 一种存储器件的制备方法，包括：
    提供衬底，所述衬底上形成有绝缘结构及若干个第一有源结构，若干个所述第一有源结构于所述绝缘结构内间隔排布；
    进行物理气相淀积工艺，在所述衬底上形成字线导电层，所述字线导电层的顶表面高于所述第一有源结构的顶表面；
    图形化刻蚀所述字线导电层，得到若干条平行间隔排布的字线结构及位于相邻所述字线结构之间的填充槽，所述填充槽包括同时露出第一有源结构部分顶表面和绝缘结构部分顶表面的第一填充槽；
    在所述第一填充槽中形成沿露出的第一有源结构的顶表面向字线结构的顶表面延伸的第二有源结构；
    在所述第一填充槽中形成沿露出的绝缘结构的顶表面向字线结构的顶表面延伸的隔离结构。
  2. 根据权利要求1所述的制备方法，其中，位于所述绝缘结构顶表面部分的所述字线导电层的底表面低于所述第一有源结构的顶表面，所述提供衬底的步骤包括：
    提供表面形成有绝缘层的衬底；
    图形化刻蚀所述绝缘层，得到所述绝缘结构及若干个于所述绝缘结构内间隔排布的有源沟槽；
    填充所述有源沟槽，形成顶表面高于所述绝缘结构顶表面的所述第一有源结构。
  3. 根据权利要求2所述的制备方法，其特征在于，所述有源沟槽露出所述衬底的上表面，所述填充所述有源沟槽，形成顶表面高于所述绝缘结构的所述第一有源结构的步骤包括：
    进行外延工艺，在所述有源沟槽中形成所述第一有源结构。
  4. 根据权利要求1所述的制备方法，其中，所述在所述衬底上形成字线导电层的步骤包括：
    在所述衬底上形成第一栅间绝缘层，所述第一栅间绝缘层覆盖所述第一有源结构的顶表面及所述绝缘结构的顶表面；
    在所述第一栅间绝缘层的顶表面形成第一导电层；
    在所述第一导电层的顶表面形成第二导电层；
    其中，所述第一栅间绝缘层、所述第一导电层、所述第二导电层构成所述字线导电层。
  5. 根据权利要求4所述的制备方法，其中，所述图形化刻蚀所述字线导电层，得到若干条平行间隔排布的所述字线结构的步骤包括：
    图形化刻蚀所述第二导电层、所述第一导电层及所述第一栅间绝缘层，得到包括依次叠加的第二导电结构、第一导电结构、第一栅间绝缘结构的字线结构。
  6. 根据权利要求5所述的制备方法，其中，所述第二导电结构包括钨导电结构，所述第一导电结构包括氮化钛结构，所述第一栅间绝缘结构包括氧化硅结构。
  7. 根据权利要求5所述的制备方法，还包括：所述得到包括依次叠加的第二导电结构、第一导电结构、第一栅间绝缘结构的字线结构之后，
    在所述字线结构的侧壁依次形成第三导电结构和第二栅间绝缘结构；
    其中，第三导电结构和第二栅间绝缘结构的延伸方向均与所述字线结构的延伸方向相同，所述第三导电结构和所述第二栅间绝缘结构的高度均等于所述字线结构的底表面与所述字线结构的顶表面之间的距离，所述存储器件的栅极字线包括所述字线结构、所述第三导电结构和所述第二栅间绝缘结构。
  8. 根据权利要求7所述的制备方法，其中，所述第三导电结构包括氮化钛结构，所述第二栅间绝缘结构包括氧化硅结构，所述字线结构包括埋入式字线结构，所述第二有源结 构、所述隔离结构的顶表面均高于所述字线结构的顶表面。
  9. 根据权利要求7所述的制备方法，其中，所述第一栅间绝缘结构和所述第二栅间绝缘结构共同构成所述存储器件的栅介质结构。
  10. 根据权利要求4所述制备方法，其中，所述在所述第一导电层的顶表面形成第二导电层的步骤包括：
    在所述第一导电层上形成第二导电层材料；
    对所述第二导电层材料进行平坦化处理，得到所述第二导电层。
  11. 根据权利要求1所述的制备方法，其中，所述第一有源结构和所述第二有源结构共同构成所述存储器件的有源区，所述隔离结构和所述绝缘结构共同构成所述有源区之间的浅槽隔离结构。
  12. 根据权利要求1所述的制备方法，其中，所述填充槽还包括露出第一有源结构部分顶表面的第二填充槽；
    在所述第一填充槽中形成沿露出的第一有源结构顶表面向字线结构顶表面延伸的第二有源结构的同时还包括：
    在所述第二填充槽中形成沿露出的第一有源结构顶表面向字线结构顶表面延伸的第三有源结构；
    其中，所述第一有源结构、所述第二有源结构和所述第三有源结构共同构成所述存储器件的有源区。
  13. 根据权利要求12所述的制备方法，其中，所述在所述第二填充槽中形成沿露出的第一有源结构顶表面向字线结构顶表面延伸的第三有源结构的步骤包括：
    进行外延工艺，在所述第二填充槽中形成沿露出的所述第一有源结构顶表面向字线结构顶表面延伸的所述第三有源结构。
  14. 根据权利要求1所述的制备方法，其中，所述在所述第一填充槽中形成沿露出的第一有源结构顶表面向字线结构顶表面延伸的第二有源结构的步骤包括：
    进行外延工艺，在第一填充槽中形成沿露出的所述第一有源结构顶表面向字线结构顶表面延伸的所述第二有源结构。
  15. 一种存储器件，其中，所述存储器件是通过权利要求1-14任一项所述的制备方法制成的。
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