TWI575612B - 鰭狀場效電晶體裝置與其形成方法 - Google Patents

鰭狀場效電晶體裝置與其形成方法 Download PDF

Info

Publication number
TWI575612B
TWI575612B TW104136965A TW104136965A TWI575612B TW I575612 B TWI575612 B TW I575612B TW 104136965 A TW104136965 A TW 104136965A TW 104136965 A TW104136965 A TW 104136965A TW I575612 B TWI575612 B TW I575612B
Authority
TW
Taiwan
Prior art keywords
fin
crystalline semiconductor
semiconductor material
dielectric
forming
Prior art date
Application number
TW104136965A
Other languages
English (en)
Other versions
TW201639043A (zh
Inventor
王志豪
蔡慶威
劉繼文
江國誠
廖忠志
連萬益
Original Assignee
台灣積體電路製造股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 台灣積體電路製造股份有限公司 filed Critical 台灣積體電路製造股份有限公司
Publication of TW201639043A publication Critical patent/TW201639043A/zh
Application granted granted Critical
Publication of TWI575612B publication Critical patent/TWI575612B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H01L27/1211—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H01L21/845—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66537—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a self aligned punch through stopper or threshold implant under the gate region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)
  • Materials Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Description

鰭狀場效電晶體裝置與其形成方法
本揭露關於半導體裝置，更特別關於FinFET裝置與其形成方法。
當半導體產業朝向奈米技術的製程節點邁進，以達更高的裝置密度、更高的效能、與更低的成本時，在三維設計如鰭狀場效電晶體(FinFET)面臨製程與設計的問題。舉例來說，一般的FinFET之形成方法具有自基板延伸之薄的垂直鰭狀物(或鰭狀結構)，其形成方法為蝕刻基板的部份矽層。FinFET的通道形成於垂直鰭狀物中。閘極提供於鰭狀物上，比如包覆鰭狀物。鰭狀物位於通道兩側上，可讓閘極自通道兩側控制通道。
然而，在半導體製程中實施這些結構與製程仍屬挑戰。舉例來說，相鄰的鰭狀物之間的隔離不足導致FinFET的高漏電流，這將劣化裝置效能。
本揭露一實施例提供之方法包括：形成鰭狀物於基板上，鰭狀物包括第一結晶半導體材料於基板上，以及第二結晶半導體材料於第一結晶半導體材料上；使鰭狀物中的至少部份第一結晶半導體材料與第二結晶半導體材料轉換成介電 材料；移除至少部份介電材料；形成閘極結構於鰭狀物上；以及形成源極/汲極區於閘極結構之相反兩側上。
本揭露一實施例提供之方法，包括：磊晶成長第一結晶半導體材料於基板上；磊晶成長第二結晶半導體材料於第一結晶半導體材料上；圖案化第一結晶半導體材料與第二結晶半導體材料，以形成鰭狀物於基板上；氧化鰭狀物中的至少部份第一結晶半導體材料與第二結晶半導體材料，以形成氧化物材料；移除至少部份氧化物材料；形成多個隔離區於基板上，以圍繞鰭狀物的較下部份；形成閘極結構於鰭狀物與隔離區上；以及形成源極/汲極區於閘極結構之相反兩側上。
本揭露一實施例提供之結構，包括鰭狀物，位於基板上，其中鰭狀物包括第一磊晶部份，且第一磊晶部份包括第一材料之第一濃縮區；多個隔離區，位於基板中及鰭狀物的相反兩側上，且鰭狀物之第一磊晶部份自隔離區之間凸起；介電區，直接位於第一磊晶部份下，且介電區之材料不同於隔離區之材料，其中第一材料之第一濃縮區位於第一磊晶部份與介電區之間的界面；以及閘極結構，沿著鰭狀物之側壁且位於鰭狀物之上表面上，且閘極結構定義通道區於第一磊晶部份中。
B-B、C-C‧‧‧剖線
30‧‧‧FinFET
32、50‧‧‧基板
34‧‧‧隔離區
36‧‧‧鰭狀物
38‧‧‧閘極介電物
40‧‧‧閘極
42、44、88‧‧‧源極/汲極區
52‧‧‧APT區
54‧‧‧佈植步驟
60‧‧‧半導體帶
62‧‧‧圖案化基板
64‧‧‧矽鍺層
66、74‧‧‧半導體層
68‧‧‧遮罩層
70‧‧‧矽鍺介電區
72‧‧‧介電材料區
76‧‧‧隔離區
78、94‧‧‧閘極介電物
80、96‧‧‧閘極
82‧‧‧遮罩
84‧‧‧閘極密封間隔物
86、92‧‧‧凹陷
90‧‧‧ILD
98‧‧‧接點
100A、100B、100C‧‧‧鍺殘留區
200、202、204、206、208、210、212、214、216、218、220、222、224、226、230、232、234‧‧‧步驟
第1圖係一例中，鰭狀物場效電晶體(FinFET)之立體圖。
第2、3、4A-4B、5A-5B、6A、6B1-6B2、7A-7B、8A-8B、9A-9B、10A-10C、與11A-11C圖係某些實施例中，FinFET之形成方法其中間階段的剖視圖。
第12圖係某些實施例中，製程之流程圖。
第13A-13C、14A-14C、15、與16圖係某些實施例中，FinFET之形成方法其中間階段的剖視圖。
第17圖係某些實施例中，製程之流程圖。
第18與19圖係某些實施例中，結構之剖視圖。
第20-22圖係實施例中，樣品之穿透式電子顯微鏡(TEM)影像。
第23-24圖係某些實施例中，結構之剖視圖。
第25-27圖係實施例中，樣品之TEM影像。
下述內容提供的不同實施例可實施本揭露的不同結構。特定構件與排列的實施例係用以簡化本揭露而非侷限本揭露。舉例來說，形成第一構件於第二構件上的敘述包含兩者直接接觸，或兩者之間隔有其他額外構件而非直接接觸。此外，本揭露之多種例子中可重複標號，但這些重複僅用以簡化與清楚說明，不代表不同實施例及/或設置之間具有相同標號之單元之間具有相同的對應關係。
此外，空間性的相對用語如「下方」、「其下」、「較下方」、「上方」、「較上方」、或類似用語可用於簡化說明某一元件與另一元件在圖示中的相對關係。空間性的相對用語可延伸至以其他方向使用之元件，而非侷限於圖示方向。元件亦可轉動90°或其他角度，因此方向性用語僅用以說明圖示中的方向。
多種實施例提供鰭狀物場效電晶體(FinFET)與其 形成方法，以及形成FinFET之中間階段。在某些實施例中，FinFET之形成方法採用閘極後製製程。在其他實施例中，可採用閘極優先製程。某些實施例亦可用於平面裝置如平面FET。下述內容亦包含實施例的某些變化。本技術領域中具有通常知識者應理解，其他改良亦屬其他實施例之範疇。雖然下述實施例之方法具有特定順序，但其他實施例之方法可以合邏輯之順序進行，並可包含較少或較多之步驟。
在提及特定實施例之前，本揭露一般先提及實施例之有利特徵。一般而言，本揭露係半導體裝置與其形成方法，可提供簡易且成本低的製程，以達FinFET中的未掺雜通道並改良裝置。此外，這些簡易且成本低的製可達絕緣體上通道(有時稱作氧化物上通道)。特別的是，下述實施例包含方向性的氧化鰭狀物步驟，使鰭狀物之側壁更垂直於基板的主要表面，亦控制通道下之絕緣層中的鍺殘留量。控制鍺殘留可增加FinFET裝置的可信度，因為鍺殘留會擴散至閘極結構並降低FinFET裝置之可信度。此外，鰭狀物之磊晶部份係磊晶成長如毯覆層，其通常比磊晶成長於溝槽/凹陷中的半導體結構具有較少缺陷及較高品質。
第1圖係一例中，FinFET 30之立體圖。FinFET 30包含鰭狀物36於基板32上。基板32包含隔離區34，且鰭狀物自相鄰的隔離區34之間凸起於隔離區34上。閘極介電物38沿著鰭狀物36之側壁與上表面，而閘極40位於閘極介電物38上。源極/汲極區42與44對應閘極介電物38與閘極40，分別位於鰭狀物36之相反兩側中，第1圖更包含後續圖式所用的剖線。剖線B-B 橫越FinFET 30之通道、閘極介電物38、與閘極40。剖線C-C平行於剖線B-B，且橫越源極/汲極區42。為清楚說明，後續圖式將對應上述剖線。
第2-11C圖係一實施例中，FinFET之形成方法其中間階段的剖視圖，而第12圖係上述製程之流程圖。第2至11C圖形成之FinFET與第1圖中的FinFET 30類似，不過前者包含多個FinFET。在第4A至11C圖中，圖式標號含A者係立體圖，圖式標號含B者係對應剖線B-B的剖視圖，而圖式標含含C者係對應剖線C-C的剖視圖。
第2圖圖示基板50。基板50可為半導體基板如基體半導體、絕緣層上半導體(SOI)基板、或類似物，且可掺雜n型或p型掺質或未掺雜。基板50可為晶圓如矽晶圓。一般而言，SOI基板包含半導體材料層形成於絕緣層上。舉例來說，絕緣層可為埋置氧化物(BOX)層、氧化矽層、或類似物。絕緣層位於基板(通常為矽或玻璃)上。其他基板可為多層或組成漸變基板。在某些實施例中，基板50之半導體材料可為矽或鍺，半導體化合物如碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦、及/或銻化銦，半導體合金如SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、GaInAsP、或上述之組合。
基板50可包含積體電路裝置(未圖示)。本技術領域中具有通常知識者應理解，多種積體電路裝置如電晶體、二極體、電容、電阻、類似物、或上述之組合可形成於基板50之中及/或之上，以符合用於FinFET之設計的結構與功能需求。積體電路裝置之形成方法可為任何合適方法。
第2圖對應步驟200，形成APT(抗擊穿)區52於基板50中。在某些實施例中，APT區之形成方法為進行於基板50之頂部上的佈植步驟54。佈植於APT區中的掺質導電型態，與基板50之井區(未圖示)的導電型態相同。APT區52延伸於後續形成之源極/汲極區88(見第11A與11C圖)下方，可降低源極/汲極區88至基板50的漏電流。APT區52之掺雜濃度可介於約1E18/cm3至約1E19/cm3之間。
如第3圖所示，形成矽鍺層64(如毯覆層)於基板50與APT區52上，並形成半導體層66(如毯覆層)於矽鍺層64上(步驟202)。在某些實施例中，矽鍺層64與半導體層66為磊晶製程形成的結晶層。在某些實施例中，矽鍺層64之厚度介於約5nm至約15nm之間。矽鍺層64之鍺原子%介於約15原子%至約35原子%之間，不過亦可高於或低於上述範圍。然而可以理解的是，說明書中的數值範圍僅用以舉例，且可改變為其他數值。
形成於矽鍺層64上的半導體層66可包含一或多個半導體層。在某些實施例中，半導體層66為純矽層而不包含鍺。在某些實施例中，半導體層66可為實質上純矽層，且包含小於1原子%之鍺。半導體層66可為本徵層，即未掺雜p型與n型掺質。
如第3圖所示，形成遮罩層68於半導體層66上(步驟204)。在某些實施例中，遮罩層68為硬遮罩。遮罩層68可為氮化矽、氮氧化矽、碳化矽、碳氮化矽、類似物、或上述之組合。為清楚說明，後續圖式將省略APT區52。
如第4A與4B圖所示，形成半導體帶60(步驟206)。 在某些實施例中，半導體帶60的形成方法為蝕刻溝槽於遮罩層68、半導體層66、矽鍺層64、與基板50中。基板50其圖案化部份，即第4A與4B圖所示之圖案化基板62。半導體層66與矽鍺層64之圖案化部份及圖案化基板62統稱為半導體帶60。半導體帶60亦可稱作半導體鰭狀物。上述蝕刻可為任何可接受的蝕刻製程如反應性離子蝕刻(RIE)、中性束蝕刻(NBE)、類似製程、或上述之組合。上述蝕刻可為非等向性。
在第5A與5B圖中，部份半導體帶60轉換為介電材料(步驟208)。在某些實施例中，上述轉換製程為氧化製程。氧化製程可採用蒸氣爐。舉例來說，可將包含半導體帶60之基板50置於爐中，使基板50暴露至蒸汽環境。蒸汽環境之溫度可介於約400℃至約600℃之間，比如約500℃。水蒸汽的流速可介於約100sccm至約1000sccm之間。基板50暴露至爐中蒸汽環境的時間可介於約0.5小時至約3小時之間，比如約1小時。如第5A與5B圖所示，半導體層66之較外部份可轉換為介電材料區72，並保留半導體層74。此外，矽鍺層64可完全轉換為矽鍺介電區70。在某些實施例中，矽鍺介電區70之組成為氧化矽鍺。除上述轉換製程，亦可採用其他轉換製程。
在相同的矽鍺區中，使矽鍺中的矽氧化，比使矽鍺中的鍺氧化容易。綜上所述，矽鍺介電區70中的矽原子被氧化，而矽鍺介電區70中的鍺原子朝矽鍺介電區70之中心擴散，即矽鍺介電區70其中心的鍺比例在氧化製程後比氧化製程前高。
在某些實施例中，介電材料區72之厚度由半導體 帶60之頂部(靠近遮罩層68)向半導體帶60之底部增加，如第5A與5B圖所示。在這些實施例中，轉換製程可為方向性的轉換製程如方向性的氧化製程，其採用遮罩層68作為氧化遮罩。舉例來說，方向性的氧化製程為氣體簇離子束氧化法。
在第6A、6B1、與6B2圖中，移除介電材料區72，並視情況(非必要)移除部份的矽鍺介電區70(步驟210)。移除介電材料區72使半導體層74之側壁更垂直於基板50的主要表面，且可增進FinFET裝置的效能與控制。介電材料區72的移除方法可為蝕刻製程。蝕刻可為任何可接受的蝕刻製程如濕蝕刻製程、乾蝕刻製程、類似製程、或上述之組合。蝕刻可為等向或非等向。在第6B1圖所示之實施例中，蝕刻製程係對矽鍺介電區70、半導體層74、與圖案化基板62具有選擇性，因此實質上不蝕刻矽鍺介電區70。在第6B2圖所示之實施例中，亦蝕刻矽鍺介電區70使其側壁與半導體層74之側壁毗連。
如第7A與7B圖所示，形成絕緣材料於相鄰之半導體帶60之間，以形成隔離區76(步驟212)。絕緣材料可為氧化物如氧化矽、氮化物、類似物、或上述之組合，且其形成方法可為高密度電漿化學氣相沉積(HDP-CVD)、可流動CVD(FCVD，比如將CVD為主的材料沉積於遠端電漿系統中，並後硬化使其轉換成另一材料如氧化物)、類似方法、或上述之組合。任何可接受的製程形成之其他絕緣材料亦可用於此步驟。在此實施例中，絕緣材料為FCVD製程形成之氧化矽。形成絕緣材料後，可進行回火製程。如第7A與7B圖所示，可採用平坦化製程如化學機械拋光(CMP)移除任何多餘的絕緣材料，使 隔離區76之上表面與半導體帶60之上表面共平面(步驟214)。
如第8A與8B圖所示，使隔離區76凹陷(步驟216)以形成淺溝槽隔離(STI)區。隔離區76凹陷後，半導體帶60之半導體層74自相鄰之隔離區76之間凸起，以形成半導體鰭狀物。如圖所示，隔離區76之上表面高於矽鍺介電區70之上表面。在其他實施例中，隔離區76之上表面可低於矽鍺介電區70之上表面並高於矽鍺介電區70之下表面，或者隔離區76之上表面可低於矽鍺介電區70之下表面。此外，隔離區76之上表面可為圖示之平坦表面、凸面、凹面(如碟狀)、或上述之組合。隔離區76之上表面的形狀如平坦、凸面、及/或凹面的形成方法為合適蝕刻。隔離區76之凹陷方法可為可接受的蝕刻製程，比如對隔離區76之材料具有選擇性的蝕刻製程。舉例來說，上述凹陷製程可採用CERTAS®蝕刻品之化學氧化物移除法、應用材料SICONI工具、或稀氫氟酸。
如第9A與9B圖所示，形成閘極結構於半導體層74之鰭狀物上(步驟218)。介電層(未圖示)形成於半導體層74之鰭狀物與隔離區76上。舉例來說，介電層可為氧化矽、氮化矽、上述之多層結構、或類似物，且其沉積方法或熱成長方法可為可接受的技術。在某些實施例中，介電層可為高介電常數之介電材料。在這些實施例中，介電層之介電常數大於約7.0，且可為下述金屬之氧化物或矽酸鹽：Hf、Al、Zr、La、Mg、Ba、Ti、Pb、上述之多層物、或上述之組合。上述介電層之形成方法可為原子束沉積(MBD)、原子層沉積(ALD)、電漿增強CVD(PECVD)、或類似方法。
閘極層(未圖示)形成於介電層上，而遮罩層(未圖示)形成於閘極層上。可沉積閘極層於介電層上，再進行平坦化如CMP。遮罩層可沉積於閘極層上。舉例來說，閘極層可為多晶矽，但亦可為其他材料。在某些實施例中，閘極層可為含金屬材料如TiN、TaN、TaC、Co、Ru、Al、上述之組合、或上述之多層結構。舉例來說，遮罩層之組成可為氮化矽或類似物。
在形成上述層狀物後，可採用可接受的光微影與蝕刻技術圖案化遮罩層，以形成遮罩82。藉由可接受的蝕刻技術，可將遮罩82之圖案轉移至閘極層與介電層，以形成閘極80與閘極介電物78。閘極80與閘極介電物78覆蓋半導體層74之鰭狀物其個別的通道區。閘極80之縱向實質上垂直於個別半導體層74之鰭狀物之縱向。
在形成閘極80與閘極介電物78後，可形成閘極密封間隔物84於閘極與遮罩82露出的表面上。在熱氧化或沉積製程後，進行非等向蝕刻可形成上述閘極密封間隔物84。
如第10A、10B、與10C圖所示，移除閘極結構以外的半導體層74之鰭狀物與矽鍺介電區70(步驟220)。閘極結構可作為移除半導體層74之鰭狀物與矽鍺介電區70之遮罩。上述步驟可形成凹陷86於圖案化基板62、半導體層74之鰭狀物、及/或隔離區76中。在某些實施例中，移除所有不直接位於閘極結構下的部份矽鍺介電區70。在其他實施例中，保留不位於閘極結構下的某些部份矽鍺介電區70。凹陷86之形成方法可為任何可接受的蝕刻製程如RIE、NBE、氫氧化四甲基銨(TMAH)、氫氧化銨、在矽與隔離區76之材料之間具有良好蝕刻選擇性且 可蝕刻矽之濕蝕刻品、類似方法、或上述之組合。蝕刻可為非等向性。蝕刻半導體層74之鰭狀物與矽鍺介電區70的方法可為單一蝕刻製程或多重蝕刻製程，比如用於半導體層74之鰭狀物的第一蝕刻製程與用於矽鍺介電區70之第二蝕刻製程。凹陷86其至少部份下表面露出圖案化基板62的表面。如圖所示，蝕刻製程後的凹陷86之下表面包含圖案化基板62的所有上表面。在此實施例中，圖案化基板62之上表面各自平坦。在其他實施例中，圖案化基板62之上表面可具有不同形態。
如第11A、11B、與11C圖所示，形成源極/汲極區88(步驟222)。源極/汲極區88形成於凹陷86中的方法為磊晶材料於凹陷86中，且磊晶法可為有機金屬CVD(MOCVD)、原子束磊晶(MBE)、液相磊晶(LPE)、氣相磊晶(VPE)、選擇性磊晶成長(SEG)、類似方法、或上述之組合。如第11A、11B、與11C圖所示，由於隔離區76阻擋，源極/汲極區88先垂直成長而非水平成長於凹陷86中。在完全填滿凹陷86後，才垂直與水平地成長源極/汲極區88以形成刻面。
在FinFET為n型FinFET之某些實施例中，源極/汲極區88包含碳化矽(SiC)、磷化矽(SiP)、掺雜磷之碳化矽(SiCP)、或類似物。在FinFET為p型FinFET之其他實施例中，源極/汲極區88包含SiGe，且p型雜質可為硼或銦。
磊晶的源極/汲極區88可佈植掺質，之後進行回火。佈植製程可包含形成圖案化遮罩如光阻，以覆蓋FinFET其所欲保護的區域免於佈植製程的影響。源極/汲極區88之雜質濃度可介於約1019cm-3至約1021cm-3之間。在某些實施例中， 磊晶的源極/汲極區88可在成長時臨場掺雜。
接著可進行FinFET裝置之後續製程，比如形成一或多個層間介電層與接點。這些製程將搭配第13A-13C、14A-14C、15、與16圖說明於下。
第13A-13C、14A-14C、15、與16圖係另一實施例中，FinFET之形成方法其中間階段的剖視圖，而第17圖係上述形成方法的流程圖。第13A-13C、14A-14C、15、與16圖形成之FinFET與第1圖之FinFET 30類似，除了包含多個FinFET。在第13A-13C與14A-14C圖中，圖式標號含A者係立體圖，圖式標號含B者係對應剖線B-B的剖視圖，而圖式標含含C者係對應剖線C-C的剖視圖。第15與16圖對應剖線C-C的剖視圖。
此實施例與前述之第2至11C圖的實施例類似，除了此實施例為閘極後製製程(又稱作置換閘極製程)，而先前實施例為閘極優先製程。此實施例與先前實施例類似的細節將不再贅述於下。
此實施例同樣進行第2至11C圖與步驟200至222，差別在於閘極80為虛置的閘極，而閘極介電物78為虛置的閘極介電物(第17圖中的步驟230)。在第13A-13C圖中，沉積ILD(層間介電物)90於第11A-11C圖中的結構上(步驟224)。ILD 90可為介電材料如磷矽酸鹽玻璃(PSG)、硼矽酸鹽玻璃(BSG)、掺雜硼之磷矽酸鹽玻璃(BPSG)、未掺雜之矽酸鹽玻璃(USG)、或類似物，且其沉積方法可為任何合適方法如CVD、PECVD、或FCVD。
如第13A-13C圖所示，可進一步進行平坦化製程如 CMP使ILD 90之上表面與虛置的閘極80之上表面齊平。CMP亦可移除虛置的閘極80上的遮罩82。綜上所述，虛置的閘極80其上表面可自ILD 90露出。
如第13A-13C圖所示，以蝕刻步驟移除虛置閘極80、視情況(非必要)形成之閘極密封間隔物、以及直接位於虛置的閘極80下之虛置的閘極介電物78，以形成凹陷92(步驟232)。凹陷92露出半導體層74之鰭狀物之通道區。通道區位於相鄰之一對磊晶的源極/汲極區88之間。在蝕刻移除虛置的閘極80時，虛置的閘極介電物78可作為蝕刻停止層。在移除虛置的閘極80後，接著可移除虛置的閘極介電物78與閘極密封間隔物84。
在第14A-14C圖中，形成置換閘極之閘極介電物94與閘極96(步驟234)。閘極介電物94順應性地沉積於凹陷92中，比如半導體層74之鰭狀物的上表面與側壁上、閘極密封間隔物84之側壁上(若閘極密封間隔物存在)或ILD 90之側壁上(若閘極密封間隔物不存在)、以及ILD 90之上表面上。在某些實施例中，閘極介電物94可為氧化矽、氮化矽、或上述之多層結構。在其他實施例中，閘極介電物94可為高介電常數介電材料。在這些實施例中，閘極介電物94之介電常數可大於約7.0，其可包含下述金屬之氧化物或矽化物：Hf、Al、Zr、La、Mg、Ba、Ti、Pb、或上述之組合。閘極介電物94的形成方法可為MBD、ALD、PECVD、或類似方法。
接著可沉積閘極96於閘極介電物94上以填入凹陷92的其餘部份。閘極96可為含金屬材料如TiN、TaN、TaC、Co、 Ru、Al、上述之組合、或上述之多層結構。在填入閘極96後，可進行平坦化製程如CMP以移除超出ILD 90上表面的多餘部份閘極介電物94與閘極96。上述步驟保留之閘極96與閘極介電物94形成之FinFET之置換閘極。
在第15與16圖中，形成接點98穿過ILD 90(步驟226)。在第15圖所示之一實施例中，不同接點98連接至每一源極/汲極區88。在第16圖所示之一實施例中，單一接點98接觸FinFET中多個(不一定為全部)源極/汲極區88。形成用於接點98之開口穿過ILD 90。開口之形成方法可為可接受的光微影與蝕刻技術。襯墊如擴散阻障層、黏著層、或類似物，以及導電材料係形成於開口中。襯墊可包含鈦、氮化鈦、鉭、氮化鉭、或類似物。導電材料可為銅、銅合金、銀、金、鎢、鋁、鎳、或類似物。接著可進行平坦化製程如CMP自ILD 90之表面移除多餘的材料。保留於開口中的襯墊與導電材料即接點98。接著可進行回火以形成矽化物於源極/汲極區88與接點98之界面處。接點98物理與電性耦接至源極/汲極區88。
雖然未圖示，但本技術領域中具有通常知識者應理解可在第14A-14C、15、與16圖之結構上進行額外製程步驟。舉例來說，可形成多種金屬間介電物(IMD)與對應之金屬化物於ILD 90上。此外，可形成接點穿過上方之介電層以接觸閘極96。
第18與19圖係某些實施例中，結構的剖視圖。第18與19圖為保留於矽鍺介電區70、半導體層74之鰭狀物、圖案化基板62、與隔離區76中的鍺殘留型態。第18圖對應第6B2圖 中的矽鍺介電區70，而第19圖對應第6B1圖之矽鍺介電區70。雖然第18與19圖為閘極後製之閘極介電物94與閘極96，其鍺殘留區100A、100B、與100C的型態亦存在於第11A-11C圖之閘極優先製程。此外，即使前述圖式省略鍺殘留區100A、100B、與100C以簡化圖式，鍺殘留區100A、100B、與100C仍可存在於前述實施例中轉換成介電物之步驟208開始時。
第18圖包含鍺殘留區100A於半導體層74之鰭狀物與圖案化基板62中、鍺殘留區100B於矽鍺介電區70中、以及鍺殘留區100C於隔離區76中。鍺殘留區100A位於矽鍺介電區70與半導體層74之鰭狀物與圖案化基板62之間的界面。鍺殘留區100B與100C分別位於矽鍺介電區70與隔離區76中並被其包圍。在某些實施例中，鍺殘留區100A中的鍺含量介於約1原子%至約20原子%之間。在某些實施例中，鍺殘留區100B中的鍺含量介於約1原子%至約20原子%之間。在某些實施例中，鍺殘留區100C中的鍺含量介於約1原子%至約20原子%之間。控制鍺殘留區使其具有較低的鍺含量很重要，因為較高的鍺含量會擴散至閘極結構並降低FinFET裝置之效能與可信度。
第19圖包含鍺殘留區100A於半導體層74之鰭狀物與圖案化基板62中，以及鍺殘留區100B於矽鍺介電區70中。在某些實施例中，鍺殘留區100A中的鍺含量介於約1原子%至約20原子%之間。在某些實施例中，鍺殘留區100B中的鍺含量介於約1原子%至約20原子%之間。
第20至22圖係第18與19圖之實施例中，樣品的穿透式電子顯微鏡(TEM)影像。第20與21圖係沿著第1圖中的剖線 B-B之剖視圖，而第22圖係沿著半導體層74之鰭狀物的長度方向之剖視圖。
第20圖顯示圖案化基板62、矽鍺介電區70、半導體層74之鰭狀物、隔離區76、與鍺殘留區100A、100B、與100C。
同樣地，第21與22圖係樣品之TEM影像，其強調鍺殘留濃度之位置。第21與22圖顯示圖案化基板62、矽鍺介電區70、半導體層74之鰭狀物、隔離區76、與鍺殘留區100A、100B、與100C。在第20至22圖中，鍺殘留區屬於100B或100C取決於矽鍺介電區70之型態，見第18與19圖。
第23與24圖係某些實施例中，結構的剖視圖。第23與24圖之實施例與第18至19圖之實施例類似，差別在進行鍺殘留物之清除步驟，以降低/移除矽鍺介電區70中的鍺殘留物。
為保留於矽鍺介電區70、半導體層74之鰭狀物、圖案化基板62、與隔離區76中的鍺殘留型態。在某些實施例中，鍺殘留物之清除步驟進行於第8A與8B圖對應之中間階段，或進行於第13A至13C圖對應之中間階段。在其他實施例中，可在製程的其他階段進行鍺殘留物之清除步驟。
鍺殘留物之清除步驟可包含低壓與高溫的回火製程。在某些實施例中，鍺殘留物之清除步驟的製程壓力介約10-3大氣壓(atm)至約10-7atm之間(如約10-5atm)，且製程溫度介於約700℃至約1100℃之間(如約900℃)。在鍺殘留物之清除步驟後，矽鍺介電區70可實質上不具有鍺殘留物，即第23與24圖中的實施例不具有鍺殘留區100B。如此一來，第23與24圖之實施例僅具有鍺殘留區100A於半導體層74之鰭狀物與圖案化基板 62中。在某些實施例中，鍺殘留區100A中的鍺含量介於約1原子%至約20原子%之間。在一實施例中，鍺殘留區100A中的鍺含量介於約1原子%至約20原子%之間。鍺殘留區100A中的鍺含量小於10原子%。控制鍺殘留區使其具有較低的鍺含量很重要，因為較高的鍺含量會擴散至閘極結構並降低FinFET裝置之效能與可信度。
第25至27圖係第23與24圖之實施例中，樣品的穿透式電子顯微鏡(TEM)影像。第25至27圖係沿著第1圖中的剖線B-B之剖視圖。第25圖顯示圖案化基板62、矽鍺介電區70、半導體層74之鰭狀物、與隔離區76。
同樣地，第26與27圖係樣品之TEM影像，分別強調鍺殘留物與矽濃度之位置。第26與27圖顯示圖案化基板62、矽鍺介電區70、半導體層74的鰭狀物、隔離區76、與鍺殘留區100A。
上述實施例可達某些優點。舉例來說，本揭露係半導體裝置與其形成方法，可提供簡單且低成本的製程以達FinFET中的未掺雜通道以改善裝置。此外，上述簡單且低成本的製程可形成通道於絕緣物上(有時稱作氧化物上通道)。特別的是，上述實施例包含方向性的氧化鰭狀物步驟，可讓鰭狀物的側壁更垂直於基板的主要表面，以增進裝置的效能與控制。此外，本揭露控制通道下絕緣層中的鍺殘餘量。由於鍺殘餘物可擴散至閘極結構並降低FinFET裝置的可信度，控制鍺殘餘物可增加FinFET裝置的可信度。此外，鰭狀物的磊晶部份係磊晶成長的毯覆層，其比磊晶成長於溝槽/凹陷中的半導體結構具 有較少缺陷與較高品質。
本揭露一實施例之方法包括形成鰭狀物於基板上。鰭狀物包括第一結晶半導體材料於基板上，以及第二結晶半導體材料於第一結晶半導體材料上。此方法亦包括使鰭狀物中的至少部份第一結晶半導體材料與第二結晶半導體材料轉換成介電材料，以及移除至少部份介電材料。此方法亦包括形成閘極結構於鰭狀物上，以及形成源極/汲極區於閘極結構之相反兩側上。
本揭露另一實施例之方法包括磊晶成長第一結晶半導體材料於基板上；磊晶成長第二結晶半導體材料於第一結晶半導體材料上；以及圖案化第一結晶半導體材料與第二結晶半導體材料，以形成鰭狀物於基板上。此方法亦包含形成多個隔離區於基板上以圍繞鰭狀物的較下部份，以及氧化鰭狀物中的至少部份第一結晶半導體材料與第二結晶半導體材料，以形成氧化物材料。此方法亦包含移除至少部份氧化物材料；形成閘極結構於鰭狀物與隔離區上；以及形成源極/汲極區於閘極結構之相反兩側上。
本揭露又一實施例之結構包括鰭狀物位於基板上，且鰭狀物包括第一磊晶部份。第一磊晶部份包括第一材料之第一濃縮區。上述結構亦包含多個隔離區位於基板中及鰭狀物的相反兩側上，且鰭狀物之第一磊晶部份自隔離區之間凸起。介電區直接位於第一磊晶部份下，且介電區之材料不同於隔離區之材料。第一材料之第一濃縮區位於第一磊晶部份與介電區之間的界面。閘極結構沿著鰭狀物之側壁且位於鰭狀物之 上表面上，且閘極結構定義通道區於第一磊晶部份中。
上述實施例之特徵有利於本技術領域中具有通常知識者理解本揭露。本技術領域中具有通常知識者應理解可採用本揭露作基礎，設計並變化其他製程與結構以完成上述實施例之相同目的及/或相同優點。本技術領域中具有通常知識者亦應理解，這些等效置換並未脫離本揭露之精神與範疇，並可在未脫離本揭露之精神與範疇的前提下進行改變、替換、或更動。
50‧‧‧基板
62‧‧‧圖案化基板
70‧‧‧矽鍺介電區
74‧‧‧半導體層
94‧‧‧閘極介電物
96‧‧‧閘極
100A、100B‧‧‧鍺殘留區

Claims (10)

  1. 一種鰭狀場效電晶體裝置的形成方法，包括：形成一鰭狀物於一基板上，該鰭狀物包括一第一結晶半導體材料於該基板上，以及一第二結晶半導體材料於該第一結晶半導體材料上；使該鰭狀物中的至少部份該第一結晶半導體材料與該第二結晶半導體材料轉換成一介電材料；移除至少部份該介電材料；形成一閘極結構於該鰭狀物上；以及形成源極/汲極區於該閘極結構之相反兩側上。
  2. 如申請專利範圍第1項所述之鰭狀場效電晶體裝置的形成方法，其中轉換成該介電材料之步驟採用一方向性氧化製程。
  3. 如申請專利範圍第2項所述之鰭狀場效電晶體裝置的形成方法，其中該第二結晶半導體材料轉換成的該介電材料其厚度，自該第二結晶半導體之上表面朝該第二結晶半導體之下表面增加。
  4. 如申請專利範圍第1項所述之鰭狀場效電晶體裝置的形成方法，其中該第一結晶半導體材料為矽，且該第二結晶半導體材料為矽鍺，且該介電材料為氧化矽鍺。
  5. 如申請專利範圍第1項所述之鰭狀場效電晶體裝置的形成方法，其中轉換成該介電材料之步驟形成該第一結晶半導體材料之濃縮區，且至少部份該濃縮區位於該第二結晶半導體材料中。
  6. 如申請專利範圍第1項所述之鰭狀場效電晶體裝置的形成方法，其中該介電材料圍繞該第一結晶半導體材料之至少部份該濃縮區。
  7. 如申請專利範圍第6項所述之鰭狀場效電晶體裝置的形成方法，更包括：進行一低壓回火製程以移除該介電材料圍繞之該第一結晶半導體材料的該濃縮區。
  8. 如申請專利範圍第5項所述之鰭狀場效電晶體裝置的形成方法，其中該第一半導體材料為鍺。
  9. 一種鰭狀場效電晶體裝置的形成方法，包括：磊晶成長一第一結晶半導體材料於一基板上；磊晶成長一第二結晶半導體材料於該第一結晶半導體材料上；圖案化該第一結晶半導體材料與該第二結晶半導體材料，以形成一鰭狀物於該基板上；氧化該鰭狀物中的至少部份該第一結晶半導體材料與該第二結晶半導體材料，以形成一氧化物材料；移除至少部份該氧化物材料；形成多個隔離區於該基板上，以圍繞該鰭狀物的較下部份；形成一閘極結構於該鰭狀物與該些隔離區上；以及形成源極/汲極區於該閘極結構之相反兩側上。
  10. 一種鰭狀場效電晶體裝置，包括：一鰭狀物，位於一基板上，其中該鰭狀物包括一第一磊晶部份，且該第一磊晶部份包括一第一材料之一第一濃縮區； 多個隔離區，位於該基板中及該鰭狀物的相反兩側上，且該鰭狀物之該第一磊晶部份自該些隔離區之間凸起；一介電區，直接位於該第一磊晶部份下，且該介電區之材料不同於該些隔離區之材料，其中該第一材料之該第一濃縮區位於該第一磊晶部份與該介電區之間的界面；以及一閘極結構，沿著該鰭狀物之側壁且位於該鰭狀物之上表面上，且該閘極結構定義一通道區於該第一磊晶部份中。
TW104136965A 2015-04-30 2015-11-10 鰭狀場效電晶體裝置與其形成方法 TWI575612B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US14/700,202 US9461110B1 (en) 2015-04-30 2015-04-30 FETs and methods of forming FETs

Publications (2)

Publication Number Publication Date
TW201639043A TW201639043A (zh) 2016-11-01
TWI575612B true TWI575612B (zh) 2017-03-21

Family

ID=56995241

Family Applications (1)

Application Number Title Priority Date Filing Date
TW104136965A TWI575612B (zh) 2015-04-30 2015-11-10 鰭狀場效電晶體裝置與其形成方法

Country Status (4)

Country Link
US (2) US9461110B1 (zh)
KR (1) KR101795870B1 (zh)
CN (1) CN106098557B (zh)
TW (1) TWI575612B (zh)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9711535B2 (en) * 2015-03-13 2017-07-18 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming FinFET channel
US9449975B1 (en) * 2015-06-15 2016-09-20 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET devices and methods of forming
US9960273B2 (en) * 2015-11-16 2018-05-01 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit structure with substrate isolation and un-doped channel
CN107958935B (zh) * 2016-10-18 2020-11-27 中芯国际集成电路制造(上海)有限公司 鳍式场效应管及其形成方法
CN108511523B (zh) * 2017-02-23 2021-08-06 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
US10522449B2 (en) * 2017-04-10 2019-12-31 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with Si-substrate-free interposer and method forming same
US10424663B2 (en) * 2017-05-23 2019-09-24 International Business Machines Corporation Super long channel device within VFET architecture
US10573745B2 (en) * 2017-05-23 2020-02-25 International Business Machines Corporation Super long channel device within VFET architecture
WO2019005106A1 (en) * 2017-06-30 2019-01-03 Intel Corporation PROHIBITED WIDE BAND CHANNEL TRANSISTOR AND SOURCE / BAND DRAIN PROHIBITED NARROW
KR102532118B1 (ko) 2018-03-20 2023-05-11 삼성전자주식회사 반도체 장치 및 이의 제조 방법
KR20200009474A (ko) * 2018-07-19 2020-01-30 삼성전자주식회사 반도체 소자
US10658224B2 (en) 2018-09-10 2020-05-19 International Business Machines Corporation Method of fin oxidation by flowable oxide fill and steam anneal to mitigate local layout effects
US10685866B2 (en) 2018-09-10 2020-06-16 International Business Machines Corporation Fin isolation to mitigate local layout effects
US10680083B2 (en) * 2018-09-18 2020-06-09 International Business Machines Corporation Oxide isolated fin-type field-effect transistors
US11069812B2 (en) * 2018-09-28 2021-07-20 Taiwan Semiconductor Manufacturing Company, Ltd. Fin field-effect transistor device and method of forming the same
US11189728B2 (en) * 2019-09-05 2021-11-30 Taiwan Semiconductor Manufacturing Co., Ltd. Method of manufacturing a semiconductor device and a semiconductor device
US11069819B2 (en) * 2019-10-30 2021-07-20 Globalfoundries U.S. Inc. Field-effect transistors with channel regions that include a two-dimensional material on a mandrel
CN113013226B (zh) * 2019-12-20 2024-02-06 台湾积体电路制造股份有限公司 半导体器件和形成半导体器件的方法
CN113611743B (zh) 2021-06-11 2022-06-07 联芯集成电路制造(厦门)有限公司 半导体晶体管结构及其制作方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8106459B2 (en) * 2008-05-06 2012-01-31 Taiwan Semiconductor Manufacturing Company, Ltd. FinFETs having dielectric punch-through stoppers
US20120171832A1 (en) * 2010-12-29 2012-07-05 Globalfoundries Singapore Pte. Ltd. Finfet with stressors
TW201312748A (zh) * 2011-09-01 2013-03-16 Taiwan Semiconductor Mfg 半導體裝置、電晶體及其形成方法
US20130075818A1 (en) * 2011-09-23 2013-03-28 Taiwan Semiconductor Manufacturing Company, Ltd. 3D Semiconductor Device and Method of Manufacturing Same
TW201505181A (zh) * 2013-07-29 2015-02-01 Taiwan Semiconductor Mfg Co Ltd 鰭狀場效電晶體裝置與其形成方法
TW201511283A (zh) * 2013-09-04 2015-03-16 Globalfoundries Us Inc 於鰭式場效電晶體半導體設備上形成接觸結構的方法及其所產生的設備

Family Cites Families (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7393733B2 (en) 2004-12-01 2008-07-01 Amberwave Systems Corporation Methods of forming hybrid fin field-effect transistor structures
US7479421B2 (en) * 2005-09-28 2009-01-20 Intel Corporation Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby
US7425740B2 (en) 2005-10-07 2008-09-16 Taiwan Semiconductor Manufacturing Company, Ltd. Method and structure for a 1T-RAM bit cell and macro
US7799592B2 (en) * 2006-09-27 2010-09-21 Taiwan Semiconductor Manufacturing Company, Ltd. Tri-gate field-effect transistors formed by aspect ratio trapping
US8124483B2 (en) * 2007-06-07 2012-02-28 Infineon Technologies Ag Semiconductor devices and methods of manufacture thereof
US20090001415A1 (en) * 2007-06-30 2009-01-01 Nick Lindert Multi-gate transistor with strained body
US7727830B2 (en) * 2007-12-31 2010-06-01 Intel Corporation Fabrication of germanium nanowire transistors
US8048723B2 (en) 2008-12-05 2011-11-01 Taiwan Semiconductor Manufacturing Company, Ltd. Germanium FinFETs having dielectric punch-through stoppers
US8776734B1 (en) 2008-05-19 2014-07-15 Innovative Environmental Solutions, Llc Remedial system: a pollution control device for utilizing and abating volatile organic compounds
US8053299B2 (en) 2009-04-17 2011-11-08 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabrication of a FinFET element
US20110065276A1 (en) * 2009-09-11 2011-03-17 Applied Materials, Inc. Apparatus and Methods for Cyclical Oxidation and Etching
US8101486B2 (en) * 2009-10-07 2012-01-24 Globalfoundries Inc. Methods for forming isolated fin structures on bulk semiconductor material
US8415718B2 (en) 2009-10-30 2013-04-09 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming epi film in substrate trench
US8395195B2 (en) 2010-02-09 2013-03-12 Taiwan Semiconductor Manufacturing Company, Ltd. Bottom-notched SiGe FinFET formation using condensation
US8263446B2 (en) * 2010-09-13 2012-09-11 International Business Machines Corporation Asymmetric FinFET devices
US8618556B2 (en) 2011-06-30 2013-12-31 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET design and method of fabricating same
US8609518B2 (en) 2011-07-22 2013-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Re-growing source/drain regions from un-relaxed silicon layer
US8815712B2 (en) 2011-12-28 2014-08-26 Taiwan Semiconductor Manufacturing Company, Ltd. Method for epitaxial re-growth of semiconductor region
US8742509B2 (en) 2012-03-01 2014-06-03 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and method for FinFETs
US8785285B2 (en) 2012-03-08 2014-07-22 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices and methods of manufacture thereof
US8652932B2 (en) * 2012-04-17 2014-02-18 International Business Machines Corporation Semiconductor devices having fin structures, and methods of forming semiconductor devices having fin structures
US9171929B2 (en) 2012-04-25 2015-10-27 Taiwan Semiconductor Manufacturing Company, Ltd. Strained structure of semiconductor device and method of making the strained structure
US8633516B1 (en) 2012-09-28 2014-01-21 Taiwan Semiconductor Manufacturing Company, Ltd. Source/drain stack stressor for semiconductor device
US8497177B1 (en) 2012-10-04 2013-07-30 Taiwan Semiconductor Manufacturing Company, Ltd. Method of making a FinFET device
US9093530B2 (en) 2012-12-28 2015-07-28 Taiwan Semiconductor Manufacturing Company, Ltd. Fin structure of FinFET
US9214555B2 (en) 2013-03-12 2015-12-15 Taiwan Semiconductor Manufacturing Co., Ltd. Barrier layer for FinFET channels
US8963258B2 (en) 2013-03-13 2015-02-24 Taiwan Semiconductor Manufacturing Company FinFET with bottom SiGe layer in source/drain
US8796666B1 (en) 2013-04-26 2014-08-05 Taiwan Semiconductor Manufacturing Company, Ltd. MOS devices with strain buffer layer and methods of forming the same
US9620642B2 (en) * 2013-12-11 2017-04-11 Globalfoundries Singapore Pte. Ltd. FinFET with isolation
US9660080B2 (en) * 2014-02-28 2017-05-23 Stmicroelectronics, Inc. Multi-layer strained channel FinFET
US9536900B2 (en) * 2014-05-22 2017-01-03 Globalfoundries Inc. Forming fins of different semiconductor materials on the same substrate
KR20160005550A (ko) * 2014-07-07 2016-01-15 삼성전자주식회사 반도체 소자
US9343371B1 (en) * 2015-01-09 2016-05-17 Globalfoundries Inc. Fabricating fin structures with doped middle portions
US9368512B1 (en) * 2015-06-03 2016-06-14 International Business Machines Corporation Double diamond shaped unmerged epitaxy for tall fins in tight pitch

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8106459B2 (en) * 2008-05-06 2012-01-31 Taiwan Semiconductor Manufacturing Company, Ltd. FinFETs having dielectric punch-through stoppers
US20120171832A1 (en) * 2010-12-29 2012-07-05 Globalfoundries Singapore Pte. Ltd. Finfet with stressors
TW201312748A (zh) * 2011-09-01 2013-03-16 Taiwan Semiconductor Mfg 半導體裝置、電晶體及其形成方法
US20130075818A1 (en) * 2011-09-23 2013-03-28 Taiwan Semiconductor Manufacturing Company, Ltd. 3D Semiconductor Device and Method of Manufacturing Same
TW201505181A (zh) * 2013-07-29 2015-02-01 Taiwan Semiconductor Mfg Co Ltd 鰭狀場效電晶體裝置與其形成方法
TW201511283A (zh) * 2013-09-04 2015-03-16 Globalfoundries Us Inc 於鰭式場效電晶體半導體設備上形成接觸結構的方法及其所產生的設備

Also Published As

Publication number Publication date
CN106098557A (zh) 2016-11-09
TW201639043A (zh) 2016-11-01
CN106098557B (zh) 2019-11-05
US9704883B2 (en) 2017-07-11
US9461110B1 (en) 2016-10-04
KR101795870B1 (ko) 2017-11-08
US20160365362A1 (en) 2016-12-15
KR20160129689A (ko) 2016-11-09

Similar Documents

Publication Publication Date Title
TWI575612B (zh) 鰭狀場效電晶體裝置與其形成方法
US20230215935A1 (en) Fets and methods of forming fets
US10163903B2 (en) FETS and methods of forming FETS
CN108231893B (zh) 半导体装置及其制造方法
TWI786077B (zh) 半導體裝置的製造方法及鰭式場效電晶體裝置的製造方法
TW201806155A (zh) 半導體結構及其製造方法
TW201926708A (zh) 半導體裝置
US11164944B2 (en) Method of manufacturing a semiconductor device
US10504796B2 (en) Semiconductor device and method for manufacturing the same
US10164053B1 (en) Semiconductor device and method
TW202127524A (zh) 半導體裝置的製造方法
US20220359730A1 (en) FinFET Structures and Methods of Forming the Same
TWI662602B (zh) 半導體裝置及其形成方法
US11824104B2 (en) Method of gap filling for semiconductor device
CN114121799A (zh) 半导体装置的制造方法
US11557518B2 (en) Gapfill structure and manufacturing methods thereof
KR102548071B1 (ko) 반도체 디바이스 및 방법