WO2019007324A1 - 双空腔结构的制备方法及双空腔结构 - Google Patents

双空腔结构的制备方法及双空腔结构 Download PDF

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WO2019007324A1
WO2019007324A1 PCT/CN2018/094252 CN2018094252W WO2019007324A1 WO 2019007324 A1 WO2019007324 A1 WO 2019007324A1 CN 2018094252 W CN2018094252 W CN 2018094252W WO 2019007324 A1 WO2019007324 A1 WO 2019007324A1
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epitaxial layer
array
cavity
trench
semiconductor substrate
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PCT/CN2018/094252
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English (en)
French (fr)
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代丹
夏长奉
董娟娟
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无锡华润上华科技有限公司
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Priority to US16/628,001 priority Critical patent/US20200216307A1/en
Publication of WO2019007324A1 publication Critical patent/WO2019007324A1/zh

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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/02—Microstructural systems; Auxiliary parts of microstructural devices or systems containing distinct electrical or optical devices of particular relevance for their function, e.g. microelectro-mechanical systems [MEMS]
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00023—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems without movable or flexible elements
    • B81C1/00047—Cavities
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B1/00—Devices without movable or flexible elements, e.g. microcapillary devices
    • B81B1/002—Holes characterised by their shape, in either longitudinal or sectional plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B60—VEHICLES IN GENERAL
    • B60C—VEHICLE TYRES; TYRE INFLATION; TYRE CHANGING; CONNECTING VALVES TO INFLATABLE ELASTIC BODIES IN GENERAL; DEVICES OR ARRANGEMENTS RELATED TO TYRES
    • B60C23/00—Devices for measuring, signalling, controlling, or distributing tyre pressure or temperature, specially adapted for mounting on vehicles; Arrangement of tyre inflating devices on vehicles, e.g. of pumps or of tanks; Tyre cooling arrangements
    • B60C23/02—Signalling devices actuated by tyre pressure
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2201/00—Specific applications of microelectromechanical systems
    • B81B2201/02—Sensors
    • B81B2201/0264—Pressure sensors
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2203/00—Basic microelectromechanical structures
    • B81B2203/03—Static structures
    • B81B2203/0315—Cavities
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2201/00—Manufacture or treatment of microstructural devices or systems
    • B81C2201/01—Manufacture or treatment of microstructural devices or systems in or on a substrate
    • B81C2201/0101—Shaping material; Structuring the bulk substrate or layers on the substrate; Film patterning
    • B81C2201/0118—Processes for the planarization of structures
    • B81C2201/0125—Blanket removal, e.g. polishing
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2201/00—Manufacture or treatment of microstructural devices or systems
    • B81C2201/01—Manufacture or treatment of microstructural devices or systems in or on a substrate
    • B81C2201/0101—Shaping material; Structuring the bulk substrate or layers on the substrate; Film patterning
    • B81C2201/0128—Processes for removing material
    • B81C2201/013—Etching
    • B81C2201/0132—Dry etching, i.e. plasma etching, barrel etching, reactive ion etching [RIE], sputter etching or ion milling
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2201/00—Manufacture or treatment of microstructural devices or systems
    • B81C2201/01—Manufacture or treatment of microstructural devices or systems in or on a substrate
    • B81C2201/0174—Manufacture or treatment of microstructural devices or systems in or on a substrate for making multi-layered devices, film deposition or growing
    • B81C2201/0176—Chemical vapour Deposition
    • B81C2201/0177—Epitaxy, i.e. homo-epitaxy, hetero-epitaxy, GaAs-epitaxy

Definitions

  • the present invention relates to the field of semiconductor technology, and in particular to a method for fabricating a dual cavity structure and a dual cavity structure.
  • Semiconductor devices include a variety of electronic devices that utilize the specific electrical characteristics of semiconductor materials to perform specific functions. For specific functions of different devices, some devices need to fabricate trench structures or cavity structures of various shapes in a semiconductor substrate to meet design requirements, especially in Micro Electro Mechanical Systems (MEMS). Complex trenches and cavities are fabricated on the substrate to form the desired micro-mechanisms and devices.
  • MEMS Micro Electro Mechanical Systems
  • Complex trenches and cavities are fabricated on the substrate to form the desired micro-mechanisms and devices.
  • the epitaxial structure of the cavity fabricated by the epitaxial method may cause a pit problem caused by the cavity sinking when the epitaxial layer is thick, and the pit may cause defects in the subsequent lithography process due to the flatness, and the subsequent process cannot be continued. Craft.
  • a method for preparing a double cavity structure comprising:
  • the first epitaxial layer and the second epitaxial layer are etched to form a straight trench in communication with the first cavity.
  • a first trench array is disposed on the semiconductor substrate, the tops of the first trench array are separated from each other, and the bottom portions are connected to each other to form a first cavity;
  • a first epitaxial layer disposed on the semiconductor substrate to cover the first trench array
  • a second trench array is disposed on the first epitaxial layer, the tops of the second trench array are separated from each other, and the bottoms are connected to each other to form a second cavity;
  • the first epitaxial layer and the second epitaxial layer are provided with straight grooves that communicate with the first cavity.
  • FIG. 1 is a flow chart showing a method of preparing a double cavity structure in one embodiment
  • 2A-2F are schematic cross-sectional views showing a double cavity structure obtained after completion of each step of the manufacturing method of the double cavity structure in one embodiment
  • FIG. 3 is a structural top view of a first epitaxial layer in one embodiment
  • Figure 5 is a partial flow chart showing a method of preparing a double cavity structure in another embodiment
  • Figure 6 is a partial flow diagram of a method of making a dual cavity structure in yet another embodiment.
  • Figure 1 is a flow chart of a method of preparing a dual cavity structure.
  • a method of preparing a dual cavity structure includes the following steps:
  • Step S110 etching on the semiconductor substrate to form a first trench array; the tops of the first trench array are separated, and the bottoms are connected to each other to form a first cavity.
  • the constituent material of the semiconductor substrate 100 may be undoped single crystal silicon, monocrystalline silicon doped with impurities, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), Silicon germanium (S-SiGeOI), silicon germanium (SiGeOI) on insulator, and germanium germanium (GeOI) are laminated on the insulator.
  • the constituent material of the semiconductor substrate 100 is selected from single crystal silicon.
  • the semiconductor substrate 100 is etched to form a first trench array 111.
  • the first trench array 111 includes a plurality of trenches 101, the tops of the plurality of trenches 101 are separated from each other, and the bottoms of the plurality of trenches 101 are interconnected to form a first cavity 103.
  • the semiconductor substrate 100 is etched to form the first trench array 111.
  • the semiconductor substrate 100 is anisotropically etched to form a plurality of discrete trenches 101. See FIG. 2A. After forming the structure shown in FIG. 2A, the bottom of the plurality of trenches 101 is isotropically etched to connect the bottoms of the plurality of trenches 101 to form the first cavity 103. 2B.
  • the semiconductor when the semiconductor is anisotropically etched, plasma etching is used, so that it is easy to form a plurality of trenches 101 having a small aperture, a good verticality, and a relatively large depth.
  • the number, shape (for example, circular or square) of the plurality of grooves 101 and the specific arrangement are not limited, and those skilled in the art can according to the shape and size of the region of the cavity to be formed, the etching conditions, and the like. select.
  • the bottom of the plurality of trenches 101 is isotropically etched by plasma dry etching.
  • the process conditions of the reactive ion etching are controlled, and gases such as SF6 and CF4 are used, and the etching rate in the direction along the array of the trenches 101 is larger than that of the trenches 101, and the lateral etching is performed at a relatively fast rate.
  • the etch is continued until the silicon substrate between the bottoms of the trenches 101 is etched away, and the bottoms of the plurality of trenches 101 are connected to form the first cavity 103.
  • the specific shape and size of the first cavity 103 therein are also not limiting.
  • Step S120 growing a first epitaxial layer on the semiconductor substrate forming the first trench array, so that the first epitaxial layer covers the first trench array.
  • the thickness of the first epitaxial layer 200 ranges from 30 to 60 micrometers. In the embodiment, the thickness of the first epitaxial layer 200 is 30 micrometers. By controlling the rate of epitaxial growth and the time of epitaxial growth, the thickness of the epitaxial layer can be precisely controlled.
  • the surface of the first epitaxial layer 200 generated by this method has almost no defects, and the surface of the first epitaxial layer 200 is relatively flat as shown in FIG. 3, and the maximum recess depth of the step is 0.88 um, and the conventional multi-chip epitaxial device uses an atmospheric pressure epitaxial process. (Chemical solution deposition technology) and other thick layer of epitaxial layer of 30 ⁇ 60um, the surface of the structure is more likely to produce defects, and the steps of 3 ⁇ 5um irregular depression will be formed as shown in Figure 4, the surface is very uneven.
  • the first epitaxial layer 200 by low-pressure growth using a monolithic epitaxial furnace, the problem that the first epitaxial layer 200 is too thick and the step is too large and uneven can be avoided.
  • Step S130 etching on the first epitaxial layer to form a second trench array; the tops of the second trench array are separated, and the bottoms are connected to each other to form a second cavity.
  • the first epitaxial layer 200 is etched to form a second trench array 211.
  • the second trench array 211 includes a plurality of trenches 201, the tops of the plurality of trenches 201 are separated from each other, and the bottoms of the plurality of trenches 201 are connected to each other to form a second cavity 203.
  • the first epitaxial layer 200 is anisotropically etched to form a plurality of separated trenches 201; and the bottoms of the plurality of trenches 201 are isotropically etched to make the plurality of The bottom of the trench 201 is in communication to form the second cavity 203.
  • the first epitaxial layer 200 is anisotropically etched, plasma etching is used, so that it is easy to form a plurality of trenches 201 having a small aperture, good verticality, and relatively large depth.
  • the number, shape (for example, circular or square) of the plurality of grooves 201 and the specific arrangement are not limited, and those skilled in the art can according to the shape and size of the region of the cavity to be formed, the etching conditions, and the like. select.
  • the bottom of the plurality of trenches 201 is isotropically etched by plasma dry etching.
  • the process conditions for controlling the reactive ion etching are etched by using SF6, CF4 or the like, and the etching rate in the direction along the array of the trenches 201 is larger than that of the trench 201, and the rate is faster.
  • the specific shape and size of the second cavity 203 is also not limiting.
  • the formed second trench array 211 has a depth in the range of about 12 micrometers. Since the thickness of the first epitaxial layer 200 ranges from 30 to 60 micrometers, there is a sufficiently large etching space to form the second. The trench array 211 does not damage the first trench array 111 during the formation of the second trench array 211.
  • the spacing between the top of the first trench array 111 and the bottom of the second trench array 211 is greater than or equal to 15 microns. That is, a certain safe distance is maintained between the first trench array 111 and the second trench array 211, and does not affect each other during the etching process.
  • Step S140 growing a second epitaxial layer on the first epitaxial layer forming the second trench array.
  • the thickness of the second epitaxial layer 300 is less than 20 micrometers. In the embodiment, the thickness of the second epitaxial layer 300 is 15 micrometers.
  • Step S150 etching the first epitaxial layer and the second epitaxial layer to form a straight trench communicating with the first cavity.
  • the first epitaxial layer 200 and the second epitaxial layer 300 are etched by plasma anisotropic dry etching to form a straight trench 205 that communicates with the first cavity 103.
  • the number, shape (for example, circular or square) of the straight grooves 205 and the specific arrangement manner are not specifically limited.
  • the corresponding photolithography, ion implantation, and wet process may be performed at a high speed according to the type of the formed semiconductor device. And other process steps. That is, after the formation of the second epitaxial layer 300, a defect-free photolithography etching process of a small line width can be performed before the formation of the straight trenches 205; and the double-cavity structure is stable, after being subjected to a high-speed drying process by a wet process, The surface of the first epitaxial layer 200 or the second epitaxial layer 300 does not break or fall off.
  • the surface of the first epitaxial layer 200 of the double-cavity structure formed by the above method is flat and has almost no defects.
  • a defect-free photolithography etching process with a small line width can be performed;
  • the cavity structure is stable, and after the high-speed drying of the wet process, the surface of the first epitaxial layer 200 or the second epitaxial layer 300 does not break or fall off.
  • TPMS Tire Pressure Monitoring System
  • a mass, and the like can be formed on the surface of the second epitaxial layer 300 of the formed double-cavity structure by providing the straight groove 205 of the first cavity 103.
  • the method before the step of growing the first epitaxial layer on the semiconductor substrate forming the first trench array, the method further includes:
  • Step S112 cleaning the etched semiconductor substrate.
  • the etched semiconductor substrate 100 is cleaned for the purpose of removing contaminating impurities on the surface of the semiconductor substrate 100.
  • the semiconductor substrate 100 is cleaned with an acidic liquid.
  • Step S114 performing a polishing process on the upper surface of the semiconductor substrate.
  • the upper surface of the cleaned semiconductor substrate 100 is subjected to a polishing process, that is, the surface of the semiconductor substrate 100 for forming the first epitaxial layer 200 is subjected to a polishing process.
  • the impurity particles on the surface of the semiconductor substrate 100 can be removed by a polishing process to obtain a flat surface of the semiconductor substrate 100.
  • the method before the step of growing the second epitaxial layer on the first epitaxial layer forming the second trench array, the method further includes:
  • Step S132 cleaning the etched first epitaxial layer.
  • the etched first epitaxial layer 200 is cleaned for the purpose of removing contaminating impurities on the surface of the first epitaxial layer 200.
  • the first epitaxial layer 200 is washed with an acidic liquid.
  • Step S134 performing a polishing process on the upper surface of the first epitaxial layer.
  • the upper surface of the cleaned first epitaxial layer 200 is subjected to a polishing process, that is, the surface of the first epitaxial layer 200 for forming the second epitaxial layer 300 is subjected to a polishing process.
  • the impurity particles on the surface of the first epitaxial layer 200 can be removed by a polishing process to obtain a flat surface of the first epitaxial layer 200.

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Abstract

一种双空腔结构的制备方法及双空腔结构，包括：在半导体衬底（100）上刻蚀，形成第一沟槽阵列（111）；第一沟槽阵列（111）的顶部各自分离，底部相互联通形成第一空腔（103）；在形成第一沟槽阵列（111）的半导体衬底（100）上生长第一外延层（200），使第一外延层（200）覆盖第一沟槽阵列（111）；在第一外延层（200）上刻蚀形成第二沟槽阵列（211）；第二沟槽阵列（211）顶部各自分离，底部相互联通形成第二空腔（203）；在形成第二沟槽阵列（211）的第一外延层（200）上生长第二外延层（300）；刻蚀第一外延层（200）、第二外延层（300），形成与第一空腔（103）联通的直槽（205）。

Description

双空腔结构的制备方法及双空腔结构 技术领域
本发明涉及半导体技术领域，特别是涉及双空腔结构的制备方法及双空腔结构。
背景技术
半导体器件包括各种利用半导体材料特殊电特性来完成特定功能的电子器件。针对不同器件的特定功能，有的器件需要在半导体衬底中制作各种形状的沟槽结构或腔体结构以满足设计要求，特别是在微机电系统(Micro Electro Mechanical Systems，MEMS)中通常需要在衬底上制作结构复杂的沟槽及腔体，以形成所需的微型机构及器件。一般，采用外延方式制作的空腔外延结构，在外延层较厚时，会出现空腔下陷导致的凹坑问题，凹坑会使后续的光刻等工艺因平整度形成缺陷，无法继续进行后续的工艺。
发明内容
基于此，有必要提供一种双空腔结构的制备方法及双空腔结构。
一种双空腔结构的制备方法，包括：
在半导体衬底上刻蚀，形成第一沟槽阵列；所述第一沟槽阵列的顶部各自分离，底部相互联通形成第一空腔；
在形成所述第一沟槽阵列的半导体衬底上生长第一外延层，使所述第一外延层覆盖所述第一沟槽阵列；
在第一外延层上刻蚀，形成第二沟槽阵列；所述第二沟槽阵列顶部各自分离，底部相互联通形成第二空腔；
在形成所述第二沟槽阵列的所述第一外延层上生长第二外延层；以及
刻蚀所述第一外延层、第二外延层，形成与所述第一空腔联通的直槽。
本申请的一个或多个实施例的细节在下面的附图和描述中提出。本申请的其它特征、目的和优点将从说明书、附图以及权利要求书变得明显。
另一方面，还提出一种双空腔结构，包括：
半导体衬底；
第一沟槽阵列，设于所述半导体衬底上，所述第一沟槽阵列的顶部各自分离，底部相互联通形成第一空腔；
第一外延层，设于所述半导体衬底上，覆盖所述第一沟槽阵列；
第二沟槽阵列，设于所述第一外延层上，所述第二沟槽阵列的顶部各自分离，底部相互联通形成第二空腔；
第二外延层，设于所述第一外延层上，覆盖所述第二沟槽阵列；
所述第一外延层和第二外延层开设有联通所述第一空腔的直槽。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他实施例的附图。
图1为一个实施例中双空腔结构的制备方法的流程图；
图2A-2F为一个实施例中双空腔结构的制作方法各步骤完成后所得双空腔结构的剖面示意图；
图3为一个实施例中第一外延层的结构形貌图；
图4为传统的外延层的结构形貌图；
图5为另一个实施例中双空腔结构的制备方法的部分流程图；
图6为再一个实施例中双空腔结构的制备方法的部分流程图。
具体实施方式
为了使本发明的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
如图1所示的为一种双空腔结构的制备方法的流程图。在一个实施例中，双空腔结构的制备方法，包括以下步骤：
步骤S110：在半导体衬底上刻蚀，形成第一沟槽阵列；所述第一沟槽阵列的顶部各自分离，底部相互联通形成第一空腔。
如图2A和图2B所示，半导体衬底100的构成材料可以采用未掺杂的单晶硅、掺杂有杂质的单晶硅、绝缘体上硅(SOI)、绝缘体上层叠硅(SSOI)、绝缘体上层叠锗化硅(S-SiGeOI)、绝缘体上锗化硅(SiGeOI)以及绝缘体上锗(GeOI)等。作为示例，在本实施例中，半导体衬底100的构成材料选用单晶硅。
对半导体衬底100进行刻蚀，形成第一沟槽阵列111。其中，第一沟槽阵列111包括多个沟槽101，其多个沟槽101的顶部各自分离，多个沟槽101的底部相互联通形成第一空腔103。具体地，对半导体衬底100进行刻蚀，形成第一沟槽阵列111，具体包括：对所述半导体衬底100进行各向异性刻蚀，形成多个各自分离的沟槽101，参见图2A；形成图2A所示的结构后，对多个所述沟槽101的底部进行各向同性刻蚀，使多个所述沟槽101的底部联通，形成所述第一空腔103，参见图2B。
其中，对半导体进行各向异性刻蚀时，采用等离子体刻蚀，这样易于形成口径较小的、垂直性好的、深宽比较大的多个沟槽101。多个沟槽101的数量、形状(例如圆形或者方形)及具体排列方式并不是限制性的，本领域技术人员可以根据欲形成的腔体的区域的形状大小、刻蚀的条件等等来选择。
采用等离子体干法刻蚀，对多个所述沟槽101的底部进行各向同性刻蚀。刻蚀的过程中，控制反应离子刻蚀的工艺条件，采用SF6、CF4等气体，其在沿沟槽101阵列排布的方向的刻蚀速率大于沟槽101延伸，会以较快速率横向刻蚀，直至沟槽101底部之间的硅衬底被刻蚀掉，使多个所述沟槽101 的底部联通，形成所述第一空腔103。其中第一空腔103的具体形状以及尺寸也不是限制性的。
步骤S120：在形成所述第一沟槽阵列的半导体衬底上生长第一外延层，使所述第一外延层覆盖所述第一沟槽阵列。
如图2C所示，在一个实施例中，采用单片式外延炉低压生长形成第一外延层200，其工艺参考范围可以设置为压力范围为30～80托，其中，1托(Torr)＝133.322帕(Pa)；温度范围为1100度～1200度，生长速率约1～2um/min。其中，第一外延层200的厚度范围为30～60微米，在本实施例中，其第一外延层200的厚度为30微米。通过控制外延生长的速率以及外延生长的时间，可以精确地控制外延层的厚度。通过此方法生成的第一外延层200的表面几乎无缺陷，同时第一外延层200表面较平整如图3，台阶最大凹陷深度为0.88um，而常规的多片式外延设备使用常压外延工艺(化学溶液沉积技术)等生长一层30～60um的厚外延层，结构表面较容易产生缺陷，同时会形成3～5um不规则凹陷的台阶如图4，表面非常不平整。采用采用单片式外延炉低压生长形成第一外延层200就可以避免第一外延层200太厚导致的台阶过大不平整的问题。
步骤S130：在第一外延层上刻蚀，形成第二沟槽阵列；所述第二沟槽阵列的顶部各自分离，底部相互联通形成第二空腔。
如图2D所示，对第一外延层200进行刻蚀，形成第二沟槽阵列211。其中，第二沟槽阵列211包括多个沟槽201，其多个沟槽201的顶部各自分离，多个沟槽201的底部相互联通形成第二空腔203。具体包括：对所述第一外延层200进行各向异性刻蚀，形成多个各自分离的沟槽201；对多个所述沟槽201的底部进行各向同性刻蚀，使多个所述沟槽201的底部联通，形成所述第二空腔203。
其中，对第一外延层200进行各向异性刻蚀时，采用等离子体刻蚀，这样易于形成口径较小的、垂直性好的、深宽比较大的多个沟槽201。多个沟槽201的数量、形状(例如圆形或者方形)及具体排列方式并不是限制性的， 本领域技术人员可以根据欲形成的腔体的区域的形状大小、刻蚀的条件等等来选择。
采用等离子体干法刻蚀，对多个所述沟槽201的底部进行各向同性刻蚀。刻蚀的过程中，控制反应离子刻蚀的工艺条件，采用SF6、CF4等气体刻蚀，其在沿沟槽201阵列排布的方向的刻蚀速率大于沟槽201延伸，会以较快速率横向刻蚀，直至沟槽201底部之间的硅衬底被刻蚀掉，使多个所述沟槽201的底部联通，形成所述第二空腔203。其中第二空腔203的具体形状以及尺寸也不是限制性的。
在一个实施例中，形成的第二沟槽阵列211的深度范围在12微米左右，由于第一外延层200的厚度范围在30～60微米之间，有足够大的刻蚀空间来形成第二沟槽阵列211，在形成第二沟槽阵列211的过程中不会破坏第一沟槽阵列111。
在一个实施例中，所述第一沟槽阵列111的顶部与所述第二沟槽阵列211的底部之间的间距大于等于15微米。也即，第一沟槽阵列111与第二沟槽阵列211之间保持一定的安全距离，在刻蚀的过程中，互不影响。
步骤S140：在形成所述第二沟槽阵列的所述第一外延层上生长第二外延层。
如图2E所示，在一个实施例中，采用单片式外延炉低压生长形成第二外延层300，其工艺参考范围可以设置为：压力范围为30～80托，其中，1托(Torr)＝133.322帕(Pa)；温度范围为1100度～1200度，生长速率约1～2um/min。其中，第二外延层300的厚度范围小于20微米，在本实施例中，其第二外延层300的厚度为15微米。通过控制外延生长的速率以及外延生长的时间，可以精确地控制外延层的厚度。
步骤S150：刻蚀所述第一外延层、第二外延层，形成与所述第一空腔联通的直槽。
如图2F所示，采用等离子体各向异性干法刻蚀对第一外延层200、第二外延层300刻蚀，形成与所述第一空腔103联通的直槽205。其中，直槽205 的数量、形状(例如圆形或者方形)及具体排列方式不作具体限定。
在一个实施例中，在形成联通所述第一空腔103的直槽205的步骤之前，还可以根据形成的半导体器件的类型，进行相应的光刻、离子注入、湿法工艺的高速甩干等工艺步骤。也即，在形成第二外延层300之后，在形成直槽205之前可以进行小线宽的无缺陷的光刻刻蚀工艺；而且双空腔结构稳固，经历湿法工艺的高速甩干后，第一外延层200或第二外延层300表面不会出现断裂或脱落现象。
通过上述方法形成的双空腔结构的第一外延层200的表面平整，几乎无缺陷，在形成第二外延层300后，还可以进行小线宽的无缺陷的光刻刻蚀工艺；而且双空腔结构稳固，经历湿法工艺的高速甩干后，第一外延层200或第二外延层300表面不会出现断裂或脱落现象。同时，通过设置联通第一空腔103的直槽205可以在形成的双空腔结构的第二外延层300表面形成轮胎压力监测结构(Tire Pressure Monitoring System，TPMS)、质量块等。
如图5所示，在一个实施例中，所述在形成所述第一沟槽阵列的半导体衬底上生长第一外延层的步骤之前，还包括：
步骤S112：清洗刻蚀后的所述半导体衬底。
清洗刻蚀后的所述半导体衬底100，其目的是清除半导体衬底100表面的污染杂质。在本实施例中，采用酸性液体清洗半导体衬底100。
步骤S114：对所述半导体衬底的上表面进行抛光处理。
对清洗后的半导体衬底100的上表面进行抛光处理，也就是，对用于形成第一外延层200的半导体衬底100表面进行抛光处理。通过抛光处理可以去除半导体衬底100表面的杂质颗粒，得到平整的半导体衬底100表面。
如图6所示，在一个实施例中，所述在形成所述第二沟槽阵列的所述第一外延层上生长第二外延层的步骤之前，还包括：
步骤S132：清洗刻蚀后的所述第一外延层。
清洗刻蚀后的所述第一外延层200，其目的是清除第一外延层200表面的污染杂质。在本实施例中，采用酸性液体清洗第一外延层200。
步骤S134：对所述第一外延层的上表面进行抛光处理。
对清洗后的第一外延层200的上表面进行抛光处理，也就是，对用于形成第二外延层300的第一外延层200表面进行抛光处理。通过抛光处理可以去除第一外延层200表面的杂质颗粒，得到平整的第一外延层200表面。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (16)

  1. 一种双空腔结构的制备方法，包括：
    在半导体衬底上刻蚀，形成第一沟槽阵列；所述第一沟槽阵列的顶部各自分离，底部相互联通形成第一空腔；
    在形成所述第一沟槽阵列的半导体衬底上生长第一外延层，使所述第一外延层覆盖所述第一沟槽阵列；
    在所述第一外延层上刻蚀，形成第二沟槽阵列；所述第二沟槽阵列的顶部各自分离，底部相互联通形成第二空腔；
    在形成所述第二沟槽阵列的所述第一外延层上生长第二外延层；以及
    刻蚀所述第一外延层、第二外延层，形成与所述第一空腔联通的直槽。
  2. 根据权利要求1所述的方法，其特征在于，所述在形成所述第一沟槽阵列的半导体衬底上生长第一外延层的步骤之前，还包括：
    清洗刻蚀后的所述半导体衬底；
    对所述半导体衬底的上表面进行抛光处理。
  3. 根据权利要求1所述的方法，其特征在于，所述在半导体衬底上刻蚀，形成第一沟槽阵列的步骤包括：
    对所述半导体衬底进行各向异性刻蚀，形成多个各自分离的沟槽；
    对多个所述沟槽的底部进行各向同性刻蚀，使多个所述沟槽的底部联通，形成所述第一空腔。
  4. 根据权利要求1所述的方法，其特征在于，所述在形成所述第二沟槽阵列的所述第一外延层上生长第二外延层的步骤之前，还包括：
    清洗刻蚀后的所述第一外延层；
    对所述第一外延层的上表面进行抛光处理。
  5. 根据权利要求1所述的方法，其特征在于，所述刻蚀所述第一外延层、第二外延层，形成与所述第一空腔联通的直槽的步骤包括：
    对所述第一外延层、第二外延层进行各向异性刻蚀，形成与所述第一空 腔联通的直槽。
  6. 根据权利要求1所述的方法，其特征在于，所述第一外延层的厚度范围为30～60微米。
  7. 根据权利要求1所述的方法，其特征在于，所述第二外延层的厚度小于20微米。
  8. 根据权利要求1所述的方法，其特征在于，所述第一沟槽阵列的顶部与所述第二沟槽阵列的底部之间的间距大于等于15微米。
  9. 根据权利要求1所述的方法，其特征在于，所述第一外延层、第二外延层均是采用单片式外延炉低压生长而成。
  10. 根据权利要求9所述的方法，其特征在于，所述低压生长的工艺参数范围包括：压力范围为30～80托；温度范围为1100℃～1200℃。
  11. 一种双空腔结构，包括：
    半导体衬底；
    第一沟槽阵列，设于所述半导体衬底上，所述第一沟槽阵列的顶部各自分离，底部相互联通形成第一空腔；
    第一外延层，设于所述半导体衬底上，覆盖所述第一沟槽阵列；
    第二沟槽阵列，设于所述第一外延层上，所述第二沟槽阵列的顶部各自分离，底部相互联通形成第二空腔；
    第二外延层，设于所述第一外延层上，覆盖所述第二沟槽阵列；
    所述第一外延层和第二外延层开设有联通所述第一空腔的直槽。
  12. 根据权利要求11所述的双空腔结构，其特征在于，第一外延层的厚度范围为30～60微米。
  13. 根据权利要求11所述的双空腔结构，其特征在于，所述第二外延层的厚度小于20微米。
  14. 根据权利要求11所述的双空腔结构，其特征在于，所述第一沟槽阵列的顶部与所述第二沟槽阵列的底部之间的间距大于等于15微米。
  15. 根据权利要求11所述的双空腔结构，其特征在于，所述第一外延层、 第二外延层均是采用单片式外延炉低压生长而成。
  16. 根据权利要求15所述的双空腔结构，其特征在于，所述低压生长的工艺参数范围包括：压力范围为30～80托；温度范围为1100℃～1200℃。
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