TWI585858B - 在非平坦矽表面上之應力鬆弛緩衝層 - Google Patents

在非平坦矽表面上之應力鬆弛緩衝層 Download PDF

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TWI585858B
TWI585858B TW105106271A TW105106271A TWI585858B TW I585858 B TWI585858 B TW I585858B TW 105106271 A TW105106271 A TW 105106271A TW 105106271 A TW105106271 A TW 105106271A TW I585858 B TWI585858 B TW I585858B
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low temperature
seed layer
germanium
stress relaxation
buffer layer
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巴特羅梅 詹 帕拉克
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格羅方德半導體公司
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Description

在非平坦矽表面上之應力鬆弛緩衝層
本發明揭露係關於半導體裝置之製造。尤其，本發明揭露係關於使用於在14奈米、10奈米、7奈米、5奈米及3奈米技術節點中製造半導體裝置之應力鬆弛緩衝(SRB,Stress Relaxed Buffer)層。
使用矽(Si,Silicon)晶圓時，具有不同的晶格常數及熱膨脹係數之不同的半導體材料之磊晶生長會造成缺陷的產生，諸如產生差排(dislocation)缺陷而接著導致不良的電晶體效能及可靠度問題。具有應力鬆弛緩衝層之基板，包含階梯式(stepped)或漸變式(graded)的砷化鎵(GaAs,Gallium Arsenide)或矽鍺(SiGe,Silicon Germanium)，是有用於達到應力鬆弛。然而，該應力鬆弛層是厚的(例如，2微米至2.5微米之間的範圍)並且因此昂貴。再者，若使用中間的化學機械研磨(CMP,Chemical Mechanical Polishing)步驟以平坦化該層及光滑化表面粗度，則在下一道磊晶步驟之前將會有氧化物殘留物殘留在頂端之風險。介電質殘留物將接著降低該頂部磊晶層之品質。
因此，存在著用於能夠鋪設薄的應力鬆弛緩衝層之方法及其裝置的需求，該應力鬆弛緩衝層達到完全的應力鬆弛並將缺陷局部地侷限在非平坦矽表面上之溝槽底部處。
本發明揭露之一態樣包含使矽晶圓之上表面非平坦化或開槽化、磊晶生長低溫晶種層於該非平坦或開槽化的矽晶圓之表面、以及沉積(磊晶生長)應力鬆弛緩衝層於該晶種層上方。缺陷可以被局部地限制或捕捉在非平坦矽表面上之10奈米的晶種磊晶厚度內。
本發明揭露之另一態樣為一種裝置，包含矽晶圓之非平坦上表面、於該矽晶圓之該非平坦表面上磊晶生長的低溫晶種層、以及在該晶種層上方之應力鬆弛緩衝層。
本發明揭露之另一態樣包含在‘V型凹槽’凹陷的溝槽內提供<111>表面並且生長低溫薄的磊晶晶種層造成有效的缺陷限制及充分的晶格參數鬆弛。後續的應力鬆弛緩衝層為充分無缺陷並且很薄，從而在磊晶生長通道材料之前提供良好品質的磊晶。<111>表面係藉由使晶圓非平坦化或開槽化而建立。
本發明揭露之額外態樣及其它特徵將於下列描述中提出，並且其中一部分對於該技術領域中具有通常知識者而言在檢視下文後將會是顯而易見的，或者可在實施該發明揭露後而得以認識本發明。可如同在所附加的 專利申請範圍中特別提出者而實現及獲得本發明揭露之優點。
依據本發明揭露，可藉由一種方法而部分達到某些技術功效，該方法包含：形成非平坦表面或V型凹槽表面於矽晶圓之上表面中；磊晶生長低溫晶種層於該矽晶圓之該非平坦表面上；沉積應力鬆弛緩衝層於該低溫晶種層上方；以及平坦化該應力鬆弛緩衝層之上表面。
本發明揭露之態樣包含使用化學機械研磨平坦化應力鬆弛緩衝層之上表面。其它態樣包含磊晶生長低溫晶種層於矽晶圓之非平坦表面之溝槽中。另一個態樣包含磊晶生長該低溫晶種層至10奈米至40奈米之厚度。額外態樣包含具有小於200奈米之深度之錐體。其它態樣包含低溫晶種層，其包含鍺(Ge)、磷化銦(InP)或砷化鎵(GaAs)。又一個態樣包含於低溫晶種層上方以200奈米至300奈米之厚度磊晶生長應力鬆弛緩衝層，其中該應力鬆弛緩衝層包含矽鍺(SiGe)、砷化銦鎵(InGaAs)或磷砷化鎵銦(GaxIn1-xAsyP1-y)。額外態樣包含形成該非平坦表面於該矽晶圓之上表面上，包含藉由蝕刻形成錐體於該矽晶圓之上表面中，其中該錐體具有低於200奈米之高度。另一個態樣包含具有矽<111>表面之錐體。額外態樣包含在晶圓之頂部上之平行的V型凹槽。
本發明揭露之另一態樣係一種方法，包含：形成非平坦表面於矽晶圓之上表面中，其中該非平坦表面包含矽<111>表面；磊晶生長低溫晶種層於該矽晶圓 之非平坦表面上，該低溫晶種層包含鍺、磷化銦或砷化鎵；於該低溫晶種層上方以200奈米至300奈米之厚度磊晶生長應力鬆弛緩衝層，其中該應力鬆弛緩衝層包含矽鍺(SiGe)、砷化銦鎵(InGaAs)或磷砷化鎵銦(GaxIn1-xAsyP1-y)；以及平坦化該應力鬆弛緩衝層之上表面。
本發明之態樣包含磊晶生長低溫晶種層至10奈米至40奈米之厚度。另一態樣包含使用化學機械研磨平坦化應力鬆弛緩衝層之上表面。額外態樣包含藉由形成錐體或V型凹槽於矽晶圓之上表面中而形成非平坦表面於該矽晶圓之上表面上。
本發明揭露之另一態樣為一種裝置，包含：具有非平坦上表面之矽晶圓；沉積在該矽晶圓之非平坦表面上之磊晶生長的低溫晶種層；以及沉積在該低溫晶種層上方之應力鬆弛緩衝層。本發明之態樣包含具有10奈米至40奈米之厚度之磊晶生長的低溫晶種層。又一態樣包含矽晶圓之非平坦表面，該矽晶圓包含具有矽<111>表面之錐體或具有矽<111>表面之V型凹槽。其它態樣包含低溫晶種層，其含有鍺、磷化銦或砷化鎵。額外態樣包含應力鬆弛緩衝層，其包含矽鍺(SiGe)、砷化銦鎵(InGaAs)或磷砷化鎵銦(GaxIn1-xAsyP1-y)。
本發明揭露之額外態樣及技術功效對該技術領域中具有通常知識者而言，藉由下文的實施方式將立即變得顯而易見，其中本發明揭露之實施例僅藉由用以實施本發明所考量之最佳模式而做說明。將可以瞭解的是， 本發明揭露能夠適用於其它及不同的實施例，並且其數項細節能夠以各種顯而易見的態樣而做修正，所有修正不違背本發明揭露。因此，圖式及說明在本質上應視為例示性，而非限制性。
101‧‧‧矽晶圓
103‧‧‧上表面
201‧‧‧錐體形狀
203‧‧‧尖峰
205‧‧‧溝槽
301‧‧‧V型凹槽
401‧‧‧低溫晶種層
501‧‧‧應力鬆弛緩衝層
503‧‧‧上表面
本發明揭露係以例示性而非限制性的方式藉由隨附圖式中之範例做說明，其中相同的元件符號意指類似的元件，並且其中：第1、2A、4及5圖係依據例示實施例概要性說明用以在非平坦矽晶圓上產生應力鬆弛緩衝層的製程流程之橫截面視圖。
第2B圖為非平坦矽晶圓表面之掃描式電子顯微鏡影像。
第2C圖為形成於矽晶圓表面中之錐體形狀之圖式。
第3圖為具有V型凹槽的溝槽所形成之矽晶圓表面之透視圖式。
在下列敘述中，為了說明之目的，係提出許多特定的細節以提供對例示性實施例的完整瞭解。然而，例示性實施例顯然也可以在不具有這些特定細節或具有等同的配置下而實施。在其它例子中，眾所周知的結構及裝置以方塊圖形式而顯示以避免非必要地混淆例示性實施例。此外，除非另外指示，所有使用於本說明書及申請 專利範圍中之數字表示的數量、比例及組成成分之數值化性質、反應條件及等等，應理解為藉由術語"大約(about)"而在所有例子中做修飾。
本發明揭露係解決當在矽晶圓上生長半導體材料(諸如應力鬆弛緩衝層)時產生差排缺陷之當前問題。
依據本發明揭露之實施例的方法包含：在矽晶圓之上表面中形成非平坦的或開槽的表面；磊晶生長低溫晶種層於該矽晶圓之該非平坦表面上；沉積應力鬆弛緩衝層於該低溫晶種層上方；以及平坦化該應力鬆弛緩衝層之上表面。
本發明之其它目的、特徵及技術功效對於熟習該項技藝之人士而言，藉由下文的詳細說明將立即變得顯而易見，其中僅藉由最佳模式所考量之說明而顯示及描述較佳實施例。本發明揭露能夠做其它及不同的實施例，並且其中幾個細節能夠以各種明顯方面做修正。因此，圖式及實施方式在性質上應視為例示性而非限制性。
留意第1圖，其係以橫截面圖說明具有光滑上表面103之矽晶圓101之例子。該矽晶圓可以具有從25.4毫米至450毫米之各種直徑並且可由結晶矽形成。該矽晶圓做為內建在晶圓內和建立在晶圓上方之微電子裝置所使用的基板，並且經歷許多微製造製程步驟，諸如各種材料之摻雜或離子佈植、蝕刻、沉積以及光學微影圖案化。
留意第2A圖，該矽晶圓101被非平坦化以形成複數個錐體形狀201於該矽晶圓之上表面103上。該 錐體形狀201具有尖峰203及溝槽205。每一個錐體形狀201從其尖峰203至溝槽205之底部的高度是在100奈米至200奈米之間。該矽晶圓101之非平坦表面是藉由蝕刻製程形成在該矽晶圓101之一側上，該蝕刻製程包含乾式或濕式蝕刻製程或濕式/乾式製程之組合以形成該錐體形狀201。可以使用諸如以六氟化硫為基礎的乾式蝕刻之乾式蝕刻製程而在該矽晶圓101之表面上產生不規則性。矽晶圓101之整個上表面可以經由蝕刻以提供高度範圍在100奈米至200奈米之間的微細的錐體形狀201。該錐體201具有矽<111>表面。濕式蝕刻製程亦可被用來形成高度小於200奈米之錐體形狀201。四甲基氫氧化銨(TMAH,TetraMethylAmmonium Hydroxide)、氫氧化鉀(KOH,Potassium Hydroxide)或氫氧化鈉(NaOH,Sodium Hydroxide)之水溶液可被用來作為濕式蝕刻溶液。
在第2B圖中，該圖為顯示有複數個錐體形狀201之非平坦矽晶圓101的掃描式電子顯微鏡影像。在第2C圖中，該圖為表示在第2B圖之影像中隨機形成的錐體201之一部分的圖式。
該矽晶圓101上所形成之錐體形狀201的另一種選擇是，對該矽晶圓101進行遮罩及方向選擇性的V型凹槽蝕刻。經過此加工處理後，會橫跨該矽晶圓101形成長且平行的V型凹槽301，如第3圖所示。
留意第4圖，磊晶生長低溫晶種層401係形成在該矽晶圓101之非平坦表面上。尤其，該低溫晶種層 401係形成在該錐體形狀201上方，使得該尖峰203及溝槽205被該磊晶生長低溫晶種層401覆蓋。該低溫晶種層401係生長至10奈米至40奈米之厚度，例如20奈米。該低溫晶種層典型包含鍺、磷化銦或砷化鎵。該晶種層401磊晶生長的溫度範圍在400℃及700℃之間。可以使用化學氣相沉積(CVD,Chemical Vapor Deposition)或分子束磊晶(MBE,Molecular Beam Epitaxy)製程來磊晶生長該晶種層401。
留意第5圖，應力鬆弛緩衝層501係沉積在該低溫晶種層401上方。應力鬆弛緩衝層501之上表面503顯示為平坦的。可以利用化學機械研磨執行平坦化。該應力鬆弛緩衝層501為形成在該低溫晶種層401上方達到200奈米至500奈米之厚度。該應力鬆弛緩衝層501包含高移動率通道材料，該高移動率通道材料包含鍺(Ge)、矽鍺(SixGe1-x)、砷化銦鎵(InGaAs)或磷砷化鎵銦(GaxIn1-xAsyP1-y)。在該應力鬆弛層501之平坦化後，該矽晶圓101可以進行進一步的加工，例如加入通道。該錐體201可以藉由横截面穿透式電子顯微鏡(X-TEM,Cross-Sectional Transmission Electron Microscopy)而進行偵測。
本發明揭露之實施例可以達到數種技術功效，例如完全鬆弛的應力鬆弛緩衝層之快速形成。本發明揭露允許應力鬆弛緩衝層以低成本製程形成。
依據本發明揭露之實施例所形成之裝置在例如微處理器、智慧型手機、行動裝置、移動手持裝置、 數位視訊轉換盒、數位多功能影音光碟燒錄器及播放器、汽車導航、印表機及週邊、網路及電路設備、遊戲機系統、數位相機之各種工業應用上享有實用性。因此，本發明揭露在使用具有薄的應力鬆弛緩衝層之矽晶圓的任何各種類型之高度整合半導體裝置之製造上享有工業可利用性，可達到完全的應力鬆弛並將缺陷局部地限制在非平坦矽表面上之溝槽的底部處。本發明揭露特別適用於14奈米以上的技術節點。
在先前的描述中，本發明揭露係參考本發明之特定例示性實施例做描述。然而，顯然可在不脫離本發明揭露之較廣義的精神及範疇的情況下做出各種修改及變化，如申請專利範圍中所提出者。說明書及圖式因此應視為例示性而非限制性。應了解到，本發明揭露能夠使用各種其它組合及實施例，並且能在本文所表述之發明概念之範疇內做任何變化或修改。
101‧‧‧矽晶圓
201‧‧‧錐體形狀
401‧‧‧低溫晶種層
501‧‧‧應力鬆弛緩衝層
503‧‧‧上表面

Claims (20)

  1. 一種用於製造半導體裝置的方法，該方法包括：於矽(Si)晶圓之上表面中形成非平坦表面或V型凹槽表面；在該矽晶圓之該非平坦表面上磊晶生長低溫晶種層；沉積應力鬆弛緩衝(SRB)層於該低溫晶種層上方；以及平坦化該應力鬆弛緩衝層之上表面。
  2. 如申請專利範圍第1項所述之方法，還包括：以化學機械研磨(CMP)平坦化該應力鬆弛緩衝層之該上表面。
  3. 如申請專利範圍第1項所述之方法，還包括：磊晶生長該低溫晶種層於該矽晶圓之該非平坦表面或該V型凹槽表面的溝槽中。
  4. 如申請專利範圍第3項所述之方法，還包括：磊晶生長該低溫晶種層至10奈米至40奈米之厚度。
  5. 如申請專利範圍第3項所述之方法，其中，該錐體具有低於200奈米之深度。
  6. 如申請專利範圍第1項所述之方法，其中，該低溫晶種層包括鍺(Ge)、磷化銦(InP)或砷化鎵(GaAs)。
  7. 如申請專利範圍第1項所述之方法，還包括：於該低溫晶種層上方以200至500奈米之厚度磊晶 生長該應力鬆弛緩衝層，其中該應力鬆弛緩衝層包含矽鍺(SixGe1-x)、砷化銦鎵(InGaAs)或磷砷化鎵銦(GaxIn1-xAsyP1-y)。
  8. 如申請專利範圍第1項所述之方法，其中，形成該非平坦表面或V型凹槽表面於該矽晶圓之該上表面上之步驟包含：藉由蝕刻形成錐體於該矽晶圓之該上表面中，其中該錐體具有小於300奈米之高度。
  9. 如申請專利範圍第8項所述之方法，其中，該錐體具有矽<111>表面。
  10. 如申請專利範圍第1項所述之方法，其中，形成該非平坦表面或V型凹槽表面於該矽晶圓之該上表面上之步驟包含：形成平行的V型凹槽於該矽晶圓之該上表面中。
  11. 如申請專利範圍第1項所述之方法，其中，上下顛倒的錐體具有矽<111>表面。
  12. 一種用於製造半導體裝置的方法，該方法包括：形成非平坦表面於矽晶圓之上表面中，其中該非平坦表面包含矽<111>表面；磊晶生長低溫晶種層於該矽晶圓之該非平坦表面上，該低溫晶種層包括鍺、磷化銦或砷化鎵；於該低溫晶種層上方以200奈米至300奈米之厚度磊晶生長應力鬆弛緩衝層，其中該應力鬆弛緩衝層包括矽鍺(SiGe)、砷化銦鎵(InGaAs)或磷砷化鎵銦 (GaxIn1-xAsyP1-y)；以及平坦化該應力鬆弛緩衝層之上表面。
  13. 如申請專利範圍第12項所述之方法，還包括：磊晶生長該低溫晶種層至10奈米至40奈米之厚度。
  14. 如申請專利範圍第12項之方法，還包括：使用化學機械研磨平坦化該應力鬆弛緩衝層之該上表面。
  15. 如申請專利範圍第12項之方法，其中，形成該非平坦表面於該矽晶圓之該上表面上之步驟包含：形成錐體或平行的V型凹槽於該矽晶圓之該上表面中。
  16. 一種半導體裝置，包括：包含非平坦上表面之矽(Si)晶圓；沉積在該矽晶圓之該非平坦表面上之磊晶生長的低溫晶種層；以及沉積在該低溫晶種層上方之應力鬆弛緩衝(SRB)層。
  17. 如申請專利範圍第16項所述之半導體裝置，其中，所磊晶生長的該低溫晶種層具有10奈米至40奈米之厚度。
  18. 如申請專利範圍第16項所述之半導體裝置，其中，該矽晶圓之該非平坦表面包含：具有矽<111>表面之錐體，或者 具有矽<111>表面之平行的V型凹槽。
  19. 如申請專利範圍第16項所述之半導體裝置，其中，該低溫晶種層包括鍺、磷化銦或砷化鎵。
  20. 如申請專利範圍第19項所述之半導體裝置，其中，該應力鬆弛緩衝層包括矽鍺(SiGe)、砷化銦鎵(InxGa1-xAs)或磷砷化鎵銦(GaxIn1-xAsyP1-y)。
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