CN110854014A - 在非平坦硅表面上的应力松弛缓冲层 - Google Patents

在非平坦硅表面上的应力松弛缓冲层 Download PDF

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CN110854014A
CN110854014A CN201911154213.9A CN201911154213A CN110854014A CN 110854014 A CN110854014 A CN 110854014A CN 201911154213 A CN201911154213 A CN 201911154213A CN 110854014 A CN110854014 A CN 110854014A
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stress relaxation
low temperature
relaxation buffer
seed layer
buffer layer
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B·J·帕夫拉克
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GlobalFoundries US Inc
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Abstract

本发明涉及在非平坦硅表面上的应力松弛缓冲层，具体提供一种形成应力松弛缓冲(SRB,Stress Relaxed Buffer)层于非平坦的或开槽的硅(Si)表面上的方法及其装置。实施例包含形成非平坦表面于硅晶圆的上表面中；外延生长低温晶种层于该硅晶圆的该非平坦表面上；沉积应力松弛缓冲层于该低温晶种层上方；以及平坦化该应力松弛缓冲层的上表面。

Description

在非平坦硅表面上的应力松弛缓冲层
本申请是申请号为201610511090.X、申请日为2016年6月30日、发明名称为“在非平坦硅表面上的应力松弛缓冲层”的中国专利申请的分案申请。
技术领域
本发明揭示关于半导体装置的制造。尤其，本发明揭示关于使用于在14纳米、10纳米、7纳米、5纳米及3纳米技术节点中制造半导体装置的应力松弛缓冲(SRB,StressRelaxed Buffer)层。
背景技术
使用硅(Si,Silicon)晶圆时，具有不同的晶格常数(lattice constant)及热膨胀系数(thermal coefficient)的不同半导体材料的外延生长会造成缺陷的产生，诸如产生差排(dislocation)缺陷而接着导致不良的晶体管效能及可靠度问题。具有应力松弛缓冲层的基板，包含阶梯式(stepped)或渐变式(graded)的砷化镓(GaAs,Gallium Arsenide)或硅锗(SiGe,Silicon Germanium)，是有用于达到应力松弛。然而，该应力松弛层是厚的(例如，2微米至2.5微米之间的范围)并且因此昂贵。再者，若使用中间的化学机械研磨(CMP,Chemical Mechanical Polishing)步骤以平坦化该层及光滑化表面粗度，则在下一道外延步骤之前将会有氧化物残留物残留在顶端的风险。介电质残留物将接着降低该顶部磊晶层的品质。
因此，存在着用于能够铺设薄的应力松弛缓冲层的方法及其装置的需求，该应力松弛缓冲层达到完全的应力松弛并将缺陷局部地局限在非平坦硅表面上的沟槽底部处。
发明内容
本发明揭示的一面向包含使硅晶圆的上表面非平坦化或开槽化、外延生长低温晶种层于该非平坦或开槽化的硅晶圆的表面、以及沉积(外延生长)应力松弛缓冲层于该晶种层上方。缺陷可以被局部地限制或捕捉在非平坦硅表面上的10纳米的晶种外延厚度内。
本发明揭示的另一面向为一种装置，包含硅晶圆的非平坦上表面、于该硅晶圆的该非平坦表面上外延生长的低温晶种层、以及在该晶种层上方的应力松弛缓冲层。
本发明揭示的另一面向包含在‘V型凹槽’凹陷的沟槽内提供＜111＞表面并且生长低温薄的外延晶种层造成有效的缺陷限制及充分的晶格参数松弛。后续的应力松弛缓冲层为充分无缺陷并且很薄，从而在外延生长通道材料之前提供良好品质的磊晶。＜111＞表面通过使晶圆非平坦化或开槽化而建立。
本发明揭示的额外面向及其它特征将于下列描述中提出，并且其中一部分对于该技术领域中的技术人员而言在检视下文后将会是显而易见的，或者可在实施该发明揭示后而得以认识本发明。可如同在权利要求书中特别提出者而实现及获得本发明揭示的优点。
依据本发明揭示，可通过一种方法而部分达到某些技术功效，该方法包含：形成非平坦表面或V型凹槽表面于硅晶圆的上表面中；外延生长低温晶种层于该硅晶圆的该非平坦表面上；沉积应力松弛缓冲层于该低温晶种层上方；以及平坦化该应力松弛缓冲层的上表面。
本发明揭示的面向包含使用化学机械研磨平坦化应力松弛缓冲层的上表面。其它面向包含外延生长低温晶种层于硅晶圆的非平坦表面的沟槽中。另一个面向包含外延生长该低温晶种层至10纳米至40纳米的厚度。额外面向包含具有小于200纳米的深度的锥体。其它面向包含低温晶种层，其包含锗(Ge)、磷化铟(InP)或砷化镓(GaAs)。又一个面向包含于低温晶种层上方以200纳米至300纳米的厚度外延生长应力松弛缓冲层，其中该应力松弛缓冲层包含硅锗(SiGe)、砷化铟镓(InGaAs)或磷砷化镓铟(GaxIn1-xAsyP1-y)。额外面向包含形成该非平坦表面于该硅晶圆的上表面上，包含通过蚀刻形成锥体于该硅晶圆的上表面中，其中该锥体具有低于200纳米的高度。另一个面向包含具有硅＜111＞表面的锥体。额外面向包含在晶圆的顶部上的平行的V型凹槽。
本发明揭示的另一面向是一种方法，包含：形成非平坦表面于硅晶圆的上表面中，其中该非平坦表面包含硅＜111＞表面；外延生长低温晶种层于该硅晶圆的非平坦表面上，该低温晶种层包含锗、磷化铟或砷化镓；于该低温晶种层上方以200纳米至300纳米的厚度外延生长应力松弛缓冲层，其中该应力松弛缓冲层包含硅锗(SiGe)、砷化铟镓(InGaAs)或磷砷化镓铟(GaxIn1-xAsyP1-y)；以及平坦化该应力松弛缓冲层的上表面。
本发明的面向包含外延生长低温晶种层至10纳米至40纳米的厚度。另一面向包含使用化学机械研磨平坦化应力松弛缓冲层的上表面。额外面向包含通过形成锥体或V型凹槽于硅晶圆的上表面中而形成非平坦表面于该硅晶圆的上表面上。
本发明揭示的另一面向为一种装置，包含：具有非平坦上表面的硅晶圆；沉积在该硅晶圆的非平坦表面上的外延生长的低温晶种层；以及沉积在该低温晶种层上方的应力松弛缓冲层。本发明的面向包含具有10纳米至40纳米的厚度的外延生长的低温晶种层。又一面向包含硅晶圆的非平坦表面，该硅晶圆包含具有硅＜111＞表面的锥体或具有硅＜111＞表面的V型凹槽。其它面向包含低温晶种层，其含有锗、磷化铟或砷化镓。额外面向包含应力松弛缓冲层，其包含硅锗(SiGe)、砷化铟镓(InGaAs)或磷砷化镓铟(GaxIn1-xAsyP1-y)。
本发明揭示的额外面向及技术功效对该技术领域中的技术人员而言，通过下文的实施方式将立即变得显而易见，其中本发明揭示的实施例仅通过用以实施本发明所考量的最佳模式而做说明。将可以了解的是，本发明揭示能够适用于其它及不同的实施例，并且其数项细节能够以各种显而易见的面向而做修正，所有修正不违背本发明揭示。因此，图式及说明在本质上应视为例示性，而非限制性。
附图说明
本发明揭示以例示性而非限制性的方式通过随附图式中的范例做说明，其中相同的元件符号意指类似的元件，并且其中：
图1、图2A、图4及图5依据例示实施例概要性说明用以在非平坦硅晶圆上产生应力松弛缓冲层的制程流程的横截面视图。
图2B为非平坦硅晶圆表面的扫描式电子显微镜影像。
图2C为形成于硅晶圆表面中的锥体形状的图式。
图3为具有V型凹槽的沟槽所形成的硅晶圆表面的透视图式。
附图标记说明
101 硅晶圆 103 上表面
201 锥体形状 203 尖峰
205 沟槽 301 V型凹槽
401 低温晶种层 501 应力松弛缓冲层
503 上表面。
具体实施方式
在下列叙述中，为了说明的目的，提出许多特定的细节以提供对例示性实施例的完整了解。然而，例示性实施例显然也可以在不具有这些特定细节或具有等同的配置下而实施。在其它例子中，众所周知的结构及装置以方块图形式而显示以避免非必要地混淆例示性实施例。此外，除非另外指示，所有使用于本说明书及权利要求书中的数字表示的数量、比例及组成成分的数值化性质、反应条件及等等，应理解为通过术语"大约(about)"而在所有例子中做修饰。
本发明揭示解决当在硅晶圆上生长半导体材料(诸如应力松弛缓冲层)时产生差排缺陷的当前问题。
依据本发明揭示的实施例的方法包含：在硅晶圆的上表面中形成非平坦的或开槽的表面；外延生长低温晶种层于该硅晶圆的该非平坦表面上；沉积应力松弛缓冲层于该低温晶种层上方；以及平坦化该应力松弛缓冲层的上表面。
本发明的其它目的、特征及技术功效对于熟习该项技艺的人士而言，通过下文的详细说明将立即变得显而易见，其中仅通过最佳模式所考量的说明而显示及描述较佳实施例。本发明揭示能够做其它及不同的实施例，并且其中几个细节能够以各种明显方面做修正。因此，图式及实施方式在性质上应视为例示性而非限制性。
留意图1，其以横截面图说明具有光滑上表面103的硅晶圆101的例子。该硅晶圆可以具有从25.4毫米至450毫米的各种直径并且可由结晶硅形成。该硅晶圆做为内建在晶圆内和建立在晶圆上方的微电子装置所使用的基板，并且经历许多微制造制程步骤，诸如各种材料的掺杂或离子布植、蚀刻、沉积以及光刻图案化。
留意图2A，该硅晶圆101被非平坦化以形成多个锥体形状201于该硅晶圆的上表面103上。该锥体形状201具有尖峰203及沟槽205。每一个锥体形状201从其尖峰203至沟槽205的底部的高度是在100纳米至200纳米之间。该硅晶圆101的非平坦表面是通过蚀刻制程形成在该硅晶圆101的一侧上，该蚀刻制程包含干式或湿式蚀刻制程或湿式/干式制程的组合以形成该锥体形状201。可以使用诸如以六氟化硫为基础的干式蚀刻的干式蚀刻制程而在该硅晶圆101的表面上产生不规则性。硅晶圆101的整个上表面可以经由蚀刻以提供高度范围在100纳米至200纳米之间的微细的锥体形状201。该锥体201具有硅＜111＞表面。湿式蚀刻制程亦可被用来形成高度小于200纳米的锥体形状201。四甲基氢氧化铵(TMAH,TetraMethylAmmonium Hydroxide)、氢氧化钾(KOH,Potassium Hydroxide)或氢氧化钠(NaOH,Sodium Hydroxide)的水溶液可被用来作为湿式蚀刻溶液。
在图2B中，该图为显示有多个锥体形状201的非平坦硅晶圆101的扫描式电子显微镜影像。在图2C中，该图为表示在图2B的影像中随机形成的锥体201的一部分的图式。
该硅晶圆101上所形成的锥体形状201的另一种选择是，对该硅晶圆101进行遮罩及方向选择性的V型凹槽蚀刻。经过此加工处理后，会横跨该硅晶圆101形成长且平行的V型凹槽301，如图3所示。
留意图4，外延生长低温晶种层401形成在该硅晶圆101的非平坦表面上。尤其，该低温晶种层401形成在该锥体形状201上方，使得该尖峰203及沟槽205被该外延生长低温晶种层401覆盖。该低温晶种层401生长至10纳米至40纳米的厚度，例如20纳米。该低温晶种层典型包含锗、磷化铟或砷化镓。该晶种层401外延生长的温度范围在400℃及700℃之间。可以使用化学气相沉积(CVD,Chemical Vapor Deposition)或分子束外延(MBE,MolecularBeam Epitaxy)制程来外延生长该晶种层401。
留意图5，应力松弛缓冲层501沉积在该低温晶种层401上方。应力松弛缓冲层501的上表面503显示为平坦的。可以利用化学机械研磨执行平坦化。该应力松弛缓冲层501为形成在该低温晶种层401上方达到200纳米至500纳米的厚度。该应力松弛缓冲层501包含高迁移率沟道材料，该高迁移率沟道材料包含锗(Ge)、硅锗(SixGe1-x)、砷化铟镓(InGaAs)或磷砷化镓铟(GaxIn1-xAsyP1-y)。在该应力松弛层501的平坦化后，该硅晶圆101可以进行进一步的加工，例如加入沟道。该锥体201可以通过横截面穿透式电子显微镜(X-TEM,Cross-Sectional Transmission Electron Microscopy)而进行侦测。
本发明揭示的实施例可以达到数种技术功效，例如完全松弛的应力松弛缓冲层的快速形成。本发明揭示允许应力松弛缓冲层以低成本制程形成。
依据本发明揭示的实施例所形成的装置在例如微处理器、智慧型手机、行动装置、移动手持装置、数位视讯转换盒、数位多功能影音光碟烧录器及播放器、汽车导航、印表机及周边、网络及电路设备、游戏机系统、数位相机的各种工业应用上享有实用性。因此，本发明揭示在使用具有薄的应力松弛缓冲层的硅晶圆的任何各种类型的高度整合半导体装置的制造上享有工业可利用性，可达到完全的应力松弛并将缺陷局部地限制在非平坦硅表面上的沟槽的底部处。本发明揭示特别适用于14纳米以上的技术节点。
在先前的描述中，本发明揭示参考本发明的特定例示性实施例做描述。然而，显然可在不脱离本发明揭示的较广义的精神及范畴的情况下做出各种修改及变化，如权利要求书中所提出者。说明书及图式因此应视为例示性而非限制性。应了解到，本发明揭示能够使用各种其它组合及实施例，并且能在本文所表述的发明概念的范畴内做任何变化或修改。

Claims (9)

1.一种制造半导体装置的方法，该方法包括：
在硅(Si)晶圆的上表面中形成非平坦表面或V型凹槽表面，其中，在该硅晶圆的该上表面上形成该非平坦表面或V型凹槽表面的步骤包含：
通过蚀刻随机形成锥体在该硅晶圆的该上表面中；
于温度范围在400℃及700℃之间在该硅晶圆的该非平坦表面上外延生长低温晶种层；
沉积应力松弛缓冲(SRB)层在该低温晶种层上方，以便将缺陷局部地限制在该非平坦表面或V型凹槽表面上的该锥体的沟槽的底部处；以及
平坦化该应力松弛缓冲层的上表面。
2.根据权利要求1所述的方法，其中该平坦化包括：
以化学机械研磨(CMP)平坦化该应力松弛缓冲层的该上表面。
3.根据权利要求1所述的方法，还包括：
外延生长该低温晶种层至10纳米至40纳米的厚度。
4.根据权利要求1所述的方法，其中，该锥体具有低于200纳米的深度。
5.根据权利要求1所述的方法，其中，该低温晶种层包括锗(Ge)、磷化铟(InP)或砷化镓(GaAs)。
6.根据权利要求1所述的方法，还包括：
在该低温晶种层上方以200至500纳米的厚度外延生长该应力松弛缓冲层，其中该应力松弛缓冲层包含硅锗(SixGe1-x)、砷化铟镓(InGaAs)或磷砷化镓铟(GaxIn1-xAsyP1-y)。
7.一种制造半导体装置的方法，该方法包括：
形成非平坦表面在硅晶圆的上表面中，其中该非平坦表面包含硅＜111＞表面；
于温度范围在400℃及700℃之间外延生长低温晶种层在该硅晶圆的该非平坦表面上，其中该低温晶种层包括锗、磷化铟或砷化镓；
在该低温晶种层上方以200纳米至300纳米的厚度外延生长应力松弛缓冲层，以便将缺陷局部地限制在该非平坦表面上的锥体的沟槽的底部处，其中该应力松弛缓冲层包括硅锗(SiGe)、砷化铟镓(InxGa1-xAs)或磷砷化镓铟(GaxIn1-xAsyP1-y)；以及
平坦化该应力松弛缓冲层的上表面，
其中，形成该非平坦表面在该硅晶圆的该上表面上的步骤包含：
随机形成该锥体在该硅晶圆的该上表面中。
8.根据权利要求7所述的方法，还包括：
外延生长该低温晶种层至10纳米至40纳米的厚度。
9.根据权利要求7所述的方法，其中该平坦化包括：
使用化学机械研磨平坦化该应力松弛缓冲的该上表面。
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