CN106356284A - 在非平坦硅表面上的应力松弛缓冲层 - Google Patents

在非平坦硅表面上的应力松弛缓冲层 Download PDF

Info

Publication number
CN106356284A
CN106356284A CN201610511090.XA CN201610511090A CN106356284A CN 106356284 A CN106356284 A CN 106356284A CN 201610511090 A CN201610511090 A CN 201610511090A CN 106356284 A CN106356284 A CN 106356284A
Authority
CN
China
Prior art keywords
seed layer
low temperature
crystal seed
silicon wafer
temperature crystal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201610511090.XA
Other languages
English (en)
Inventor
B·J·帕夫拉克
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
GlobalFoundries Inc
Original Assignee
GlobalFoundries Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by GlobalFoundries Inc filed Critical GlobalFoundries Inc
Priority to CN201911154213.9A priority Critical patent/CN110854014A/zh
Publication of CN106356284A publication Critical patent/CN106356284A/zh
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02647—Lateral overgrowth
    • H01L21/0265—Pendeoepitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/02428—Structure
    • H01L21/0243—Surface structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/02433—Crystal orientation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02441—Group 14 semiconducting materials
    • H01L21/0245—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H01L21/02461—Phosphides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H01L21/02463—Arsenides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/02543—Phosphides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/02546—Arsenides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02639—Preparation of substrate for selective deposition
    • H01L21/02645—Seed materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30625—With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/201—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Materials Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

本发明涉及在非平坦硅表面上的应力松弛缓冲层，具体提供一种形成应力松弛缓冲(SRB,Stress Relaxed Buffer)层于非平坦的或开槽的硅(Si)表面上的方法及其装置。实施例包含形成非平坦表面于硅晶圆的上表面中；外延生长低温晶种层于该硅晶圆的该非平坦表面上；沉积应力松弛缓冲层于该低温晶种层上方；以及平坦化该应力松弛缓冲层的上表面。

Description

在非平坦硅表面上的应力松弛缓冲层
技术领域
本发明揭露关于半导体装置的制造。尤其，本发明揭露关于使用于在14纳米、10纳米、7纳米、5纳米及3纳米技术节点中制造半导体装置的应力松弛缓冲(SRB,StressRelaxed Buffer)层。
背景技术
使用硅(Si,Silicon)晶圆时，具有不同的晶格常数(lattice constant)及热膨胀系数(thermal coefficient)的不同半导体材料的外延生长会造成缺陷的产生，诸如产生差排(dislocation)缺陷而接着导致不良的晶体管效能及可靠度问题。具有应力松弛缓冲层的基板，包含阶梯式(stepped)或渐变式(graded)的砷化镓(GaAs,Gallium Arsenide)或硅锗(SiGe,Silicon Germanium)，是有用于达到应力松弛。然而，该应力松弛层是厚的(例如，2微米至2.5微米之间的范围)并且因此昂贵。再者，若使用中间的化学机械研磨(CMP,Chemical Mechanical Polishing)步骤以平坦化该层及光滑化表面粗度，则在下一道外延步骤之前将会有氧化物残留物残留在顶端的风险。介电质残留物将接着降低该顶部磊晶层的品质。
因此，存在着用于能够铺设薄的应力松弛缓冲层的方法及其装置的需求，该应力松弛缓冲层达到完全的应力松弛并将缺陷局部地局限在非平坦硅表面上的沟槽底部处。
发明内容
本发明揭露的一面向包含使硅晶圆的上表面非平坦化或开槽化、外延生长低温晶种层于该非平坦或开槽化的硅晶圆的表面、以及沉积(外延生长)应力松弛缓冲层于该晶种层上方。缺陷可以被局部地限制或捕捉在非平坦硅表面上的10纳米的晶种外延厚度内。
本发明揭露的另一面向为一种装置，包含硅晶圆的非平坦上表面、于该硅晶圆的该非平坦表面上外延生长的低温晶种层、以及在该晶种层上方的应力松弛缓冲层。
本发明揭露的另一面向包含在‘V型凹槽’凹陷的沟槽内提供＜111＞表面并且生长低温薄的外延晶种层造成有效的缺陷限制及充分的晶格参数松弛。后续的应力松弛缓冲层为充分无缺陷并且很薄，从而在外延生长通道材料之前提供良好品质的磊晶。＜111＞表面藉由使晶圆非平坦化或开槽化而建立。
本发明揭露的额外面向及其它特征将于下列描述中提出，并且其中一部分对于该技术领域中的技术人员而言在检视下文后将会是显而易见的，或者可在实施该发明揭露后而得以认识本发明。可如同在权利要求书中特别提出者而实现及获得本发明揭露的优点。
依据本发明揭露，可藉由一种方法而部分达到某些技术功效，该方法包含：形成非平坦表面或V型凹槽表面于硅晶圆的上表面中；外延生长低温晶种层于该硅晶圆的该非平坦表面上；沉积应力松弛缓冲层于该低温晶种层上方；以及平坦化该应力松弛缓冲层的上表面。
本发明揭露的面向包含使用化学机械研磨平坦化应力松弛缓冲层的上表面。其它面向包含外延生长低温晶种层于硅晶圆的非平坦表面的沟槽中。另一个面向包含外延生长该低温晶种层至10纳米至40纳米的厚度。额外面向包含具有小于200纳米的深度的锥体。其它面向包含低温晶种层，其包含锗(Ge)、磷化铟(InP)或砷化镓(GaAs)。又一个面向包含于低温晶种层上方以200纳米至300纳米的厚度外延生长应力松弛缓冲层，其中该应力松弛缓冲层包含硅锗(SiGe)、砷化铟镓(InGaAs)或磷砷化镓铟(GaxIn1-xAsyP1-y)。额外面向包含形成该非平坦表面于该硅晶圆的上表面上，包含藉由蚀刻形成锥体于该硅晶圆的上表面中，其中该锥体具有低于200纳米的高度。另一个面向包含具有硅＜111＞表面的锥体。额外面向包含在晶圆的顶部上的平行的V型凹槽。
本发明揭露的另一面向是一种方法，包含：形成非平坦表面于硅晶圆的上表面中，其中该非平坦表面包含硅＜111＞表面；外延生长低温晶种层于该硅晶圆的非平坦表面上，该低温晶种层包含锗、磷化铟或砷化镓；于该低温晶种层上方以200纳米至300纳米的厚度外延生长应力松弛缓冲层，其中该应力松弛缓冲层包含硅锗(SiGe)、砷化铟镓(InGaAs)或磷砷化镓铟(GaxIn1-xAsyP1-y)；以及平坦化该应力松弛缓冲层的上表面。
本发明的面向包含外延生长低温晶种层至10纳米至40纳米的厚度。另一面向包含使用化学机械研磨平坦化应力松弛缓冲层的上表面。额外面向包含藉由形成锥体或V型凹槽于硅晶圆的上表面中而形成非平坦表面于该硅晶圆的上表面上。
本发明揭露的另一面向为一种装置，包含：具有非平坦上表面的硅晶圆；沉积在该硅晶圆的非平坦表面上的外延生长的低温晶种层；以及沉积在该低温晶种层上方的应力松弛缓冲层。本发明的面向包含具有10纳米至40纳米的厚度的外延生长的低温晶种层。又一面向包含硅晶圆的非平坦表面，该硅晶圆包含具有硅＜111＞表面的锥体或具有硅＜111＞表面的V型凹槽。其它面向包含低温晶种层，其含有锗、磷化铟或砷化镓。额外面向包含应力松弛缓冲层，其包含硅锗(SiGe)、砷化铟镓(InGaAs)或磷砷化镓铟(GaxIn1-xAsyP1-y)。
本发明揭露的额外面向及技术功效对该技术领域中的技术人员而言，藉由下文的实施方式将立即变得显而易见，其中本发明揭露的实施例仅藉由用以实施本发明所考量的最佳模式而做说明。将可以了解的是，本发明揭露能够适用于其它及不同的实施例，并且其数项细节能够以各种显而易见的面向而做修正，所有修正不违背本发明揭露。因此，图式及说明在本质上应视为例示性，而非限制性。
附图说明
本发明揭露以例示性而非限制性的方式藉由随附图式中的范例做说明，其中相同的元件符号意指类似的元件，并且其中：
图1、2A、4及5依据例示实施例概要性说明用以在非平坦硅晶圆上产生应力松弛缓冲层的制程流程的横截面视图。
图2B为非平坦硅晶圆表面的扫描式电子显微镜影像。
图2C为形成于硅晶圆表面中的锥体形状的图式。
图3为具有V型凹槽的沟槽所形成的硅晶圆表面的透视图式。
符号说明
101 硅晶圆 103 上表面
201 锥体形状 203 尖峰
205 沟槽 301 V型凹槽
401 低温晶种层 501 应力松弛缓冲层
503 上表面。
具体实施方式
在下列叙述中，为了说明的目的，提出许多特定的细节以提供对例示性实施例的完整了解。然而，例示性实施例显然也可以在不具有这些特定细节或具有等同的配置下而实施。在其它例子中，众所周知的结构及装置以方块图形式而显示以避免非必要地混淆例示性实施例。此外，除非另外指示，所有使用于本说明书及权利要求书中的数字表示的数量、比例及组成成分的数值化性质、反应条件及等等，应理解为藉由术语"大约(about)"而在所有例子中做修饰。
本发明揭露解决当在硅晶圆上生长半导体材料(诸如应力松弛缓冲层)时产生差排缺陷的当前问题。
依据本发明揭露的实施例的方法包含：在硅晶圆的上表面中形成非平坦的或开槽的表面；外延生长低温晶种层于该硅晶圆的该非平坦表面上；沉积应力松弛缓冲层于该低温晶种层上方；以及平坦化该应力松弛缓冲层的上表面。
本发明的其它目的、特征及技术功效对于熟习该项技艺的人士而言，藉由下文的详细说明将立即变得显而易见，其中仅藉由最佳模式所考量的说明而显示及描述较佳实施例。本发明揭露能够做其它及不同的实施例，并且其中几个细节能够以各种明显方面做修正。因此，图式及实施方式在性质上应视为例示性而非限制性。
留意图1，其以横截面图说明具有光滑上表面103的硅晶圆101的例子。该硅晶圆可以具有从25.4毫米至450毫米的各种直径并且可由结晶硅形成。该硅晶圆做为内建在晶圆内和建立在晶圆上方的微电子装置所使用的基板，并且经历许多微制造制程步骤，诸如各种材料的掺杂或离子布植、蚀刻、沉积以及光刻图案化。
留意图2A，该硅晶圆101被非平坦化以形成多个锥体形状201于该硅晶圆的上表面103上。该锥体形状201具有尖峰203及沟槽205。每一个锥体形状201从其尖峰203至沟槽205的底部的高度是在100纳米至200纳米之间。该硅晶圆101的非平坦表面是藉由蚀刻制程形成在该硅晶圆101的一侧上，该蚀刻制程包含干式或湿式蚀刻制程或湿式/干式制程的组合以形成该锥体形状201。可以使用诸如以六氟化硫为基础的干式蚀刻的干式蚀刻制程而在该硅晶圆101的表面上产生不规则性。硅晶圆101的整个上表面可以经由蚀刻以提供高度范围在100纳米至200纳米之间的微细的锥体形状201。该锥体201具有硅＜111＞表面。湿式蚀刻制程亦可被用来形成高度小于200纳米的锥体形状201。四甲基氢氧化铵(TMAH,TetraMethylAmmonium Hydroxide)、氢氧化钾(KOH,Potassium Hydroxide)或氢氧化钠(NaOH,Sodium Hydroxide)的水溶液可被用来作为湿式蚀刻溶液。
在图2B中，该图为显示有多个锥体形状201的非平坦硅晶圆101的扫描式电子显微镜影像。在图2C中，该图为表示在图2B的影像中随机形成的锥体201的一部分的图式。
该硅晶圆101上所形成的锥体形状201的另一种选择是，对该硅晶圆101进行遮罩及方向选择性的V型凹槽蚀刻。经过此加工处理后，会横跨该硅晶圆101形成长且平行的V型凹槽301，如图3所示。
留意图4，外延生长低温晶种层401形成在该硅晶圆101的非平坦表面上。尤其，该低温晶种层401形成在该锥体形状201上方，使得该尖峰203及沟槽205被该外延生长低温晶种层401覆盖。该低温晶种层401生长至10纳米至40纳米的厚度，例如20纳米。该低温晶种层典型包含锗、磷化铟或砷化镓。该晶种层401外延生长的温度范围在400℃及700℃之间。可以使用化学气相沉积(CVD,Chemical Vapor Deposition)或分子束外延(MBE,MolecularBeam Epitaxy)制程来外延生长该晶种层401。
留意图5，应力松弛缓冲层501沉积在该低温晶种层401上方。应力松弛缓冲层501的上表面503显示为平坦的。可以利用化学机械研磨执行平坦化。该应力松弛缓冲层501为形成在该低温晶种层401上方达到200纳米至500纳米的厚度。该应力松弛缓冲层501包含高迁移率沟道材料，该高迁移率沟道材料包含锗(Ge)、硅锗(SixGe1-x)、砷化铟镓(InGaAs)或磷砷化镓铟(GaxIn1-xAsyP1-y)。在该应力松弛层501的平坦化后，该硅晶圆101可以进行进一步的加工，例如加入沟道。该锥体201可以藉由横截面穿透式电子显微镜(X-TEM,Cross-Sectional Transmission Electron Microscopy)而进行侦测。
本发明揭露的实施例可以达到数种技术功效，例如完全松弛的应力松弛缓冲层的快速形成。本发明揭露允许应力松弛缓冲层以低成本制程形成。
依据本发明揭露的实施例所形成的装置在例如微处理器、智慧型手机、行动装置、移动手持装置、数位视讯转换盒、数位多功能影音光碟烧录器及播放器、汽车导航、印表机及周边、网络及电路设备、游戏机系统、数位相机的各种工业应用上享有实用性。因此，本发明揭露在使用具有薄的应力松弛缓冲层的硅晶圆的任何各种类型的高度整合半导体装置的制造上享有工业可利用性，可达到完全的应力松弛并将缺陷局部地限制在非平坦硅表面上的沟槽的底部处。本发明揭露特别适用于14纳米以上的技术节点。
在先前的描述中，本发明揭露参考本发明的特定例示性实施例做描述。然而，显然可在不脱离本发明揭露的较广义的精神及范畴的情况下做出各种修改及变化，如权利要求书中所提出者。说明书及图式因此应视为例示性而非限制性。应了解到，本发明揭露能够使用各种其它组合及实施例，并且能在本文所表述的发明概念的范畴内做任何变化或修改。

Claims (20)

1.一种方法，包括：
在硅(Si)晶圆的上表面中形成非平坦表面或V型凹槽表面；
在该硅晶圆的该非平坦表面上外延生长低温晶种层；
沉积应力松弛缓冲(SRB)层于该低温晶种层上方；以及
平坦化该应力松弛缓冲层的上表面。
2.根据权利要求1所述的方法，还包括：
以化学机械研磨(CMP)平坦化该应力松弛缓冲层的该上表面。
3.根据权利要求1所述的方法，还包括：
外延生长该低温晶种层于该硅晶圆的该非平坦表面或该V型凹槽表面的沟槽中。
4.根据权利要求3所述的方法，还包括：
外延生长该低温晶种层至10纳米至40纳米的厚度。
5.根据权利要求3所述的方法，其中，该锥体具有低于200纳米的深度。
6.根据权利要求1所述的方法，其中，该低温晶种层包括锗(Ge)、磷化铟(InP)或砷化镓(GaAs)。
7.根据权利要求1所述的方法，还包括：
于该低温晶种层上方以200至500纳米的厚度外延生长该应力松弛缓冲层，其中该应力松弛缓冲层包含硅锗(SixGe1-x)、砷化铟镓(InGaAs)或磷砷化镓铟(GaxIn1-xAsyP1-y)。
8.根据权利要求1所述的方法，其中，形成该非平坦表面或V型凹槽表面于该硅晶圆的该上表面上的步骤包含：
藉由蚀刻形成锥体于该硅晶圆的该上表面中，其中该锥体具有小于300纳米的高度。
9.根据权利要求8所述的方法，其中，该锥体具有硅＜111＞表面。
10.根据权利要求1所述的方法，其中，形成该非平坦表面或V型凹槽表面于该硅晶圆的该上表面上的步骤包含：
形成平行的V型凹槽于该硅晶圆的该上表面中。
11.根据权利要求1所述的方法，其中，上下颠倒的锥体具有硅＜111＞表面。
12.一种方法，包括：
形成非平坦表面于硅晶圆的上表面中，其中该非平坦表面包含硅＜111＞表面；
外延生长低温晶种层于该硅晶圆的该非平坦表面上，该低温晶种层包括锗、磷化铟或砷化镓；
于该低温晶种层上方以200纳米至300纳米的厚度外延生长应力松弛缓冲层，其中该应力松弛缓冲层包括硅锗(SiGe)、砷化铟镓(InGaAs)或磷砷化镓铟(GaxIn1-xAsyP1-y)；以及
平坦化该应力松弛缓冲层的上表面。
13.根据权利要求12所述的方法，还包括：
外延生长该低温晶种层至10纳米至40纳米的厚度。
14.根据权利要求12所述的方法，还包括：
使用化学机械研磨平坦化该应力松弛缓冲的该上表面。
15.根据权利要求12所述的方法，其中，形成该非平坦表面于该硅晶圆的该上表面上的步骤包含：
形成锥体或平行的V型凹槽于该硅晶圆的该上表面中。
16.一种装置，包括：
包含非平坦上表面的硅(Si)晶圆；
沉积在该硅晶圆的该非平坦表面上的外延生长的低温晶种层；以及
沉积在该低温晶种层上方的应力松弛缓冲(SRB)层。
17.根据权利要求16所述的装置，其中，所外延生长的该低温晶种层具有10纳米至40纳米的厚度。
18.根据权利要求16所述的装置，其中，该硅晶圆的该非平坦表面包含：
具有硅＜111＞表面的锥体，或者
具有硅＜111＞表面的平行的V型凹槽。
19.根据权利要求16所述的装置，其中，该低温晶种层包括锗、磷化铟或砷化镓。
20.根据权利要求19所述的装置，其中，该应力松弛缓冲层包括硅锗(SiGe)、砷化铟镓(InxGa1-xAs)或磷砷化镓铟(GaxIn1-xAsyP1-y)。
CN201610511090.XA 2015-07-13 2016-06-30 在非平坦硅表面上的应力松弛缓冲层 Pending CN106356284A (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201911154213.9A CN110854014A (zh) 2015-07-13 2016-06-30 在非平坦硅表面上的应力松弛缓冲层

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14/797,531 US9558943B1 (en) 2015-07-13 2015-07-13 Stress relaxed buffer layer on textured silicon surface
US14/797,531 2015-07-13

Related Child Applications (1)

Application Number Title Priority Date Filing Date
CN201911154213.9A Division CN110854014A (zh) 2015-07-13 2016-06-30 在非平坦硅表面上的应力松弛缓冲层

Publications (1)

Publication Number Publication Date
CN106356284A true CN106356284A (zh) 2017-01-25

Family

ID=57776550

Family Applications (2)

Application Number Title Priority Date Filing Date
CN201911154213.9A Pending CN110854014A (zh) 2015-07-13 2016-06-30 在非平坦硅表面上的应力松弛缓冲层
CN201610511090.XA Pending CN106356284A (zh) 2015-07-13 2016-06-30 在非平坦硅表面上的应力松弛缓冲层

Family Applications Before (1)

Application Number Title Priority Date Filing Date
CN201911154213.9A Pending CN110854014A (zh) 2015-07-13 2016-06-30 在非平坦硅表面上的应力松弛缓冲层

Country Status (3)

Country Link
US (1) US9558943B1 (zh)
CN (2) CN110854014A (zh)
TW (1) TWI585858B (zh)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109585526A (zh) * 2017-09-29 2019-04-05 台湾积体电路制造股份有限公司 半导体衬底及其制造方法
CN110491950A (zh) * 2019-07-10 2019-11-22 中国科学院上海技术物理研究所 一种控制铟镓砷光敏芯片平面度的平衡层结构
US11749526B2 (en) 2017-09-29 2023-09-05 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor substrate and method of manufacturing thereof

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111146320A (zh) * 2018-11-02 2020-05-12 华为技术有限公司 硅基衬底、衬底基板及其制造方法、光电器件
US11515408B2 (en) 2020-03-02 2022-11-29 Taiwan Semiconductor Manufacturing Company, Ltd. Rough buffer layer for group III-V devices on silicon

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1863944A (zh) * 2001-02-14 2006-11-15 丰田合成株式会社 半导体晶体的制造方法和半导体发光元件
CN102130224A (zh) * 2010-12-10 2011-07-20 映瑞光电科技(上海)有限公司 发光二极管及其制造方法
CN104600070A (zh) * 2013-10-31 2015-05-06 三星电子株式会社 衬底结构、cmos器件和制造cmos器件的方法

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001043174A2 (en) * 1999-12-13 2001-06-14 North Carolina State University Fabrication of gallium nitride layers on textured silicon substrates
DE60233386D1 (de) * 2001-02-14 2009-10-01 Toyoda Gosei Kk Verfahren zur herstellung von halbleiterkristallen und halbleiter-leuchtelementen
EP1439570A1 (en) * 2003-01-14 2004-07-21 Interuniversitair Microelektronica Centrum ( Imec) SiGe strain relaxed buffer for high mobility devices and a method of fabricating it
EP2104135B1 (en) * 2008-03-20 2013-06-12 Siltronic AG A semiconductor wafer with a heteroepitaxial layer and a method for producing the wafer
KR101671793B1 (ko) * 2010-07-01 2016-11-04 삼성전자주식회사 반도체 발광소자 및 그 제조방법
JPWO2012067079A1 (ja) * 2010-11-15 2014-05-12 Hoya株式会社 炭化珪素基板ならびに半導体素子
US8697541B1 (en) * 2010-12-24 2014-04-15 Ananda H. Kumar Methods and structures for preparing single crystal silicon wafers for use as substrates for epitaxial growth of crack-free gallium nitride films and devices
JP2012184144A (ja) * 2011-03-07 2012-09-27 Tokuyama Corp 窒化ガリウム結晶積層基板及びその製造方法
US20130140592A1 (en) * 2011-12-01 2013-06-06 Taiwan Semiconductor Manufacturing Company, Ltd. Light emitting diode with improved light extraction efficiency and methods of manufacturing same
US8642430B2 (en) * 2012-04-09 2014-02-04 GlobalFoundries, Inc. Processes for preparing stressed semiconductor wafers and for preparing devices including the stressed semiconductor wafers
CN103563051A (zh) * 2012-05-23 2014-02-05 日本碍子株式会社 复合基板、发光元件以及复合基板的制造方法
KR102019058B1 (ko) * 2012-08-21 2019-09-06 오지 홀딩스 가부시키가이샤 반도체 발광 소자용 기판, 반도체 발광 소자 및 이들의 제조 방법
JP6120204B2 (ja) * 2012-09-06 2017-04-26 パナソニック株式会社 エピタキシャルウェハ及びその製造方法、紫外発光デバイス
KR101987056B1 (ko) * 2012-11-07 2019-06-10 엘지이노텍 주식회사 발광 소자 및 발광 소자 패키지
DE112013007072T5 (de) * 2013-06-28 2016-01-28 Intel Corporation Nano-Strukturen und Nano-Merkmale mit Si (111)-Ebenen auf Si (100)-Wafer für III-N Epitaxie

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1863944A (zh) * 2001-02-14 2006-11-15 丰田合成株式会社 半导体晶体的制造方法和半导体发光元件
CN102130224A (zh) * 2010-12-10 2011-07-20 映瑞光电科技(上海)有限公司 发光二极管及其制造方法
CN104600070A (zh) * 2013-10-31 2015-05-06 三星电子株式会社 衬底结构、cmos器件和制造cmos器件的方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109585526A (zh) * 2017-09-29 2019-04-05 台湾积体电路制造股份有限公司 半导体衬底及其制造方法
CN109585526B (zh) * 2017-09-29 2022-09-23 台湾积体电路制造股份有限公司 半导体衬底及其制造方法
US11749526B2 (en) 2017-09-29 2023-09-05 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor substrate and method of manufacturing thereof
CN110491950A (zh) * 2019-07-10 2019-11-22 中国科学院上海技术物理研究所 一种控制铟镓砷光敏芯片平面度的平衡层结构

Also Published As

Publication number Publication date
US9558943B1 (en) 2017-01-31
TW201703152A (zh) 2017-01-16
CN110854014A (zh) 2020-02-28
US20170018421A1 (en) 2017-01-19
TWI585858B (zh) 2017-06-01

Similar Documents

Publication Publication Date Title
CN106356284A (zh) 在非平坦硅表面上的应力松弛缓冲层
US9263528B2 (en) Method for producing strained Ge fin structures
EP1892766B1 (fr) Procédé de réalisation d'un dispositif comportant une structure dotée d'un ou plusieurs micro-fils ou nano-fils à base d'un composé de Si et de Ge, par condensation germanium.
US20160049299A1 (en) Growing III-V Compound Semiconductors from Trenches Filled with Intermediate Layers
KR101516619B1 (ko) 물질 아일랜드 형성 방법, 그 물질 아일랜드를 이용한 반도체 소자 제조 방법 및 그 웨이퍼
US9870940B2 (en) Methods of forming nanosheets on lattice mismatched substrates
US20130233238A1 (en) Methods and Mask Structures for Substantially Defect-Free Epitaxial Growth
TW201344758A (zh) 半導體裝置及其製造方法
US20130264609A1 (en) Semiconductor Structure of Hybrid of Coplanar Ge and III-V and Preparation Method Thereof
EP2849219A1 (en) Method for manufacturing transistors and associated substrate
KR20160128246A (ko) 감소된 결함들을 갖는 완화된 반도체 층들 및 그 제조 방법
US9640411B2 (en) Method for manufacturing a transistor device comprising a germanium channel material on a silicon based substrate, and associated transistor device
CN102107852B (zh) 半导体纳米结构和制造方法及其应用
US9443940B1 (en) Defect reduction with rotated double aspect ratio trapping
CN102280469A (zh) 硅表面上ⅲ-v化合物半导体的外延生长
KR101867999B1 (ko) Ｉｉｉ-ｖ족 물질층을 형성하는 방법, ｉｉｉ-ｖ족 물질층을 포함하는 반도체 소자 및 그 제조방법
EP2963674A1 (fr) Procédé de réalisation d'un dispositif microélectronique
US20150048422A1 (en) A method for forming a crystalline compound iii-v material on a single element substrate
CN108807279B (zh) 半导体结构与其制作方法
CN109478764B (zh) 基于异质结构的集成光子装置、方法和应用
US20220276512A1 (en) Optical modulator and method of fabricating an optical modulator
CN102592966B (zh) 半导体器件及其制作方法
US8828840B2 (en) Semiconductor device and method for manufacturing the same
KR102203033B1 (ko) 평면형 이종 디바이스
CN105702728B (zh) 一种半导体器件及其制造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication
RJ01 Rejection of invention patent application after publication

Application publication date: 20170125