WO2019033595A1 - 一种薄膜晶体管阵列基板的制造方法 - Google Patents

一种薄膜晶体管阵列基板的制造方法 Download PDF

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Publication number
WO2019033595A1
WO2019033595A1 PCT/CN2017/111248 CN2017111248W WO2019033595A1 WO 2019033595 A1 WO2019033595 A1 WO 2019033595A1 CN 2017111248 W CN2017111248 W CN 2017111248W WO 2019033595 A1 WO2019033595 A1 WO 2019033595A1
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Prior art keywords
photoresist
layer
region
photoresist region
manufacturing
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PCT/CN2017/111248
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English (en)
French (fr)
Inventor
徐洪远
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Priority to US15/576,773 priority Critical patent/US10497906B2/en
Publication of WO2019033595A1 publication Critical patent/WO2019033595A1/zh
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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/26—Processing photosensitive materials; Apparatus therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates

Definitions

  • the present invention relates to the field of flat panel display manufacturing technology, and in particular, to a method of fabricating a thin film transistor array substrate.
  • LCD Liquid crystal Display, liquid crystal display
  • OLED Organic Light Emitting Diode
  • TFT Thin Film
  • AS active layer
  • S/D source drain
  • HTM halftone mask
  • GTM grey
  • the order mask is formed at the same time.
  • HTM or GTM reticles allow the photoresist to be obtained in two different film thicknesses, which can be used to define the AS and SD patterns, respectively.
  • the ITO (transparent metal layer) and PV (passivation layer) can be simultaneously formed by a single mask using the Lift-off process, thereby reducing the total number of masks to three. (3mask).
  • the traditional 3mask process is mostly only for TN (Twisted). Nematic, twisted nematic mode), ITO does not form a slit pattern; or ITO forms a slit pattern, but since ITO can only be deposited at the burrow, all ITO layers (including the pixel region) are in the nitrogen bismuth compound. In the groove, the transverse electric field of the ITO is weakened, which affects the liquid crystal display effect, and the brightness of the display is uneven.
  • the improved 3mask technology PV/ITO layer is formed by using an HTM or GTM mask, so that the ITO in the pixel region can form a slit and cover the PV layer to form exactly the same as the 4mask. structure.
  • the difficulty of this 3mask technology is that the photoresist is difficult to be peeled off after being covered by the ITO, so that the peeling effect is poor and the efficiency is low. In addition, photoresist stripping residue and burrs can seriously affect process or product performance.
  • the present invention provides a method of manufacturing a thin film transistor array substrate to solve the problem that the photoresist is difficult to be peeled off due to being covered by a transparent metal layer during the manufacturing process of the thin film transistor array substrate.
  • the invention provides a method for manufacturing a thin film transistor array substrate, the manufacturing method comprising:
  • Step S110 using a first photomask to form a gate and a gate line of the thin film transistor on the surface of the substrate;
  • Step S120 forming a gate insulating layer, an active layer, a source electrode, a drain electrode, and a passivation layer of the thin film transistor on a surface of the substrate by using a second photomask;
  • Step S130 applying a first photoresist layer on the passivation layer, exposing the first photoresist layer by using a gray tone mask or a semi-transparent mask, and patterning the photoresist to form mutual a separated first photoresist region and a second photoresist region;
  • Step S140 removing a portion of the passivation layer that is not covered by the first photoresist region and the second photoresist region by an etching process to form a passivation layer via hole to expose a drain;
  • Step S150 performing ashing treatment on the first photoresist region and the second photoresist region, and retaining a portion of the first photoresist region and a portion of the second photoresist region;
  • the second photoresist region includes a first photoresist sub-region and a second photoresist sub-region, and the first photoresist sub-region has a thickness smaller than a thickness of the second photoresist sub-region;
  • the step of performing ashing treatment on the first photoresist region and the second photoresist region includes: removing a first photoresist subregion of the second photoresist region and reducing the second photoresist region The thickness is formed to form a portion of the second photoresist region; the thickness of the first photoresist region is reduced to form a portion of the first photoresist region.
  • Step S160 performing hydrophobic treatment on the surface of the portion of the first photoresist region and the portion of the second photoresist region;
  • Step S170 coating a solution-type transparent metal on the passivation layer not covered by the portion of the first photoresist region and a portion of the second photoresist region, and curing the solution-type transparent metal to form a connection between the drain and the drain.
  • Step S180 performing a stripping process on the portion of the first photoresist region and the portion of the second photoresist region.
  • the step S110 includes:
  • Step S111 providing a substrate, depositing a first metal layer on the surface of the substrate;
  • Step S112 coating a second photoresist layer on the first metal layer
  • Step S113 after exposing and developing the second photoresist layer, etching the first metal layer to form the gate and the gate line of the thin film transistor;
  • step S114 the second photoresist layer is peeled off.
  • the step S120 includes:
  • Step S121 sequentially depositing a gate insulating layer, an active layer, and a second metal layer on the surface of the substrate;
  • Step S122 coating a third photoresist layer on the second metal layer
  • Step S123 after exposing and developing the third photoresist layer, etching the second metal layer to form a source electrode and a drain electrode;
  • Step S124 peeling off the third photoresist layer
  • Step S125 depositing a passivation layer on the gate insulating layer.
  • the step S150 includes:
  • the first photoresist region and the second photoresist region are subjected to ashing treatment using a second plasma, the second plasma being oxygen.
  • the step S160 includes:
  • the portions of the first photoresist region and a portion of the second photoresist region are subjected to a hydrophobic treatment using a first plasma to form a hydrophobic group on the surface of the photoresist, the hydrophobic group being a hydrocarbon group having no affinity for water.
  • the first plasma is one or a mixture of one of nitrogen tetrafluoride, sulfur hexafluoride, and oxygen.
  • the method before performing the stripping process on the portion of the first photoresist region and the portion of the second photoresist region, the method further includes the steps of:
  • a solution type OLED material is coated on the transparent metal layer on the surface of the substrate.
  • the etching process is dry etching.
  • the first reticle process and the second reticle process are halftone reticle or grayscale reticle.
  • the invention also provides a method for manufacturing a thin film transistor array substrate, the manufacturing method comprising:
  • Step S310 using a first photomask to form a gate and a gate line of the thin film transistor on the surface of the substrate;
  • Step S320 forming a gate insulating layer, an active layer, a source electrode, a drain electrode, and a passivation layer of the thin film transistor on a surface of the substrate by using a second photomask;
  • Step S330 applying a first photoresist layer on the passivation layer, exposing the first photoresist layer by using a gray tone mask or a semi-transparent mask, patterning the photoresist to form mutual a separated first photoresist region and a second photoresist region;
  • Step S340 removing a portion of the passivation layer that is not covered by the first photoresist region and the second photoresist region by an etching process to form a passivation layer via hole to expose a drain;
  • Step S350 performing ashing treatment on the first photoresist region and the second photoresist region, and retaining a portion of the first photoresist region and a portion of the second photoresist region;
  • Step S360 performing hydrophobic treatment on the surface of the portion of the first photoresist region and the portion of the second photoresist region;
  • Step S370 coating a solution-type transparent metal on the passivation layer not covered by the portion of the first photoresist region and a portion of the second photoresist region, and curing the solution-type transparent metal to form the connection.
  • Step S380 performing a stripping process on the portion of the first photoresist region and the portion of the second photoresist region.
  • the step S310 includes:
  • Step S311 providing a substrate, depositing a first metal layer on the surface of the substrate;
  • Step S312 coating a second photoresist layer on the first metal layer
  • Step S313 after exposing and developing the second photoresist layer, etching the first metal layer to form the gate and the gate line of the thin film transistor;
  • step S314 the second photoresist layer is peeled off.
  • the step S320 includes:
  • Step S321 sequentially depositing a gate insulating layer, an active layer and a second metal layer on the surface of the substrate;
  • Step S322 coating a third photoresist layer on the second metal layer
  • Step S323 after exposing and developing the third photoresist layer, etching the second metal layer to form a source electrode and a drain electrode;
  • Step S324 peeling off the third photoresist layer
  • Step S325 depositing a passivation layer on the gate insulating layer.
  • the step S350 includes:
  • the first photoresist region and the second photoresist region are subjected to ashing treatment using a second plasma, the second plasma being oxygen.
  • the step S360 includes:
  • the portions of the first photoresist region and a portion of the second photoresist region are subjected to a hydrophobic treatment using a first plasma to form a hydrophobic group on the surface of the photoresist, the hydrophobic group being a hydrocarbon group having no affinity for water.
  • the first plasma is one or a mixture of one of nitrogen tetrafluoride, sulfur hexafluoride, and oxygen.
  • the method before performing the stripping process on the portion of the first photoresist region and the portion of the second photoresist region, the method further includes the steps of:
  • a solution type OLED material is coated on the transparent metal layer on the surface of the substrate.
  • the etching process is dry etching.
  • the first reticle process and the second reticle process are halftone reticle or grayscale reticle.
  • the beneficial effects of the present invention are: compared with the prior art, the present invention performs hydrophobic treatment on the photoresist surface in the third mask process, so that the transparent metal and the OLED material do not cover the photoresist surface, which is convenient for photoresist.
  • the peeling improves the peeling efficiency and the process efficiency; and the presence of the photoresist enables the OLED material to form a fixed pattern, which saves a mask and reduces the manufacturing cost.
  • FIG. 1 is a flow chart of a method of fabricating a thin film transistor array substrate according to an embodiment of the present invention
  • FIGS. 2A to 2G are process flowcharts of a method for fabricating a thin film transistor array substrate according to an embodiment of the present invention
  • FIG. 3 is a flow chart of a method for manufacturing a thin film transistor array substrate according to Embodiment 2 of the present invention.
  • 4A to 4H are process flow diagrams of a method for fabricating a thin film transistor array substrate according to a second embodiment of the present invention.
  • the present invention proposes a method for manufacturing a thin film transistor in the prior art 3Mask technology, in which the photoresist is difficult to be peeled off after being covered by ITO, resulting in a poor peeling effect and low efficiency, and the present embodiment can improve the defect.
  • FIG. 1 is a flow chart of a method for fabricating a thin film transistor array substrate according to an embodiment of the present invention, the method comprising the steps of:
  • step S110 the gate and the gate line of the thin film transistor are formed on the surface of the substrate by using the first photomask.
  • a first metal layer film is deposited on the glass substrate 101 by a magnetron sputtering process
  • the metal material can generally be a metal such as molybdenum, aluminum, aluminum-nickel alloy, molybdenum-tungsten alloy, chromium, or copper.
  • a combination structure of several materials of the above materials may also be used;
  • a second photoresist layer is coated on the first metal layer film, and the gate electrode 102 is formed on the substrate by a patterning process of exposure, development, etching, and stripping using a mask.
  • Step S120 forming a gate insulating layer, an active layer, a source electrode, a drain electrode, and a passivation layer of the thin film transistor on the surface of the substrate using a second photomask.
  • the gate insulating layer 103 is deposited on the glass substrate 101 by using a chemical method; in the embodiment, the material of the gate insulating layer 103 is silicon nitride, and silicon oxide, silicon oxynitride or the like may also be used;
  • a metal oxide film may be deposited on the gate insulating layer 103 as an active layer by a sputtering method; finally, a second metal layer may be deposited on the active layer by a magnetron sputtering process;
  • a passivation layer 106 is deposited on the glass substrate 101.
  • the passivation layer material is typically a tantalum nitride compound.
  • Step S130 applying a first photoresist layer on the passivation layer, exposing the first photoresist layer by using a gray tone mask or a semi-transparent mask, and patterning the photoresist to form mutual The separated first photoresist region and second photoresist region.
  • a first photoresist layer is coated on the surface of the passivation layer 106, and the photoresist is exposed by a gray tone mask or a semi-transparent mask to form a photoresist completely reserved region after development.
  • a semi-reserved area and a completely removed area in this embodiment, the photoresist completely removed area corresponds to the passivation layer burrowing portion, and the photoresist completely reserved area corresponds to the first photoresist area 107, the light
  • the resistive full retention region corresponds to the second photoresist region 108.
  • Step S140 removing a portion of the passivation layer that is not covered by the first photoresist region and the second photoresist region by an etching process to form a passivation layer via hole to expose the drain.
  • the portion of the passivation layer 106 that is not covered by the first photoresist region 107 and the second photoresist region 108 is removed by an etching process to form a passivation layer via hole to expose The drain; in this embodiment, the etching process is dry etching.
  • Step S150 performing ashing processing on the first photoresist region and the second photoresist region, and retaining a portion of the first photoresist region and a portion of the second photoresist region.
  • the second photoresist region includes a first photoresist sub-region and a second photoresist sub-region, and the first photoresist sub-region has a thickness smaller than the second The thickness of the photoresist subregion;
  • ashing the first photoresist region and the second photoresist region on the surface of the glass substrate by using a second plasma removing the first photoresist subregion of the second photoresist region and reducing the second photoresist a thickness of the region, forming a portion of the second photoresist region; reducing a thickness of the first photoresist region to form a portion of the first photoresist region; in the embodiment, preferably, the second used by the ashing process
  • the plasma is oxygen.
  • Step S160 performing hydrophobic treatment on the surfaces of the portion of the first photoresist region and the portion of the second photoresist region.
  • the specific steps include: performing hydrophobic treatment on the surface of the portion of the first photoresist region and the portion of the second photoresist region by using the first plasma, so that the portion of the first photoresist region and the portion of the second portion are as shown in FIG. 2E a surface of the photoresist region forms a hydrophobic group 110; the hydrophobic group 110 is a hydrocarbon group having no affinity for water;
  • the first plasma of the hydrophobic treatment is one or a mixture of one or more of a gas such as nitrogen tetrafluoride, sulfur hexafluoride or oxygen.
  • Step S170 coating a solution-type transparent metal on the passivation layer not covered by the portion of the first photoresist region and a portion of the second photoresist region, and curing the solution-type transparent metal to form a connection between the drain and the drain.
  • Extreme pixel electrode coating a solution-type transparent metal on the passivation layer not covered by the portion of the first photoresist region and a portion of the second photoresist region, and curing the solution-type transparent metal to form a connection between the drain and the drain.
  • the specific steps include: coating a solution-type transparent metal on the surface of the glass substrate 101 as shown in FIG. 2F; and due to the presence of hydrophobic moieties on the surface of the portion of the first photoresist region and a portion of the second photoresist region 110, The transparent metal solution will be covered in a place where there is no photoresist; the solvent in the transparent metal solution is removed by baking or the like, and the solution-type transparent metal is subjected to a curing treatment to form a pixel electrode connected to the drain.
  • Step S180 performing a stripping process on the portion of the first photoresist region and the portion of the second photoresist region.
  • the specific steps include: performing a stripping process on the portion of the first photoresist region and a portion of the second photoresist region on the glass substrate 101, removing the photoresist on the surface of the glass substrate 101, and forming a pixel electrode, as shown in FIG. 2G. Pattern 111;
  • the stripping method employs a photoresist stripping solution.
  • FIG. 3 is a flow chart showing a method of fabricating a thin film transistor array substrate according to a second embodiment of the present invention, the method comprising the steps of:
  • step S210 the gate and the gate line of the thin film transistor are formed on the surface of the substrate by using the first photomask.
  • a first metal layer film is deposited on the glass substrate 201 by a magnetron sputtering process, and the metal material can generally be a metal such as molybdenum, aluminum, aluminum-nickel alloy, molybdenum-tungsten alloy, chromium, or copper. , a combination structure of several materials of the above materials may also be used;
  • a second photoresist layer is coated on the first metal layer film, and a gate 202 is formed on the substrate by a patterning process of exposure, development, etching, and stripping using a mask.
  • Step S220 forming a gate insulating layer, an active layer, a source electrode, a drain electrode, and a passivation layer of the thin film transistor on the surface of the substrate using a second photomask.
  • the gate insulating layer 203 is deposited on the glass substrate 201 by using a chemical method; in this embodiment, the material of the gate insulating layer 203 is silicon nitride, and silicon oxide, silicon oxynitride or the like may also be used;
  • a metal oxide film may be deposited on the gate insulating layer 203 as an active layer by a sputtering method; finally, a second metal layer may be deposited on the active layer by a magnetron sputtering process;
  • a passivation layer 206 is deposited on the glass substrate 201.
  • the passivation layer material is typically a tantalum nitride compound.
  • Step S230 applying a first photoresist layer on the passivation layer, exposing the first photoresist layer by using a gray tone mask or a semi-transparent mask, and patterning the photoresist to form mutual The separated first photoresist region and second photoresist region.
  • a first photoresist layer is coated on the surface of the passivation layer 206, and the photoresist is exposed by a gray tone mask or a semi-transparent mask to form a photoresist completely reserved region after development.
  • a semi-reserved area and a completely removed area in this embodiment, the photoresist completely removed area corresponds to the passivation layer burrowing portion, and the photoresist completely reserved area corresponds to the first photoresist area 207, the light
  • the resistive full retention region corresponds to the second photoresist region 208.
  • Step S240 removing a portion of the passivation layer that is not covered by the first photoresist region and the second photoresist region by an etching process to form a passivation layer via hole to expose the drain.
  • a portion of the passivation layer 206 that is not covered by the first photoresist region 207 and the second photoresist region 208 is removed by an etching process to form a passivation layer via hole to expose The drain; in this embodiment, the etching process is dry etching.
  • Step S250 performing ashing treatment on the first photoresist region and the second photoresist region, and retaining a portion of the first photoresist region and a portion of the second photoresist region.
  • the second photoresist region includes a first photoresist sub-region and a second photoresist sub-region, and the first photoresist sub-region has a thickness smaller than the second The thickness of the photoresist subregion;
  • ashing the first photoresist region and the second photoresist region on the surface of the glass substrate by using a second plasma removing the first photoresist subregion of the second photoresist region and reducing the second photoresist a thickness of the region, forming a portion of the second photoresist region; reducing a thickness of the first photoresist region to form a portion of the first photoresist region; in the embodiment, preferably, the second used by the ashing process
  • the plasma is oxygen.
  • Step S260 performing hydrophobic treatment on the surface of the portion of the first photoresist region and the portion of the second photoresist region.
  • the specific steps include: performing hydrophobic treatment on the surfaces of the portion of the first photoresist region and the portion of the second photoresist region by using the first plasma, so that the portion of the first photoresist region and the portion of the second portion are as shown in FIG. 4E a surface of the photoresist region forms a hydrophobic group 210; the hydrophobic group 210 is a hydrocarbon group having no affinity for water;
  • the first plasma of the hydrophobic treatment is one or a mixture of one or more of a gas such as nitrogen tetrafluoride, sulfur hexafluoride or oxygen.
  • Step S270 coating a solution-type transparent metal on the passivation layer not covered by the portion of the first photoresist region and a portion of the second photoresist region, and curing the solution-type transparent metal to form the connection.
  • Extreme pixel electrode coating a solution-type transparent metal on the passivation layer not covered by the portion of the first photoresist region and a portion of the second photoresist region, and curing the solution-type transparent metal to form the connection.
  • the specific steps include: coating a solution-type transparent metal on the surface of the glass substrate 201 as shown in FIG. 4F; and due to the presence of hydrophobic groups on the surface of the portion of the first photoresist region and a portion of the second photoresist region 210, The transparent metal solution will be covered in a place where there is no photoresist; the solvent in the transparent metal solution is removed by baking or the like, and the solution-type transparent metal is subjected to a curing treatment to form a pixel electrode connected to the drain.
  • Step S280 coating a solution type OLED material on the transparent metal layer on the surface of the substrate.
  • the specific steps include: coating the solution type OLED material on the surface of the substrate by inkjet printing; the solution is present due to the presence of the hydrophobic portion of the portion of the first photoresist region and a portion of the second photoresist region
  • the OLED material does not cover the photoresist surface; and the photoresist is present such that the OLED material in the recess can fix the OLED pattern 212; finally, the solvent in the solution OLED material is removed by baking or the like.
  • Step S290 performing a stripping process on the portion of the first photoresist region and the portion of the second photoresist region.
  • the specific steps include: performing a stripping process on the portion of the first photoresist region and a portion of the second photoresist region on the glass substrate 201, removing the photoresist on the surface of the glass substrate 201, and forming a pixel electrode, as shown in FIG. 4G. Pattern 211;
  • the stripping method employs a photoresist stripping solution.
  • the present invention provides a method of fabricating a thin film transistor array substrate.
  • the present invention is a typical 3Mask process that saves a Mask by completing the passivation layer and the pixel electrode in a single Mask.
  • the main features are:
  • the invention performs hydrophobic treatment on the photoresist surface, so that the solution-type transparent metal and the OLED material do not cover the photoresist surface, facilitate the peeling of the photoresist, and improve the stripping efficiency and the process efficiency; the existence of the photoresist enables the OLED material to be fixed.
  • the pattern saves a mask and reduces the cost of production.

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Abstract

一种薄膜晶体管阵列基板的制造方法，在第三道光罩工艺中，对光阻表面进行疏水性处理，形成疏水性基团（110、210）；而疏水性基团（110、210）的存在，使得溶液型透明金属和OLED材料不会覆盖在光阻表面，便于光阻的剥离，使得剥离效率以及制程效率提高；而光阻的存在使得OLED材料能形成固定的图案（212），节省了一道光罩，降低了制作成本。

Description

一种薄膜晶体管阵列基板的制造方法 技术领域
本发明涉及平板显示器制造技术领域，特别涉及一种薄膜晶体管阵列基板的制造方法。
 背景技术
LCD(Liquid crystal displays，液晶显示器)是一种被广泛应用的平板显示器，主要是通过液晶开关调制背光源光场强度来实现画面显示。而OLED (Organic Light Emitting Diode，有机发光二极管)器件由于自发光、全固态、宽视角、响应快等优点，在平板显示产品中有巨大应用前景，甚至被认为是继LCD、PDP (plasma display panel，等离子)之后的新一代的平板显示产品。
LCD和OLED显示装置中均包括TFT（Thin Film Transistor，薄膜晶体管）器件。在工艺上，薄膜晶体管制程一般采用五道光罩（5mask），过多的光罩次数会增加制程成本，同时也会增大生产时间，使生产效率大大降低。为了达到缩减光罩数量的目的，很多公司纷纷发展四道光罩（4mask）技术，将AS（有源层）和S/D(源漏极)用一道HTM（半色调光罩）或GTM（灰阶光罩）同时形成。HTM或GTM光罩可以使光阻得到两种不同的膜厚，这两种膜厚分别可以用来定义AS和SD的图案。
为了进一步缩减光罩数量，采用Lift-off（剥离工艺）制程可以将ITO（透明金属层）和PV（钝化层）用一张光罩同时形成，从而使总光罩数量减小至三张（3mask）。但传统的3mask制程多数只针对TN（Twisted Nematic，扭曲向列型）模式，ITO并不形成狭缝图形；或者ITO形成狭缝图形，但因ITO只能沉积于挖洞处，使所有ITO层（包括像素区）都处在氮矽化合物的凹槽中，ITO横向电场减弱，影响液晶显示效果，形成使显示器亮度不均匀。随着技术的发展，改进后的3mask技术PV/ITO层使用一张HTM或GTM光罩形成，使像素区的ITO既能形成狭缝，又能覆盖在PV层上方，形成与4mask完全一样的结构。
而此3mask技术难点在于光阻被ITO覆盖后难以被剥离，使剥离效果差，效率低。另外，光阻剥离残留和毛边问题都会严重影响制程或产品性能。
 技术问题
本发明提供一种薄膜晶体管阵列基板的制造方法，以解决薄膜晶体管阵列基板的制造过程中光阻因被透明金属层覆盖而难以被剥离的问题。
 技术解决方案
为实现上述目的，本发明提供的技术方案如下：
本发明提供了一种薄膜晶体管阵列基板制造方法，所述制造方法包括：
步骤S110，使用第一光罩，在基板表面形成薄膜晶体管的栅极与栅线；
步骤S120，使用第二光罩，在所述基板表面形成所述薄膜晶体管的栅极绝缘层、有源层、源电极、漏电极以及钝化层；
步骤S130，在所述钝化层上涂布第一光阻层，采用灰色调掩模板或半透式掩模板对所述第一光阻层进行曝光，使所述光阻图案化，形成相互分离的第一光阻区域和第二光阻区域；
步骤S140，通过蚀刻工艺移除所述钝化层中未被所述第一光阻区域和所述第二光阻区域覆盖的部分，形成钝化层过孔，以露出漏极；
步骤S150，对所述第一光阻区域和所述第二光阻区域进行灰化处理，保留部分第一光阻区域和部分第二光阻区域；
所述第二光阻区域包括相互连接的第一光阻子区域和第二光阻子区域，所述第一光阻子区域的厚度小于所述第二光阻子区域的厚度；
所述对所述第一光阻区域和所述第二光阻区域进行灰化处理的步骤包括：去除第二光阻区域的第一光阻子区域并减少所述第二光阻子区域的厚度，形成部分第二光阻区域；减少所述第一光阻区域的厚度，形成部分第一光阻区域。
步骤S160，对所述部分第一光阻区域和部分第二光阻区域的表面进行疏水处理；
步骤S170，在未被所述部分第一光阻区域和部分第二光阻区域覆盖的钝化层上涂布溶液型透明金属，对所述溶液型透明金属进行固化处理，形成连接所述漏极的像素电极；
步骤S180，对所述部分第一光阻区域和部分第二光阻区域进行剥离处理。
根据本发明一优选实施例，所述步骤S110包括：
步骤S111，提供一基板，在所述基板表面沉积第一金属层；
步骤S112，在所述第一金属层上涂布第二光阻层；
步骤S113，所述第二光阻层经曝光、显影后，对所述第一金属层进行蚀刻，，形成所述薄膜晶体管的所述栅极和所述栅线；
步骤S114，剥离第二光阻层。
根据本发明一优选实施例，所述步骤S120包括：
步骤S121，在所述基板表面依次沉积栅极绝缘层、有源层以及第二金属层；
步骤S122，在所述第二金属层上涂布第三光阻层；
步骤S123，所述第三光阻层经曝光、显影后，对所述第二金属层进行蚀刻，形成源电极和漏电极；
步骤S124，剥离第三光阻层；
步骤S125，在所述栅极绝缘层上沉积钝化层。
根据本发明一优选实施例，所述步骤S150包括：
使用第二等离子体对所述第一光阻区域和所述第二光阻区域进行灰化处理，所述第二等离子体为氧气。
根据本发明一优选实施例，所述步骤S160包括：
使用第一等离子体对所述部分第一光阻区域和部分第二光阻区域表面作疏水处理，使光阻表面形成疏水性基团，所述疏水性基团为对水无亲和力的烃基。
根据本发明一优选实施例，所述第一等离子体为四氟化氮、六氟化硫、氧气中的一种或者一种以上的混合体。
根据本发明一优选实施例，对所述部分第一光阻区域和部分第二光阻区域进行剥离处理之前，还包括步骤：
在所述基板表面的透明金属层上涂布溶液型OLED材料。
根据本发明一优选实施例，所述刻蚀工艺为干刻。
根据本发明一优选实施例，所述第一道光罩工艺和所述第二道光罩工艺为半色调光罩或灰阶光罩。
本发明还提供了一种薄膜晶体管阵列基板制造方法，所述制造方法包括：
步骤S310，使用第一光罩，在基板表面形成薄膜晶体管的栅极与栅线；
步骤S320，使用第二光罩，在所述基板表面形成所述薄膜晶体管的栅极绝缘层、有源层、源电极、漏电极以及钝化层；
步骤S330，在所述钝化层上涂布第一光阻层，采用灰色调掩模板或半透式掩模板对所述第一光阻层进行曝光，使所述光阻图案化，形成相互分离的第一光阻区域和第二光阻区域；
步骤S340，通过蚀刻工艺移除所述钝化层中未被所述第一光阻区域和所述第二光阻区域覆盖的部分，形成钝化层过孔，以露出漏极；
步骤S350，对所述第一光阻区域和所述第二光阻区域进行灰化处理，保留部分第一光阻区域和部分第二光阻区域；
步骤S360，对所述部分第一光阻区域和部分第二光阻区域的表面进行疏水处理；
步骤S370，在未被所述部分第一光阻区域和部分第二光阻区域覆盖的钝化层上涂布溶液型透明金属，对所述溶液型透明金属进行固化处理，形成连接所述漏极的像素电极；
步骤S380，对所述部分第一光阻区域和部分第二光阻区域进行剥离处理。
根据本发明一优选实施例，所述步骤S310包括：
步骤S311，提供一基板，在所述基板表面沉积第一金属层；
步骤S312，在所述第一金属层上涂布第二光阻层；
步骤S313，所述第二光阻层经曝光、显影后，对所述第一金属层进行蚀刻，，形成所述薄膜晶体管的所述栅极和所述栅线；
步骤S314，剥离第二光阻层。
根据本发明一优选实施例，所述步骤S320包括：
步骤S321，在所述基板表面依次沉积栅极绝缘层、有源层以及第二金属层；
步骤S322，在所述第二金属层上涂布第三光阻层；
步骤S323，所述第三光阻层经曝光、显影后，对所述第二金属层进行蚀刻，形成源电极和漏电极；
步骤S324，剥离第三光阻层；
步骤S325，在所述栅极绝缘层上沉积钝化层。
根据本发明一优选实施例，所述步骤S350包括：
使用第二等离子体对所述第一光阻区域和所述第二光阻区域进行灰化处理，所述第二等离子体为氧气。
根据本发明一优选实施例，所述步骤S360包括：
使用第一等离子体对所述部分第一光阻区域和部分第二光阻区域表面作疏水处理，使光阻表面形成疏水性基团，所述疏水性基团为对水无亲和力的烃基。
根据本发明一优选实施例，所述第一等离子体为四氟化氮、六氟化硫、氧气中的一种或者一种以上的混合体。
根据本发明一优选实施例，对所述部分第一光阻区域和部分第二光阻区域进行剥离处理之前，还包括步骤：
在所述基板表面的透明金属层上涂布溶液型OLED材料。
根据本发明一优选实施例，所述刻蚀工艺为干刻。
根据本发明一优选实施例，所述第一道光罩工艺和所述第二道光罩工艺为半色调光罩或灰阶光罩。
 有益效果
本发明的有益效果为：相比于现有技术，本发明在第三道光罩工艺中，对光阻表面进行疏水处理，使得透明金属和OLED材料不会覆盖在光阻表面，便于光阻的剥离，使得剥离效率以及制程效率提高；而光阻的存在使得OLED材料能形成固定的图案，节省了一道光罩，降低了制作成本。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明实施例一薄膜晶体管阵列基板的制造方法流程图；
图2A至2G为本发明实施例一薄膜晶体管阵列基板制造方法工艺流程图；
图3为本发明实施例二薄膜晶体管阵列基板的制造方法流程图；
图4A至4H为本发明实施例二薄膜晶体管阵列基板制造方法工艺流程图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图示，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是用以相同标号表示。
本发明针对现有3Mask技术中，因光阻被ITO覆盖后难以被剥离而导致剥离效果差、效率低等问题，而提出了一种薄膜晶体管的制造方法，本实施例能够改善该缺陷。
图1为本发明实施例一薄膜晶体管阵列基板的制造方法流程图，所述方法包括步骤：
步骤S110，使用第一光罩，在基板表面形成薄膜晶体管的栅极与栅线。
具体包括：如图2A所示，在玻璃基板101上利用磁控溅射工艺沉积第一金属层薄膜，金属材料通常可以采用钼、铝、铝镍合金、钼钨合金、铬、或铜等金属，也可以使用上述几种材料薄膜的组合结构；
然后，在第一金属层薄膜上涂布第二光阻层，采用掩模板通过曝光、显影、蚀刻、剥离的构图工艺处理，在基板上形成栅极102。
步骤S120，使用第二光罩，在所述基板表面形成所述薄膜晶体管的栅极绝缘层、有源层、源电极、漏电极以及钝化层。
具体包括：利用化学方法在玻璃基板101上沉积栅极绝缘层103；在本实施例中，所述栅极绝缘层103的材料为氮化硅，也可以使用氧化硅和氮氧化硅等；
然后，可以通过溅射方法，在所述栅极绝缘层103上沉积金属氧化物薄膜作为有源层；最后，可以采用磁控溅射工艺，在所述有源层沉积第二金属层；
在形成栅极绝缘层103、有源层、第二金属层的基板上涂布第三光阻层；利用灰色调掩模板或半透式掩模板对所述第三光阻层进行曝光、显影后，对所述第二金属层进行蚀刻工艺；最后，将所述光阻剥离，形成源漏极105和有源层图案104；其中，所述第二道光罩为半色调光罩或灰阶光罩。
最后，在所述玻璃基板101上沉积钝化层106，优选的，所述钝化层材料通常为氮化矽化合物。
步骤S130，在所述钝化层上涂布第一光阻层，采用灰色调掩模板或半透式掩模板对所述第一光阻层进行曝光，使所述光阻图案化，形成相互分离的第一光阻区域和第二光阻区域。
具体包括：如图2B所示，在所述钝化层106表面涂布第一光阻层，利用灰色调掩模板或半透式掩模板对光阻进行曝光，显影后形成光阻完全保留区域、半保留区域和完全去除区域；在本实施例中，所述光阻完全去除区域对应钝化层挖洞处，所述光阻完全保留区域对应所述第一光阻区域107，所述光阻完全保留区域对应所述第二光阻区域108。
步骤S140，通过蚀刻工艺移除所述钝化层中未被所述第一光阻区域和所述第二光阻区域覆盖的部分，形成钝化层过孔，以露出漏极。
具体包括：如图2C所示，利用蚀刻工艺蚀移除所述钝化层106中未被第一光阻区域107和第二光阻区域108覆盖的部分，形成钝化层过孔，以露出漏极；在本实施例中，该蚀刻工艺为干刻。
步骤S150，对所述第一光阻区域和所述第二光阻区域进行灰化处理，保留部分第一光阻区域和部分第二光阻区域。
具体步骤包括：如图2D所示，所述第二光阻区域包括相互连接的第一光阻子区域和第二光阻子区域，所述第一光阻子区域的厚度小于所述第二光阻子区域的厚度；
利用第二等离子体对所述玻璃基板表面的第一光阻区域和第二光阻区域进行灰化处理：去除第二光阻区域的第一光阻子区域并减少所述第二光阻子区域的厚度，形成部分第二光阻区域；减少所述第一光阻区域的厚度，形成部分第一光阻区域；在本实施例中，优选的，所述灰化处理所使用的第二等离子体为氧气。
步骤S160，对所述部分第一光阻区域和部分第二光阻区域的表面进行疏水处理。
具体步骤包括：如图2E所示，利用第一等离子体对所述部分第一光阻区域和部分第二光阻区域的表面进行疏水处理，使所述部分第一光阻区域和部分第二光阻区域表面形成疏水性基团110；所述疏水性基团110为对水无亲和力的烃基；
所述疏水处理的第一等离子体为四氟化氮、六氟化硫、氧气等气体中的一种或者一种以上的混合体。
步骤S170，在未被所述部分第一光阻区域和部分第二光阻区域覆盖的钝化层上涂布溶液型透明金属，对所述溶液型透明金属进行固化处理，形成连接所述漏极的像素电极。
具体步骤包括：如图2F所示，在所述玻璃基板101表面涂布溶液型透明金属；而由于所述部分第一光阻区域和部分第二光阻区域110表面疏水性基团的存在，透明金属溶液将覆盖在没有光阻的地方；再用烘烤等方法去除透明金属溶液中的溶剂，并所述溶液型透明金属进行固化处理，形成连接所述漏极的像素电极。
步骤S180，对所述部分第一光阻区域和部分第二光阻区域进行剥离处理。
具体步骤包括：如图2G所示，对所述玻璃基板101上的所述部分第一光阻区域和部分第二光阻区域作剥离处理，移除玻璃基板101表面的光阻，形成像素电极图案111；在本实施例中，该剥离方式采用光阻剥离液。
至此，整个薄膜晶体管阵列基板基本构架已经完成，此薄膜晶体管阵列基板制造过程也可以根据实际情况稍作改变。
图3所示为本发明实施例二薄膜晶体管阵列基板的制造方法流程图，所述方法包括步骤：
步骤S210，使用第一光罩，在基板表面形成薄膜晶体管的栅极与栅线。
具体包括：如图4A所示，在玻璃基板201上利用磁控溅射工艺沉积第一金属层薄膜，金属材料通常可以采用钼、铝、铝镍合金、钼钨合金、铬、或铜等金属，也可以使用上述几种材料薄膜的组合结构；
然后，在第一金属层薄膜上涂布第二光阻层，采用掩模板通过曝光、显影、蚀刻、剥离的构图工艺处理，在基板上形成栅极202。
步骤S220，使用第二光罩，在所述基板表面形成所述薄膜晶体管的栅极绝缘层、有源层、源电极、漏电极以及钝化层。
具体包括：利用化学方法在玻璃基板201上沉积栅极绝缘层203；在本实施例中，所述栅极绝缘层203的材料为氮化硅，也可以使用氧化硅和氮氧化硅等；
然后，可以通过溅射方法，在所述栅极绝缘层203上沉积金属氧化物薄膜作为有源层；最后，可以采用磁控溅射工艺，在所述有源层沉积第二金属层；
在形成栅极绝缘层203、有源层、第二金属层的基板上涂布第三光阻层；利用灰色调掩模板或半透式掩模板对所述第三光阻层进行曝光、显影后，对所述第二金属层进行蚀刻工艺；最后，将所述光阻剥离，形成源漏极205和有源层图案204；其中，所述第二道光罩为半色调光罩或灰阶光罩。
最后，在所述玻璃基板201上沉积钝化层206，优选的，所述钝化层材料通常为氮化矽化合物。
步骤S230，在所述钝化层上涂布第一光阻层，采用灰色调掩模板或半透式掩模板对所述第一光阻层进行曝光，使所述光阻图案化，形成相互分离的第一光阻区域和第二光阻区域。
具体包括：如图4B所示，在所述钝化层206表面涂布第一光阻层，利用灰色调掩模板或半透式掩模板对光阻进行曝光，显影后形成光阻完全保留区域、半保留区域和完全去除区域；在本实施例中，所述光阻完全去除区域对应钝化层挖洞处，所述光阻完全保留区域对应所述第一光阻区域207，所述光阻完全保留区域对应所述第二光阻区域208。
步骤S240，通过蚀刻工艺移除所述钝化层中未被所述第一光阻区域和所述第二光阻区域覆盖的部分，形成钝化层过孔，以露出漏极。
具体包括：如图4C所示，利用蚀刻工艺蚀移除所述钝化层206中未被第一光阻区域207和第二光阻区域208覆盖的部分，形成钝化层过孔，以露出漏极；在本实施例中，该蚀刻工艺为干刻。
步骤S250，对所述第一光阻区域和所述第二光阻区域进行灰化处理，保留部分第一光阻区域和部分第二光阻区域。
具体步骤包括：如图4D所示，所述第二光阻区域包括相互连接的第一光阻子区域和第二光阻子区域，所述第一光阻子区域的厚度小于所述第二光阻子区域的厚度；
利用第二等离子体对所述玻璃基板表面的第一光阻区域和第二光阻区域进行灰化处理：去除第二光阻区域的第一光阻子区域并减少所述第二光阻子区域的厚度，形成部分第二光阻区域；减少所述第一光阻区域的厚度，形成部分第一光阻区域；在本实施例中，优选的，所述灰化处理所使用的第二等离子体为氧气。
步骤S260，对所述部分第一光阻区域和部分第二光阻区域的表面进行疏水处理。
具体步骤包括：如图4E所示，利用第一等离子体对所述部分第一光阻区域和部分第二光阻区域的表面进行疏水处理，使所述部分第一光阻区域和部分第二光阻区域表面形成疏水性基团210；所述疏水性基团210为对水无亲和力的烃基；
所述疏水处理的第一等离子体为四氟化氮、六氟化硫、氧气等气体中的一种或者一种以上的混合体。
步骤S270，在未被所述部分第一光阻区域和部分第二光阻区域覆盖的钝化层上涂布溶液型透明金属，对所述溶液型透明金属进行固化处理，形成连接所述漏极的像素电极。
具体步骤包括：如图4F所示，在所述玻璃基板201表面涂布溶液型透明金属；而由于所述部分第一光阻区域和部分第二光阻区域210表面疏水性基团的存在，透明金属溶液将覆盖在没有光阻的地方；再用烘烤等方法去除透明金属溶液中的溶剂，并所述溶液型透明金属进行固化处理，形成连接所述漏极的像素电极。
步骤S280，在所述基板表面的透明金属层上涂布溶液型OLED材料。
具体步骤包括：在所述基板表面上，使用喷墨打印方式涂布溶液型OLED材料；由于所述部分第一光阻区域和部分第二光阻区域表面疏水性基团的存在，所述溶液型OLED材料不会覆盖在所述光阻表面；并且，光阻的存在，使得凹槽内的OLED材料能固定的OLED图案212；最后，再用烘烤等方法去除溶液型OLED材料中的溶剂。
步骤S290，对所述部分第一光阻区域和部分第二光阻区域进行剥离处理。
具体步骤包括：如图4G所示，对所述玻璃基板201上的所述部分第一光阻区域和部分第二光阻区域作剥离处理，移除玻璃基板201表面的光阻，形成像素电极图案211；在本实施例中，该剥离方式采用光阻剥离液。
本发明提供了一种薄膜晶体管阵列基板的制造方法。参照本发明的较佳实施例，本发明为典型的3Mask制程，通过把钝化层和像素电极在一道Mask内完成而节约一道Mask。主要特征为：
本发明对光阻表面进行疏水处理，使得溶液型透明金属和OLED材料不会覆盖在光阻表面，便于光阻的剥离，使得剥离效率以及制程效率提高；光阻的存在使得OLED材料能形成固定的图案，节省了一道光罩，降低了制作成本。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (18)

  1. 一种薄膜晶体管阵列基板的制造方法，其中，所述方法包括：
    步骤S110，使用第一光罩，在基板表面形成薄膜晶体管的栅极与栅线；
    步骤S120，使用第二光罩，在所述基板表面形成所述薄膜晶体管的栅极绝缘层、有源层、源电极、漏电极以及钝化层；
    步骤S130，在所述钝化层上涂布第一光阻层，采用灰色调掩模板或半透式掩模板对所述第一光阻层进行曝光，使所述光阻图案化，形成相互分离的第一光阻区域和第二光阻区域；
    步骤S140，通过蚀刻工艺移除所述钝化层中未被所述第一光阻区域和所述第二光阻区域覆盖的部分，形成钝化层过孔，以露出漏极；
    步骤S150，对所述第一光阻区域和所述第二光阻区域进行灰化处理，保留部分第一光阻区域和部分第二光阻区域；
    所述第二光阻区域包括相互连接的第一光阻子区域和第二光阻子区域，所述第一光阻子区域的厚度小于所述第二光阻子区域的厚度；
    所述对所述第一光阻区域和所述第二光阻区域进行灰化处理的步骤包括：去除第二光阻区域的第一光阻子区域并减少所述第二光阻子区域的厚度，形成部分第二光阻区域；减少所述第一光阻区域的厚度，形成部分第一光阻区域。
    步骤S160，对所述部分第一光阻区域和部分第二光阻区域的表面进行疏水处理；
    步骤S170，在未被所述部分第一光阻区域和部分第二光阻区域覆盖的钝化层上涂布溶液型透明金属，对所述溶液型透明金属进行固化处理，形成连接所述漏极的像素电极；
    步骤S180，对所述部分第一光阻区域和部分第二光阻区域进行剥离处理。
  2. 根据权利要求1所述的制造方法，其中，所述步骤S110包括：
    步骤S111，提供一基板，在所述基板表面沉积第一金属层；
    步骤S112，在所述第一金属层上涂布第二光阻层；
    步骤S113，所述第二光阻层经曝光、显影后，对所述第一金属层进行蚀刻，，形成所述薄膜晶体管的所述栅极和所述栅线；
    步骤S114，剥离第二光阻层。
  3. 根据权利要求1所述的制造方法，其中，所述步骤S120包括：
    步骤S121，在所述基板表面依次沉积栅极绝缘层、有源层以及第二金属层；
    步骤S122，在所述第二金属层上涂布第三光阻层；
    步骤S123，所述第三光阻层经曝光、显影后，对所述第二金属层进行蚀刻，形成源电极和漏电极；
    步骤S124，剥离第三光阻层；
    步骤S125，在所述栅极绝缘层上沉积钝化层。
  4. 根据权利要求1所述的制造方法，其中，所述步骤S150包括：
    使用第二等离子体对所述第一光阻区域和所述第二光阻区域进行灰化处理，所述第二等离子体为氧气。
  5. 根据权利要求1所述的制造方法，其中，所述步骤S160包括：
    使用第二等离子体对所述部分第一光阻区域和部分第二光阻区域表面作疏水处理，使光阻表面形成疏水性基团，所述疏水性基团为对水无亲和力的烃基。
  6. 根据权利要求5所述的制造方法，其中，所述第一等离子体为四氟化氮、六氟化硫、氧气中的一种或者一种以上的混合体。
  7. 根据权利要求1所述的制造方法，其中，对所述部分第一光阻区域和部分第二光阻区域进行剥离处理之前，还包括步骤：
    在所述基板表面的透明金属层上涂布溶液型OLED材料。
  8. 根据权利要求2所述的制造方法，其中，所述刻蚀工艺为干刻。
  9. 根据权利要求1所述的制造方法，其中，所述第一道光罩工艺和所述第二道光罩工艺为半色调光罩或灰阶光罩。
  10. 一种薄膜晶体管阵列基板的制造方法，其中，所述方法包括：
    步骤S310，使用第一光罩，在基板表面形成薄膜晶体管的栅极与栅线；
    步骤S320，使用第二光罩，在所述基板表面形成所述薄膜晶体管的栅极绝缘层、有源层、源电极、漏电极以及钝化层；
    步骤S330，在所述钝化层上涂布第一光阻层，采用灰色调掩模板或半透式掩模板对所述第一光阻层进行曝光，使所述光阻图案化，形成相互分离的第一光阻区域和第二光阻区域；
    步骤S340，通过蚀刻工艺移除所述钝化层中未被所述第一光阻区域和所述第二光阻区域覆盖的部分，形成钝化层过孔，以露出漏极；
    步骤S350，对所述第一光阻区域和所述第二光阻区域进行灰化处理，保留部分第一光阻区域和部分第二光阻区域；
    步骤S360，对所述部分第一光阻区域和部分第二光阻区域的表面进行疏水处理；
    步骤S370，在未被所述部分第一光阻区域和部分第二光阻区域覆盖的钝化层上涂布溶液型透明金属，对所述溶液型透明金属进行固化处理，形成连接所述漏极的像素电极；
    步骤S380，对所述部分第一光阻区域和部分第二光阻区域进行剥离处理。
  11. 根据权利要求10所述的制造方法，其中，所述步骤S310包括：
    步骤S311，提供一基板，在所述基板表面沉积第一金属层；
    步骤S312，在所述第一金属层上涂布第二光阻层；
    步骤S313，所述第二光阻层经曝光、显影后，对所述第一金属层进行蚀刻，，形成所述薄膜晶体管的所述栅极和所述栅线；
    步骤S314，剥离第二光阻层。
  12. 根据权利要求10所述的制造方法，其中，所述步骤S320包括：
    步骤S321，在所述基板表面依次沉积栅极绝缘层、有源层以及第二金属层；
    步骤S322，在所述第二金属层上涂布第三光阻层；
    步骤S323，所述第三光阻层经曝光、显影后，对所述第二金属层进行蚀刻，形成源电极和漏电极；
    步骤S324，剥离第三光阻层；
    步骤S325，在所述栅极绝缘层上沉积钝化层。
  13. 根据权利要求10所述的制造方法，其中，所述步骤S350包括：
    使用第二等离子体对所述第一光阻区域和所述第二光阻区域进行灰化处理，所述第二等离子体为氧气。
  14. 根据权利要求10所述的制造方法，其中，所述步骤S360包括：
    使用第二等离子体对所述部分第一光阻区域和部分第二光阻区域表面作疏水处理，使光阻表面形成疏水性基团，所述疏水性基团为对水无亲和力的烃基。
  15. 根据权利要求14所述的制造方法，其中，所述第一等离子体为四氟化氮、六氟化硫、氧气中的一种或者一种以上的混合体。
  16. 根据权利要求10所述的制造方法，其中，对所述部分第一光阻区域和部分第二光阻区域进行剥离处理之前，还包括步骤：
    在所述基板表面的透明金属层上涂布溶液型OLED材料。
  17. 根据权利要求11所述的制造方法，其中，所述刻蚀工艺为干刻。
  18. 根据权利要求10所述的制造方法，其中，所述第一道光罩工艺和所述第二道光罩工艺为半色调光罩或灰阶光罩。
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