WO2019029182A1 - 阵列基板及其制造方法、显示面板及其制造方法 - Google Patents

阵列基板及其制造方法、显示面板及其制造方法 Download PDF

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Publication number
WO2019029182A1
WO2019029182A1 PCT/CN2018/082961 CN2018082961W WO2019029182A1 WO 2019029182 A1 WO2019029182 A1 WO 2019029182A1 CN 2018082961 W CN2018082961 W CN 2018082961W WO 2019029182 A1 WO2019029182 A1 WO 2019029182A1
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Prior art keywords
area
protective layer
array substrate
metal layer
display area
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PCT/CN2018/082961
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English (en)
French (fr)
Inventor
刘权
张露
韩珍珍
胡思明
朱晖
Original Assignee
昆山国显光电有限公司
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Application filed by 昆山国显光电有限公司 filed Critical 昆山国显光电有限公司
Priority to EP18844428.5A priority Critical patent/EP3667725B1/en
Priority to US16/323,075 priority patent/US20210335839A1/en
Priority to KR1020197019302A priority patent/KR102201113B1/ko
Priority to JP2019537131A priority patent/JP7000437B2/ja
Publication of WO2019029182A1 publication Critical patent/WO2019029182A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/70—Testing, e.g. accelerated lifetime tests
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H10K59/871—Self-supporting sealing arrangements
    • H10K59/8722—Peripheral sealing arrangements, e.g. adhesives, sealants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H10K59/873—Encapsulations

Definitions

  • the present invention relates to the field of flat panel display, and in particular to an array substrate, a method of manufacturing the same, a display panel, and a method of fabricating the same.
  • the display panel has a display area (or active area, AA area) and a non-display area.
  • the display area is configured with a plurality of pixels to form a pixel array
  • the non-display area is provided with a plurality of metal layers to form a peripheral line.
  • Each pixel typically includes at least a thin film transistor and a pixel electrode coupled to the thin film transistor, and each pixel is surrounded by two adjacent scan lines and two adjacent data lines.
  • the scan lines and the data lines extend from the display area to the non-display area, and are electrically connected to the driving chip through the peripheral lines of the non-display area, thereby realizing the normal operation of the display panel.
  • the peripheral line is formed by the end of the connection of the scan line and the data line to the area where the driver chip is located to form a fan-out trace, that is, the plurality of peripheral lines have a larger pitch at one end near the active area, and the end is closer to the drive chip. Small spacing, thus roughly forming a fan shape.
  • An object of the present invention is to provide an array substrate, a method of manufacturing the same, a display panel, and a method of fabricating the same, which can reduce the incidence of lead cracks, and can avoid electrostatic damage of the detection circuit in the bonding area and improve the picture quality of the display panel. .
  • an array substrate comprising:
  • a detection circuit on the substrate substrate, and at least one metal layer deviating from the detection circuit
  • a protective layer covering the metal layer and exposing the detection circuit.
  • the material of the protective layer is one of silicon nitride, silicon oxide, silicon oxynitride or a combination thereof.
  • the array substrate further includes a plurality of input and output terminals formed on the base substrate, and the protective layer exposes the plurality of input and output terminals.
  • the detecting circuit and the plurality of input and output terminals form a binding area, and the exposed area of the protection layer is equal to the binding area or larger than the binding area.
  • the substrate substrate includes a package region; the protective layer covers only the metal layer in the package region.
  • the present invention also provides a method for manufacturing an array substrate, comprising:
  • a protective layer is formed such that the protective layer covers the metal layer and exposes the detection circuit.
  • the method further includes disposing a plurality of input and output terminals on the base substrate, the protective layer exposing the plurality of input and output terminals.
  • the substrate substrate includes a package region; the protective layer covers only the metal layer in the package region.
  • the substrate substrate includes a display area and a non-display area, the package area and the detecting circuit, the plurality of input and output terminals are all located in the non-display area; and the metal layer is simultaneously formed Forming the detecting circuit in the non-display area and forming a plurality of thin film transistors in the display area in the non-display area and the display area, and while forming the metal layer; a protective layer is simultaneously formed in the non-display area and the display area; the step of forming the protective layer further includes: removing the contact in the display area while exposing the protective layer to the detecting circuit A protective layer at the location of the aperture exposes the contact aperture.
  • the present invention further provides a display panel comprising an array substrate and a glass cover, the display panel comprising a display area and a non-display area, the non-display area further comprising a package area and a binding area, the array substrate include:
  • a detection circuit on the substrate substrate, and at least one metal layer deviating from the detection circuit
  • the glass substrate is coated in the package area of the array substrate or the glass cover plate to encapsulate the array substrate and the glass cover plate.
  • the display panel further includes a driver chip bound in the binding area.
  • the material of the protective layer is one of silicon nitride, silicon oxide, silicon oxynitride or a combination thereof.
  • the array substrate further includes a plurality of input and output terminals formed on the base substrate, and the protective layer exposes the plurality of input and output terminals.
  • the detecting circuit and the plurality of input and output terminals are located in the binding area, and the exposed area of the protection layer is equal to the binding area or larger than the binding area.
  • the protective layer covers only the metal layer in the package area.
  • the present invention further provides a method of manufacturing a display panel, the display panel comprising a display area and a non-display area, the non-display area further comprising a package area and a binding area, the method comprising:
  • the array substrate provided by the present invention Compared with the prior art, the array substrate provided by the present invention, the manufacturing method thereof, the display panel and the method of manufacturing the same, after forming at least one metal layer on the base substrate, forming a protective layer on the metal layer, the protection The layer can protect the metal layer, avoid damage to the metal layer when the glass frit in the display panel is subsequently irradiated with laser light, thereby reducing the incidence of lead cracks, and is beneficial to improving the yield of the display panel.
  • the protective layer exposes the detecting circuit, and the electrostatic damage caused by the covering of the detecting circuit due to the cover layer can be avoided, thereby further improving the yield of the display panel.
  • 1 is a partial cross-sectional view of a non-display area of a display panel including a package area;
  • FIG. 2 is a flow chart of a method for fabricating an array substrate according to an embodiment of the present invention
  • FIG. 3 is a partial cross-sectional view of a non-display area including an encapsulation area of an array substrate according to an embodiment of the present invention
  • FIG. 4 is a partial plan view of a non-display area including a binding area of an array substrate according to an embodiment of the present invention
  • FIG. 5 is a schematic diagram showing a positional relationship between a package area and a binding area in a display panel according to an embodiment of the present invention
  • FIG. 6 is a partial cross-sectional view of a non-display area including a package area of a display panel according to an embodiment of the present invention.
  • a display panel such as an OLED (Organic Electroluminescent) display panel, generally includes an array substrate and a glass cover disposed opposite each other.
  • the display panel includes a display area and a non-display area, and a package area is disposed in the non-display area for coating a frit to package the array substrate and the glass cover.
  • FIG. 1 it is a partial structural diagram of a non-display area of a display panel.
  • the display panel includes a substrate substrate 10 and a glass cover 20 disposed opposite each other.
  • a plurality of metal layers are formed on the base substrate 10.
  • FIG. 1 only three metal layers are shown, namely, an underlying metal layer 11, an intermediate metal layer 12, and a top metal layer 13.
  • the three metal layers are separated from each other by the dielectric layer 14, and a frit 15 is directly coated on the top metal layer 13 in the package region, and then the substrate substrate 10 and the glass cover 20 are packaged to form a display panel. .
  • the metal layer such as the underlying metal layer 11, the intermediate metal layer 12, and the top metal layer 13 formed in the non-display area belongs to a fan-out trace, and is used for connecting a driving chip and a data line, a scanning line, and the like in the display area, and driving the chip.
  • the provided electrical signal is transmitted to the data line or scan line.
  • an embodiment of the present application is as follows: after forming at least one metal layer on the base substrate; forming a protective layer on the metal layer.
  • the protective layer can protect the metal layer, and can avoid damage to the metal layer after laser irradiation of the glass frit in the display panel (for example, avoiding cracks in the direction perpendicular to the laser advancement), thereby reducing lead cracking. occur.
  • this method also reduces the bright line defect rate of the display panel, because the damage or crack of the metal layer may cause a certain data line or scan line in the display area to receive no signal or receive signal. Inaccurate, resulting in a bright line on the display panel.
  • a substrate is provided, a detecting circuit is formed on the substrate, and at least one metal layer deviating from the detecting circuit; a protective layer is formed, and the protective layer is covered The metal layer is exposed to the detection circuit.
  • a protective layer is formed on the metal layer, and the protective layer can protect the metal layer from the metal when the glass frit in the display panel is subsequently irradiated with laser light. The damage caused by the layer, thereby reducing the incidence of lead cracks, is conducive to improving the yield of the display panel.
  • the protective layer exposes the detecting circuit, which can avoid electrostatic failure caused by the covering of the detecting circuit due to the covering of the protective layer, and in particular, can eliminate the static charge accumulated in the detecting circuit (CT circuit), thereby The yield of the display panel is further improved.
  • FIG. 2 is a flowchart of a method for fabricating an array substrate according to an embodiment of the present invention.
  • the present invention provides a method for fabricating an array substrate, including the following steps:
  • Step S01 providing a substrate on which a detecting circuit is formed, and at least one metal layer deviating from the detecting circuit;
  • Step S02 forming a protective layer covering the metal layer and exposing the detecting circuit.
  • FIG. 3 is a partial cross-sectional view of a non-display area including an encapsulation area of an array substrate according to an embodiment of the present invention
  • FIG. 4 is a part of a non-display area of an array substrate including a binding area according to an embodiment of the present invention.
  • the top view please refer to FIG. 2, and in conjunction with FIG. 3 and FIG. 4, the manufacturing method of the array substrate proposed by the present invention is described in detail:
  • a base substrate 100 is provided.
  • the base substrate 100 includes a display area and a non-display area, and the non-display area surrounds the display area.
  • the non-display area is provided with a package area and a driving chip binding area.
  • the non-display area may also be located on a different surface of the base substrate from the display area.
  • the non-display area is located on the back surface of the base substrate, and does not occupy the area of the display area. , thereby increasing the resolution and achieving a narrow border or no border.
  • the invention is not limited thereto.
  • the base substrate 100 may be made of a transparent material, such as glass, quartz, silicon wafer, polycarbonate, polymethyl methacrylate or metal foil, or the like.
  • the base substrate 100 may be a rigid substrate or a flexible substrate.
  • the selection and pretreatment of the base substrate 100 are familiar to those skilled in the art and will not be described in detail.
  • the display area is subsequently used to form a scan line, a data line, a transistor switch or a pixel electrode, etc. on the base substrate 100, and the non-display area is subsequently used to form a fan-out trace on the base substrate 100 for connection display.
  • the scan lines, data lines, etc. of the area are driven to the driver chip.
  • the non-display area includes a package area A.
  • a frit is coated on the package area A for packaging the array substrate and the glass cover to form a display panel.
  • Fan-out traces are also provided on the package area.
  • the package area A is annular and surrounds the display area. Only a cross-sectional view of a portion of the non-display area including the package area A is shown in FIG.
  • the non-display area further includes a driving chip binding area B.
  • the driving chip is bonded in the driving chip binding area B.
  • One end of the fan-out line in the non-display area is connected to the scan line, the data line, and the like of the display area, and the other end extends to the binding area B, that is, the fan-out line sets the input terminal 310 in the binding area B.
  • the output terminal 320 serves as an input and output of the driving chip.
  • a detection circuit 330 is further disposed between the input terminal 310 and the output terminal 320, and the detection circuit 330 includes a plurality of transistors connected to each other, and is connected to the display area through the fan-out trace for binding the driving chip.
  • FIG. 4 shows only a top view of a portion of the non-display area including the binding area B.
  • the finally formed display panel includes a display area 10 and a non-display area 20, the non-display area 20 surrounding the display area 10, and the package area A and the binding area B are both located in the non-display area.
  • the package area A surrounds the display area 10 for packaging the array substrate and the glass cover plate
  • the binding area B is located at one side edge of the non-display area 20 for binding Fixed drive chip.
  • a detection circuit 330 and a plurality of input terminals 310 and output terminals 320 are formed in the bonding region B of the base substrate 100.
  • the input terminal 310 and the output terminal 320 are regularly arranged.
  • the plurality of input terminals 310 are arranged in a row, and the plurality of output terminals 320 are arranged in a row, and both columns are parallel to one side of the array substrate.
  • the detection circuit 330 is located between the input terminal 310 and the output terminal 320.
  • the layer metal layer here, means “offset” means that they do not overlap each other in a direction perpendicular to the base substrate 100.
  • three metal layers are formed in the non-display area of the base substrate 100, which are an underlying metal layer 110, an intermediate metal layer 120, and a top metal layer 130.
  • the underlying metal layer 110, the intermediate metal layer 120, and the top metal layer 130 are separated by a dielectric layer 140.
  • the positional relationship between the metal layer and the input terminal 310, the output terminal 320, and the detecting circuit 330 is as shown in FIG. 4.
  • the input terminal 310 is adjacent to the edge of the base substrate, and the output terminal 320 is adjacent to the base substrate.
  • the central region may be provided with a metal layer in the non-display area of the output terminal 320 away from the side of the input terminal 310, and the top metal layer 130 is schematically illustrated in FIG.
  • the positional relationship can also be referred to as shown in FIG. 5.
  • a metal layer can be disposed in the non-display area 20 between the binding area B and the display area 10, and of course, the remaining three sides of the non-display area 20
  • a metal layer can also be provided inside.
  • the input terminal 310 and the output terminal 320 both comprise two metal layers connected through a contact hole.
  • the input terminal 310 and the output terminal 320 are formed while forming the underlying metal layer 110, the intermediate metal layer 120, and the top metal layer 130.
  • a first metal layer is formed in the bonding region while forming the underlying metal layer 110, and then a dielectric layer is formed on the underlying metal layer 110 while forming a dielectric layer in the bonding region.
  • Etching the dielectric layer to form a via hole (which may be synchronized with an etching in the display region), and then filling the via hole and forming a second metal layer while forming the intermediate layer metal layer 120
  • the first metal layer and the second metal layer constitute an input terminal 310 or an output terminal 320.
  • a detecting circuit is formed in the bonding region.
  • the detecting circuit comprises a plurality of thin film transistors connected to each other, wherein the number of transistors and the connection relationship between the transistors need to be determined according to actual requirements.
  • the specific structure of the detecting circuit is not described in detail.
  • the present invention does not specifically limit the detecting circuit.
  • a plurality of metal film layers are also formed in the display area of the base substrate 100, for example, forming a data line, scanning a line or a pixel electrode or the like, that is, a plurality of metal layers are formed in the non-display area while forming a data line, a scan line, a pixel electrode or another metal film layer in the display area, and binding in the non-display area Input/output terminals are formed in the area.
  • the material of the multi-layer metal layer and the input/output terminal depends on the material of the data line, the scan line, the pixel electrode or the other metal film layer formed simultaneously in the display area, and the material of the multi-layer metal layer may be different. The same, it can be exactly the same.
  • the material of the multilayer metal layer may include, but is not limited to, materials such as copper, aluminum, nickel, magnesium, chromium, molybdenum, tungsten, and alloys thereof. Of course, it is also possible to form a plurality of metal layers separately in the non-display area of the base substrate 100.
  • the plurality of metal layers are separated by a dielectric layer 140, and the dielectric layer 140 between the different metal layers is formed in different steps, but both function to isolate the metal layer. Therefore, in FIG. No distinction was made. It can be understood that the forming step of the dielectric layer 140 is also synchronized with the formation of the insulating layer in the display region, for example, in forming a gate insulating layer of an transistor, an interlayer insulating layer, or the like. In any one of the layers 140, the material of the dielectric layer is the same as the material of the gate insulating layer and the interlayer insulating layer formed at the same time.
  • the material of the dielectric layer 140 includes, but is not limited to, an oxide or a nitride.
  • the material of the dielectric layer between different metal layers may be different. It can be understood that the dielectric layer 140 can also be formed separately between the multiple metal layers, that is, the multilayer metal layer and the dielectric layer formed in the non-display area can be combined with the display area.
  • the metal layer or the insulating layer may be formed at the same time or may be formed separately.
  • a first dielectric layer is formed on the base substrate 100, preferably by chemical vapor deposition, such as high density plasma chemical vapor deposition (HDPCVD), low pressure chemical vapor deposition (LPCVD), or ultra high vacuum. Chemical vapor deposition (UHVCVD) and the like.
  • chemical vapor deposition such as high density plasma chemical vapor deposition (HDPCVD), low pressure chemical vapor deposition (LPCVD), or ultra high vacuum.
  • Forming an underlying metal on the first dielectric layer preferably by sputtering; then patterning the underlying metal, for example, including spin-on photoresist, exposure, and development And an etching process to form the underlying metal layer 110.
  • the first dielectric layer, the second dielectric layer and the third dielectric layer constitute the dielectric layer 140 shown in FIG. It is to be understood that the number of the metal layers is not limited to the three layers described above, and may include only two metal layers, or may include four or more metal layers. Accordingly, the number of dielectric layers may also be based on metal. The number of layers is adaptive.
  • a protective layer 150 is formed in the non-display area, the protective layer 150 covering the top metal layer 130 and the detecting circuit in the multi-layer metal layer in the non-display area. 330 and input terminal 310 and output terminal 320.
  • the protective layer 150 may be a single layer structure or a laminated structure.
  • the material of the protective layer 150 includes, but is not limited to, silicon nitride, silicon oxide or silicon oxynitride. Of course, the material of the protective layer 150 may also be other materials known to those skilled in the art, and the metal layer can be protected from The destruction of the laser irradiation used in the subsequent packaging is sufficient.
  • the thickness of the protective layer 150 is preferably Most preferably, the thickness of the protective layer 150 is The protective layer 150 of this thickness can protect the metal layer from damage by laser irradiation and does not affect the thickness of the finally formed display panel.
  • the protective layer 150 is formed by chemical vapor deposition.
  • the conditions for forming the protective layer 150 are preferably: a chamber temperature of 350 ° C to 400 ° C, a chamber pressure of 900 mtorr to 1100 mtorr, and a film formation time of 350 s to 450 s.
  • the chamber temperature is 385 ° C
  • the chamber pressure is 1000 mtorr
  • the film formation time is 400 s.
  • a protective layer is also formed in the display region, that is, a protective layer is simultaneously formed on the entire substrate substrate 100, and the display region is provided with The protective layer at the location of the contact hole is etched to expose the contact hole, thereby preventing the protective layer from affecting the connection of the display area.
  • the film layer before the formation of the protective layer in the display region is not limited. For example, while forming a data line in the display region, a top metal layer is formed in the non-display region, and then if a protective layer is directly formed, the display is performed. In the region, a protective layer is formed on the data line. If a protective layer is formed after forming another film layer (for example, a scan line) on the data line in the display region, the display region is formed on the scan line. The protective layer.
  • a protective layer 150 is formed on the top metal layer 130.
  • the protective layer 150 is used to protect the metal layer from the influence of the laser on the metal layer after laser irradiation, thereby avoiding the occurrence of lead cracks and reducing the incidence of lead cracks. Finally, the yield of the display panel is improved.
  • the protection layer 150 is also formed in the bonding area B, the detection circuit 330 in the binding area B is covered by the protection layer 150, which is disadvantageous for eliminating the surface charge and easily causing static electricity in the detection circuit. Therefore, it is necessary to proceed to step S04.
  • the protective layer 150 is patterned to form an opening, and the opening exposes the detecting circuit 330 and the input terminal 310 and the output terminal 320 in the binding area B.
  • a photoresist layer is formed on the protective layer 150, and the photoresist layer is exposed and developed to form a patterned photoresist layer to expose the detecting circuit 330 in the binding region B.
  • the etching gas is preferably a mixed gas of C 2 HF 5 (pentafluoroethane), H 2 (hydrogen), and Ar (argon).
  • the argon gas can increase the energy of ion bombardment, utilize ion bombardment to promote the reaction of pentafluoroethane with the protective layer, and can accelerate the reaction rate.
  • the etching gas may also be a mixed gas of CF 4 (carbon tetrafluoride) and O 2 (oxygen), or other etching gas known to those skilled in the art, and of course, it is also known to those skilled in the art.
  • the etching layer 150 is etched by other etching methods, which is not limited in the present invention.
  • the protecting layer 150 is patterned, and further includes exposing the remaining bonding regions except the detecting circuit 330 and the input terminal 310 and the output terminal 320, that is, by patterning the protective layer 150,
  • the size of the opening formed is equal to the size of the binding zone.
  • the protective layer 150 is patterned, and the bonding region B can be directly etched and exposed, and only the detecting circuit 330 and the input terminal 310 and the output terminal in the binding region B are exposed. 320, the range of etching is increased, which can reduce the process difficulty to some extent.
  • a non-display area within 0 to 100 ⁇ m from the periphery of the binding area B may also be exposed.
  • the size of the opening 170 is larger than the size of the binding zone B. That is, when the protective layer 150 is etched, the opening 170 is directly formed, which further increases the etching range compared with the above-mentioned exposure of the bonding region B, thereby further reducing the process difficulty.
  • the opening 170 increases a length a in a direction parallel to the long side of the driving chip than on both sides of the binding region B, and the opening 170 is in a direction parallel to the short side of the driving chip.
  • the two sides of the binding region B are each increased in width b, wherein the length a and the width b are both in the range of 0 to 100 ⁇ m, for example, 20 ⁇ m, 40 ⁇ m, 60 ⁇ m, 80 ⁇ m or 100 ⁇ m, of course, if the size of the non-display area allows It can also be larger than 100 ⁇ m, and its specific size is determined by the size in the actual display panel and the etching process conditions.
  • the protection layer 150 when the protection layer 150 is patterned, the protection layer in the binding area B is removed, and the non-display area is etched except the package area A, and only the package area is reserved.
  • the protective layer 150 on the top metal layer 130 in A (as shown in FIG. 3) can not only reduce the occurrence of lead cracks, but also avoid the static failure caused by the formation of the protective layer on the detecting circuit in the bonded region. , which helps to increase the yield of the product.
  • the protective layer 150 When the protective layer 150 is etched, the protective layer of the display region may be simultaneously etched away. That is, after the protective layer is formed, it is necessary to etch a protective layer at a position where the contact hole is provided in the display region to expose the contact hole.
  • the protective layer on the bonding area in the non-display area may be etched away, or the protective layer in the remaining area except the package area of the non-display area may be etched away, or may be displayed. All protective layers in the area are etched away and need to be selected according to the actual situation.
  • a photoresist layer is coated on the protective layer 150, and the photoresist layer is exposed through a mask.
  • the mask may expose only the display. Contact holes in the area, either exposing the entire display area, or exposing the binding area in the non-display area, or exposing other areas in the non-display area except the package area, or exposing all but the package area The non-display area and all the display areas determine the reticle used according to the specific situation.
  • the exposed photoresist layer is developed to form a patterned photoresist layer, and then the protective layer is etched by using the patterned photoresist layer as a mask, and finally the remaining lithography is stripped.
  • the glue layer forms a pattern of the desired protective layer.
  • the etching selection ratio can be adjusted, and the protective layer can be etched by selecting an appropriate etching selectivity to ensure a high etching rate for the protective layer and a low etching rate for the remaining layers. Or do not etch the remaining layers.
  • the etching selectivity ratio of the protective layer to the remaining film layers is preferably greater than 5:1.
  • the protective layer 150 in the package region may be partially etched, so that the protective layer 150 in the package region at least partially faces away from the top metal layer
  • the surface of the 130 is a concave, convex or concave surface, that is, the surface of the protective layer 150 at least partially facing away from the top metal layer 130 is a non-planar surface, so that the subsequently coated frit and the protective layer 150 are better.
  • the adhesive force that is, the adhesion of the frit to the protective layer is enhanced by the non-planar surface, thereby improving the reliability of the finally formed display panel.
  • the concave surface or the convex surface is a combination of one or more of a cylinder, a cone, a truncated cone or a hemisphere, and the concave and convex surface is formed by interlacing the concave surface and the convex surface, or may be The concave surface and the convex surface are alternately arranged at intervals.
  • the concave surface is formed, for example, by a plurality of grooves formed on the surface of the protective layer 150, and the grooves may be the same or different in size and shape.
  • the convex surface is composed, for example, of a plurality of protrusions formed on the surface of the protective layer 150, and the protrusions may be the same or different in size and shape.
  • the uneven surface is formed by a plurality of grooves and a plurality of protrusions formed on the surface of the protective layer 150.
  • the shape and size of the grooves and protrusions are not limited.
  • FIG. 3 and FIG. 4 The structure shown in FIG. 3 and FIG. 4 is finally formed.
  • the protective layer 150 is formed, the fabrication of the remaining film layers in the display region of the substrate substrate 100 is completed before the packaging, and the manufacturing method thereof is performed by those skilled in the art. Familiar, so will not be detailed, and finally complete the fabrication of the array substrate.
  • the present invention further provides a method for manufacturing a display panel, comprising the method for manufacturing an array substrate as described above.
  • the method for manufacturing the display panel includes:
  • the fabrication of the array substrate is completed and a glass cover 200 is provided.
  • the glass frit 160 is applied to the package region of the array substrate or the glass cover 200, and the array substrate is bonded to the cover glass 200.
  • the glass frit is irradiated with laser light; the protective layer 150 can protect the metal layer, avoid cracking of the metal layer, reduce the incidence of cracks, and improve the yield of the display panel.
  • the driving chip is bound in the binding region of the array substrate. Since the protective layer of the testing circuit 330 is removed, the detecting circuit can be prevented from being electrostatically damaged, the incidence of static electricity is reduced, and the yield of the display panel is further improved. .
  • the present invention also provides an array substrate manufactured by the method of manufacturing an array substrate as described above.
  • the array substrate includes:
  • a detection circuit on the substrate substrate, and at least one metal layer deviating from the detection circuit
  • a protective layer covering the metal layer and exposing the detection circuit.
  • the array substrate includes: a base substrate 100 including a display area and a non-display area (only part of the non-display area including the package area A is shown in FIG. 3 , Only a part of the non-display area including the binding area B is shown in FIG. 4, and a plurality of metal layers, preferably three layers, which are located in the non-display area of the base substrate 100, are an underlying metal layer 110 and an intermediate metal layer.
  • a protective layer 150 is formed on the top metal layer 130.
  • the protective layer 150 can protect the metal layer from damage caused by subsequent laser irradiation on the glass frit in the display panel, thereby reducing the incidence of lead cracks. It is advantageous to improve the yield of the display panel; and after the protective layer 150 is formed, the protective layer 150 is patterned to expose the detection circuit 330 and the input/output terminals 310/320 in the binding region, thereby preventing the detection circuit from being protected. The poor static electricity caused by the coverage of the layer further improves the yield of the display panel.
  • the present invention also provides a display panel manufactured by the method of manufacturing a display panel as described above.
  • the array substrate, the method of manufacturing the same, the display panel, and the method of fabricating the same after forming at least one metal layer on the substrate, forming a protective layer on the metal layer, the protective layer capable of The metal layer is protected from damage to the metal layer caused by the laser material in the subsequent display panel, thereby reducing the incidence of lead cracks and improving the yield of the display panel.
  • the protective layer exposes the detecting circuit, and the static defect caused by the covering of the detecting circuit due to the covering of the protective layer can be avoided, and the yield of the display panel is further improved.

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Abstract

本发明提供一种阵列基板及其制造方法、显示面板及其制造方法，在衬底基板上形成金属层之后，在金属层上形成保护层，所述保护层能够保护金属层，避免在后续对显示面板内的玻璃料进行激光照射时对金属层造成的损伤，从而降低引线裂纹的发生率，有利于提高显示面板的良率。此外，通过本申请的技术方案，所述保护层暴露出检测电路，能够避免检测电路由于保护层的覆盖所造成的静电不良，进一步提高了显示面板的良率。

Description

阵列基板及其制造方法、显示面板及其制造方法 技术领域
本发明涉及平板显示领域，具体涉及一种阵列基板及其制造方法、显示面板及其制造方法。
背景技术
显示面板具有显示区(或称主动区(active area)，AA区)和非显示区，显示区内配置有多个像素以形成像素阵列，非显示区则设置有多层金属层以构成周边线路。每个像素一般至少包括薄膜晶体管以及与该薄膜晶体管连接的像素电极，且每个像素都被两条相邻的扫描线以及两条相邻的数据线包围。这些扫描线以及数据线从显示区延伸至非显示区，并通过非显示区的周边线路与驱动芯片电连接，进而实现显示面板的正常工作。周边线路由连接扫描线与数据线的一端向驱动芯片所在区域集中汇拢而构成扇出走线，即多条周边线路在靠近主动区的一端具有较大间距，而在靠近驱动芯片的一端具有较小间距，从而大致形成扇形。
发明人研究发现，扇出走线尤其是金属引线很容易出现引线裂纹(Metal Crack)现象，最终导致显示面板出现亮线，对显示面板的良率造成了很大的影响。因此，如何降低甚至避免引线裂纹的发生率，是本领域技术人员亟需解决的技术问题。
发明内容
本发明的目的在于提供一种阵列基板及其制造方法、显示面板及其制造方法，能够降低引线裂纹的发生率，并且能够避免绑定区内检测电路的静电击伤,提高显示面板的画面品质。
为实现上述目的，本发明提供一种阵列基板，包括：
衬底基板；
位于所述衬底基板上的检测电路，以及偏离所述检测电路的至少一层金属层；以及
保护层，所述保护层覆盖所述金属层，并且暴露所述检测电路。
可选的，所述保护层的材质为氮化硅、氧化硅、氮氧化硅中的一种或其组合。
可选的，所述阵列基板还包括形成于所述衬底基板上的多个输入及输出端子，所述保护层暴露所述多个输入及输出端子。
可选的，所述检测电路与所述多个输入及输出端子组成绑定区，所述保护层暴露出的区域等于所述绑定区或大于所述绑定区。
可选的，所述衬底基板包括封装区；所述保护层仅覆盖所述封装区内的所述金属层。
相应的，本发明还提供一种阵列基板的制造方法，包括：
提供一衬底基板，在所述衬底基板上形成检测电路，以及偏离所述检测电路的至少一层金属层；
形成保护层，令所述保护层覆盖所述金属层，并且暴露所述检测电路。
可选的，所述方法还包括在所述衬底基板上设置多个输入及输出端子，所述保护层暴露所述多个输入及输出端子。
可选的，所述衬底基板包括封装区；所述保护层仅覆盖所述封装区内的所述金属层。
可选的，所述衬底基板包括显示区和非显示区，所述封装区以及所述检测电路、所述多个输入及输出端子均位于所述非显示区内；所述金属层同时形成在所述非显示区和所述显示区内，且在形成所述金属层的同时，在所述非显示区内形成所述检测电路以及在所述显示区内形成多个薄膜晶体管；所述保护层同时形成在所述非显示区和所述显示区内；所述形成保护层的步骤还包括：在使所述保护层暴露所述检测电路的同时，去除所述显示区内设置有接触孔的位置处的保护层，暴露出所述接触孔。
相应的，本发明还提供一种显示面板，包括阵列基板及玻璃盖板，所述显示面板包括显示区和非显示区，所述非显示区进一步包括封装区和绑定区，所述阵列基板包括：
衬底基板；
位于所述衬底基板上的检测电路，以及偏离所述检测电路的至少一层金属层；以及
保护层，所述保护层覆盖着所述金属层，并且暴露着所述检测电路，
所述阵列基板或玻璃盖板的封装区内涂布有玻璃料，以对所述阵列基板与所述玻璃盖板进行封装，
所述显示面板进一步包括绑定在绑定区内的驱动芯片。
可选的，所述保护层的材质为氮化硅、氧化硅、氮氧化硅中的一种或其组合。
可选的，所述阵列基板还包括形成于所述衬底基板上的多个输入及输出端子，所述保护层暴露所述多个输入及输出端子。
可选的，所述检测电路与所述多个输入及输出端子均位于所述绑定区内，所述保护层暴露出的区域等于所述绑定区或大于所述绑定区。
可选的，所述保护层仅覆盖所述封装区内的所述金属层。
相应的，本发明还提供一种显示面板的制造方法，所述显示面板包括显示区和非显示区，所述非显示区进一步包括封装区和绑定区，所述方法包括：
采用如上所述的阵列基板的制造方法制造阵列基板，并提供玻璃盖板；
在所述阵列基板或玻璃盖板的封装区涂布玻璃料，将阵列基板与所述玻璃盖板进行封装；
对所述玻璃料进行激光照射；
在绑定区内绑定驱动芯片。
与现有技术相比，本发明提供的阵列基板及其制造方法、显示面板及其制造方法中，在衬底基板上形成至少一层金属层之后，在金属层上形成保护层，所述保护层能够保护金属层，避免在后续对显示面板内的玻璃料进行激光照射时对金属层造成的损伤，从而降低引线裂纹的发生率，有利于提高显示面板的良率。此外，通过本申请的技术方案，所述保护层暴露出检测电路，能够避免检测电路由于保护层的覆盖所造成的静电损伤，进一步提高了显示面板的良率。
附图说明
图1为一显示面板的包含封装区的非显示区的部分截面图；
图2为本发明一实施例所提供的阵列基板的制造方法的流程图；
图3为本发明一实施例所提供的阵列基板的包含封装区的非显示区的部分截面图；
图4为本发明一实施例所提供的阵列基板的包含绑定区的非显示区的部分俯视图；
图5为本发明一实施例所提供的显示面板中封装区与绑定区的位置关系示意图；
图6为本发明一实施例所提供的显示面板的包含封装区的非显示区的部分截面图。
具体实施方式
显示面板，例如OLED(有机电致发光二极管)显示面板一般包括相对设置的阵列基板和玻璃盖板。所述显示面板包括显示区与非显示区，在非显示区内设置有封装区，用于涂布玻璃料(Frit)来封装阵列基板与玻璃盖板。
如图1所示，其为显示面板的非显示区的部分结构示意图。如图1所示，所述显示面板包括相对设置的衬底基板10与玻璃盖板20。在非显示区内，在所述衬底基板10上形成多层金属层，在图1中仅示出了三层金属层，分别为：底层金属层11、中间金属层12以及顶层金属层13，三层金属层之间通过介质层14相互隔离，在封装区内的顶层金属层13上直接涂布玻璃料(Frit)15，然后将衬底基板10与玻璃盖板20相封装形成显示面板。所述非显示区内形成的底层金属层11、中间金属层12以及顶层金属层13等金属层属于扇出走线，用于连接驱动芯片与显示区内的数据线、扫描线等，将驱动芯片提供的电信号传输至所述数据线或扫描线。
为了能将衬底基板10与玻璃盖板20良好地封装在一起，本申请的一个实施例的方案如下：衬底基板上形成至少一层金属层之后；在金属层上形成保护层。保护层能够保护金属层，并且可以避免后续对显示面板内的玻璃料进行激光照射时对金属层造成损伤(例如，避免金属层在垂直于激光前进的方向上出 现裂纹)，从而降低引线裂纹的发生。申请人还意外发现，这种方法还降低了显示面板的亮线不良率，这是由于金属层的损伤或裂纹会导致显示区内的某一条数据线或扫描线无法接收到信号或接受的信号不准确，从而导致显示面板出现亮线。
在本申请的另一个实施例中：提供一衬底基板，在所述衬底基板上形成检测电路，以及偏离所述检测电路的至少一层金属层；形成保护层，所述保护层覆盖着所述金属层，并且暴露着所述检测电路。发明人发现，在衬底基板上形成至少一层金属层之后，在金属层上形成保护层，所述保护层能够保护金属层，避免在后续对显示面板内的玻璃料进行激光照射时对金属层造成的损伤，从而降低引线裂纹的发生率，有利于提高显示面板的良率。此外，形成保护层之后，所述保护层暴露着所述检测电路，能够避免检测电路由于保护层的覆盖所造成的静电不良，特别是可以消除检测电路(CT电路)中累积的静电荷，从而进一步提高了显示面板的良率。
为使本发明的内容更加清楚易懂，以下结合说明书附图，对本发明的内容做进一步说明。当然本发明并不局限于该具体实施例，本领域的技术人员所熟知的一般替换也涵盖在本发明的保护范围内。
其次，本发明利用示意图进行了详细的表述，在详述本发明实例时，为了便于说明，示意图不依照一般比例局部放大，不应对此作为本发明的限定。
请参考图2所示，其为本发明一实施例所提供的阵列基板的制造方法的流程图，如图2所示，本发明提出一种阵列基板的制造方法，包括以下步骤：
步骤S01：提供一衬底基板，在所述衬底基板上形成检测电路，以及偏离所述检测电路的至少一层金属层；
步骤S02：形成保护层，所述保护层覆盖着所述金属层，并且暴露着所述检测电路。
图3为本发明一实施例所提供的阵列基板的包含封装区的非显示区的部分截面图，图4为本发明一实施例所提供的阵列基板的包含绑定区的非显示区的部分俯视图，请参考图2所示，并结合图3与图4，详细说明本发明提出的所述阵列基板的制造方法：
在步骤S01中，提供一衬底基板100。在本实施例中，所述衬底基板100包括显示区和非显示区，所述非显示区包围所述显示区。所述非显示区内设置有封装区与驱动芯片绑定区。当然，在其他实施例中，所述非显示区也可以与所述显示区位于衬底基板的不同表面，例如，所述非显示区位于所述衬底基板的背面，不占用显示区的面积，从而提高分辨率，以及实现窄边框或无边框。本发明对此不做限定。
所述衬底基板100可以由透明材料制成，例如可以是玻璃、石英、硅晶片、聚碳酸酯、聚甲基丙烯酸甲酯或者金属箔等。所述衬底基板100可以为刚性基板，也可以为柔性基板。所述衬底基板100的选择及预处理为本领域技术人员所熟悉，故不再详述。所述显示区后续用于在衬底基板100上形成扫描线、数据线、晶体管开关或像素电极等，所述非显示区后续用于在衬底基板100上形成扇出走线，用于连接显示区的扫描线、数据线等至驱动芯片。
如图3所示，所述非显示区包括封装区A，形成阵列基板之后在所述封装区A上涂布玻璃料，用于封装阵列基板与玻璃盖板形成显示面板。所述封装区上同样会设置有扇出走线。在一个实施例中，所述封装区A呈环形，包围所述显示区。图3中仅示出了包含封装区A的部分非显示区的截面图。
如图4所示，所述非显示区还包括驱动芯片绑定区B，形成显示面板之后，在驱动芯片绑定区B绑定(bonding)驱动芯片。所述非显示区内的扇出走线一端连接至所述显示区的扫描线、数据线等，另一端延伸至所述绑定区B，即扇出走线在绑定区B设置输入端子310与输出端子320，作为驱动芯片的输入与输出。在所述输入端子310与输出端子320之间还设置有检测电路330，所述检测电路330包含彼此连接的多个晶体管，通过所述扇出走线连接至显示区，用于在绑定驱动芯片之前，或者在形成显示面板之前，对阵列基板的电路进行检测。需要说明的是，所述绑定区B的尺寸与所述驱动芯片的外框尺寸完全一致。图4仅示出了包含了绑定区B的部分非显示区的俯视图。
所述封装区A与绑定区B的位置关系示意图请参照图5。如图5所示，最终形成的显示面板包括显示区10与非显示区20，所述非显示区20包围所述显示区10，所述封装区A与绑定区B均位于所述非显示区20内，所述封装区A 包围所述显示区10，用于将阵列基板与玻璃盖板封装在一起，所述绑定区B位于所述非显示区20的一侧边缘，用于绑定驱动芯片。
接着，请参考图3与图4所示，在所述衬底基板100的绑定区B内形成检测电路330以及多个输入端子310与输出端子320。所述输入端子310与所述输出端子320均规则排列。优选地，多个输入端子310排成一列，多个输出端子320排成一列，且两列均与所述阵列基板的一侧边平行。所述检测电路330位于所述输入端子310与输出端子320之间。
在所述衬底基板100的绑定区B内形成检测电路330以及输入端子310、输出端子320的同时，在所述衬底基板100的非显示区内形成偏离所述检测电路330的至少一层金属层，此处，“偏离”的含义是指在垂直于衬底基板100的方向上互不交叠。在本实施例中，优选地，在所述衬底基板100的非显示区内形成三层金属层，分别为底层金属层110、中间金属层120以及顶层金属层130，在其他实施例中，也可以形成两层、四层或更多的金属层，需要根据阵列基板实际的需求来确定，本发明并不做限定。所述底层金属层110、中间金属层120以及顶层金属层130之间通过介质层140相隔离。金属层与所述输入端子310、输出端子320以及检测电路330的位置关系如图4所示，所述输入端子310靠近所述衬底基板的边缘，所述输出端子320靠近所述衬底基板的中心区域，在所述输出端子320远离所述输入端子310一侧的非显示区内均可以设置有金属层，如图4中示意性的标示出了顶层金属层130。当然，其位置关系也可以参照图5所示，在所述绑定区B到所述显示区10之间的非显示区20内都可以设置金属层，当然在其余三侧的非显示区20内也可以设置金属层。
优选的，所述输入端子310与所述输出端子320均包括通过接触孔相连接两层金属层。在形成底层金属层110、中间金属层120以及顶层金属层130的同时形成所述输入端子310与所述输出端子320。
例如，在形成底层金属层110的同时在所述绑定区内形成第一层金属层，之后在底层金属层110上形成介质层的同时在所述绑定区内形成一层介质层，之后对该介质层进行刻蚀形成通孔(该刻蚀可以与显示区内的某一次刻蚀同步)，然后在形成中间层金属层120的同时，填充所述通孔并形成第二层金属层， 第一层金属层与第二层金属层构成输入端子310或输出端子320。
优选的，在所述显示区内形成薄膜晶体管的过程中，在所述绑定区形成检测电路。优选的，所述检测电路包括多个相互连接的薄膜晶体管，其中晶体管的数量以及晶体管之间的连接关系需要根据实际的需求来确定，在本实施例中不对检测电路的具体结构进行详细描述，并且本发明对检测电路不做具体限定。
优选的，在所述衬底基板100的非显示区内形成输入端子310与输出端子320的同时，在所述衬底基板100的显示区也形成多层金属膜层，例如形成数据线、扫描线或像素电极等，即在显示区内形成数据线、扫描线、像素电极或其他金属膜层的同时在所述非显示区内形成多层金属层、以及在所述非显示区的绑定区内形成输入/输出端子。由此，多层金属层及输入/输出端子的材质取决于在所述显示区内同时形成的数据线、扫描线、像素电极或其他金属膜层的材质，多层金属层的材质可以各不相同，也可以完全相同。所述多层金属层的材质可以包含但不限于铜、铝、镍、镁、铬、钼、钨及其合金等材料。当然，也可以单独在所述衬底基板100的非显示区内形成多层金属层。
所述多层金属层之间通过介质层140相隔离，不同金属层之间的介质层140是在不同的步骤中形成的，但是都起到隔离金属层的作用，因此，在附图3中没有进行区分。可以理解的是，所述介质层140的形成步骤也与所述显示区内的绝缘层的形成同步，例如，在形成晶体管的栅极绝缘层、层间绝缘层等的过程中形成所述介质层140中的任意一层，则所述介质层的材质与同时形成的栅极绝缘层、层间绝缘层的材质相同。所述介质层140的材质包含但不限于氧化物或氮化物，当然，不同金属层之间的介质层的材质可以不同。可以理解的是，也可以单独的在所述多层金属层之间形成所述介质层140，亦即，在非显示区内形成的多层金属层以及介质层可以与所述显示区内的金属层或绝缘层同时形成，也可以单独的形成。
以下简单介绍在所述衬底基板100的非显示区内形成所述多层金属层以及介质层的其中的一个方法，包括以下步骤：
首先，在所述衬底基板100上形成第一层介质层，优选的可以采用化学气相沉积法形成，例如高密度等离子体化学气相沉积(HDPCVD)、低压化学气相 沉积(LPCVD)或超高真空化学气相沉积(UHVCVD)等。然后在所述第一层介质层上形成底层金属，优选的，采用溅射的方法形成；然后对所述底层金属进行图形化，所述图形化工艺例如包括旋涂光刻胶、曝光、显影以及刻蚀工艺，形成底层金属层110。然后重复上述的步骤，在所述底层金属层110上形成第二介质层，所述第二介质层覆盖所述底层金属层110，接着在第二介质层上形成中间金属，并刻蚀形成中间金属层120，然后在中间金属层120上形成第三介质层，所述第三介质层覆盖所述中间金属层120，最后在第三介质层上形成顶层金属，刻蚀之后形成顶层金属层130。所述第一介质层、第二介质层与第三介质层构成图3所示的介质层140。可以理解的是，所述金属层的数量并不限于上述所介绍的三层，也可以仅包括两层金属层，或者是包括四层以上金属层，相应的，介质层的数量也可以根据金属层的数量适应性变化。
在步骤S02中，请参考图3所示，在所述非显示区内形成保护层150，所述保护层150覆盖所述非显示区内的多层金属层中的顶层金属层130以及检测电路330与输入端子310与输出端子320。所述保护层150可以是单层结构，也可以是叠层结构。所述保护层150的材质包含但不限于氮化硅、氧化硅或氮氧化硅，当然，所述保护层150的材质也可以为本领域技术人员已知的其他材料，能够保护金属层不受后续封装所使用的激光照射的破坏即可。由于氮化硅、氧化硅或氮氧化硅为本领域的常规材料，所以可作为本实施例的优选材料。所述保护层150的厚度优选为
Figure PCTCN2018082961-appb-000001
最佳的，所述保护层150的厚度为
Figure PCTCN2018082961-appb-000002
该厚度的所述保护层150能够保护金属层不受激光照射的损伤，也不会对最终形成的显示面板的厚度造成影响。
本实施例中，采用化学气相沉积法形成所述保护层150，形成所述保护层150的条件优选为：腔室温度350℃～400℃，腔室压强900mtorr～1100mtorr，成膜时间350s～450s，最佳的，腔室温度为385℃，腔室压强1000mtorr，成膜时间400s。
优选的，在非显示区内形成保护层150的同时，在所述显示区内也形成保护层，即在整个所述衬底基板100上同时形成保护层，并对所述显示区内设置有接触孔的位置处的保护层进行刻蚀，暴露出所述接触孔，避免保护层对显示 区的连接造成影响。在显示区内形成保护层之前的膜层并不受限定，例如，在显示区内形成数据线的同时，在所述非显示区内形成顶层金属层，之后如果直接形成保护层，则在显示区内，是在数据线上形成保护层，如果在显示区内还要在数据线上形成其他膜层(例如扫描线)之后再形成保护层，则在显示区内，是在扫描线上形成保护层。
在顶层金属层130上形成保护层150，所述保护层150用于保护金属层，避免后续进行激光照射时激光对金属层造成的影响，从而避免引线裂纹的产生，降低引线裂纹的发生率，最终提高了显示面板的良率。但是由于在绑定区B内也形成了所述保护层150，所述绑定区B内的检测电路330被所述保护层150覆盖，不利于表面电荷的消除，容易引起检测电路发生静电不良，因此，需要继续进行步骤S04。
接着，请参考图4所示，对所述保护层150进行图形化，形成开孔，所述开孔暴露出所述绑定区B内的检测电路330以及输入端子310与输出端子320。
具体的，在所述保护层150上形成光刻胶层，对所述光刻胶层进行曝光与显影，形成图形化的光刻胶层，暴露出所述绑定区B内的检测电路330以及输入端子310与输出端子320上方的保护层150；然后，以图形化的光刻胶层为掩膜，对所述保护层150进行刻蚀，优选的，采用等离子体干法刻蚀对所述保护层150进行刻蚀，去除暴露出的所述保护层150，暴露出所述绑定区B内的检测电路330以及输入端子310与输出端子320。
刻蚀气体优选为C 2HF 5(五氟乙烷)、H 2(氢气)与Ar(氩气)的混合气体。所述氩气可以提高离子轰击的能量，利用离子轰击促进五氟乙烷与保护层的反应，并可以加快反应速率。所述刻蚀气体还可以为CF 4(四氟化碳)与O 2(氧气)的混合气体，或者本领域技术人员已知的其他刻蚀气体，当然，也可以采用本领域技术人员已知的其他刻蚀方法对所述保护层150进行刻蚀，本发明对此不做限定。
优选的，对所述保护层150进行图形化，还包括暴露出除检测电路330以及输入端子310与输出端子320之外的其余绑定区，亦即通过对所述保护层150进行图形化，形成的开孔的尺寸等于所述绑定区的尺寸。如图4所示，对所述 保护层150进行图形化，可以直接刻蚀暴露出绑定区B，与上述只暴露出所述绑定区B内的检测电路330以及输入端子310与输出端子320，刻蚀的范围增大，可以在一定程度上降低工艺难度。
当然，为了避免后续在绑定驱动芯片时对显示面板造成影响，对所述保护层150进行图形化时，还可以暴露出距离所述绑定区B的外围0～100μm内的非显示区，如图4中的开口170，所述开口170的尺寸大于所述绑定区B的尺寸。即在对所述保护层150进行刻蚀时，直接形成所述开口170，与上述暴露出所述绑定区B相比，进一步增大了刻蚀的范围，进一步降低了工艺难度。所述开口170在平行于所述驱动芯片长边的方向上，比所述绑定区B的两侧各增加长度a，在平行于所述驱动芯片短边的方向上，所述开口170比所述绑定区B的两侧各增加宽度b，其中长度a与宽度b的尺寸均在0～100μm内，例如20μm、40μm、60μm、80μm或100μm，当然，如果非显示区的尺寸允许的话，也可以大于100μm，其具体尺寸由实际的显示面板内的尺寸以及刻蚀的工艺条件来确定。
当然，对所述保护层150进行图形化时，去除所述绑定区B内的保护层的同时，也可以对所述非显示区除封装区A以外的区域进行刻蚀，只保留封装区A内的顶层金属层130上的保护层150(如图3所示)，这样不仅可以减少引线裂纹的发生，而且还可以避免由于绑定区内的检测电路上形成保护层所造成的静电不良，从而有助于提高产品的良率。
在对所述保护层150进行刻蚀时，还可以同时刻蚀去除显示区域的保护层。也就是说，在形成所述保护层之后，需要对显示区内设置有接触孔的位置处的保护层进行刻蚀，暴露出所述接触孔。此外，在该刻蚀过程中，可以刻蚀去除非显示区内绑定区上的保护层，也可以刻蚀去除非显示区除封装区之外的其余区域内的保护层，也可以将显示区内的所有保护层均刻蚀掉，需要根据实际情况进行选择。
具体的，在所述保护层150上涂布光刻胶层，通过掩膜板对所述光刻胶层进行曝光，对于正光刻胶而言，所述掩模板可以仅暴露出所述显示区内的接触孔，或者暴露出整个显示区，或者暴露出非显示区内的绑定区，或者暴露出非显示区内除封装区之外的其他区域，或者暴露出除封装区以外的所有的非显示 区与所有的显示区，根据具体情况来确定所使用的掩模板。然后对经过曝光的光刻胶层进行显影，形成图形化的光刻胶层，然后以所述图像化的光刻胶层为掩膜对所述保护层进行刻蚀，最后剥离剩余的光刻胶层，形成所需的保护层的图案。
需要说明的是，以图形化的光刻胶层为掩膜对保护层进行刻蚀的过程中，要避免对保护层之下的其他膜层造成损伤，例如刻蚀非显示区除封装区外其余区域的保护层时，要避免对保护层下的顶层金属层造成损伤。针对该问题，可以调节刻蚀选择比，选择合适的刻蚀选择比对所述保护层进行刻蚀，保证对所述保护层具有高的刻蚀率，对于其余膜层具有低的刻蚀率，或者不对其余膜层进行刻蚀。例如，所述保护层与其余膜层的刻蚀选择比优选为大于5:1。
另外，在对所述保护层150进行刻蚀的步骤中，还可以对所述封装区内的保护层150进行部分刻蚀，使得封装区内的保护层150至少有部分背离所述顶层金属层130的表面为凹面、凸面或凹凸面，即所述保护层150至少有部分背离所述顶层金属层130的表面为非平面表面，使得之后涂覆的玻璃料与所述保护层150具有更好的粘接力，即通过非平面表面提高玻璃料与保护层的粘接力，从而提高最终形成的显示面板的可靠性。
优选的，所述凹面或凸面为圆柱体、圆锥体、圆台或半球体中的一种或两种以上的组合，所述凹凸面由所述凹面、凸面交错相连而成，也可以是由所述凹面、凸面交错间隔分布而成。所述凹面例如是由形成于所述保护层150表面的若干凹槽构成，这些凹槽的尺寸和形状可以相同，也可以不相同。所述凸面例如是由形成于所述保护层150表面的若干凸起构成，这些凸起的尺寸和形状可以相同，也可以不相同。所述凹凸面则是由形成于所述保护层150表面的若干凹槽和若干凸起共同构成，同样的，不限定凹槽和凸起的形状和尺寸。
最终形成如图3与图4所示的结构，形成所述保护层150之后，在封装之前还包括完成衬底基板100显示区内剩余各膜层的制作，其制作方法为本领域技术人员所熟悉，故不再详述，最终完成阵列基板的制作。
相应的，本发明还提供一种显示面板的制造方法，包括如上所述的阵列基板的制造方法，请参照图3、图4与图6所示，所述显示面板的制造方法包括：
完成阵列基板的制作，并提供一玻璃盖板200。
在所述阵列基板或玻璃盖板200的封装区涂布玻璃料160，将阵列基板与玻璃盖板200相贴合。
对所述玻璃料进行激光照射；所述保护层150能够保护金属层，避免金属层产生裂纹，降低了裂纹的发生率，提高了显示面板的良率。
在所述阵列基板的绑定区内绑定驱动芯片，由于在测试电路330的保护层被去除，能够避免检测电路被静电损伤，降低了静电不良的发生率，进一步提高了显示面板的良率。
相应的，本发明还提供一种阵列基板，采用如上所述的阵列基板的制造方法制造而成。所述阵列基板包括：
衬底基板；
位于所述衬底基板上的检测电路，以及偏离所述检测电路的至少一层金属层；以及
保护层，所述保护层覆盖着所述金属层，并且暴露着所述检测电路。
具体的，请参考图3与图4所示，所述阵列基板包括：包含显示区和非显示区的衬底基板100(图3中仅示出了包含封装区A的部分非显示区，图4中仅示出了包含绑定区B的部分非显示区)，位于所述衬底基板100的非显示区内的多层金属层，优选为三层，即底层金属层110、中间金属层120以及顶层金属层130，还包括位于三层金属层之间、包围底层金属层110与中间金属层120、并且位于底层金属层110与衬底基板100之间的介质层140；还包括位于除绑定区B内的检测电路330以及输入端子310与输出端子320以外的其余非显示区内顶层金属层130上的保护层150。
在顶层金属层130上形成保护层150，所述保护层150能够保护金属层，避免在后续对显示面板内的玻璃料进行激光照射时对金属层造成的损伤，从而降低引线裂纹的发生率，有利于提高显示面板的良率；并且形成保护层150之后对所述保护层150进行图形化，暴露出绑定区内的检测电路330以及输入/输出端子310/320，能够避免检测电路由于保护层的覆盖所造成的静电不良，进一步提高了显示面板的良率。
相应的，本发明还提供一种显示面板，采用如上所述的显示面板的制造方法制造而成。
综上所述，本发明提供的阵列基板及其制造方法、显示面板及其制造方法中，在衬底基板上形成至少一层金属层之后，在金属层上形成保护层，所述保护层能够保护金属层，避免后续显示面板内的玻璃料进行激光照射时对金属层造成的损伤，从而降低引线裂纹的发生率，有利于提高显示面板的良率。此外，通过本申请的技术方案，所述保护层暴露出检测电路，能够避免检测电路由于保护层的覆盖所造成的静电不良，进一步提高了显示面板的良率。
上述描述仅是对本发明较佳实施例的描述，并非对本发明范围的任何限定，本发明领域的普通技术人员根据上述揭示内容做的任何变更、修饰，均属于权利要求书的保护范围。

Claims (15)

  1. 一种阵列基板，其特征在于，所述阵列基板包括：
    衬底基板；
    位于所述衬底基板上的检测电路，以及偏离所述检测电路的至少一层金属层；以及
    保护层，所述保护层覆盖所述金属层，并且暴露所述检测电路。
  2. 如权利要求1所述的阵列基板，其特征在于，所述保护层的材质为氮化硅、氧化硅、氮氧化硅中的一种或其组合。
  3. 如权利要求1所述的阵列基板，其特征在于，所述阵列基板还包括形成于所述衬底基板上的多个输入及输出端子，所述保护层暴露所述多个输入及输出端子。
  4. 如权利要求3所述的阵列基板，其特征在于，所述检测电路与所述多个输入及输出端子组成绑定区，所述保护层暴露出的区域等于所述绑定区或大于所述绑定区。
  5. 如权利要求1所述的阵列基板，其特征在于，所述衬底基板包括封装区；所述保护层仅覆盖所述封装区内的所述金属层。
  6. 一种阵列基板的制造方法，其特征在于，包括：
    提供一衬底基板，在所述衬底基板上形成检测电路，以及偏离所述检测电路的至少一层金属层；
    形成保护层，令所述保护层覆盖所述金属层，并且暴露所述检测电路。
  7. 如权利要求6所述的阵列基板的制造方法，其特征在于，所述方法还包括在所述衬底基板上设置多个输入及输出端子，所述保护层暴露所述多个输入及输出端子。
  8. 如权利要求7所述的阵列基板的制造方法，其特征在于，所述衬底基板 包括封装区；所述保护层仅覆盖所述封装区内的所述金属层。
  9. 如权利要求8所述的阵列基板的制造方法，其特征在于，所述衬底基板包括显示区和非显示区，所述封装区以及所述检测电路、所述多个输入及输出端子均位于所述非显示区内；
    所述金属层同时形成在所述非显示区和所述显示区内，且在形成所述金属层的同时，在所述非显示区内形成所述检测电路以及在所述显示区内形成多个薄膜晶体管；
    所述保护层同时形成在所述非显示区和所述显示区内；
    所述形成保护层的步骤还包括：在使所述保护层暴露所述检测电路的同时，去除所述显示区内设置有接触孔的位置处的保护层，暴露出所述接触孔。
  10. 一种显示面板，包括：阵列基板及玻璃盖板，所述显示面板包括显示区和非显示区，所述非显示区进一步包括封装区和绑定区，
    所述阵列基板包括：
    衬底基板；
    位于所述衬底基板上的检测电路，以及偏离所述检测电路的至少一层金属层；以及
    保护层，所述保护层覆盖着所述金属层，并且暴露着所述检测电路，
    所述阵列基板或玻璃盖板的封装区内涂布有玻璃料，以对所述阵列基板与所述玻璃盖板进行封装，
    所述显示面板进一步包括绑定在绑定区内的驱动芯片。
  11. 如权利要求10所述的显示面板，其特征在于，所述保护层的材质为氮化硅、氧化硅、氮氧化硅中的一种或其组合。
  12. 如权利要求10所述的显示面板，其特征在于，所述阵列基板还包括形成于所述衬底基板上的多个输入及输出端子，所述保护层暴露所述多个输入及输出端子。
  13. 如权利要求12所述的显示面板，其特征在于，所述检测电路与所述多个输入及输出端子均位于所述绑定区内，所述保护层暴露出的区域等于所述绑定区或大于所述绑定区。
  14. 如权利要求10所述的显示面板，其特征在于，所述保护层仅覆盖所述封装区内的所述金属层。
  15. 一种显示面板的制造方法，所述显示面板包括显示区和非显示区，所述非显示区进一步包括封装区和绑定区，其特征在于，所述方法包括：
    采用如权利要求6-9中任一项所述的阵列基板的制造方法制造阵列基板，并提供玻璃盖板；
    在所述阵列基板或玻璃盖板的封装区涂布玻璃料，将阵列基板与所述玻璃盖板进行封装；
    对所述玻璃料进行激光照射；
    在绑定区内绑定驱动芯片。
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