WO2019029169A1 - 阵列基板及其制造方法、显示面板及其制造方法 - Google Patents

阵列基板及其制造方法、显示面板及其制造方法 Download PDF

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Publication number
WO2019029169A1
WO2019029169A1 PCT/CN2018/081499 CN2018081499W WO2019029169A1 WO 2019029169 A1 WO2019029169 A1 WO 2019029169A1 CN 2018081499 W CN2018081499 W CN 2018081499W WO 2019029169 A1 WO2019029169 A1 WO 2019029169A1
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Prior art keywords
display area
array substrate
metal layer
protective layer
substrate
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PCT/CN2018/081499
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English (en)
French (fr)
Inventor
孙正上
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昆山国显光电有限公司
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Application filed by 昆山国显光电有限公司 filed Critical 昆山国显光电有限公司
Priority to JP2019562455A priority Critical patent/JP6876829B2/ja
Priority to EP18842919.5A priority patent/EP3667729B1/en
Priority to US16/324,661 priority patent/US11362302B2/en
Priority to KR1020197021405A priority patent/KR102303734B1/ko
Publication of WO2019029169A1 publication Critical patent/WO2019029169A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • H10K50/844—Encapsulations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/06—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials
    • H01L21/08—Preparation of the foundation plate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/70—Testing, e.g. accelerated lifetime tests
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H10K59/871—Self-supporting sealing arrangements

Definitions

  • the present invention relates to the field of flat panel display, and in particular to an array substrate, a method of manufacturing the same, a display panel, and a method of fabricating the same.
  • the display panel has a display area (or active area, AA area) and a non-display area.
  • the display area is configured with a plurality of pixels to form a pixel array
  • the non-display area is provided with a plurality of metal layers to form a peripheral line.
  • Each pixel typically includes at least a thin film transistor and a pixel electrode coupled to the thin film transistor, and each pixel is surrounded by two adjacent scan lines and two adjacent data lines.
  • the scan lines and the data lines extend from the display area to the non-display area, and are electrically connected to the driving chip through the peripheral lines of the non-display area, thereby realizing the normal operation of the display panel.
  • the peripheral line is formed by the end of the connection of the scan line and the data line to the area where the driver chip is located to form a fan-out trace, that is, the plurality of peripheral lines have a larger pitch at one end near the active area, and the end is closer to the drive chip. Small spacing, thus roughly forming a fan shape.
  • An object of the present invention is to provide an array substrate, a method of manufacturing the same, a display panel, and a method of manufacturing the same, which can reduce the incidence of lead cracks and improve the picture quality of the display panel.
  • the present invention provides an array substrate comprising: a base substrate; a metal layer on the base substrate; and a protective layer covering the metal layer.
  • the material of the protective layer is one of silicon nitride, silicon oxide, silicon oxynitride or a combination thereof.
  • the substrate substrate includes a package region, and the protection layer covers the metal layer in the package region.
  • At least a portion of the surface of the protective layer in the package region facing away from the metal layer is a concave surface, a convex surface or a concave surface.
  • the concave or convex surface is one or a combination of two or more of a cylinder, a cone, a truncated cone or a hemisphere, and the concave and convex surface is interlaced or staggered by the concave surface and the convex surface. Distribution composition.
  • the present invention also provides a method for manufacturing an array substrate, comprising:
  • a protective layer is formed, the protective layer covering the metal layer.
  • the substrate substrate includes a package region; the protective layer covers the metal layer in the package region.
  • the substrate substrate includes a display area and a non-display area, the package area is located in the non-display area; the metal layer is simultaneously formed in the non-display area and the display area; A protective layer is simultaneously formed in the non-display area and the display area, and the method further includes removing a protective layer at a position corresponding to the contact hole in the display area to expose the contact hole.
  • the substrate substrate comprises a display area and a non-display area
  • the metal layer comprises a plurality of layers formed in the non-display area
  • a dielectric layer is disposed between the plurality of metal layers
  • the metal The layer is a fan-out trace for transmitting an electrical signal provided by a driver chip provided in the display area.
  • the present invention further provides a display panel, the display panel comprising an array substrate and a glass cover, the array substrate comprising: a substrate; a metal layer, the metal layer is located on the substrate; a protective layer covering the metal layer, wherein a sealing layer of the array substrate or the glass cover is coated with a glass frit to encapsulate the array substrate and the glass cover.
  • the present invention also provides a method of manufacturing a display panel, the method comprising:
  • the frit is subjected to laser irradiation.
  • the laser irradiation condition is that the laser energy is between 7.2 w and 7.5 w, and the laser moving speed is between 10 mm/s and 11 mm/s.
  • the array substrate provided by the present invention the manufacturing method thereof, the display panel, and the method of manufacturing the same, after forming a metal layer on the substrate, forming a protective layer on the metal layer, the protective layer can protect The metal layer avoids damage to the metal layer when the glass frit in the display panel is subsequently irradiated with laser light, thereby reducing the incidence of lead cracks, and is advantageous for improving the yield of the display panel.
  • the surface of the protective layer located in the package region at least partially facing away from the top metal layer is a concave surface, a convex surface or an uneven surface, and a glass frit is formed on the surface to improve the adhesion between the glass frit and the protective layer.
  • 1 is a partial structural view of a non-display area of a display panel
  • FIG. 2 is a flow chart of a method for fabricating an array substrate according to an embodiment of the present invention
  • FIG. 3 is a partial structural diagram of a non-display area of an array substrate according to an embodiment of the present invention.
  • FIG. 4 is a top plan view of an array substrate according to an embodiment of the invention.
  • FIG. 5 is a partial schematic structural diagram of a non-display area of a display panel according to an embodiment of the present invention.
  • FIG. 6 is a data diagram of lead cracks of a display panel according to an embodiment of the present invention.
  • FIG. 7 is a partial structural diagram of a non-display area of a display panel according to another embodiment of the present invention.
  • a display panel such as an OLED (Organic Electroluminescent) display panel, generally includes an array substrate and a glass cover disposed opposite each other.
  • the display panel includes a display area and a non-display area, and a package area is disposed in the non-display area for coating the glass frit to encapsulate the array substrate and the glass cover.
  • FIG. 1 it is a partial structural diagram of a non-display area of a display panel.
  • the display panel includes a substrate substrate 10 and a glass cover 20 disposed opposite each other.
  • a plurality of metal layers are formed on the base substrate 10.
  • FIG. 1 only three metal layers are shown, namely, an underlying metal layer 11, an intermediate metal layer 12, and a top metal layer 13.
  • the three metal layers are separated from each other by the dielectric layer 14, and a frit 15 is directly coated on the top metal layer 13 in the package region, and then the substrate substrate 10 and the glass cover 20 are packaged to form a display panel. .
  • the metal layer such as the underlying metal layer 11, the intermediate metal layer 12, and the top metal layer 13 formed in the non-display area belongs to a fan-out trace, and is used for connecting a driving chip and a data line, a scanning line, and the like in the display area, and driving the chip.
  • the provided electrical signal is transmitted to the data line or scan line.
  • an embodiment of the present application is as follows: providing a substrate; forming at least one metal layer on the substrate; and forming A protective layer covering the metal layer.
  • the protective layer can protect the metal layer, and can avoid damage to the metal layer after laser irradiation of the glass frit in the display panel (for example, avoiding cracks in the direction perpendicular to the laser advancement), thereby reducing lead cracking. occur.
  • this method also reduces the bright line defect rate of the display panel, because the damage or crack of the metal layer may cause a certain data line or scan line in the display area to receive no signal or receive signal. Inaccurate, resulting in a bright line on the display panel.
  • FIG. 2 is a flowchart of a method for fabricating an array substrate according to an embodiment of the present invention.
  • the present invention provides a method for fabricating an array substrate, including the following steps:
  • Step S01 providing a substrate on which at least one metal layer is formed
  • Step S02 forming a protective layer, the protective layer covering the metal layer.
  • FIG. 3 is a partial structural diagram of a non-display area of an array substrate according to an embodiment of the present invention. Referring to FIG. 2 and FIG. 3, a method for manufacturing the array substrate according to the present invention is described in detail:
  • a base substrate 100 is provided.
  • the base substrate 100 includes a display area and a non-display area, the non-display area surrounding the display area, and only a part of the non-display area including the package area is shown in FIG.
  • the non-display area may also be located on a different surface of the base substrate from the display area.
  • the non-display area is located on the back surface of the base substrate, and does not occupy the area of the display area. , thereby increasing the resolution and achieving a narrow border or no border.
  • the invention is not limited thereto.
  • the base substrate 100 may be made of a transparent material, such as glass, quartz, silicon wafer, polycarbonate, polymethyl methacrylate or metal foil, or the like.
  • the base substrate 100 may be a rigid substrate or a flexible substrate.
  • the selection and pretreatment of the base substrate 100 are familiar to those skilled in the art and will not be described in detail.
  • the display area is subsequently used to form a scan line, a data line, a transistor switch or a pixel electrode, etc. on the base substrate 100, and the non-display area is subsequently used to form a fan-out trace on the base substrate 100 for connection display.
  • the scan lines, data lines, etc. of the area are driven to the driver chip.
  • the non-display area further includes a package area.
  • the glass frit is coated on the package area for packaging the array substrate and the glass cover to form a display panel.
  • Fan-out traces are also provided on the package area.
  • the encapsulation area is annular and surrounds the display area. Only a cross-sectional view of a portion of the non-display area including the package area is shown in FIG.
  • At least one metal layer is formed on the base substrate 100.
  • at least one metal layer is formed in the non-display area of the base substrate 100.
  • three metal layers are formed in the non-display area of the base substrate 100, respectively.
  • the layer 110, the intermediate metal layer 120, and the top metal layer 130, in other embodiments, may also form two, four or more metal layers, which need to be determined according to the actual needs of the array substrate, and the invention is not limited thereto. .
  • a plurality of metal film layers are also formed in the display area of the base substrate 100, for example, forming data lines, scan lines or pixels.
  • An electrode or the like that is, a plurality of metal layers are formed in the non-display area while forming data lines, scan lines, pixel electrodes or other metal film layers in the display region. Therefore, the material of the multi-layer metal layer depends on the material of the data line, the scan line, the pixel electrode or the other metal film layer formed simultaneously in the display area, and the material of the multi-layer metal layer may be different or completely the same.
  • the material of the multilayer metal layer may include, but is not limited to, materials such as copper, aluminum, nickel, magnesium, chromium, molybdenum, tungsten, and alloys thereof. Of course, it is also possible to form a plurality of metal layers separately in the non-display area of the base substrate 100.
  • the plurality of metal layers are separated by a dielectric layer 140, and the dielectric layer 140 between the different metal layers is formed in different steps, but both function to isolate the metal layer. Therefore, in FIG. No distinction was made. It can be understood that the forming step of the dielectric layer 140 is also synchronized with the formation of the insulating layer in the display region, for example, in forming a gate insulating layer of an transistor, an interlayer insulating layer, or the like. In any one of the layers 140, the material of the dielectric layer is the same as the material of the gate insulating layer and the interlayer insulating layer formed at the same time.
  • the material of the dielectric layer 140 includes, but is not limited to, an oxide or a nitride.
  • the material of the dielectric layer between different metal layers may be different. It can be understood that the dielectric layer 140 can also be formed separately between the multiple metal layers, that is, the multilayer metal layer and the dielectric layer formed in the non-display area can be combined with the display area.
  • the metal layer or the insulating layer may be formed at the same time or may be formed separately.
  • a first dielectric layer is formed on the base substrate 100, preferably by chemical vapor deposition, such as high density plasma chemical vapor deposition (HDPCVD), low pressure chemical vapor deposition (LPCVD), or ultra high vacuum. Chemical vapor deposition (UHVCVD) and the like.
  • chemical vapor deposition such as high density plasma chemical vapor deposition (HDPCVD), low pressure chemical vapor deposition (LPCVD), or ultra high vacuum.
  • Forming an underlying metal on the first dielectric layer preferably by sputtering; then patterning the underlying metal, for example, including spin-on photoresist, exposure, and development And an etching process to form the underlying metal layer 110.
  • the first dielectric layer, the second dielectric layer and the third dielectric layer constitute the dielectric layer 140 shown in FIG. It is to be understood that the number of the metal layers is not limited to the three layers described above, and may include only two metal layers, or may include four or more metal layers. Accordingly, the number of dielectric layers may also be based on metal. The number of layers is adaptive.
  • a protective layer is formed, the protective layer covering the metal layer.
  • the protective layer 150 is formed on the top metal layer 130 in the plurality of metal layers in the non-display region.
  • the protective layer 150 may be a single layer structure or a laminated structure.
  • the material of the protective layer 150 includes, but is not limited to, silicon nitride, silicon oxide or silicon oxynitride.
  • the material of the protective layer 150 may also be other materials known to those skilled in the art, and the metal layer can be protected from The destruction of the laser irradiation used in the subsequent packaging is sufficient.
  • the thickness of the protective layer 150 is preferably Most preferably, the thickness of the protective layer 150 is The protective layer 150 of this thickness can protect the metal layer from damage by laser irradiation and does not affect the thickness of the finally formed display panel.
  • the protective layer 150 is formed by chemical vapor deposition.
  • the conditions for forming the protective layer 150 are preferably: a chamber temperature of 350 ° C to 400 ° C, a chamber pressure of 900 mtorr to 1100 mtorr, and a film formation time of 350 s to 450 s.
  • the chamber temperature is 385 ° C
  • the chamber pressure is 1000 mtorr
  • the film formation time is 400 s.
  • a protective layer is also formed in the display region, that is, a protective layer is simultaneously formed on the entire substrate substrate 100, and The protective layer at the position where the contact hole is disposed in the display area is etched to expose the contact hole, thereby preventing the protective layer from affecting the connection of the display area.
  • the film layer before the formation of the protective layer in the display region is not limited. For example, while forming a data line in the display region, a top metal layer is formed in the non-display region, and then if a protective layer is directly formed, the display is performed. In the region, a protective layer is formed on the data line. If a protective layer is formed after forming another film layer (for example, a scan line) on the data line in the display region, the display region is formed on the scan line. The protective layer.
  • a protective layer 150 is formed on the top metal layer 130.
  • the protective layer 150 is used to protect the metal layer from the influence of the laser on the metal layer after laser irradiation, thereby avoiding the occurrence of lead cracks and reducing the incidence of lead cracks. Finally, the yield of the display panel is improved.
  • the protective layer 150 can also be patterned.
  • the protective layer 150 is etched, and only the protective layer 150 on the top metal layer 130 in the package region is retained (as shown in FIG. 3).
  • Show). 4 is a top view of an array substrate according to an embodiment of the present invention.
  • the array substrate includes a display area 10 and a non-display area 20 surrounding the display area 10, in the non-display area. 20 is provided with a package area 30 and a binding area 40.
  • the package area 30 is annular and surrounds the display area 10.
  • the binding area 40 is located between the package area 30 and one side edge of the array substrate.
  • the protective layer 150 is formed only on the package region 30.
  • the protective layer 150 in the remaining area of the non-display area may not be etched, that is, the protective layer 150 is located in the entire non-display area, which can reduce the generation of the micro-bright line, but the generation of static electricity is increased. . That is, in addition to the fact that the protective layer 150 is located above the package region to reduce the occurrence of lead cracks, forming a protective layer at the remaining positions of the non-display region can reduce the generation of the micro-bright lines.
  • the protective layer 150 When the protective layer 150 is etched, the protective layer of the display region may be simultaneously etched away, that is, after the protective layer is formed, protection at a position where the contact hole is disposed in the display region is required. The layer is etched to expose the contact hole. During the etching process, the protective layer in the remaining area except the package area of the non-display area may be etched away, or all the protective layers in the display area may be Etching, you need to choose according to the actual situation.
  • a photoresist layer is coated on the protective layer 150, and the photoresist layer is exposed through a mask.
  • the mask may expose only the display. Contact holes in the area, either exposing the entire display area, or exposing other areas except the package area in the non-display area, or exposing all areas except the package area, and determining the mask used according to the specific situation .
  • the exposed photoresist layer is developed to form a patterned photoresist layer, and then the protective layer is etched by using the patterned photoresist layer as a mask, and finally the remaining lithography is stripped.
  • the glue layer forms a pattern of the desired protective layer.
  • the etching selection ratio can be adjusted, and the protective layer can be etched by selecting an appropriate etching selectivity to ensure a high etching rate for the protective layer and a low etching rate for the remaining layers. Or do not etch the remaining layers.
  • the protective layer is etched by plasma etching, including but not limited to a mixed gas of C 2 HF 5 (pentafluoroethane), H 2 (hydrogen), and Ar (argon).
  • the etching selectivity ratio of the protective layer to the remaining film layers is preferably greater than 5:1.
  • the protective layer 150 in the package region may be partially etched, so that the protective layer 150 in the package region at least partially faces away from the top metal layer
  • the surface of the 130 is a concave, convex or concave surface, that is, the surface of the protective layer 150 at least partially facing away from the top metal layer 130 is a non-planar surface, so that the subsequently coated frit and the protective layer 150 are better.
  • the adhesive force that is, the adhesion of the frit to the protective layer is enhanced by the non-planar surface, thereby improving the reliability of the finally formed display panel.
  • the concave surface or the convex surface is a combination of one or more of a cylinder, a cone, a truncated cone or a hemisphere, and the concave and convex surface is formed by interlacing the concave surface and the convex surface, or may be The concave surface and the convex surface are alternately arranged at intervals.
  • the concave surface is formed, for example, by a plurality of grooves formed on the surface of the protective layer 150, and the grooves may be the same or different in size and shape.
  • the convex surface is composed, for example, of a plurality of protrusions formed on the surface of the protective layer 150, and the protrusions may be the same or different in size and shape.
  • the uneven surface is formed by a plurality of grooves and a plurality of protrusions formed on the surface of the protective layer 150.
  • the shape and size of the grooves and protrusions are not limited.
  • the protective layer 150 can also be formed only in the package region, thereby avoiding etching of the protective layer 150, saving production time and saving manufacturing costs.
  • a mask that exposes a package region is formed, and a protective layer is deposited by using the mask as a mask, but the precision of the protective layer produced by the method is relatively low, if the product specification is not high or the capability of the device is good.
  • the etching layer is formed after the protective layer is formed, or the protective layer is formed only in the place where it is needed, which needs to be determined according to actual needs, and the invention is not limited thereto.
  • the protective layer can also be formed by other methods known to those skilled in the art.
  • FIG. 4 a structure as shown in FIG. 4 is formed. After the protective layer 150 is formed, before the package is completed, the fabrication of each film layer in the display region of the substrate substrate 100 is completed, and the manufacturing method thereof is familiar to those skilled in the art, so Further, the fabrication of the array substrate is finally completed.
  • the present invention also provides a method for manufacturing a display panel, comprising the method for manufacturing an array substrate as described above, the method for manufacturing the display panel comprises:
  • the glass frit 160 is coated on the package area of the array substrate or the glass cover 200, and the array substrate and the glass cover 200 are packaged; the array substrate and the glass cover 200 are packaged by coating the glass frit 160 to form a display panel. Finally, a structure as shown in FIG. 5 is formed. After the laser irradiation of the frit 160 is performed, the protective layer 150 can protect the metal layer, avoid cracking of the metal layer, reduce the incidence of cracks, and improve the display panel. rate.
  • FIG. 6 is a schematic diagram of data of lead cracks of a display panel according to an embodiment of the present invention.
  • the display panel of a certain size for example, a 5.5-inch panel is used as an example to form a protective layer on the top metal layer of the package region, and the ratio of crack occurrence is 20% compared with the previous one (no protection is formed). Layer) has fallen sharply.
  • the row of 7.5w 11mm/s in the table of FIG. 5 represents the condition for laser irradiation, wherein 7.5w represents the energy of the laser, and 11mm/s represents the speed of the laser movement, as can be seen from FIG.
  • the adjustment of the conditions of the laser irradiation can completely avoid the crack phenomenon.
  • the preferable conditions for the laser irradiation are: the laser energy is between 7.2 w and 7.5 w, and the speed of the laser movement is 10 mm/s. Between 11mm/s.
  • Table 1 is a schematic diagram of reliability results of a display panel according to an embodiment of the present invention.
  • the display panel finally manufactured by the method for manufacturing an array substrate provided by the present invention is subjected to reliability verification, for example, a temperature and humidity operation test, a temperature of 60 ° C, a humidity of 90% RH, and a test time of 120H, 10 pieces of display panel showed a negative R/G/B dark spot (red/green/blue dark spot) when tested to 60H.
  • the defect is an anode black dot, which is made by anode abnormality or anode. Caused by etching anomalies, independent of cracks.
  • the high temperature operation test was carried out, the temperature was 60 ° C, the test time was 120H, and no new abnormality was observed.
  • the high temperature storage test was carried out at a temperature of 70 ° C and a test time of 120 H, and no new abnormalities were observed. Therefore, it can be confirmed that the method of forming the protective layer on the top metal layer of the package region can reduce the incidence of cracks without causing other abnormalities.
  • the present invention also provides an array substrate manufactured by the method of manufacturing an array substrate as described above.
  • the array substrate includes:
  • the array substrate includes: a base substrate 100 including a display area and a non-display area (only part of the non-display area including the package area is shown in FIG. 3), and the lining is located
  • the plurality of metal layers in the non-display area of the base substrate 100 are preferably three layers, that is, the bottom metal layer 110, the intermediate metal layer 120, and the top metal layer 130, and further include a layer of the metal layer 110 between the three metal layers.
  • the dielectric layer 140 is disposed with the intermediate metal layer 120 and between the underlying metal layer 110 and the substrate 100; and further includes a protective layer 150 on the top metal layer 130.
  • the protective layer 150 is only located above the top metal layer 130 in the package region. In other embodiments, the protective layer 150 may also be located in a non-display area other than the package area, or the protective layer 150 may also be located in the display area. Of course, the display area is provided with a contact hole. At the location of the protective layer 150, the protective layer 150 needs to be removed to prevent the contact of the display area from being affected.
  • the present invention also provides a display panel manufactured by the method of manufacturing a display panel as described above.
  • the display panel includes:
  • An array substrate comprising: a substrate; a metal layer on the substrate; and a protective layer, the protective layer covering the metal layer;
  • a cover glass is placed on the frit.
  • FIG. 7 is a partial structural diagram of a non-display area of a display panel according to another embodiment of the present invention, wherein a metal layer and a protective layer of a non-display area in the array substrate are respectively in a display area.
  • the metal layer and the protective layer are formed in the same step.
  • the display panel includes:
  • An array substrate comprising: a substrate substrate 300 including a display region and a non-display region (only a portion of the non-display region including the package region is shown in FIG. 6); and sequentially located in the non-display region of the substrate substrate 300 a first dielectric layer 310, a second dielectric layer 320, and a third dielectric layer 330, and an underlying metal layer 340 located in the third dielectric layer, an intermediate metal layer 350 on the third dielectric layer 330, and a fourth dielectric layer 360 on the third dielectric layer 330 and the intermediate metal layer 350, and a top metal layer 370 on the fourth dielectric layer 360, and the first dielectric layer 310, the second dielectric layer 320,
  • the third dielectric layer 330 and the fourth dielectric layer 360 are both formed in the same step as the dielectric layer or the insulating layer in the display region.
  • the preferred dielectric layer is made of silicon oxide or silicon nitride; the array substrate further includes The fourth dielectric layer 360 and the protective layer 380 on
  • a frit 390 is located above the protective layer 380.
  • a cover glass 400 is encapsulated by the frit 390 and the array substrate.
  • the method of manufacturing the same, the display panel, and the method of fabricating the same after the metal layer is formed on the substrate, a protective layer is formed on the metal layer, and the protective layer can protect the metal layer.
  • the protective layer can protect the metal layer.
  • the surface of the protective layer located in the package region at least partially away from the surface of the top metal layer is a concave surface, a convex surface or a concave-convex surface, and a glass frit is formed on the surface to improve the adhesion between the glass frit and the protective layer.

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Abstract

一种阵列基板及其制造方法、显示面板及其制造方法，在衬底基板（100）上形成金属层之后，在金属层上形成保护层（150），保护层能够保护金属层，避免在后续对显示面板内的玻璃料进行激光照射时对金属层造成的损伤，从而降低引线裂纹的发生率，有利于提高显示面板的良率。

Description

阵列基板及其制造方法、显示面板及其制造方法 技术领域
本发明涉及平板显示领域，具体涉及一种阵列基板及其制造方法、显示面板及其制造方法。
背景技术
显示面板具有显示区(或称主动区(active area)，AA区)和非显示区，显示区内配置有多个像素以形成像素阵列，非显示区则设置有多层金属层以构成周边线路。每个像素一般至少包括薄膜晶体管以及与该薄膜晶体管连接的像素电极，且每个像素都被两条相邻的扫描线以及两条相邻的数据线包围。这些扫描线以及数据线从显示区延伸至非显示区，并通过非显示区的周边线路与驱动芯片电连接，进而实现显示面板的正常工作。周边线路由连接扫描线与数据线的一端向驱动芯片所在区域集中汇拢而构成扇出走线，即多条周边线路在靠近主动区的一端具有较大间距，而在靠近驱动芯片的一端具有较小间距，从而大致形成扇形。
发明人研究发现，扇出走线尤其是金属引线很容易出现引线裂纹(Metal Crack)现象，最终导致显示面板出现亮线，对显示面板的良率造成了很大的影响。因此，如何降低甚至避免引线裂纹的发生率，是本领域技术人员亟需解决的技术问题。
发明内容
本发明的目的在于提供一种阵列基板及其制造方法、显示面板及其制造方法，能够降低引线裂纹的发生率，提高显示面板的画面品质。
为实现上述目的，本发明提供一种阵列基板，包括：衬底基板；金属层，所述金属层位于所述衬底基板上；以及保护层，所述保护层覆盖所述金属层。
可选的，所述保护层的材质为氮化硅、氧化硅、氮氧化硅中的一种或其组合。
可选的，所述衬底基板包括封装区，所述保护层覆盖所述封装区内的所述 金属层。
可选的，所述封装区内的保护层的背离所述金属层的表面的至少一部分为凹面、凸面或凹凸面。
可选的，所述凹面或凸面为圆柱体、圆锥体、圆台或半球体中的一种或两种以上的组合，所述凹凸面由所述凹面、所述凸面交错相连而成或交错间隔分布构成。
相应的，本发明还提供一种阵列基板的制造方法，包括：
提供一衬底基板，在所述衬底基板上形成至少一层金属层；
形成保护层，所述保护层覆盖所述金属层。
可选的，所述衬底基板包括封装区；所述保护层覆盖所述封装区内的所述金属层。
可选的，所述衬底基板包括显示区和非显示区，所述封装区位于所述非显示区内；所述金属层同时形成在所述非显示区和所述显示区内；所述保护层同时形成在所述非显示区和所述显示区内，且所述方法还包括去除所述显示区内对应于接触孔的位置处的保护层，暴露出所述接触孔。
可选的，所述衬底基板包括显示区和非显示区，所述金属层包括若干层，形成于所述非显示区内，所述若干层金属层之间设有介质层，所述金属层为扇出走线，用于传输设于所述显示区的驱动芯片提供的电信号。
相应的，本发明还提供一种显示面板，所述显示面板包括阵列基板及玻璃盖板，所述阵列基板包括：衬底基板；金属层，所述金属层位于所述衬底基板上；以及保护层，所述保护层覆盖所述金属层，其中，所述阵列基板或玻璃盖板的封装区内涂布有玻璃料以封装所述阵列基板与玻璃盖板。
相应的，本发明还提供一种显示面板的制造方法，所述方法包括：
采用上述阵列基板的制造方法制造阵列基板，并提供玻璃盖板；
在所述阵列基板或玻璃盖板的封装区涂布玻璃料，将阵列基板与玻璃盖板进行封装；
对所述玻璃料进行激光照射。
可选的，所述激光照射的条件为激光能量在7.2w～7.5w之间，激光移动的速度在10mm/s～11mm/s之间。
与现有技术相比，本发明提供的阵列基板及其制造方法、显示面板及其制造方法中，在衬底基板上形成金属层之后，在金属层上形成保护层，所述保护层能够保护金属层，避免在后续对显示面板内的玻璃料进行激光照射时对金属层造成的损伤，从而降低引线裂纹的发生率，有利于提高显示面板的良率。
进一步的，位于封装区内的保护层至少部分背离所述顶层金属层的表面为为凹面、凸面或凹凸面，在该表面上形成玻璃料，能够提高玻璃料与保护层的粘结力。
附图说明
图1为一显示面板的非显示区的部分结构示意图；
图2为本发明一实施例所提供的阵列基板的制造方法的流程图；
图3为本发明一实施例所提供的阵列基板的非显示区的部分结构示意图；
图4为本发明一实施例所提供的阵列基板的俯视图；
图5为本发明一实施例所提供的显示面板的非显示区的部分结构示意图；
图6为本发明一实施例所提供的显示面板的引线裂纹的数据图；
图7为本发明另一实施例所提供的显示面板的非显示区的部分结构示意图。
具体实施方式
显示面板，例如OLED(有机电致发光二极管)显示面板一般包括相对设置的阵列基板和玻璃盖板。所述显示面板包括显示区与非显示区，在非显示区内设置有封装区，用于涂布玻璃料来封装阵列基板与玻璃盖板。
如图1所示，其为一显示面板的非显示区的部分结构示意图。如图1所示，所述显示面板包括相对设置的衬底基板10与玻璃盖板20。在非显示区内，在所述衬底基板10上形成多层金属层，在图1中仅示出了三层金属层，分别为：底 层金属层11、中间金属层12以及顶层金属层13，三层金属层之间通过介质层14相互隔离，在封装区内的顶层金属层13上直接涂布玻璃料(Frit)15，然后将衬底基板10与玻璃盖板20相封装形成显示面板。所述非显示区内形成的底层金属层11、中间金属层12以及顶层金属层13等金属层属于扇出走线，用于连接驱动芯片与显示区内的数据线、扫描线等，将驱动芯片提供的电信号传输至所述数据线或扫描线。
为了能将衬底基板10与玻璃盖板20良好地封装在一起，本申请的一个实施例的方案如下：提供一衬底基板；在所述衬底基板上形成至少一层金属层；以及形成一保护层，所述保护层覆盖所述金属层。保护层能够保护金属层，并且可以避免后续对显示面板内的玻璃料进行激光照射时对金属层造成损伤(例如，避免金属层在垂直于激光前进的方向上出现裂纹)，从而降低引线裂纹的发生。申请人还意外发现，这种方法还降低了显示面板的亮线不良率，这是由于金属层的损伤或裂纹会导致显示区内的某一条数据线或扫描线无法接收到信号或接受的信号不准确，从而导致显示面板出现亮线。
为使本发明的内容更加清楚易懂，以下结合说明书附图，对本发明的内容做进一步说明。当然本发明并不局限于该具体实施例，本领域的技术人员所熟知的一般替换也涵盖在本发明的保护范围内。
其次，本发明利用示意图进行了详细的表述，在详述本发明实例时，为了便于说明，示意图不依照一般比例局部放大，不应对此作为本发明的限定。
请参考图2所示，其为本发明一实施例所提供的阵列基板的制造方法的流程图，如图2所示，本发明提出一种阵列基板的制造方法，包括以下步骤：
步骤S01：提供一衬底基板，在所述衬底基板上形成至少一层金属层；
步骤S02：形成保护层，所述保护层覆盖所述金属层。
图3为本发明一实施例所提供的阵列基板的非显示区的部分结构示意图，请参考图2所示，并结合图3，详细说明本发明提出的所述阵列基板的制造方法：
在步骤S01中，提供一衬底基板100。在本实施例中，所述衬底基板100包括显示区和非显示区，所述非显示区包围所述显示区，在图3中仅示出了包含封装区的部分非显示区。当然，在其他实施例中，所述非显示区也可以与所 述显示区位于衬底基板的不同表面，例如，所述非显示区位于所述衬底基板的背面，不占用显示区的面积，从而提高分辨率，以及实现窄边框或无边框。本发明对此不做限定。
所述衬底基板100可以由透明材料制成，例如可以是玻璃、石英、硅晶片、聚碳酸酯、聚甲基丙烯酸甲酯或者金属箔等。所述衬底基板100可以为刚性基板，也可以为柔性基板。所述衬底基板100的选择及预处理为本领域技术人员所熟悉，故不再详述。所述显示区后续用于在衬底基板100上形成扫描线、数据线、晶体管开关或像素电极等，所述非显示区后续用于在衬底基板100上形成扇出走线，用于连接显示区的扫描线、数据线等至驱动芯片。
所述非显示区还包括封装区，形成阵列基板之后在所述封装区涂布玻璃料，用于封装阵列基板与玻璃盖板形成显示面板。所述封装区上同样会设置有扇出走线。在一个实施例中，所述封装区呈环形，包围所述显示区。图3中仅示出了包含封装区的部分非显示区的截面图。
接着，在所述衬底基板100上形成至少一层金属层。在本实施例中，在所述衬底基板100的非显示区内形成至少一层金属层，优选的，在所述衬底基板100的非显示区内形成三层金属层，分别为底层金属层110、中间金属层120以及顶层金属层130，在其他实施例中，也可以形成两层、四层或更多的金属层，需要根据阵列基板实际的需求来确定，本发明并不做限定。
优选的，在所述衬底基板100的非显示区内形成多层金属层的同时，在所述衬底基板100的显示区也形成多层金属膜层，例如形成数据线、扫描线或像素电极等，即在显示区内形成数据线、扫描线、像素电极或其他金属膜层的同时在所述非显示区内形成多层金属层。由此，多层金属层的材质取决于在所述显示区内同时形成的数据线、扫描线、像素电极或其他金属膜层的材质，多层金属层的材质可以各不相同，也可以完全相同。所述多层金属层的材质可以包含但不限于铜、铝、镍、镁、铬、钼、钨及其合金等材料。当然，也可以单独在所述衬底基板100的非显示区内形成多层金属层。
所述多层金属层之间通过介质层140相隔离，不同金属层之间的介质层140是在不同的步骤中形成的，但是都起到隔离金属层的作用，因此，在附图3中 没有进行区分。可以理解的是，所述介质层140的形成步骤也与所述显示区内的绝缘层的形成同步，例如，在形成晶体管的栅极绝缘层、层间绝缘层等的过程中形成所述介质层140中的任意一层，则所述介质层的材质与同时形成的栅极绝缘层、层间绝缘层的材质相同。所述介质层140的材质包含但不限于氧化物或氮化物，当然，不同金属层之间的介质层的材质可以不同。可以理解的是，也可以单独的在所述多层金属层之间形成所述介质层140，亦即，在非显示区内形成的多层金属层以及介质层可以与所述显示区内的金属层或绝缘层同时形成，也可以单独的形成。
以下简单介绍在所述衬底基板100的非显示区内形成所述多层金属层以及介质层的其中的一个方法，包括以下步骤：
首先，在所述衬底基板100上形成第一层介质层，优选的可以采用化学气相沉积法形成，例如高密度等离子体化学气相沉积(HDPCVD)、低压化学气相沉积(LPCVD)或超高真空化学气相沉积(UHVCVD)等。然后在所述第一层介质层上形成底层金属，优选的，采用溅射的方法形成；然后对所述底层金属进行图形化，所述图形化工艺例如包括旋涂光刻胶、曝光、显影以及刻蚀工艺，形成底层金属层110。然后重复上述的步骤，在所述底层金属层110上形成第二介质层，所述第二介质层覆盖所述底层金属层110，接着在第二介质层上形成中间金属，并刻蚀形成中间金属层120，然后在中间金属层120上形成第三介质层，所述第三介质层覆盖所述中间金属层120，最后在第三介质层上形成顶层金属，刻蚀之后形成顶层金属层130。所述第一介质层、第二介质层与第三介质层构成图3所示的介质层140。可以理解的是，所述金属层的数量并不限于上述所介绍的三层，也可以仅包括两层金属层，或者是包括四层以上金属层，相应的，介质层的数量也可以根据金属层的数量适应性变化。
在步骤S02中，形成保护层，所述保护层覆盖所述金属层。在本实施例中，在所述非显示区内的多层金属层中的顶层金属层130上形成保护层150。所述保护层150可以是单层结构，也可以是叠层结构。所述保护层150的材质包含但不限于氮化硅、氧化硅或氮氧化硅，当然，所述保护层150的材质也可以为本领域技术人员已知的其他材料，能够保护金属层不受后续封装所使用的激光照 射的破坏即可。由于氮化硅、氧化硅或氮氧化硅为本领域的常规材料，所以可作为本实施例的优选材料。所述保护层150的厚度优选为
Figure PCTCN2018081499-appb-000001
最佳的，所述保护层150的厚度为
Figure PCTCN2018081499-appb-000002
该厚度的所述保护层150能够保护金属层不受激光照射的损伤，也不会对最终形成的显示面板的厚度造成影响。
本实施例中，采用化学气相沉积法形成所述保护层150，形成所述保护层150的条件优选为：腔室温度350℃～400℃，腔室压强900mtorr～1100mtorr，成膜时间350s～450s，最佳的，腔室温度为385℃，腔室压强1000mtorr，成膜时间400s。
优选的，在非显示区内的顶层金属层130上形成保护层150的同时，在所述显示区内也形成保护层，即在整个所述衬底基板100上同时形成保护层，并对所述显示区内设置有接触孔的位置处的保护层进行刻蚀，暴露出所述接触孔，避免保护层对显示区的连接造成影响。在显示区内形成保护层之前的膜层并不受限定，例如，在显示区内形成数据线的同时，在所述非显示区内形成顶层金属层，之后如果直接形成保护层，则在显示区内，是在数据线上形成保护层，如果在显示区内还要在数据线上形成其他膜层(例如扫描线)之后再形成保护层，则在显示区内，是在扫描线上形成保护层。
在顶层金属层130上形成保护层150，所述保护层150用于保护金属层，避免后续进行激光照射时激光对金属层造成的影响，从而避免引线裂纹的产生，降低引线裂纹的发生率，最终提高了显示面板的良率。
接着，还可以对所述保护层150进行图形化，优选的，对所述保护层150进行刻蚀，只需保留封装区内的顶层金属层130上的保护层150即可(如图3所示)。图4为本发明一实施例所提供的阵列基板的俯视图，请参考图4所示，所述阵列基板包含显示区10与包围所述显示区10的非显示区20，在所述非显示区20内设置有封装区30与绑定区40，所述封装区30呈环形，包围所述显示区10，所述绑定区40位于所述封装区30与所述阵列基板一侧边缘之间的非显示区20上。优选的，仅在所述封装区30上形成有保护层150。这样不仅可以减少引线裂纹的发生，而且还可以避免由于非显示区其余区域内形成保护层所造成的静电不良，例如避免所述绑定区40内的检测电路(CT电路)被保护层覆 盖所造成的静电不良。当然，也可以不对非显示区其余区域内的保护层150进行刻蚀，即所述保护层150位于整个所述非显示区，这样能够降低微亮线的产生，但是静电不良的产生会升高。即除所述保护层150位于封装区上方能够降低引线裂纹的产生之外，在非显示区的其余位置处形成保护层能够降低微亮线的产生。
在对所述保护层150进行刻蚀时，还可以同时刻蚀去除显示区域的保护层，也就是说，在形成所述保护层之后，需要对显示区内设置有接触孔的位置处的保护层进行刻蚀，暴露出所述接触孔，在该刻蚀过程中，可以刻蚀去除非显示区除封装区之外的其余区域内的保护层，也可以将显示区内的所有保护层均刻蚀掉，需要根据实际情况进行选择。
具体的，在所述保护层150上涂布光刻胶层，通过掩膜板对所述光刻胶层进行曝光，对于正光刻胶而言，所述掩模板可以仅暴露出所述显示区内的接触孔，或者暴露出整个显示区，或者暴露出非显示区内除封装区之外的其他区域，或者暴露出除封装区以外的所有区域，根据具体情况来确定所使用的掩模板。然后对经过曝光的光刻胶层进行显影，形成图形化的光刻胶层，然后以所述图像化的光刻胶层为掩膜对所述保护层进行刻蚀，最后剥离剩余的光刻胶层，形成所需的保护层的图案。
需要说明的是，以图形化的光刻胶层为掩膜对保护层进行刻蚀的过程中，要避免对保护层之下的其他膜层造成损伤，例如刻蚀非显示区除封装区外其余区域的保护层时，要避免对保护层下的顶层金属层造成损伤。针对该问题，可以调节刻蚀选择比，选择合适的刻蚀选择比对所述保护层进行刻蚀，保证对所述保护层具有高的刻蚀率，对于其余膜层具有低的刻蚀率，或者不对其余膜层进行刻蚀。例如，采用等离子体刻蚀对所述保护层进行刻蚀，所述刻蚀气体包含但不限于C 2HF 5(五氟乙烷)、H 2(氢气)与Ar(氩气)的混合气体，所述保护层与其余膜层的刻蚀选择比优选为大于5:1。
另外，在对所述保护层150进行刻蚀的步骤中，还可以对所述封装区内的保护层150进行部分刻蚀，使得封装区内的保护层150至少有部分背离所述顶层金属层130的表面为凹面、凸面或凹凸面，即所述保护层150至少有部分背 离所述顶层金属层130的表面为非平面表面，使得之后涂覆的玻璃料与所述保护层150具有更好的粘接力，即通过非平面表面提高玻璃料与保护层的粘接力，从而提高最终形成的显示面板的可靠性。
优选的，所述凹面或凸面为圆柱体、圆锥体、圆台或半球体中的一种或两种以上的组合，所述凹凸面由所述凹面、凸面交错相连而成，也可以是由所述凹面、凸面交错间隔分布而成。所述凹面例如是由形成于所述保护层150表面的若干凹槽构成，这些凹槽的尺寸和形状可以相同，也可以不相同。所述凸面例如是由形成于所述保护层150表面的若干凸起构成，这些凸起的尺寸和形状可以相同，也可以不相同。所述凹凸面则是由形成于所述保护层150表面的若干凹槽和若干凸起共同构成，同样的，不限定凹槽和凸起的形状和尺寸。
当然，也可以只在封装区内形成所述保护层150，从而避免对所述保护层150的刻蚀，可以节省制作时间并节约制作成本。例如，制作暴露出封装区的掩模板，以该掩模板为掩膜沉积形成保护层，但是采用该方法制作的保护层的精度相对较低，如果产品规格不是很高或者设备的能力较好时，完全可以采用掩模板加化学气相沉积的方法在封装区形成保护层。当然，是形成保护层之后再进行刻蚀，还是只在需要的地方形成保护层，需要根据实际需求来决定，本发明并不做限定。当然，也可以采用本领域技术人员已知的其他方法形成所述保护层。
最终形成如图4所示的结构，形成所述保护层150之后，进行封装之前还包括完成衬底基板100显示区内各膜层的制作，其制作方法为本领域技术人员所熟悉，故不再详述，最终完成阵列基板的制作。
相应的，本发明还提供一种显示面板的制造方法，包括如上所述的阵列基板的制造方法，所述显示面板的制造方法包括：
完成阵列基板的制作，并提供玻璃盖板200；
在所述阵列基板或玻璃盖板200的封装区涂布玻璃料160，将阵列基板与玻璃盖板200相封装；通过涂布玻璃料160将阵列基板与玻璃盖板200进行封装形成显示面板，最终形成如图5所示的结构，之后对玻璃料160激光照射进行熔融时，所述保护层150能够保护金属层，避免金属层产生裂纹，降低了裂纹 的发生率，提高了显示面板的良率。
请参考图6所示，其为本发明一实施例所提供的显示面板的引线裂纹的数据示意图。如图6所示，以某一尺寸，例如以5.5英寸的显示面板为例来进行验证，在封装区的顶层金属层上形成保护层，裂纹发生的比例相比以前的20％(未形成保护层)发生大幅下降。需要说明的是，在图5的表格中7.5w 11mm/s这一行代表的是进行激光照射的条件，其中7.5w代表激光的能量，11mm/s代表激光移动的速度，从图5可以看出，在形成保护层的基础上，对激光照射的条件进行调整能够完全避免裂纹现象，激光照射的较佳条件为：激光能量在7.2w～7.5w之间，激光移动的速度在10mm/s～11mm/s之间。
请参考表1所示，其为本发明一实施例所提供的显示面板的可靠性结果示意图。如表1所示，对本发明所提供的阵列基板的制造方法最终制造而成的显示面板进行可靠性验证，例如：进行温湿度动作试验，温度为60℃，湿度为90％RH，试验时间为120H，10片显示面板在试验到60H时出现1片R/G/B暗点(红/绿/蓝暗点)不良，经研究发现，该不良是阳极黑点，是由阳极制作异常或阳极刻蚀异常所导致的，与裂纹无关。进行高温动作试验，温度为60℃，试验时间为120H，无新增异常。进行高温存储试验，温度为70℃，试验时间为120H，也无新增异常。因此，可以确定在封装区的顶层金属层上形成保护层的方法能够降低裂纹的发生率，并且不会产生其他的异常。
表1
Figure PCTCN2018081499-appb-000003
相应的，本发明还提供一种阵列基板，采用如上所述的阵列基板的制造方法制造而成。所述阵列基板包括：
衬底基板；
金属层，所述金属层位于所述衬底基板上；以及
保护层，所述保护层覆盖所述金属层。
具体的，请参考图3所示，所述阵列基板包括：包含显示区和非显示区的衬底基板100(图3中仅示出了包含封装区的部分非显示区)，位于所述衬底基板100的非显示区内的多层金属层，优选为三层，即底层金属层110、中间金属层120以及顶层金属层130，还包括位于三层金属层之间、包围底层金属层110与中间金属层120、并且位于底层金属层110与衬底基板100之间的介质层140；还包括位于顶层金属层130上的保护层150。
在本实施例中，所述保护层150仅位于封装区内的顶层金属层130的上方。在其他实施例中，所述保护层150还可以位于非显示区除去封装区之外的其他区域，或者，所述保护层150还可以位于显示区，当然，在所述显示区设置有接触孔的位置处，所述保护层150需要去除，防止对显示区的接触造成影响。
相应的，本发明还提供一种显示面板，采用如上所述的显示面板的制造方法制造而成。所述显示面板包括：
阵列基板，所述阵列基板包括：衬底基板；金属层，所述金属层位于所述衬底基板上；以及保护层，所述保护层覆盖所述金属层；
玻璃料，所述玻璃料位于所述保护层上；以及
玻璃盖板，所述玻璃盖板位于所述玻璃料上。
具体的，请参考图7所示，其为本发明另一实施例所提供的显示面板的非显示区的部分结构示意图，其中阵列基板内非显示区的金属层及保护层均与显示区内的金属层及保护层在同一步骤中形成。
如图7所示，所述显示面板包括：
阵列基板，所述阵列基板包括：包含显示区和非显示区的衬底基板300(图6中仅示出了包含封装区的部分非显示区)；依次位于衬底基板300的非显示区内的第一介质层310、第二介质层320以及第三介质层330，以及位于所述第三 介质层内的底层金属层340，位于所述第三介质层330上的中间金属层350，以及位于所述第三介质层330及中间金属层350上的第四介质层360，以及位于第四介质层360上的顶层金属层370，并且所述第一介质层310、第二介质层320、第三介质层330以及第四介质层360均与显示区内的介质层或绝缘层在同一步骤中形成，优选的介质层的材质均为氧化硅或氮化硅；所述阵列基板还包括位于所述第四介质层360及顶层金属层370上的保护层380。
玻璃料390，位于所述保护层380之上。
玻璃盖板400，所述玻璃盖板400通过所述玻璃料390与所述阵列基板进行封装。
综上所述，本发明提供的阵列基板及其制造方法、显示面板及其制造方法中，在衬底基板上形成金属层之后，在金属层上形成保护层，所述保护层能够保护金属层，避免后续显示面板内的玻璃料进行激光照射时对金属层造成的损伤，从而降低引线裂纹的发生率，有利于提高显示面板的良率。
进一步的，位于封装区内的保护层至少部分背离所述顶层金属层的表面为凹面、凸面或凹凸面，在该表面上形成玻璃料，能够提高玻璃料与保护层的粘结力。
上述描述仅是对本发明较佳实施例的描述，并非对本发明范围的任何限定，本发明领域的普通技术人员根据上述揭示内容做的任何变更、修饰，均属于权利要求书的保护范围。

Claims (16)

  1. 一种阵列基板，其特征在于，所述阵列基板包括：
    衬底基板；
    金属层，所述金属层位于所述衬底基板上；以及
    保护层，所述保护层覆盖所述金属层。
  2. 如权利要求1所述的阵列基板，其特征在于，所述保护层的材质为氮化硅、氧化硅、氮氧化硅中的一种或其组合。
  3. 如权利要求1所述的阵列基板，其特征在于，所述衬底基板包括封装区，所述保护层覆盖所述封装区内的所述金属层。
  4. 如权利要求3所述的阵列基板，其特征在于，所述封装区内的保护层的背离所述金属层的表面的至少一部分为凹面、凸面或凹凸面。
  5. 如权利要求4所述的阵列基板，其特征在于，所述凹面或凸面为圆柱体、圆锥体、圆台或半球体中的一种或两种以上的组合，所述凹凸面由所述凹面、所述凸面交错相连而成或交错间隔分布构成。
  6. 如权利要求1所述的阵列基板，其特征在于，所述衬底基板包括显示区和非显示区，所述金属层包括若干层，形成于所述非显示区内，所述若干层金属层之间设有介质层，所述金属层为扇出走线，用于传输设于所述显示区的驱动芯片提供的电信号。
  7. 一种阵列基板的制造方法，其特征在于，包括：
    提供一衬底基板，在所述衬底基板上形成至少一层金属层；
    形成保护层，所述保护层覆盖所述金属层。
  8. 如权利要求7所述的阵列基板的制造方法，其特征在于，所述衬底基板包括封装区；所述保护层覆盖所述封装区内的所述金属层。
  9. 如权利要求8所述的阵列基板的制造方法，其特征在于，所述衬底基板 包括显示区和非显示区，所述封装区位于所述非显示区内；
    所述金属层同时形成在所述非显示区和所述显示区内；
    所述保护层同时形成在所述非显示区和所述显示区内，且所述方法还包括去除所述显示区内对应于接触孔的位置处的保护层，暴露出所述接触孔。
  10. 一种显示面板，其特征在于，所述显示面板包括阵列基板及玻璃盖板，所述阵列基板包括：
    衬底基板；
    金属层，所述金属层位于所述衬底基板上；以及
    保护层，所述保护层覆盖所述金属层，
    其中，所述阵列基板或玻璃盖板的封装区内涂布有玻璃料以封装所述阵列基板与玻璃盖板。
  11. 如权利要求10所述的显示面板，其特征在于，所述衬底基板包括显示区和非显示区，所述非显示区包围所述显示区，所述金属层包括若干层，形成于所述非显示区内，所述若干层金属层之间设有介质层，所述金属层为扇出走线，用于传输设于所述显示区的驱动芯片提供的电信号。
  12. 如权利要求10所述的显示面板，其特征在于，所述保护层的材质为氮化硅、氧化硅、氮氧化硅中的一种或其组合。
  13. 如权利要求10所述的阵列基板，其特征在于，所述衬底基板包括封装区，所述保护层覆盖所述封装区内的所述金属层。
  14. 如权利要求13所述的阵列基板，其特征在于，所述封装区内的保护层的背离所述金属层的表面的至少一部分为凹面、凸面或凹凸面，所述凹面或凸面为圆柱体、圆锥体、圆台或半球体中的一种或两种以上的组合，所述凹凸面由所述凹面、所述凸面交错相连而成或交错间隔分布构成。
  15. 一种显示面板的制造方法，其特征在于，所述方法包括：
    采用如权利要求7～9中任一项所述的阵列基板的制造方法制造阵列基板， 并提供玻璃盖板；
    在所述阵列基板或玻璃盖板的封装区涂布玻璃料，将阵列基板与玻璃盖板进行封装；
    对所述玻璃料进行激光照射。
  16. 如权利要求15所述的显示面板的制造方法，其特征在于，所述激光照射的条件为激光能量在7.2w～7.5w之间，激光移动的速度在10mm/s～11mm/s之间。
PCT/CN2018/081499 2017-08-09 2018-04-02 阵列基板及其制造方法、显示面板及其制造方法 WO2019029169A1 (zh)

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