WO2020147216A1 - Tft阵列基板的制备方法及tft阵列基板 - Google Patents

Tft阵列基板的制备方法及tft阵列基板 Download PDF

Info

Publication number
WO2020147216A1
WO2020147216A1 PCT/CN2019/084007 CN2019084007W WO2020147216A1 WO 2020147216 A1 WO2020147216 A1 WO 2020147216A1 CN 2019084007 W CN2019084007 W CN 2019084007W WO 2020147216 A1 WO2020147216 A1 WO 2020147216A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
light
gate
tft array
array substrate
Prior art date
Application number
PCT/CN2019/084007
Other languages
English (en)
French (fr)
Inventor
马倩
Original Assignee
深圳市华星光电半导体显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Priority to US16/627,819 priority Critical patent/US11469328B2/en
Publication of WO2020147216A1 publication Critical patent/WO2020147216A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1237—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a different composition, shape, layout or thickness of the gate insulator in different devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors

Definitions

  • the present invention relates to the field of display technology, in particular to a method for preparing a TFT array substrate and a TFT array substrate.
  • Top-gate self-aligned oxide is the preferred TFT (Thin Film Transistor (thin film transistor) backplane technology
  • top gate self-aligned oxide TFT devices usually use IGZO (indium gallium zinc oxide (indium gallium zinc oxide) is used as the active layer. This material is sensitive to light. Therefore, oxide TFT devices will be designed with a light-shielding layer to block the light at the bottom of the TFT device.
  • IGZO indium gallium zinc oxide
  • oxide TFT devices will be designed with a light-shielding layer to block the light at the bottom of the TFT device.
  • the gate, source, drain and light-shielding layer of the TFT device are made of metal materials, light is reflected by the interlayer of the metal inside the device, and a part of the light will eventually be reflected to the The source layer in turn affects the performance of the TFT device and affects the life of the device.
  • the present invention provides a method for preparing a TFT array substrate and a TFT array substrate to solve the problem of the existing TFT array substrate. Since most of the TFT devices are made of metal materials, the light is reflected by the metal inside the device, causing a part of the light to end up Reflect to the active layer, and then affect the performance of the TFT device, and affect the technical problem of the life of the device.
  • the present invention provides a method for preparing a TFT array substrate, including:
  • a light absorbing layer is prepared on the side of the light shielding layer close to the active layer, and the gate and the gate insulating layer are prepared through the same yellow light process.
  • the S10 includes:
  • the preparation process of the gate and the gate insulating layer includes:
  • the gate is self-aligned, and the gate insulating material is etched to form a patterned gate insulating layer.
  • the present invention provides another method for preparing a TFT array substrate, including:
  • a light absorption layer is prepared on the side of the light shielding layer close to the active layer.
  • the S10 includes:
  • the light absorption layer is prepared on the side of the source and drain metal layer close to the active layer.
  • the S20 includes:
  • the gate and the gate insulating layer are prepared through the same yellowing process.
  • the preparation process of the gate and the gate insulating layer includes:
  • the gate is self-aligned, and the gate insulating material is etched to form a patterned gate insulating layer.
  • the present invention also provides a TFT array substrate, including: a substrate, a light shielding layer formed on the substrate, a buffer layer formed on the light shielding layer, an active layer formed on the buffer layer, The gate insulating layer on the active layer, the gate formed on the gate insulating layer, the interlayer insulating layer formed on the gate, and the source and drain formed on the interlayer insulating layer Metal layer; wherein a light absorption layer is provided on one side of the active layer.
  • the light absorption layer is disposed on a side of the light shielding layer close to the active layer.
  • the light absorption layer and the light shielding layer are arranged correspondingly.
  • the light absorption layer is disposed on a side of the source and drain metal layer close to the active layer.
  • the light absorbing layer is disposed corresponding to the source and drain metal layer.
  • the light absorption layer is a black photoresist layer.
  • the beneficial effects of the present invention are: in the present invention, by arranging a black photoresist under the source and drain electrodes or setting a black photoresist as an absorbing layer above the light shielding layer to absorb light, it can prevent most of the light from being reflected to the active layer, thereby improving TFT device performance; in addition, the absorption layer is formed by a black photoresist that has not been stripped after the other film layers are etched, and no new manufacturing process is generated, the process is simple, and the cost is saved.
  • FIG. 1 is a flow chart of the steps of the method for preparing the TFT array substrate of the present invention
  • FIG. 2 is a flow chart of the steps of a method for manufacturing a TFT array substrate according to the first embodiment of the present invention
  • FIG. 3 is a schematic diagram of the structure of a TFT array substrate according to the first embodiment of the present invention.
  • FIGS. 4 to 6 are schematic diagrams of the structure during the manufacturing process of the TFT array substrate according to the first embodiment of the present invention.
  • FIG. 7 is a flow chart of the steps of the manufacturing method of the TFT array substrate of the second embodiment of the present invention.
  • FIG. 8 is a schematic diagram of the structure of a TFT array substrate according to the second embodiment of the present invention.
  • 9 to 10 are schematic diagrams of the structure during the manufacturing process of the TFT array substrate of the second embodiment of the present invention.
  • the present invention is aimed at the existing TFT array substrate. Since the gate, source and drain, and light-shielding layer in the array substrate are made of metal materials, light is reflected by the interlayer of the metal inside the device, causing a part of the light to eventually be reflected to the active layer, affecting The performance of the TFT device and the technical problem that affects the lifetime of the device can be solved by this embodiment.
  • the present invention provides a method for preparing a TFT array substrate, which includes: providing a substrate, on which a light shielding layer and a buffer layer are sequentially prepared; and an active layer and a gate are sequentially prepared on the buffer layer.
  • the active layer Since the active layer is sensitive to light, it is made of metal materials. The light is reflected by the gate, source, drain and light shielding layer inside the TFT device, which causes part of the light to be reflected to the active layer, which affects the device. The performance is affected. Therefore, the light-absorbing layer prepared in the present invention mainly targets the above-mentioned metal layer, and plays a role of absorbing light.
  • the light-absorbing layer can be prepared on the side of the light-shielding layer close to the active layer to absorb and reflect
  • the light on the light shielding layer can also be prepared on the side of the source and drain metal layer close to the active layer to absorb the light reflected on the source and drain metal layer.
  • the present invention provides a method for preparing a TFT array substrate 10, which includes the following steps:
  • the substrate 11 is cleaned first.
  • the substrate 11 may be a glass substrate or a flexible substrate, such as a base imide substrate.
  • the light shielding layer 12 is prepared by depositing a metal film layer 121 on the substrate 11.
  • the thickness of the metal film layer 121 is between 500 and 2000 angstroms, and the metal film layer 121 can be Preparation of an alloy composed of one or more of molybdenum, aluminum, copper, and titanium.
  • a black photoresist 131 is coated on the surface of the metal film layer 121, and the black photoresist 131 is exposed by a mask. After development, a predetermined pattern of light absorbing layer 13 is formed, and then the The metal film layer 121 is etched to obtain the patterned light shielding layer 12. After the etching is completed, the black photoresist is not stripped off, that is, the light absorbing layer 12 is formed on the light shielding layer 12.
  • the light-shielding layer 12 is made of metal, when light is irradiated on the light-shielding layer 12, it will be reflected to the active layer 15, which will adversely affect the electrical performance of the TFT device.
  • the commonly used photoresist material is replaced with a black photoresist. After the etching is completed, the black photoresist is not peeled off, which has the effect of absorbing light and will not produce unnecessary manufacturing processes.
  • silicon oxide or silicon nitride is deposited on the substrate 11 as the buffer layer 14.
  • the buffer layer 14 is etched by the same yellow light process, and the buffer layer 14 is A first via hole 141 is formed, and a second via hole 132 is formed on the light absorbing layer.
  • the second via hole 132 communicates with the first via hole 141 to form a channel for realizing the source and drain metal
  • the source or drain on the layer 19 is in contact with the light shielding layer 12 to realize the signal connection of the light shielding layer 12.
  • the buffer layer 14 may be a composite structure of multiple inorganic film layers.
  • the buffer layer covers the substrate 11 and the light absorption layer 13 to protect the underlying substrate.
  • the overall thickness of the buffer layer 14 is 1000 ⁇ Between 5000 Angstroms.
  • a layer of metal oxide semiconductor material is deposited on the buffer layer 14 as the active layer 15.
  • the semiconductor material is one of indium gallium zinc oxide, indium zinc tin oxide, or indium gallium zinc tin oxide
  • the thickness of the active layer 15 is between 100 and 1000 angstroms.
  • the gate insulating layer 16 and the gate 17 are prepared, and the pattern of the gate 17 is first etched, and then the gate 17 is self-aligned, and the gate insulating layer 16 is etched only on the gate 17 The gate insulating layer 16 exists under 17 and the remaining part of the gate insulating layer material is etched away.
  • the active layer 15 is subjected to surface plasma treatment, so that the part of the active layer 15 covered by the gate insulating layer 16 is not processed, and the semiconductor characteristics are maintained as a TFT channel, and the rest is processed , The resistance is reduced, and an N+ conductor layer is formed.
  • the gate insulating layer 16 may be a composite structure of multiple film layers, and the overall thickness of the gate insulating layer 16 is 1000-3000 angstroms.
  • the gate 17 can be made of one of molybdenum, aluminum, copper, and titanium, or an alloy of two or more of them, and the overall thickness of the gate 17 is 2000-8000 angstroms.
  • the interlayer insulating layer 18 is etched to form a third via hole and a fourth via hole with different depths on the interlayer insulating layer 18.
  • the third via hole The depth of is greater than the depth of the fourth via, and the transmittance of the mask corresponding to the third via is greater than the transmittance of the mask corresponding to the fourth via.
  • the third via hole communicates with the second via hole and the first via hole, and the three form a channel.
  • the thickness of the interlayer insulating layer 18 is 2000-10000 angstroms.
  • a metal layer is deposited on the interlayer insulating layer 18 as the source/drain metal layer 19, and the source or drain of the source/drain metal layer passes through the third via hole and the first via hole 141
  • the second via hole 132 is in contact with the light shielding layer 12 to realize signal connection of the light shielding layer, and the source and drain are connected to the active layer through the fourth via hole.
  • the thickness of the source and drain metal layer 19 is 2000-8000 angstroms.
  • an inorganic film layer is deposited on the source and drain metal layer 19 as a passivation layer.
  • the passivation layer can be silicon nitride or silicon oxide, and the thickness of the passivation layer is 1000-5000 angstroms.
  • the preparation method provided by the present invention can be applied to the preparation of display panels. After the TFT array substrate of the present invention is completed, a planarization layer, an anode, a pixel definition layer, a light emitting layer, an encapsulation layer, etc. can be sequentially prepared on the passivation layer. Preparation of display panel.
  • a layer of black photoresist is provided on the light shielding layer.
  • the black photoresist is provided under the source and drain of the source and drain metal layers in this embodiment.
  • this embodiment provides another method for preparing the TFT array substrate 20, including:
  • a substrate 21 is provided, and a light shielding layer 22 and a buffer layer 23 are sequentially prepared on the substrate;
  • a first via 231 is formed on the buffer layer 23, a third via 271 and a fourth via 272 are formed on the interlayer insulating layer 27, and the light absorbing layer A second via 281 is formed thereon, as shown in FIG. 8.
  • the second via 281 is in communication with the fourth via 272, and the source and drain on the source-drain metal layer 29 pass through the second via 282, the fourth via 272 and the
  • the active layer 24 is in contact and connected, the third via 271 communicates with the second via 281 and the first via 231, and the three form a via, and the source or drain passes through the second via
  • the hole 281, the third via hole 271, and the first via hole 231 are in contact with the light shielding layer 22.
  • the preparation of the light absorbing layer 28 is described in detail.
  • preparation methods of other film layers please refer to the first embodiment, which will not be repeated here.
  • a layer of inorganic material is deposited on the buffer layer 23, and then a black photoresist is coated on the surface of the inorganic material, and the black photoresist is exposed with a mask with different light transmittance, and after development, a predetermined pattern is formed
  • the light absorbing layer 28, the second via 281 is formed on the light absorbing layer 28, and then the inorganic material is etched to form the patterned interlayer insulating layer 27, in the
  • the third via 271 and the fourth via 272 are formed on the interlayer insulating layer 27, and after the etching is completed, the black photoresist is not stripped.
  • a metal layer is deposited on the light absorbing layer, and then the metal layer is etched by a yellow light process to form the source and drain of the source and drain metal layer 29, and then The source electrode and the drain electrode are self-aligned, and the light absorption layer 28 is continuously etched, so that the part of the light absorption layer 28 outside the region of the source and drain metal layer 29 is etched away.
  • a black light absorbing layer is provided under the source and drain of the source and drain metal layer 29, which can absorb the light reflected between the metal layers inside the TFT device, and reduce the reflection of light under the source and drain to the active layer.
  • the light absorbing layer 28 is a black photoresist layer left after the interlayer insulating layer 27 is etched to form via holes by a yellow light process, and no unnecessary manufacturing process is generated.
  • the present invention also provides a TFT array substrate prepared by the above method, including a substrate, a light shielding layer, a buffer layer, an active layer, a gate insulating layer, a gate electrode, an interlayer insulating layer, a source and drain metal layer, and a passivation
  • the TFT array substrate further includes a light absorption layer.
  • the light absorbing layer is arranged on one side of the active layer to absorb the light reflected by the metal film layer inside the TFT device and prevent the light from entering the active layer.
  • the light absorbing layer 13 is disposed on the side of the light shielding layer 12 close to the active layer 15. Specifically, the light absorbing layer 13 may be disposed on the The upper surface of the light-shielding layer 12 covers the light-shielding layer 12 for absorbing light reflected on the light-shielding layer 12, and the light absorbing layer 13 is a black photoresist.
  • the light absorbing layer 28 is disposed on the side of the source-drain metal layer 29 close to the active layer 24, that is, disposed on the side of the source-drain metal layer 29 Below, corresponding to the source and drain of the source and drain metal layer, to absorb light reflected to the source and drain, the light absorbing layer covers the interlayer insulating layer 27, and the light absorbing layer 28 is Black photoresist.
  • a black photoresist is arranged below the source and drain or a black photoresist is arranged as an absorption layer above the light shielding layer to absorb light, which can prevent most of the light from being reflected to the active layer, thereby improving the performance of the TFT device;
  • the absorption layer is formed by a black photoresist that has not been stripped after the other film layers are etched, and no new manufacturing process will be generated, the process is simple, and the cost is saved.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Thin Film Transistor (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种TFT阵列基板的制备方法，包括提供一基板，在基板上制备遮光层、缓冲层；在所述缓冲层上制备有源层、栅极绝缘层、栅极、层间绝缘层、以及源漏金属层；其中，在有源层的一侧制备光吸收层。通过在源漏极下方或在遮光层上方设置黑色光阻作为吸收层，用以吸收光线，能够避免大部分光线反射到有源层，进而改善TFT器件性能。

Description

TFT阵列基板的制备方法及TFT阵列基板 技术领域
本发明涉及显示技术领域，尤其涉及一种TFT阵列基板的制备方法及TFT阵列基板。
 背景技术
顶栅自对准氧化物由于寄生电容较小，是目前大尺寸显示面板首选的TFT（Thin Film Transistor，薄膜晶体管）背板技术，顶栅自对准氧化物TFT器件通常采用IGZO（indium gallium zinc oxide，铟镓锌氧化物）作为有源层，这种材料对光照敏感，因此氧化物TFT器件会设计一层遮光层，用以遮挡TFT器件底部的光。
但在实际工艺制作过程中，由于TFT器件的栅极、源极、漏极以及遮光层都是由金属材料制作而成的，光线经由器件内部金属的层间反射，一部分光线最终会反射到有源层，进而影响TFT器件性能，影响器件的寿命。
 技术问题
本发明提供一种TFT阵列基板的制备方法及TFT阵列基板，以解决现有的TFT阵列基板，由于TFT器件大部分是由金属材料制备，光线经由器件内部金属的层间反射，导致一部分光线最终反射到有源层，进而影响到TFT器件性能，影响器件的寿命的技术问题。
 技术解决方案
为解决上述问题，本发明提供的技术方案如下：
本发明提供一种TFT阵列基板的制备方法，包括：
S10，提供一基板，在所述基板上依次制备遮光层、缓冲层；
S20，在所述缓冲层上依次制备有源层、栅极绝缘层、栅极、层间绝缘层、以及源漏金属层；其中，
在所述遮光层靠近所述有源层的一侧制备光吸收层，所述栅极和所述栅极绝缘层经过同一道黄光工艺制备。
在本发明的至少一种实施例中，所述S10包括：
S101，提供一基板，在所述基板上沉积金属膜层；
S102，在所述金属膜层表面涂布黑色光阻，对所述黑色光阻进行曝光、显影，形成光吸收层；
S103，对所述金属膜层进行刻蚀，形成图案化的遮光层；
S104，在所述光吸收层上制备所述缓冲层。
在本发明的至少一种实施例中，所述栅极和所述栅极绝缘层的制备过程包括：
在所述有源层表面沉积一层栅极绝缘材料；
在所述栅极绝缘材料表面沉积一层栅极金属薄膜；
在所述栅极金属薄膜表面形成图案化的光刻胶，对所述栅极金属薄膜进行刻蚀，形成图案化的所述栅极；
以所述栅极为自对准，对所述栅极绝缘材料进行刻蚀，形成图案化的栅极绝缘层。
本发明提供另一种TFT阵列基板的制备方法，包括：
S10，提供一基板，在所述基板上依次制备遮光层、缓冲层；
S20，在所述缓冲层上依次制备有源层、栅极绝缘层、栅极、层间绝缘层、以及源漏金属层；其中，在所述有源层的一侧制备光吸收层
在本发明的至少一种实施例中，在所述遮光层靠近所述有源层的一侧制备光吸收层。
在本发明的至少一种实施例中，所述S10包括：
S101，提供一基板，在所述基板上沉积金属膜层；
S102，在所述金属膜层表面涂布黑色光阻，对所述黑色光阻进行曝光、显影，形成光吸收层；
S103，对所述金属膜层进行刻蚀，形成图案化的遮光层；
S104，在所述光吸收层上制备所述缓冲层。
在本发明的至少一种实施例中，在所述源漏金属层靠近所述有源层的一侧制备所述光吸收层。
在本发明的至少一种实施例中，所述S20包括：
S201，在所述缓冲层上依次制备有源层、栅极绝缘层、栅极；
S202，在所述缓冲层上沉积无机材料；
S203，在所述无机材料表面涂布黑色光阻，对所述黑色光阻进行曝光、显影，形成光吸收层；
S204，对所述无机材料进行刻蚀，形成图案化的层间绝缘层；
S205，在所述光吸收层上制备源漏金属层。
在本发明的至少一种实施例中，所述栅极和所述栅极绝缘层经过同一道黄光工艺制备。
在本发明的至少一种实施例中，所述栅极和所述栅极绝缘层的制备过程包括：
在所述有源层表面沉积一层栅极绝缘材料；
在所述栅极绝缘材料表面沉积一层栅极金属薄膜；
在所述栅极金属薄膜表面形成图案化的光刻胶，对所述栅极金属薄膜进行刻蚀，形成图案化的所述栅极；
再以所述栅极为自对准，对所述栅极绝缘材料进行刻蚀，形成图案化的栅极绝缘层。
本发明还提供一种TFT阵列基板，包括：基板、形成于所述基板上的遮光层、形成于所述遮光层上的缓冲层、形成于所述缓冲层上的有源层、形成于所述有源层上的栅极绝缘层、形成于所述栅极绝缘层上的栅极、形成于所述栅极上的层间绝缘层、以及形成于所述层间绝缘层上的源漏金属层；其中，所述有源层的一侧设置有光吸收层。
在本发明的至少一种实施例中，所述光吸收层设置于所述遮光层靠近所述有源层的一侧。
在本发明的至少一种实施例中所述光吸收层与所述遮光层对应设置。
在本发明的至少一种实施例中，所述光吸收层设置于所述源漏金属层靠近所述有源层的一侧。
在本发明的至少一种实施例中，所述光吸收层与所述源漏金属层对应设置。
在本发明的至少一种实施例中，所述光吸收层为黑色光阻层。
 有益效果
本发明的有益效果为：本发明通过在源漏极下方设置黑色光阻或在遮光层上方设置黑色光阻作为吸收层，用以吸收光线，能够避免大部分光线反射到有源层，进而改善TFT器件性能；另外，吸收层是在其他膜层刻蚀完成后未剥离的黑色光阻形成的，不会产生新的制程，工艺简单，节约成本。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为为本发明的TFT阵列基板的制备方法的步骤流程图；
图2为本发明实施例一的TFT阵列基板的制备方法的步骤流程图；
图3为本发明实施例一的TFT阵列基板的结构示意图；
图4~图6为本发明实施例一的TFT阵列基板制备过程中的结构示意图；
图7为本发明实施例二的TFT阵列基板的制备方法的步骤流程图；
图8为本发明实施例二的TFT阵列基板的结构示意图；
图9~图10为本发明实施例二的TFT阵列基板制备过程中的结构示意图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是用以相同标号表示。
本发明针对现有TFT阵列基板，由于阵列基板中的栅极、源漏极以及遮光层由金属材料制作，光线经由器件内部金属的层间反射，导致一部分光线最终会反射到有源层，影响TFT器件的性能，进而影响器件寿命的技术问题，本实施例能够解决该缺陷。
如图1所示，本发明提供一种TFT阵列基板的制备方法，包括：提供一基板，在所述基板上依次制备遮光层、缓冲层；在所述缓冲层上依次制备有源层、栅极绝缘层、栅极、以及层间绝缘层、以及源漏金属层；其中，在所述有源层的一侧制备光吸收层。
由于有源层对光照敏感，都是由金属材料制作而成的，光线经由TFT器件内部的栅极、源极、漏极以及遮光层层间反射，导致部分光线反射到有源层，对器件性能造成影响，因此本发明制备的光吸收层主要针对上述金属层，起到吸收光线的作用，所述光吸收层可制备在所述遮光层靠近所述有源层的一侧，吸收反射到所述遮光层上的光线，也可制备在所述源漏金属层靠近所述有源层的一侧，吸收反射到所述源漏金属层上的光线。下面结合具体实施例，对本发明进行详细说明。
实施例一
如图2~5所示，本发明提供一种TFT阵列基板10的制备方法，包括以下步骤：
S10，提供一基板11，在所述基板11上沉积金属膜层121；
S20，在所述金属膜层121表面涂布黑色光阻131，对所述黑色光阻131进行曝光、显影，形成光吸收层13；
S30，对所述金属膜层121进行刻蚀，以形成图案化的遮光层12；
S40，在所述基板11上制备缓冲层14，所述缓冲层14覆盖所述光吸收层13；
S50，在所述缓冲层14上依次制备有源层15、栅极绝缘层16、栅极17、层间绝缘层18、以及源漏金属层19。
下面对所述制备方法进行详细说明。
先清洗基板11，基板11可为玻璃基板，也可为柔性基板，如基酰亚胺基板。
如图3所示，在所述基板11上通过沉积一层金属膜层121来制备遮光层12，所述金属膜层121的厚度在500~2000埃之间，所述金属膜层121可采用钼、铝、铜、钛中的一种或者两种以上组合而成的合金制备。
如图4所示，在所述金属膜层121表面涂布黑色光阻131，利用掩膜板对所述黑色光阻131进行曝光，显影后形成预定图案的光吸收层13，再对所述金属膜层121进行刻蚀，得到图案化的所述遮光层12，在刻蚀完成后，不将黑色光阻剥离，即在所述遮光层12上方形成所述光吸收层12。
由于所述遮光层12是采用金属制备的，光线照射到所述遮光层12上时会反射到所述有源层15，对TFT器件的电性性能造成不良影响，在制备所述遮光层12时，将平常用到的光阻材料换成黑色光阻，在刻蚀完成后，不将黑色光阻剥离，起到吸收光线的作用，也不会产生多余的制程。
如图6所示，在所述基板11上沉积氧化硅或者氮化硅，作为所述缓冲层14，利用同一道黄光工艺对所述缓冲层14进行刻蚀，在所述缓冲层14上形成第一过孔141，以及在所述光吸收层上形成第二过孔132，所述第二过孔132与所述第一过孔141连通，形成通道，用以实现所述源漏金属层19上的源极或漏极与所述遮光层12接触，实现所述遮光层12的讯号连接。
所述缓冲层14可以是多层无机膜层的复合结构，所述缓冲层覆盖所述基板11和所述光吸收层13，用以保护下层基板，所述缓冲层14的整体厚度在1000~5000埃之间。
在所述缓冲层14上沉积一层金属氧化物半导体材料作为所述有源层15，所述半导体材料为铟镓锌氧化物、铟锌锡氧化物或铟镓锌锡氧化物中的一种，所述有源层15的厚度在100~1000埃之间。
在所述有源层15上沉积氮化硅或氧化硅作为所述栅极绝缘层16，再在所述栅极绝缘层16上沉积一层金属作为所述栅极17，利用一道黄光制程制备所述栅极绝缘层16和所述栅极17，先刻蚀出所述栅极17的图形，再以所述栅极17为自对准，刻蚀栅极绝缘层16，只在栅极17的下方存在所述栅极绝缘层16，其余部分的栅极绝缘层材料被刻蚀掉。
之后对所述有源层15进行表面等离子处理，使得所述有源层15的被所述栅极绝缘层16覆盖的部分没有被处理到，保持半导体特性，作为TFT沟道，其余部分被处理，电阻降低，形成N+导体层。
所述栅极绝缘层16可为多层膜层的复合结构，所述栅极绝缘层16的整体厚度为1000~3000埃。
所述栅极17可采用钼、铝、铜和钛中的一种金属或其中两者以上组合而成的合金，所述栅极17的整体厚度为2000~8000埃。
在所述缓冲层14上沉积氧化硅或氮化硅作为所述层间绝缘层18，在所述层间绝缘层上涂布光刻胶，利用具有不同透光率的掩膜板对所述光刻胶进行曝光、显影后，多所述层间绝缘层18进行刻蚀，在所述层间绝缘层18上形成深度不同的第三过孔和第四过孔，所述第三过孔的深度大于所述第四过孔的深度，所述第三过孔对应的掩膜板的透光率大于所述第四过孔对应的掩膜板的透光率。所述第三过孔与所述第二过孔、所述第一过孔连通，三者形成通道，所述层间绝缘层18的厚度为2000~10000埃。
在所述层间绝缘层18上沉积一层金属层作为所述源漏金属层19，所述源漏金属层的源极或漏极通过所述第三过孔、所述第一过孔141、所述第二过孔132与所述遮光层12接触，实现遮光层的讯号连接，所述源极和漏极通过所述第四过孔与所述有源层连接。所述源漏金属层19的厚度为2000~8000埃。
最后在所述源漏金属层19上沉积无机膜层作为钝化层，所述钝化层可采用氮化硅或氧化硅，所述钝化层的厚度为1000~5000埃。
本发明提供的制备方法可应用于制备显示面板，在完成本发明TFT阵列基板之后，可在所述钝化层上依次制备平坦化层、阳极以及像素定义层、发光层、封装层等，完成显示面板的制备。
实施例二
上述实施例一是在遮光层上设置一层黑色光阻，与实施例一不同的是，本实施例在源漏金属层的源漏极下方设置黑色光阻。
如图7、图8所示，本实施例提供另一种TFT阵列基板20的制备方法，包括：
S10，提供一基板21，在所述基板上依次制备遮光层22、缓冲层23；
S20，在所述缓冲层23上依次制备有源层24、栅极绝缘层25、栅极26；
S30，在所述缓冲层23上沉积无机材料；
S40，在所述无机材料表面涂布黑色光阻，对所述黑色光阻进行曝光、显影，形成光吸收层28；
S50，对所述无机材料进行刻蚀，形成图案化的层间绝缘层27；
S60，在所述光吸收层上制备源漏金属层29。
如图9所示，其中，在所述缓冲层23上形成第一过孔231，在所述层间绝缘层27上形成有第三过孔271、第四过孔272，所述光吸收层上形成有第二过孔281，如图8所示。所述第二过孔281和所述第四过孔272连通，所述源漏金属层29上的源极和漏极通过所述第二过孔282、所述第四过孔272与所述有源层24接触连接，所述第三过孔271与所述第二过孔281、所述第一过孔231连通，三者形成通路，所述源极或漏极通过所述第二过孔281、所述第三过孔271、所述第一过孔231与所述遮光层22接触连接。
本实施例对所述光吸收层28的制备进行详细说明，其他膜层的制备方法请参照实施例一，这里不再赘述。
在所述缓冲层23上沉积一层无机材料，再在所述无机材料表面涂布黑色光阻，利用具有不同透光率的掩模板对所述黑色光阻进行曝光，显影后，形成预定图案的所述光吸收层28，在所述光吸收层28上形成所述第二过孔281，再对所述无机材料进行刻蚀，形成图案化的所述层间绝缘层27，在所述层间绝缘层27上形成所述第三过孔271和第四过孔272，刻蚀完成后，不剥离所述黑色光阻。
如图10所示，在所述光吸收层上沉积一层金属层，之后利用黄光工艺对所述金属层进行刻蚀，形成所述源漏金属层29的源极、漏极，再以源极、漏极为自对准，继续对所述光吸收层28进行刻蚀，使得所述光吸收层28的位于所述源漏金属层29区域外的部分被刻蚀掉。在所述源漏金属层29的源漏极下方设置一层黑色光吸收层，能够吸收TFT器件内部的金属膜层之间的层间反射光线，减少源漏极下方的光线反射到有源层，所述光吸收层28是利用黄光工艺对所述层间绝缘层27刻蚀形成过孔后留下来的黑色光阻层，不会产生多余的制程。
本发明还提供一种上述方法制备的TFT阵列基板，包括依次层叠设置的基板、遮光层、缓冲层、有源层、栅极绝缘层、栅极、层间绝缘层、源漏金属层、钝化层，所述TFT阵列基板还包括光吸收层。
其中，所述光吸收层设置于所述有源层的一侧，用以吸收TFT器件内部的金属膜层反射的光线，避免光线进入到所述有源层中。
如图3所示，在一实施例中，所述光吸收层13设置于所述遮光层12靠近所述有源层15的一侧，具体地，所述光吸收层13可设置在所述遮光层12的上表面，覆盖所述遮光层12，用以吸收反射到所述遮光层12上的光线，所述光吸收层13为黑色光阻。
如图8所示，在另一实施例中，所述光吸收层28设置于所述源漏金属层29靠近所述有源层24的一侧，即设置于所述源漏金属层29的下方，与所述源漏金属层的源极、漏极对应设置，以吸收反射到源漏极上的光线，所述光吸收层覆盖所述层间绝缘层27，所述光吸收层28为黑色光阻。
有益效果：本发明通过在源漏极下方设置黑色光阻或在遮光层上方设置黑色光阻作为吸收层，用以吸收光线，能够避免大部分光线反射到有源层，进而改善TFT器件性能；另外，吸收层是在其他膜层刻蚀完成后未剥离的黑色光阻形成的，不会产生新的制程，工艺简单，节约成本。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (16)

  1. 一种TFT阵列基板的制备方法，其中，包括：
    S10，提供一基板，在所述基板上依次制备遮光层、缓冲层；
    S20，在所述缓冲层上依次制备有源层、栅极绝缘层、栅极、层间绝缘层、以及源漏金属层；其中，
    在所述遮光层靠近所述有源层的一侧制备光吸收层，所述栅极和所述栅极绝缘层经过同一道黄光工艺制备。
  2. 根据权利要求1所述的TFT阵列基板的制备方法，其中，所述S10包括：
    S101，提供一基板，在所述基板上沉积金属膜层；
    S102，在所述金属膜层表面涂布黑色光阻，对所述黑色光阻进行曝光、显影，形成光吸收层；
    S103，对所述金属膜层进行刻蚀，形成图案化的遮光层；
    S104，在所述光吸收层上制备所述缓冲层。
  3. 根据权利要求1所述的TFT阵列基板的制备方法，其中，所述栅极和所述栅极绝缘层的制备过程包括：
    在所述有源层表面沉积一层栅极绝缘材料；
    在所述栅极绝缘材料表面沉积一层栅极金属薄膜；
    在所述栅极金属薄膜表面形成图案化的光刻胶，对所述栅极金属薄膜进行刻蚀，形成图案化的所述栅极；
    以所述栅极为自对准，对所述栅极绝缘材料进行刻蚀，形成图案化的栅极绝缘层。
  4. 一种TFT阵列基板的制备方法，其中，包括：
    S10，提供一基板，在所述基板上依次制备遮光层、缓冲层；
    S20，在所述缓冲层上依次制备有源层、栅极绝缘层、栅极、层间绝缘层、以及源漏金属层；其中，
    在所述有源层的一侧制备光吸收层。
  5. 根据权利要求4所述的TFT阵列基板的制备方法，其中，在所述遮光层靠近所述有源层的一侧制备光吸收层。
  6. 根据权利要求5所述的TFT阵列基板的制备方法，其中，所述S10包括：
    S101，提供一基板，在所述基板上沉积金属膜层；
    S102，在所述金属膜层表面涂布黑色光阻，对所述黑色光阻进行曝光、显影，形成光吸收层；
    S103，对所述金属膜层进行刻蚀，形成图案化的遮光层；
    S104，在所述光吸收层上制备所述缓冲层。
  7. 根据权利要求4所述的TFT阵列基板的制备方法，其中，在所述源漏金属层靠近所述有源层的一侧制备所述光吸收层。
  8. 、根据权利要求7所述的TFT阵列基板的制备方法，其中，所述S20包括：
    S201，在所述缓冲层上依次制备有源层、栅极绝缘层、栅极；
    S202，在所述缓冲层上沉积无机材料；
    S203，在所述无机材料表面涂布黑色光阻，对所述黑色光阻进行曝光、显影，形成光吸收层；
    S204，对所述无机材料进行刻蚀，形成图案化的层间绝缘层；
    S205，在所述光吸收层上制备源漏金属层。
  9. 根据权利要求4所述的TFT阵列基板的制备方法，其中，所述栅极和所述栅极绝缘层经过同一道黄光工艺制备。
  10. 根据权利要求9所述的TFT阵列基板的制备方法，其中，所述栅极和所述栅极绝缘层的制备过程包括：
    在所述有源层表面沉积一层栅极绝缘材料；
    在所述栅极绝缘材料表面沉积一层栅极金属薄膜；
    在所述栅极金属薄膜表面形成图案化的光刻胶，对所述栅极金属薄膜进行刻蚀，形成图案化的所述栅极；
    以所述栅极为自对准，对所述栅极绝缘材料进行刻蚀，形成图案化的栅极绝缘层。
  11. 一种TFT阵列基板，其中，包括：
    基板；
    遮光层，形成于所述基板上；
    缓冲层，形成于所述遮光层上；
    有源层，形成于所述缓冲层上；
    栅极绝缘层，形成于所述有源层上；
    栅极，形成于所述栅极绝缘层上；
    层间绝缘层，形成于所述栅极上；
    源漏金属层，形成于所述层间绝缘层上；其中，
    所述有源层的一侧设置有光吸收层。
  12. 根据权利要求11所述的TFT阵列基板，其中，所述光吸收层设置于所述遮光层靠近所述有源层的一侧。
  13. 根据权利要求12所述的TFT阵列基板，其中，所述光吸收层与所述源漏金属层对应设置。
  14. 根据权利要求11所述的TFT阵列基板，其中，所述光吸收层设置于所述源漏金属层靠近所述有源层的一侧。
  15. 根据权利要求14所述的TFT阵列基板，其中，所述光吸收层与所述源漏金属层对应设置。
  16. 根据权利要求11所述的TFT阵列基板，其中，所述光吸收层为黑色光阻层。
PCT/CN2019/084007 2019-01-16 2019-04-24 Tft阵列基板的制备方法及tft阵列基板 WO2020147216A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US16/627,819 US11469328B2 (en) 2019-01-16 2019-04-24 TFT array substrate and preparation method thereof

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201910041297.9A CN109786323A (zh) 2019-01-16 2019-01-16 Tft阵列基板的制备方法及tft阵列基板
CN201910041297.9 2019-01-16

Publications (1)

Publication Number Publication Date
WO2020147216A1 true WO2020147216A1 (zh) 2020-07-23

Family

ID=66500756

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/084007 WO2020147216A1 (zh) 2019-01-16 2019-04-24 Tft阵列基板的制备方法及tft阵列基板

Country Status (3)

Country Link
US (1) US11469328B2 (zh)
CN (1) CN109786323A (zh)
WO (1) WO2020147216A1 (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2590428A (en) * 2019-12-17 2021-06-30 Flexanable Ltd Semiconductor devices
CN111584550A (zh) * 2020-05-06 2020-08-25 武汉华星光电半导体显示技术有限公司 一种显示面板及显示装置

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013065569A1 (ja) * 2011-11-04 2013-05-10 ソニー株式会社 固体撮像素子、固体撮像素子の製造方法、及び、電子機器
CN105789247A (zh) * 2014-08-14 2016-07-20 乐金显示有限公司 有机发光显示面板
CN107302032A (zh) * 2017-06-19 2017-10-27 京东方科技集团股份有限公司 一种薄膜晶体管及其制作方法、阵列基板、显示面板
CN107564945A (zh) * 2017-08-30 2018-01-09 上海天马微电子有限公司 透明显示面板、透明显示装置及透明显示面板的制作方法
CN107910355A (zh) * 2017-11-27 2018-04-13 信利（惠州）智能显示有限公司 阵列基板及其制备方法以及有机电致发光显示装置
CN108110060A (zh) * 2017-12-12 2018-06-01 合肥京东方显示技术有限公司 薄膜晶体管及其制作方法、阵列基板和显示装置
CN207503983U (zh) * 2017-10-26 2018-06-15 京东方科技集团股份有限公司 显示基板和显示面板

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201217860A (en) * 2010-10-25 2012-05-01 Ind Tech Res Inst Cholesteric liquid crystal device
KR102230943B1 (ko) * 2014-08-14 2021-03-24 엘지디스플레이 주식회사 광흡수층을 포함하는 유기발광 표시장치 및 이를 제조하는 방법
CN106981478A (zh) * 2017-04-07 2017-07-25 京东方科技集团股份有限公司 顶栅型薄膜晶体管及其制作方法、阵列基板、显示面板
CN107086181B (zh) * 2017-04-18 2021-08-13 京东方科技集团股份有限公司 薄膜晶体管及其制作方法、阵列基板和显示器
CN108550582B (zh) * 2018-05-09 2022-11-08 京东方科技集团股份有限公司 显示基板及其制造方法、显示装置
CN108987595A (zh) * 2018-07-13 2018-12-11 京东方科技集团股份有限公司 一种oled基板及显示装置

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013065569A1 (ja) * 2011-11-04 2013-05-10 ソニー株式会社 固体撮像素子、固体撮像素子の製造方法、及び、電子機器
CN105789247A (zh) * 2014-08-14 2016-07-20 乐金显示有限公司 有机发光显示面板
CN107302032A (zh) * 2017-06-19 2017-10-27 京东方科技集团股份有限公司 一种薄膜晶体管及其制作方法、阵列基板、显示面板
CN107564945A (zh) * 2017-08-30 2018-01-09 上海天马微电子有限公司 透明显示面板、透明显示装置及透明显示面板的制作方法
CN207503983U (zh) * 2017-10-26 2018-06-15 京东方科技集团股份有限公司 显示基板和显示面板
CN107910355A (zh) * 2017-11-27 2018-04-13 信利（惠州）智能显示有限公司 阵列基板及其制备方法以及有机电致发光显示装置
CN108110060A (zh) * 2017-12-12 2018-06-01 合肥京东方显示技术有限公司 薄膜晶体管及其制作方法、阵列基板和显示装置

Also Published As

Publication number Publication date
US20210328072A1 (en) 2021-10-21
US11469328B2 (en) 2022-10-11
CN109786323A (zh) 2019-05-21

Similar Documents

Publication Publication Date Title
US10325942B2 (en) TFT substrate manufacturing method
WO2016173027A1 (zh) 薄膜晶体管阵列基板及其制作方法
CN110164873B (zh) 阵列基板的制作方法、阵列基板、显示面板及显示装置
WO2014012334A1 (zh) 阵列基板的制造方法及阵列基板、显示装置
US20160254298A1 (en) Array Substrate, Manufacturing Method Thereof, and Display Device
CN109638078B (zh) Tft的制备方法、tft、oled背板和显示装置
US20240014225A1 (en) Display substrate, preparation method thereof, and display panel
TW201622158A (zh) 薄膜電晶體以及其製作方法
JP2012103697A (ja) アレイ基板及び液晶ディスプレイ
KR102318054B1 (ko) Tft 기판 및 이의 제조 방법
WO2016165517A1 (zh) 阵列基板及其制作方法和显示面板
US20180059456A1 (en) Pixel structure and manufacturing method thereof, array substrate and display apparatus
WO2021031312A1 (zh) 有机发光显示面板及其制备方法
CN110556406A (zh) 一种oled显示面板及其制备方法
WO2016192446A1 (zh) 薄膜晶体管及其制作方法、阵列基板及其制作方法
KR20150015429A (ko) 어레이 기판, 디스플레이 장치, 및 어레이 기판의 제조 방법
WO2020093458A1 (zh) 阵列基板及其制备方法、液晶显示面板、显示装置
CN110828476B (zh) 阵列基板及其制备方法、显示装置
WO2017028493A1 (zh) 薄膜晶体管及其制作方法、显示器件
WO2016090807A1 (zh) 阵列基板及其制作方法、显示装置
WO2020147216A1 (zh) Tft阵列基板的制备方法及tft阵列基板
WO2021026990A1 (zh) 一种阵列基板及其制作方法
CN108538725B (zh) 薄膜晶体管及其制造方法
WO2017012292A1 (zh) 阵列基板及其制备方法、显示面板、显示装置
WO2021248609A1 (zh) 一种阵列基板及其制备方法以及显示面板

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19910774

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 19910774

Country of ref document: EP

Kind code of ref document: A1