WO2019017076A1 - 半導体装置およびその製造方法 - Google Patents

半導体装置およびその製造方法 Download PDF

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WO2019017076A1
WO2019017076A1 PCT/JP2018/020457 JP2018020457W WO2019017076A1 WO 2019017076 A1 WO2019017076 A1 WO 2019017076A1 JP 2018020457 W JP2018020457 W JP 2018020457W WO 2019017076 A1 WO2019017076 A1 WO 2019017076A1
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insulating film
semiconductor region
semiconductor
region
view
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PCT/JP2018/020457
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English (en)
French (fr)
Japanese (ja)
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貴博 森川
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株式会社日立パワーデバイス
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Priority to CN201880023964.4A priority Critical patent/CN110521002B/zh
Publication of WO2019017076A1 publication Critical patent/WO2019017076A1/ja

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched

Definitions

  • the present invention relates to a semiconductor device and its manufacturing technology, for example, to a technology effectively applicable to a power semiconductor device and its manufacturing method.
  • Patent Document 1 JP-A-2004-39744
  • the SiC substrate is inclined relative to the normal direction of the SiC substrate while rotating the SiC substrate around the normal of the SiC substrate through the mask material whose inclination is formed on the pattern sidewall by taper etching.
  • Techniques for implanting low concentration base regions and high concentration base regions are described.
  • Patent Document 1 describes a technique for forming the source region and the channel region of the vertical MOSFET in a self-aligned manner using the same mask. Further, Patent Document 1 exemplifies a stripe type cell of a vertical MOSFET.
  • the stripe type cell (source region) is formed in a strip shape whose length in one direction is longer than the length in the other direction orthogonal to the one direction in the shape in plan view.
  • an impurity of the opposite conductivity type to the source region is not necessarily sufficiently injected into portions adjacent to both end portions in the longitudinal direction of the stripe type cell (source region). Therefore, the threshold voltage of a portion adjacent to both ends in the longitudinal direction of the stripe type cell (source region) is a portion adjacent to both ends in the width direction (short direction) of the stripe type cell (source region) Approximately equal to or lower than the threshold voltage of As a result, a leak current is generated at both ends in the longitudinal direction of the stripe type cell, and there is a problem that the reliability of the semiconductor device is lowered.
  • An object of the present invention is to provide a technology capable of improving the reliability of a semiconductor device.
  • the length of the first direction in plan view is longer than the length in the second direction intersecting with the first direction on the first surface of the semiconductor substrate, and A first semiconductor region of a first conductivity type is provided which extends from one surface in the depth direction of the semiconductor substrate. Further, a gate electrode is provided on portions adjacent to both end portions of at least the first semiconductor region in the second direction via an insulating film. Then, the threshold voltage of a portion adjacent to both ends of the first semiconductor region in the first direction in plan view is made higher than the threshold voltage of a portion adjacent to both ends of the first semiconductor region in the second direction. .
  • the reliability of the semiconductor device can be improved. Problems, configurations, and effects other than those described above will be apparent from the description of the embodiments below.
  • FIG. 2 is a cross-sectional view taken along line X10-X10 of FIG.
  • FIG. 1 is a plan view of an example of a semiconductor chip constituting a semiconductor device of a first embodiment. It is an enlarged plan view of an example of field A1 enclosed with a dashed line of FIG.
  • FIG. 4 is an enlarged plan view of an example of a gate electrode made of polycrystalline silicon in a region A2 surrounded by a broken line in FIG. 3.
  • FIG. 5 is an enlarged plan view of an example of an active region of a region A2 surrounded by a dashed line in FIG. 3; FIG.
  • FIG. 7 is a cross-sectional view taken along line X1-X1 and line Y1-Y1 of FIG. 6; It is a principal part top view of the semiconductor substrate which shows the modification of a short side body field.
  • FIG. 7 is a cross-sectional view taken along line Y1-Y1 of FIG. 6;
  • FIG. 7 is a cross-sectional view of a portion corresponding to the Y1-Y1 line and the X1-X1 line of FIG. 6 in the step of forming the embedded body region that configures the semiconductor device of the first embodiment.
  • FIG. 7 is a cross-sectional view of a portion corresponding to the Y1-Y1 line and the X1-X1 line of FIG.
  • Left and right are cross-sectional views of a portion corresponding to the Y1-Y1 line of FIG. 6 at the time of the step of forming the long side body region that constitutes the semiconductor device of the first embodiment. It is a principal part top view of an active field of a semiconductor substrate after a formation process of a long side body field.
  • the left is a cross-sectional view taken along line Y1-Y1 of FIG. 13, and the right is a cross-sectional view taken along line X1-X1 of FIG.
  • Left and right are cross-sectional views of portions corresponding to the Y1-Y1 line and the X1-X1 line of FIG.
  • FIG. 6 is a cross-sectional view of portions corresponding to the Y1-Y1 line and the X1-X1 line of FIG. 6 in the process of forming the short side body region constituting the semiconductor device of the first embodiment.
  • FIG. 7 is a cross-sectional view of a portion corresponding to the Y1-Y1 line and the X1-X1 line of FIG. 6 showing a modification of the process of forming the body contact region and the short side body region constituting the semiconductor device of the first embodiment; It is a principal part top view of the active field of a semiconductor substrate after the formation process of a body contact field and a short side body field.
  • FIG. 7 is a cross-sectional view of a portion corresponding to the Y1-Y1 line and the X1-X1 line of FIG. 6 showing a modification of the process of forming the body contact region and the short side body region constituting the semiconductor device of the first embodiment.
  • It is a principal part top view of the active field of a semiconductor substrate
  • FIG. 7 is a cross-sectional view of a portion corresponding to the Y1-Y1 line and the X1-X1 line of FIG. 6 in the step of forming the gate electrode constituting the semiconductor device of Embodiment 1;
  • FIG. 20 is a cross-sectional view of a portion corresponding to the Y1-Y1 line and the X1-X1 line of FIG. 6 in the manufacturing process of the semiconductor device after the process of FIG. 19;
  • FIG. 16 is an enlarged plan view of a main part of an active region of the semiconductor device of Second Embodiment;
  • FIG. 22 is a cross-sectional view taken along line X1-X1 of FIG. It is a principal part top view of the semiconductor substrate which shows the modification of field insulating film.
  • FIG. 20 is a cross-sectional view of a portion corresponding to the Y1-Y1 line and the X1-X1 line of FIG. 6 in the step of forming the gate electrode constituting the semiconductor device of Embod
  • FIG. 17 is a cross-sectional view of a portion corresponding to the Y1-Y1 line and the X1-X1 line of FIG. 6 in the step of forming the field insulating film that configures the semiconductor device of Second Embodiment;
  • FIG. 25 is a cross-sectional view of a portion corresponding to the Y1-Y1 line and the X1-X1 line of FIG. 6 in the film formation step of the polycrystalline silicon film constituting the semiconductor device of Embodiment 2 after the step of FIG. 24;
  • FIG. 26 is a cross-sectional view of a portion corresponding to the Y1-Y1 line and the X1-X1 line of FIG. 6 after the source contact forming step of the semiconductor device of the second embodiment after the step of FIG. 25;
  • FIG. 16 is an enlarged plan view of a main part of an active region of the semiconductor device of the third embodiment.
  • FIG. 28 is a cross-sectional view taken along line X1-X1 of FIG.
  • a silicon (Si) substrate has long been used as a substrate for power semiconductor devices, but as a result of achieving lower loss and improved performance of Si-based power semiconductor devices, the device performance is based on the material properties of Si. It is approaching the theoretical limit to be determined, and it is becoming difficult to further improve performance in the future.
  • SiC and GaN have been actively studied.
  • SiC and GaN have a breakdown electric field strength about one digit larger than that of Si and can make the drift layer thinner. Therefore, in the power semiconductor device using the wide gap semiconductor, the on-resistance can be reduced, that is, the loss can be reduced, as compared with the Si-based power semiconductor device.
  • an n-type source region, a p-type body region and the like are formed by selective ion implantation.
  • impurity ion implantation usually, lithography is performed on each of the n-type source region and the p-type body region, and impurities are implanted using different masks.
  • small changes in exposure dose and temperature may shift the dimensions of the resist mask formed after development. Since the channel length is usually less than 1 ⁇ m, changes and variations in device performance caused by misalignment and dimensional shifts can not be ignored.
  • the channel length can be defined without being affected by misalignment or dimensional shift caused by the two exposures, and a short channel, low on-resistance power MOSFET can be manufactured without variation.
  • Patent Document 1 discloses a method of manufacturing a vertical MOSFET by implanting ions of a source region and a channel region using the same mask. According to the method of Patent Document 1, the n-type impurity of the source region is implanted from the normal direction of the substrate surface to the substrate on which the mask is formed, and further, at an angle inclined to the normal direction of the substrate. A channel is formed under the mask by implanting P-type impurities. Further, Patent Document 1 discloses a method in which ion implantation is performed twice in a diagonal direction so as to cross a stripe-like cell.
  • Patent Document 1 when the inventor examined Patent Document 1, it became clear that the manufactured MOSFET had a problem. That is, in the method of Patent Document 1, P-type impurities are not sufficiently implanted into portions adjacent to both end portions in the longitudinal direction of the N-type source region constituting the stripe-shaped unit cell. Therefore, the threshold voltage of the portion adjacent to the both ends (long side) in the width direction (short direction) of the source region is the portion adjacent to the both ends (short side) in the longitudinal direction of the source region. The threshold voltage is lower.
  • a current flowing through a channel formed in a portion adjacent to both ends (long sides) in the width direction of the N-type source region is the main component of conduction.
  • the current flowing through the channel formed in the portion adjacent to both ends (short sides) in the longitudinal direction of the N-type source region is taken as a leak current. Then, the element having a large leak current is regarded as a defective product.
  • Patent Document 1 discloses a method of adding ion implantation twice more from the direction in which the substrate is rotated 90 degrees, and a method of implanting ions while rotating the substrate.
  • FIG. 1 is a plan view of a unit cell of a power semiconductor device examined by the present inventor
  • FIG. 2 is a cross-sectional view taken along line X10-X10 of FIG.
  • FIG. 1 illustrates two unit cells 100 formed in a strip shape in plan view.
  • a P-type body region 102 is formed to surround the outer periphery of the N-type source region 101 of the unit cell 100. Therefore, the threshold voltage of a portion adjacent to both ends (short side) in the longitudinal direction of N-type source region 101 and the portion adjacent to both ends (long side) in the width direction of N-type source region 101 And the threshold voltage of the
  • Patent Document 1 neither suggests nor discloses the problem of the leak current IL flowing from both end portions in the longitudinal direction of the unit cell 100 (N-type source region 101). Moreover, in Patent Document 1, the threshold voltage of the portion adjacent to both ends (short side) in the width direction of the N-type source region is set low from the viewpoint of achieving high-speed switching of the power semiconductor device. Therefore, the threshold voltage of the portion adjacent to both ends (short sides) in the longitudinal direction of the N-type source region is also lowered. Therefore, even if ion implantation as described above is performed, as shown in FIG. 1, normal operation is performed through the channels formed in the portions adjacent to both ends (long sides) in the width direction of unit cell 100 during operation of the power MOSFET.
  • plan view means the case of viewing from the direction perpendicular to the main surface of the semiconductor substrate.
  • arrows X and Y in the drawing indicate two directions intersecting (preferably orthogonal) with each other in plan view.
  • the semiconductor device according to the first embodiment is, for example, a switching device (power semiconductor device) having an n-channel vertical double diffused MOSFET (hereinafter, abbreviated as DMOSFET).
  • FIG. 3 is a plan view of an example of a semiconductor chip constituting the semiconductor device of the first embodiment. Although the areas A1 and A2 in FIG. 1 are not actually formed, they are illustrated for the sake of explanation.
  • the semiconductor chip (hereinafter simply referred to as a chip) 1C is formed in, for example, a substantially square shape in a plan view.
  • a termination region (a so-called guard ring region) GA is provided in the outer peripheral edge portion in the main surface of the chip 1C.
  • the termination region GA is formed of, for example, a p-type (second conductivity type) semiconductor region, and has an electric field relaxation function and the like.
  • a p-type impurity such as aluminum (Al) or boron (B) is introduced.
  • the source electrode 2S and the gate electrode 2G of the DMOSFET are provided in a mutually insulated state.
  • the source electrode 2S and the gate electrode 2G are formed, for example, by sequentially stacking a titanium (Ti) film, a titanium nitride (TiN) film, and an aluminum film (Al) from the lower layer.
  • the source electrode 2S and the gate electrode 2G are covered with a surface protection film (not shown) on the main surface of the chip 1C, the source electrode 2S and the gate are formed through an opening formed in part of the surface protection film.
  • a part of the electrode 2G is exposed.
  • a part of the source electrode 2S and the gate electrode 2G exposed from the opening formed in the surface protective film is a source pad and a gate pad.
  • Under the source electrode 2S and the gate electrode 2G a gate electrode made of polycrystalline silicon described later is formed.
  • FIG. 4 is an enlarged plan view of an example of a region A1 surrounded by a broken line in FIG. Note that FIG. 4 shows a state in which the source electrode 2S, the gate electrode 2G, and the gate electrode in the lower layer thereof are removed.
  • An active area ACA is disposed inside the termination area GA in the main surface of the chip 1C.
  • stripe-type unit cells UC constituting a DMOSFET are arranged. That is, in the active area ACA, a plurality of strip-like unit cells UC in which the dimension in the X direction (first direction) in plan view is longer than the dimension in the Y direction (second direction) have predetermined intervals along the Y direction. Is located in
  • the plurality of unit cells UC are electrically connected in parallel.
  • the chip 1C The resistance of the entire DMOSFET can be reduced.
  • the field area FA is disposed between both ends of the unit cell UC in the longitudinal direction (X direction) and the inner periphery of the termination area GA. That is, both ends in the longitudinal direction of each unit cell UC are separated from the inner periphery of the termination area GA.
  • FIG. 5 is an enlarged plan view of an example of a gate electrode made of polycrystalline silicon in a region A2 surrounded by a broken line in FIG. 3
  • FIG. 6 is an enlarged plan view of an example of an active region in a region A2 surrounded by a broken line in FIG. 7 is a cross-sectional view taken along line X1-X1 and line Y1-Y1 of FIG. 5 shows a state in which the source electrode 2S of the chip 1C is removed
  • FIG. 6 shows a state in which the gate electrode layer made of polycrystalline silicon in FIG. 5 is removed.
  • the arrow Z in FIG. 7 indicates a direction intersecting (preferably orthogonal to) the main surface of the chip 1C.
  • the semiconductor substrate 1S constituting the chip 1C is formed of, for example, a wide gap semiconductor such as silicon carbide (SiC).
  • the semiconductor substrate 1S has a substrate layer SB and an epitaxial layer EP formed thereon.
  • the substrate layer SB is made of, for example, n + -type SiC
  • the epitaxial layer EP is made of, for example, n ⁇ -type SiC.
  • an n-type impurity such as nitrogen (N) or phosphorus (P) is introduced.
  • the semiconductor substrate 1S has a main surface (first surface) of the epitaxial layer EP and a main surface (second surface) of the substrate layer SB on the opposite side.
  • the main surface of the epitaxial layer EP corresponds to the main surface of the chip 1C.
  • the drain electrode 3D is formed on the main surface of the substrate layer SB.
  • the drain electrode 3D is formed, for example, by sequentially laminating a Ti film, a TiN film, and an Al film from the lower layer.
  • a p-type buried body region 7B1, an n-type source region 8S, and ap + -type body contact are provided on the main surface side of the epitaxial layer EP of the semiconductor substrate 1S as components of the unit cell UC.
  • a region 9BC, a p-type long side body region 7B2, and a p-type short side body region 7B3 are provided.
  • the p-type buried body region (second semiconductor region) 7B1 is longer than the source region 8S in plan view so as to cover the bottom of the source region 8S of each unit cell UC. It is formed in a strip shape along the direction (X direction). That is, as shown on the right of FIG. 7, both ends in the longitudinal direction (X direction) of the embedded body region 7B1 reach the termination region GA. Further, as shown in the left of FIG. 7, the dimension in the width direction (Y direction) of the embedded body region 7B1 is wider than the dimension in the width direction (Y direction) of the source region 8S. Buried body region 7B1 is formed at a position away from the main surface of epitaxial layer EP (below the bottom of source region 8S).
  • buried body region 7B1 extends from the bottom of source region 8S toward substrate layer SB, and terminates at an intermediate position in the depth direction (Z direction) of epitaxial layer EP without reaching substrate layer SB. There is.
  • p-type impurities such as Al or boron (B) are introduced.
  • n-type (first conductivity type) source region (first semiconductor region) 8S is formed on the p-type buried body region 7B1.
  • the source region 8S is formed in a band shape along the longitudinal direction (X direction) of each unit cell UC in a plan view, as shown in FIG.
  • the source region 8S is disposed in a state of being overlapped with the embedded body region 7B1 so as to be included in each embedded body region 7B1 in plan view.
  • both ends in the longitudinal direction of the source region 8S do not reach the termination region GA, and terminate at a position distant from the termination region GA. Further, as shown in FIG.
  • source region 8S extends from the main surface of epitaxial layer EP toward substrate layer SB and terminates at a position where buried body region 7B1 is reached.
  • an n-type impurity such as nitrogen (N) or phosphorus (P) is introduced.
  • Source electrode 2S is electrically connected to source region 8S through source contact SC.
  • the body contact region 9BC is a conductive region for electrically connecting the source electrode 2S of the DMOSFET and the buried body region 7B1. That is, as shown in FIG. 7, body contact region 9BC extends in the depth direction from the main surface of epitaxial layer EP, and reaches and terminates embedded body region 7B1. Thus, source electrode 2S is electrically connected to embedded body region 7B1 through body contact region 9BC.
  • a p-type impurity such as Al or boron is introduced into the body contact region 9BC, for example.
  • body contact region 9BC is formed, for example, in a substantially rectangular shape in plan view, along the longitudinal direction (X direction) of source region 8S at the central position in the width direction (Y direction) of source region 8S. Are arranged at predetermined intervals. Since the number of unit cells UC that can be arranged in the active area ACA can be increased by reducing the area of the body contact area 9BC as described above, the on-resistance of the DMOSFET can be reduced. However, the number, size, or interval of the body contact regions 9BC can be changed variously. Further, the shape in plan view of the body contact region 9BC can be changed variously, and for example, it may be a strip extending continuously along the longitudinal direction of the source region 8S. In this case, since the resistance between the source electrode 2S and the embedded body region 7B1 can be reduced, the electrical stability of the body region can be improved.
  • a long side body region (third semiconductor region) 7B2 of the die is formed.
  • the long side body region 7B2 extends from the main surface of the epitaxial layer EP toward the substrate layer SB so as to cover the side portions on both long sides of the source region 8S, and reaches the buried body region 7B1 and terminates. ing.
  • a normal channel of the DMOSFET is formed on the surface side of the long side body region 7B2 when the DMOSFET operates.
  • the surface layer of the p-type long side body region 7B2 is inverted to n-type to pass electrons.
  • a p-type impurity such as Al or boron is introduced.
  • a strip-like p-type short side body region (fourth semiconductor in plan view) Region) 7B3 is formed.
  • This short side body region 7B3 extends from the main surface of epitaxial layer EP toward substrate layer SB so as to cover the side portions on both short sides of source region 8S, and reaches embedded body region 7B1 and terminates. ing. Therefore, the entire circumference of the source region 8S is surrounded by the p-type body region (p-type embedded body region 7B1, p-type long side body region 7B2 and p-type short side body region 7B3) .
  • the short side body region 7B3 has a function of suppressing or preventing a leak current from flowing from both ends of the source region 8S in the longitudinal direction during the operation of the DMOSFET.
  • a p-type impurity such as Al or boron is introduced.
  • the concentration of the p-type impurity contained in the short side body region 7B3 is higher than the concentration of the p-type impurity contained in the long side body region 7B2. Therefore, the threshold voltage when the surface layer portion of p-type short side body region 7B3 is inverted to n-type to form a channel during operation of the DMOSFET is the same as that of p-type long side body region 7B2.
  • the current (leakage current) flowing through the p-type short side body region 7B3 can be made extremely smaller than the current flowing through the p-type long side body region 7B2 in the operation of a normal DMOSFET. Therefore, the leakage current flowing from both ends in the longitudinal direction of the source region 8S can be reduced, so that the reliability of the power semiconductor device having the DMOSFET can be improved.
  • the short side body region 7B3 is separated for each unit cell UC.
  • the short side body region 7B3 may be formed so as to cover both end portions in the longitudinal direction of the source region 8S of each unit cell UC in order to suppress or prevent the above-described leakage current.
  • FIG. 8 is a plan view of relevant parts of a semiconductor substrate showing a modification of the short side body region.
  • the short side body regions 7B3 are formed to extend continuously along the Y direction so as to connect the plurality of unit cells UC. As a result, since the dimension of the opening of the mask when forming the short side body region 7B3 can be increased, the short side body region 7B3 can be formed more easily.
  • a gate insulating film (second insulating film) 10a is formed on the main surface of the epitaxial layer EP of such a semiconductor substrate 1S.
  • the gate insulating film 10 a is made of, for example, a silicon oxide film (SiO 2 ).
  • a gate electrode 11G is formed on the gate insulating film 10a.
  • the gate electrode 11G is made of, for example, a low resistance n-type polycrystalline silicon film. Although this gate electrode 11G is formed so as to cover the active area ACA in plan view as shown in FIG. 5, it does not overlap the termination area GA.
  • An opening 12 is formed in a part of the gate electrode 11G to expose a part of each unit cell UC.
  • the opening 12 is formed in a band shape so as to overlap the source region 8S in plan view. A portion of the source region 8S of the unit cell UC and the body contact region 9BC are exposed from the opening 12. Both ends in the width direction and the longitudinal direction of the opening 12 are located in the source region 8S. Therefore, the gate electrode 11G overlaps in plan view with a part inside the outer periphery of the source region 8S, the entire region of the long side body region 7B2 and the entire region 7B3 of the short side body region.
  • the interlayer insulating film 13 is deposited so as to cover the gate electrode 11G.
  • the interlayer insulating film 13 is made of, for example, a silicon oxide film (SiO 2 ).
  • the source electrode 2S and the gate electrode 2G described above are formed on the interlayer insulating film 13.
  • the source electrode 2S and the underlying gate electrode 11G are electrically insulated by an interlayer insulating film 13 provided therebetween.
  • the gate electrode 2G and the gate electrode 11G under the gate electrode 2G are electrically connected through an opening (gate contact; not shown) formed in the interlayer insulating film 13.
  • a source contact SC having an area smaller than that of the opening 12 is opened at a position overlapping the opening 12 of the gate electrode 11G in plan view.
  • a portion of source region 8S and body contact region 9BC are exposed from source contact SC. That is, source electrode 2S is electrically connected to source region 8S and body contact region 9BC of unit cell UC through source contact SC. Therefore, source region 8S and body contact region 9BC are electrically shorted through source electrode 2S.
  • FIG. 9 is a cross-sectional view taken along line Y1-Y1 of FIG.
  • a channel is formed in the surface layer of the p-type long side body region 7B2 in contact with the gate insulating film 10a.
  • electrons flow from the n-type source region 8S to the drain electrode 3D through the channel on the surface layer of the p-type long side body region 7B2. That is, a current Isd flows from the drain electrode 3D to the source electrode 2S through the surface layer channel of the p-type long side body region 7B2.
  • the switching operation is performed by thus applying a voltage to the gate electrode 11G.
  • FIGS. 10 to 20 an example of a method of manufacturing the semiconductor device of the first embodiment will be described with reference to FIGS. 10 to 20.
  • a portion corresponding to the cross section along line X1-X1 of FIG. 6 or the cross section along line Y1-Y1 is illustrated.
  • a plan view is also shown if necessary.
  • FIG. 10 is a cross-sectional view of a portion corresponding to the Y1-Y1 line and the X1-X1 line of FIG. 6 in the step of forming the buried body region constituting the semiconductor device of the first embodiment.
  • an epitaxial layer EP made of n ⁇ -type SiC is formed on the main surface of the substrate layer SB made of n + -type 4H—SiC.
  • the n-type impurity introduced into the substrate layer SB is, for example, nitrogen (N), and the impurity concentration thereof is, for example, in the range of 1 ⁇ 10 18 to 1 ⁇ 10 21 cm ⁇ 3 .
  • the epitaxial layer EP can be formed on the main surface of the substrate layer SB, for example, by an epitaxial method.
  • the epitaxial layer EP has a predetermined thickness and dopant concentration determined by the specifications of the device.
  • the thickness of the epitaxial layer EP is, for example, in the range of 3 to 30 ⁇ m.
  • the n-type dopant added to the epitaxial layer EP is, for example, nitrogen, and the dopant concentration is, for example, in the range of 1 ⁇ 10 14 to 1 ⁇ 10 17 cm ⁇ 3 .
  • a mask material is deposited on the main surface of the n ⁇ -type epitaxial layer EP and patterned to form a mask MA.
  • the shape of the mask MA in a plan view is formed to expose the embedded body region and to cover the rest.
  • a photoresist is used as the material of the mask MA
  • the photoresist is applied and then patterned by a known lithography method to form the mask MA.
  • silicon oxide SiO 2
  • a silicon oxide film is deposited, a photoresist is applied thereon, and a resist pattern is formed by a known lithography method.
  • the silicon oxide film is etched by, eg, reactive ion etching, and then the photoresist is removed to form a mask MA.
  • the thickness of the mask MA is sufficient to shield the ion implantation, and can be, for example, 1.0 to 5.0 ⁇ m.
  • a p-type impurity (second impurity) is implanted into epitaxial layer EP from the main surface side of epitaxial layer EP, from the main surface of epitaxial layer EP in the element formation region of epitaxial layer EP.
  • a p-type embedded body region 7B1 is formed at a distant position.
  • aluminum (Al) or boron (B) can be used as the p-type impurity to be ion implanted.
  • the depth on the bottom side (the depth from the main surface of the epitaxial layer EP) of the buried body region 7B1 can be, for example, about 0.5 to 2.0 ⁇ m.
  • the depth on the main surface side of buried body region 7B1 (the depth from the main surface of epitaxial layer EP) can be, for example, about 0.2 to 0.5 ⁇ m. Further, the concentration of the p-type impurity in the outermost surface (the depth of 0.05 ⁇ m or less from the surface) region of the epitaxial layer EP on the buried body region 7B1 is, for example, 1 ⁇ 10 17 cm ⁇ 3 or less. . . The dopant concentration of the buried body region 7B1 is, for example, in the range of 1 ⁇ 10 16 to 1 ⁇ 10 19 cm ⁇ 3 . After the ion implantation step for forming such embedded body region 7B1, the mask MA is removed. ⁇ Formation of Source Region>
  • FIG. 11 is a cross-sectional view of a portion corresponding to the Y1-Y1 line and the X1-X1 line of FIG. 6 in the process of forming the source region that constitutes the semiconductor device of the first embodiment.
  • another mask MB is formed on the main surface of the epitaxial layer EP.
  • the shape in plan view of the mask MB is formed in a shape that exposes the source region and covers the other.
  • the material and formation method of the mask MB are the same as the mask MA.
  • an n-type impurity (first impurity) is ion-implanted into the epitaxial layer EP from the main surface side of the epitaxial layer EP to form an n-type source region 8S.
  • this n-type impurity for example, nitrogen (N) or phosphorus (P) can be used.
  • the impurity concentration of the source region 8S can be, for example, in the range of 1 ⁇ 10 17 to 1 ⁇ 10 21 cm ⁇ 3 .
  • the depth of the source region 8S (the depth from the main surface of the epitaxial layer EP) is shallower than that of the buried body region 7B1, and can be, for example, about 0.01 to 0.2 ⁇ m.
  • FIG. 12 is a cross-sectional view of a portion corresponding to the Y1-Y1 line of FIG. 6 in the process of forming the long side body region constituting the semiconductor device of the first embodiment.
  • a p-type impurity (third impurity) is implanted obliquely to the main surface of epitaxial layer EP from the main surface side of epitaxial layer EP using the same mask MB as FIG. Do. That is, the p-type impurity is ion-implanted into the epitaxial layer EP from one direction along the Y direction in a state in which the ion implantation angle of the impurity is inclined by the inclination angle ⁇ with respect to the normal to the main surface of the epitaxial layer EP.
  • a p-type impurity is implanted into a part (below the mask MB end) of the part shielded by the mask MB, and a length adjacent to one end (one long side) in the width direction of the source region 8S Side body regions 7B2 can be formed.
  • the p-type impurity for ion implantation can be used as the p-type impurity for ion implantation.
  • the inclination angle ⁇ at the time of ion implantation can be, for example, 15 to 45 degrees.
  • the acceleration energy at the time of ion implantation be, for example, 300 keV to 1500 keV at maximum.
  • the p-type impurity can permeate the mask MB and reach the epitaxial layer EP.
  • the impurity concentration of the long side body region 7B2 is, for example, in the range of 1 ⁇ 10 16 to 5 ⁇ 10 18 cm ⁇ 3 .
  • a p-type impurity (third impurity) is implanted obliquely to the main surface of the epitaxial layer EP using the same mask MB as that of FIG. That is, in a state where the ion implantation angle of the impurity is inclined by the inclination angle ⁇ with respect to the normal to the main surface of the epitaxial layer EP, the p-type impurity is ion implanted into the epitaxial layer EP from the reverse direction to the left in FIG. Do.
  • a p-type impurity is implanted into a part of the portion shielded by the mask MB (below the end of the mask MB), and a portion adjacent to the other end (other long side) in the width direction of the source region 8S.
  • the long side body region 7B2 can be formed.
  • the conditions such as the inclination angle ⁇ , the implanted ion species, the acceleration energy, and the implantation amount are the same except that the impurity implantation direction is different.
  • the implantation depth may differ depending on the crystal orientation of the main surface of epitaxial layer EP. In that case, by changing the implantation conditions such as the inclination angle ⁇ for each impurity implantation direction, each of the two long side body regions 7B2 on both end sides in the width direction of the source region 8S is formed.
  • the channel length and the impurity concentration can be adjusted to be the same.
  • FIG. 13 is a plan view of an essential part of the active region of the semiconductor substrate after the step of forming the long side body region
  • FIG. 14 right and left are cross-sectional views taken along line Y1-Y1 and X1-X1 of FIG.
  • the mask MB (see FIGS. 11 and 12) is removed to form the source region 8S and the long side body region 7B2 on the main surface of the epitaxial layer EP.
  • the long side body regions 7B2 are formed adjacent to both long sides of each source region 8S.
  • the long side body region 7B2 extends from the main surface of the epitaxial layer EP to the buried body region 7B1 so as to cover the side portion on the long side of the source region 8S as shown in the left of FIG. ing.
  • FIG. 15 are cross-sectional views corresponding to the Y1-Y1 line and the X1-X line of FIG. 6 during the process of forming the body contact region constituting the semiconductor device of the first embodiment.
  • the mask MC is formed on the main surface of the epitaxial layer EP.
  • the shape of the mask MC in a plan view is formed to expose the body contact region and cover the other.
  • the material and formation method of the mask MC are the same as the mask MA.
  • p + -type body contact region 9 BC is formed in epitaxial layer EP by ion-implanting p-type impurity in epitaxial layer EP using mask MC as a mask for impurity implantation, and then mask MC is removed.
  • mask MC for impurity implantation
  • aluminum or boron can be used as the p-type impurity to be ion implanted.
  • the p + -type body contact region 9BC extends from the main surface of the epitaxial layer EP to the p-type buried body region 7B1 and terminates.
  • the impurity concentration of the p + -type body contact region 9BC is, for example, in the range of 1 ⁇ 10 19 to 1 ⁇ 10 21 cm ⁇ 3 .
  • the depth of the p + -type body contact region 9BC (the depth from the main surface of the epitaxial layer EP) is, for example, about 0.1 to 0.4 ⁇ m.
  • 16A and 16B are cross-sectional views corresponding to the Y1-Y1 line and the XX line of FIG. 6 in the process of forming the short side body region constituting the semiconductor device of the first embodiment.
  • the mask MD is formed on the main surface of the epitaxial layer EP.
  • the shape in plan view of the mask MD is formed in a shape that exposes the short side body region and covers the other.
  • the material and forming method of the mask MD are the same as the mask MA.
  • p-type impurity (fourth impurity) is ion-implanted into the epitaxial layer EP from the main surface side of the epitaxial layer EP using the mask MD as a mask for impurity implantation, and the p-type short side body region is formed in the epitaxial layer EP.
  • the mask MD is removed.
  • aluminum or boron can be used as the p-type impurity to be ion implanted.
  • the p-type short side body region 7B3 extends from the main surface of the epitaxial layer EP to the buried body region 7B1 and terminates.
  • the impurity concentration of the short side body region 7B3 is higher than the p-type impurity concentration of the long side body region 7B2, and is, for example, in the range of 5 ⁇ 10 16 to 1 ⁇ 10 21 cm ⁇ 3 .
  • FIG. 17 is a cross-sectional view of a portion corresponding to the Y1-Y1 line and the X1-X1 line of FIG. 6 showing a modification of the process of forming the body contact region and the short side body region constituting the semiconductor device of the first embodiment. It is.
  • the p-type short side body region 7B3 and the p + -type body contact region 9BC described above are formed for different functions and purposes, in the above example, the p-type short side body region 7B3 and The case where the p + -type body contact regions 9BC are formed using different masks is shown. Thereby, the setting accuracy of the impurity concentration of each of the p-type short side body region 7B3 and the p + -type body contact region 9BC can be improved.
  • the impurity concentrations of the p-type short side body region 7B3 and the p + -type body contact region 9BC are close to each other, they may be simultaneously formed as long as their respective functions can be achieved. That is, as shown in FIG. 17, on the main surface of epitaxial layer EP, mask ME is formed in which both the p-type short side body region and the p + -type body contact region are exposed and the other is covered. .
  • a p-type impurity is ion-implanted into the epitaxial layer EP using the mask ME as a mask for impurity implantation, thereby collectively forming the p-type short side body region 7B3 and the p + -type body contact region 9BC in the epitaxial layer EP.
  • the mask ME is removed.
  • the concentrations of p-type impurities in the p-type short side body region 7B3 and the p + -type body contact region 9BC are substantially the same.
  • the semiconductor substrate 1S is heat-treated to activate the impurities.
  • a surface covering film (not shown) made of carbon (C) having a thickness of about 0.05 ⁇ m is deposited on the main surface of epitaxial layer EP and the main surface of substrate layer SB. It is good.
  • This surface coating film has an effect of preventing the main surfaces of the epitaxial layer EP and the substrate layer SB from being roughened during the activation heat treatment.
  • the surface coating film is removed by, for example, oxygen plasma treatment after the activation heat treatment.
  • FIG. 18 is a plan view of an essential part of an active region of a semiconductor substrate after a process of forming a body contact region and a short side body region.
  • a plurality of body contact regions 9BC are arranged side by side along the longitudinal direction of source region 8S.
  • short side body regions 7B3 are formed in portions adjacent to both end portions in the longitudinal direction of each source region 8S.
  • the shape of (.) Be a shape that continuously extends along the arrangement direction of the plurality of source regions 8S.
  • FIG. 19 is a cross-sectional view of a portion corresponding to the Y1-Y1 line and the X1-X1 line of FIG. 6 in the step of forming the gate electrode constituting the semiconductor device of the first embodiment.
  • a silicon oxide film for example, is formed on the main surface of the epitaxial layer EP.
  • the gate insulating film 10a is formed by a thermal CVD method or the like.
  • the thickness of the gate insulating film 10a can be, for example, 0.02 to 0.2 ⁇ m.
  • an n-type polycrystalline silicon film 11 for forming a gate electrode is formed on the gate insulating film 10a by a thermal CVD method or the like.
  • the thickness of the polycrystalline silicon film 11 is, for example, about 0.2 to 0.5 ⁇ m.
  • the polycrystalline silicon film 11 may be deposited in a polycrystalline state, or may be polycrystallized by heat treatment after being deposited in an amorphous state.
  • a mask MF is formed on the polycrystalline silicon film 11.
  • the shape of the mask MF in plan view is formed to cover the gate electrode formation region and expose the other regions.
  • the material and forming method of the mask MF are the same as those of the mask MA.
  • FIG. 20 is a cross-sectional view of a portion corresponding to the Y1-Y1 line and the X1-X1 line of FIG. 6 in the manufacturing process of the semiconductor device after the process of FIG.
  • the polycrystalline silicon film 11 is subjected to dry etching to form a gate electrode 11G.
  • An opening 12 is formed in part of the gate electrode 11G.
  • an interlayer insulating film 13 is deposited on the epitaxial layer EP by plasma CVD or the like so as to cover the gate electrode 11G and the gate insulating film 10a, and then a mask MG is formed on the interlayer insulating film 13.
  • the shape of the mask MG in a plan view is formed to expose the source contact region and cover the other.
  • the material and formation method of the mask MG are the same as the mask MA.
  • the source contact SC is formed by removing portions of the interlayer insulating film 13 and the gate insulating film 10a exposed from the mask MG by dry etching using the mask MG as an etching mask, and then the mask MG is removed. A portion of n-type source region 8S and a plurality of p + -type body contact regions 9BC are exposed from source contact SC.
  • the interlayer insulating film 13 is processed by dry etching or the like to partially expose the upper surface of the gate electrode 11G in the interlayer insulating film 13. Form a contact hole (gate contact).
  • a titanium (Ti) film, a titanium nitride (TiN) film, and an aluminum film are sequentially deposited from the lower layer on the epitaxial layer EP of the semiconductor substrate 1S to form a laminated film, and then the laminated film is formed.
  • Source electrode 2S is electrically connected to n type source region 8S and a plurality of p + type body contact regions 9BC through source contact SC.
  • the gate electrode 2G is electrically connected to the gate electrode 11G through the gate contact.
  • drain electrode 3D made of metal is formed on the main surface of the substrate layer SB of the semiconductor substrate 1S.
  • an n-type impurity is heavily implanted into the main surface of substrate layer SB prior to the step of forming drain electrode 3D.
  • a silicide layer can be formed in the high concentration impurity implantation region.
  • the semiconductor substrate 1S is divided into individual chips, whereby the chip 1C having the DMOSFET shown in FIG. 1 can be manufactured.
  • FIG. 21 is an enlarged plan view of an essential part of the active region of the semiconductor device of the second embodiment
  • FIG. 22 is a cross-sectional view taken along the line X1-X1 of FIG.
  • thick field insulating film (first insulating film) 10b is partially provided on epitaxial layer EP in a region adjacent to both ends (short sides) in the longitudinal direction of source region 8S.
  • a gate electrode 11G is provided thereon via a gate insulating film 10a.
  • the field insulating film 10b is made of the same silicon oxide film as the gate insulating film 10a, but the thickness of the field insulating film 10b is, for example, in the range of 200 nm to 5 ⁇ m, and the thickness of the gate insulating film 10a (for example, 0. Thicker than 02 ⁇ m to 0.2 ⁇ m).
  • the gate electrode 11G is disposed via the gate insulating film 10a. That is, in the regions adjacent to both ends (long sides) in the width direction of the source region 8S, the voltage of the gate electrode 11G is affected via the thin gate insulating film 10a.
  • the threshold voltage of the channel formed in the portion adjacent to the both ends (short side) in the longitudinal direction of source region 8S of unit cell UC is the both ends in the width direction of source region 8S of unit cell UC. It is higher than the threshold voltage of the channel formed in the portion adjacent to the long side).
  • a part of the field insulating film 10b overlaps with a part of both end portions in the longitudinal direction of the source region 8S in plan view.
  • the short side body region 7B3 is not formed.
  • both end portions in the longitudinal direction (X direction) of the opening 12 of the gate electrode 11G are located outside the both end portions in the longitudinal direction of the source region 8S of the unit cell UC. That is, the gate electrode 11G is formed at a position apart from both end portions in the longitudinal direction of the source region 8S. Moreover, both end portions in the longitudinal direction of the opening 12 of the gate electrode 11G are formed on the laminated film of the field insulating film 10b and the gate insulating film 10a. That is, the part (short side) adjacent to both ends in the longitudinal direction of source region 8S of unit cell UC is affected by the voltage of gate electrode 11G through the stacked film of thick field insulating film 10b and thin gate insulating film 10a. Receive Thus, the influence of the gate voltage can be further reduced in portions (short sides) adjacent to both ends of the source region 8S of the unit cell UC in the longitudinal direction.
  • both ends in the width direction of the opening 12 of the gate electrode 11G are located inside the both ends in the width direction of the source region 8S of the unit cell UC. Therefore, the gate electrode 11G is provided only at the thin gate insulating film 10a in a portion adjacent to the source region 8S in the width direction. That is, portions (long sides) adjacent to both ends in the width direction of the source region 8S of the unit cell UC are affected by the voltage of the gate electrode 11G only via the thin gate insulating film 10a. As a result, the influence of the gate voltage can be further increased in portions (long sides) adjacent to both ends in the width direction of the source region 8S of the unit cell UC.
  • the threshold voltage of the channel formed in the portion adjacent to both ends (short side) in the longitudinal direction of source region 8S is formed in the portion adjacent to both ends (long side) in the width direction of source region 8S. Higher than the threshold voltage of the channel being
  • the field insulating film 10b when the thickness of the field insulating film 10b is sufficiently thick, the field insulating film 10b is not provided at both ends in the longitudinal direction of the opening 12 of the gate electrode 11G, as in the first embodiment.
  • the opening 12 may be formed to be located inside the source region 8S.
  • the thickness of the field insulating film 10 b is sufficiently thick, the following formula (1) is satisfied. tox1 ⁇ ⁇ NA1> tox2 ⁇ ⁇ NA2 (1)
  • NA1 is a concentration of p-type impurities in a portion adjacent to both ends (short side) in the longitudinal direction of source region 8S, and tox1 is formed on a portion adjacent to both ends (short side) in the longitudinal direction of source region 8S
  • the thickness of the insulating film eg, the sum of the thickness of the field insulating film 10 b and the thickness of the gate insulating film 10 a.
  • NA2 is the concentration of p-type impurities in a portion adjacent to both ends (long side) in the width direction of the source region 8S, and tox2 is on a portion adjacent to both ends (long side) in the width direction of the source region 8S. It is the thickness of the formed insulating film (example: thickness of the gate insulating film 10a).
  • field insulating film 10b is formed to extend continuously along the Y direction so as to connect a plurality of unit cells UC.
  • the dimensions of the mask when forming the field insulating film 10b can be increased, so that the field insulating film 10b can be formed more easily.
  • the field insulating film 10b may be formed to cover both longitudinal ends of the source region 8S of each unit cell UC in order to suppress or prevent the above-described leakage current.
  • FIG. 23 is a plan view of relevant parts of a semiconductor substrate showing a modification of the field insulating film. In FIG. 23, the field insulating film 10b is separated for each unit cell UC.
  • the shape and the arrangement of the opening 12 of the gate electrode 11G may be simply as described above without providing the field insulating film 10b. That is, both end portions in the longitudinal direction (X direction) of the opening 12 of the gate electrode 11G are positioned outside the both ends in the longitudinal direction of the source region 8S, and the width direction (Y direction) of the opening 12 of the gate electrode 11G is Both ends may be located inside the both ends in the width direction of the source region 8S.
  • the threshold voltage of a portion adjacent to both ends (short side) in the longitudinal direction of source region 8S is set to a channel formed in the portion adjacent to both ends (long side) in the width direction of source region 8S. It can be higher than the threshold voltage.
  • the same method as that of the first embodiment can be used up to the step of forming the body contact region (step of FIG. 18) (however, the present embodiment).
  • the short side body region 7B3 is not formed). Therefore, the following steps will be described with reference to FIGS. 24 to 26.
  • FIG. 24 is a cross-sectional view of a portion corresponding to the Y1-Y1 line and the X1-X1 line of FIG. 6 in the step of forming the field insulating film constituting the semiconductor device of the second embodiment.
  • the field insulating film 10b is formed on the epitaxial layer EP by the CVD method or the like.
  • a mask MH is formed on the field insulating film 10b.
  • the mask MH is formed to cover the formation region of the field insulating film 10 b and expose the other regions.
  • the material and formation method of the mask MH are the same as the mask MA.
  • field insulating film 10b exposed from mask MH is etched away to expose a part of the surface of epitaxial layer EP. Thereafter, the mask MH is removed.
  • FIG. 25 is a cross-sectional view of a portion corresponding to the Y1-Y1 line and the X1-X1 line of FIG. 6 during the film formation step of the polycrystalline silicon film constituting the semiconductor device of Embodiment 2 after the step of FIG. is there.
  • the gate insulating film 10a and the polycrystalline silicon film 11 are sequentially deposited from the lower layer by the CVD method or the like on the epitaxial layer EP so as to cover the field insulating film 10b. Subsequently, a mask MJ is formed on the polycrystalline silicon film 11. The mask MJ is formed to cover the formation region of the gate electrode and to expose the other. The material and formation method of the mask MJ are the same as the mask MA.
  • FIG. 26 is a cross-sectional view of a portion corresponding to the Y1-Y1 line and the X1-X1 line of FIG. 6 after the source contact forming step of the semiconductor device of the second embodiment after the step of FIG.
  • the polycrystalline silicon film 11 is processed by dry etching to form the gate electrode 11G, and after the opening 12 is formed, the mask MJ is removed. Do.
  • an interlayer insulating film 13 is formed by, eg, plasma CVD to cover the gate electrode 11G and the gate insulating film 10a, and then a mask (not shown) is formed on the interlayer insulating film 13. Form).
  • a mask (not shown) is formed on the interlayer insulating film 13.
  • interlayer insulating film 13 and gate insulating film 10a are processed by dry etching to form part of the surface of n-type source region 8S and the surface of p + -type body contact region 9BC.
  • An exposed source contact SC is formed.
  • another mask is formed on the interlayer insulating film 13, and this is used as an etching mask to form a gate contact in the interlayer insulating film 13 in which a part of the gate electrode 11G is exposed.
  • FIG. 27 is an enlarged plan view of an essential part of the active region of the semiconductor device according to the third embodiment
  • FIG. 28 is a cross-sectional view taken along line X1-X1 of FIG.
  • the short side body is provided in portions adjacent to both end portions of the source region 8S of the unit cell UC in the longitudinal direction. Region 7B3 is formed.
  • the concentration of the p-type impurity contained in the short side body region 7B3 may not be sufficiently high due to reasons such as the manufacturing process.
  • the thickness of the field insulating film 10b may not be sufficiently thick.
  • the threshold voltage of a portion adjacent to both ends (short side) of source region 8S of unit cell UC is the threshold voltage of a portion adjacent to both ends (long side) of source region 8S in the width direction. Sometimes it can not be higher than the voltage.
  • the threshold voltage of the portion (short side) adjacent to both ends of the source region 8S of the unit cell UC. can be set higher than the threshold voltage of the portion (long side) adjacent to both ends in the width direction of the source region 8S.
  • both end portions in the longitudinal direction of the opening 12 of the gate electrode 11G are located outside the both end portions in the longitudinal direction of the source region 8S. Then, gate electrodes 11G located on both end sides in the longitudinal direction of the source region 8S are formed on the laminated film of the thick field insulating film 10b and the gate insulating film 10a. As a result, the influence of the gate voltage can be further reduced in portions (short sides) adjacent to both ends of the source region 8S of the unit cell UC in the longitudinal direction.
  • both end portions in the width direction of the opening 12 of the gate electrode 11G are located inside the both end portions in the width direction of the source region 8S. Then, gate electrodes 11G located on both end sides in the width direction of the source region 8S are formed on the thin gate insulating film 10a. As a result, the influence of the gate voltage can be further increased in portions (long sides) adjacent to both ends in the width direction of the source region 8S of the unit cell UC.
  • the threshold voltage of the channel (short side) adjacent to both ends in the longitudinal direction of source region 8S of unit cell UC is the portion adjacent to both ends in the width direction of source region 8S of unit cell UC. It can be made higher than the threshold voltage of the (long side) channel.
  • both end portions in the longitudinal direction of the opening 12 of the gate electrode 11G are not provided with the field insulating film 10b.
  • the opening 12 may be formed to be located in the area of 8S.
  • the process of forming the short side body region 7B3 is the same as that of the first embodiment. Further, since the step of forming field insulating film 10b is the same as that of the second embodiment, the example of the method of manufacturing the semiconductor device of the third embodiment is omitted.
  • the present invention is not limited to the above-described embodiment, but includes various modifications.
  • the above-described embodiment has been described in detail in order to explain the invention in an easy-to-understand manner, and is not necessarily limited to one having all the described configurations.
  • part of the configuration of one embodiment can be replaced with the configuration of another embodiment.
  • the functions of the “source” and the “drain” of the transistor may be switched when adopting transistors of different polarities, when the direction of current changes in circuit operation, or the like. Therefore, in the present specification, the terms “source” and “drain” can be used interchangeably.
  • electrode and “wiring” do not functionally limit these components.
  • electrodes may be used as part of “wirings” and vice versa.
  • the terms “electrode” and “wiring” include the case where a plurality of “electrodes” and “wirings” are integrally formed.
  • DMOSFET was illustrated as a switching transistor, it is not limited to this, For example, you may use IGBT (Insulated Gate Bipolar Transistor). Further, for example, the present invention can be applied to an inverter having a switching transistor such as a DMOSFET or an IGBT. Further, for example, the present invention can be applied to a power module having a switching transistor such as a DMOSFET or an IGBT.
  • IGBT Insulated Gate Bipolar Transistor

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PCT/JP2018/020457 2017-07-18 2018-05-29 半導体装置およびその製造方法 WO2019017076A1 (ja)

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