WO2019017076A1 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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Publication number
WO2019017076A1
WO2019017076A1 PCT/JP2018/020457 JP2018020457W WO2019017076A1 WO 2019017076 A1 WO2019017076 A1 WO 2019017076A1 JP 2018020457 W JP2018020457 W JP 2018020457W WO 2019017076 A1 WO2019017076 A1 WO 2019017076A1
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insulating film
semiconductor region
semiconductor
region
view
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PCT/JP2018/020457
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French (fr)
Japanese (ja)
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貴博 森川
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株式会社日立パワーデバイス
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Priority to CN201880023964.4A priority Critical patent/CN110521002B/en
Publication of WO2019017076A1 publication Critical patent/WO2019017076A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched

Definitions

  • the present invention relates to a semiconductor device and its manufacturing technology, for example, to a technology effectively applicable to a power semiconductor device and its manufacturing method.
  • Patent Document 1 JP-A-2004-39744
  • the SiC substrate is inclined relative to the normal direction of the SiC substrate while rotating the SiC substrate around the normal of the SiC substrate through the mask material whose inclination is formed on the pattern sidewall by taper etching.
  • Techniques for implanting low concentration base regions and high concentration base regions are described.
  • Patent Document 1 describes a technique for forming the source region and the channel region of the vertical MOSFET in a self-aligned manner using the same mask. Further, Patent Document 1 exemplifies a stripe type cell of a vertical MOSFET.
  • the stripe type cell (source region) is formed in a strip shape whose length in one direction is longer than the length in the other direction orthogonal to the one direction in the shape in plan view.
  • an impurity of the opposite conductivity type to the source region is not necessarily sufficiently injected into portions adjacent to both end portions in the longitudinal direction of the stripe type cell (source region). Therefore, the threshold voltage of a portion adjacent to both ends in the longitudinal direction of the stripe type cell (source region) is a portion adjacent to both ends in the width direction (short direction) of the stripe type cell (source region) Approximately equal to or lower than the threshold voltage of As a result, a leak current is generated at both ends in the longitudinal direction of the stripe type cell, and there is a problem that the reliability of the semiconductor device is lowered.
  • An object of the present invention is to provide a technology capable of improving the reliability of a semiconductor device.
  • the length of the first direction in plan view is longer than the length in the second direction intersecting with the first direction on the first surface of the semiconductor substrate, and A first semiconductor region of a first conductivity type is provided which extends from one surface in the depth direction of the semiconductor substrate. Further, a gate electrode is provided on portions adjacent to both end portions of at least the first semiconductor region in the second direction via an insulating film. Then, the threshold voltage of a portion adjacent to both ends of the first semiconductor region in the first direction in plan view is made higher than the threshold voltage of a portion adjacent to both ends of the first semiconductor region in the second direction. .
  • the reliability of the semiconductor device can be improved. Problems, configurations, and effects other than those described above will be apparent from the description of the embodiments below.
  • FIG. 2 is a cross-sectional view taken along line X10-X10 of FIG.
  • FIG. 1 is a plan view of an example of a semiconductor chip constituting a semiconductor device of a first embodiment. It is an enlarged plan view of an example of field A1 enclosed with a dashed line of FIG.
  • FIG. 4 is an enlarged plan view of an example of a gate electrode made of polycrystalline silicon in a region A2 surrounded by a broken line in FIG. 3.
  • FIG. 5 is an enlarged plan view of an example of an active region of a region A2 surrounded by a dashed line in FIG. 3; FIG.
  • FIG. 7 is a cross-sectional view taken along line X1-X1 and line Y1-Y1 of FIG. 6; It is a principal part top view of the semiconductor substrate which shows the modification of a short side body field.
  • FIG. 7 is a cross-sectional view taken along line Y1-Y1 of FIG. 6;
  • FIG. 7 is a cross-sectional view of a portion corresponding to the Y1-Y1 line and the X1-X1 line of FIG. 6 in the step of forming the embedded body region that configures the semiconductor device of the first embodiment.
  • FIG. 7 is a cross-sectional view of a portion corresponding to the Y1-Y1 line and the X1-X1 line of FIG.
  • Left and right are cross-sectional views of a portion corresponding to the Y1-Y1 line of FIG. 6 at the time of the step of forming the long side body region that constitutes the semiconductor device of the first embodiment. It is a principal part top view of an active field of a semiconductor substrate after a formation process of a long side body field.
  • the left is a cross-sectional view taken along line Y1-Y1 of FIG. 13, and the right is a cross-sectional view taken along line X1-X1 of FIG.
  • Left and right are cross-sectional views of portions corresponding to the Y1-Y1 line and the X1-X1 line of FIG.
  • FIG. 6 is a cross-sectional view of portions corresponding to the Y1-Y1 line and the X1-X1 line of FIG. 6 in the process of forming the short side body region constituting the semiconductor device of the first embodiment.
  • FIG. 7 is a cross-sectional view of a portion corresponding to the Y1-Y1 line and the X1-X1 line of FIG. 6 showing a modification of the process of forming the body contact region and the short side body region constituting the semiconductor device of the first embodiment; It is a principal part top view of the active field of a semiconductor substrate after the formation process of a body contact field and a short side body field.
  • FIG. 7 is a cross-sectional view of a portion corresponding to the Y1-Y1 line and the X1-X1 line of FIG. 6 showing a modification of the process of forming the body contact region and the short side body region constituting the semiconductor device of the first embodiment.
  • It is a principal part top view of the active field of a semiconductor substrate
  • FIG. 7 is a cross-sectional view of a portion corresponding to the Y1-Y1 line and the X1-X1 line of FIG. 6 in the step of forming the gate electrode constituting the semiconductor device of Embodiment 1;
  • FIG. 20 is a cross-sectional view of a portion corresponding to the Y1-Y1 line and the X1-X1 line of FIG. 6 in the manufacturing process of the semiconductor device after the process of FIG. 19;
  • FIG. 16 is an enlarged plan view of a main part of an active region of the semiconductor device of Second Embodiment;
  • FIG. 22 is a cross-sectional view taken along line X1-X1 of FIG. It is a principal part top view of the semiconductor substrate which shows the modification of field insulating film.
  • FIG. 20 is a cross-sectional view of a portion corresponding to the Y1-Y1 line and the X1-X1 line of FIG. 6 in the step of forming the gate electrode constituting the semiconductor device of Embod
  • FIG. 17 is a cross-sectional view of a portion corresponding to the Y1-Y1 line and the X1-X1 line of FIG. 6 in the step of forming the field insulating film that configures the semiconductor device of Second Embodiment;
  • FIG. 25 is a cross-sectional view of a portion corresponding to the Y1-Y1 line and the X1-X1 line of FIG. 6 in the film formation step of the polycrystalline silicon film constituting the semiconductor device of Embodiment 2 after the step of FIG. 24;
  • FIG. 26 is a cross-sectional view of a portion corresponding to the Y1-Y1 line and the X1-X1 line of FIG. 6 after the source contact forming step of the semiconductor device of the second embodiment after the step of FIG. 25;
  • FIG. 16 is an enlarged plan view of a main part of an active region of the semiconductor device of the third embodiment.
  • FIG. 28 is a cross-sectional view taken along line X1-X1 of FIG.
  • a silicon (Si) substrate has long been used as a substrate for power semiconductor devices, but as a result of achieving lower loss and improved performance of Si-based power semiconductor devices, the device performance is based on the material properties of Si. It is approaching the theoretical limit to be determined, and it is becoming difficult to further improve performance in the future.
  • SiC and GaN have been actively studied.
  • SiC and GaN have a breakdown electric field strength about one digit larger than that of Si and can make the drift layer thinner. Therefore, in the power semiconductor device using the wide gap semiconductor, the on-resistance can be reduced, that is, the loss can be reduced, as compared with the Si-based power semiconductor device.
  • an n-type source region, a p-type body region and the like are formed by selective ion implantation.
  • impurity ion implantation usually, lithography is performed on each of the n-type source region and the p-type body region, and impurities are implanted using different masks.
  • small changes in exposure dose and temperature may shift the dimensions of the resist mask formed after development. Since the channel length is usually less than 1 ⁇ m, changes and variations in device performance caused by misalignment and dimensional shifts can not be ignored.
  • the channel length can be defined without being affected by misalignment or dimensional shift caused by the two exposures, and a short channel, low on-resistance power MOSFET can be manufactured without variation.
  • Patent Document 1 discloses a method of manufacturing a vertical MOSFET by implanting ions of a source region and a channel region using the same mask. According to the method of Patent Document 1, the n-type impurity of the source region is implanted from the normal direction of the substrate surface to the substrate on which the mask is formed, and further, at an angle inclined to the normal direction of the substrate. A channel is formed under the mask by implanting P-type impurities. Further, Patent Document 1 discloses a method in which ion implantation is performed twice in a diagonal direction so as to cross a stripe-like cell.
  • Patent Document 1 when the inventor examined Patent Document 1, it became clear that the manufactured MOSFET had a problem. That is, in the method of Patent Document 1, P-type impurities are not sufficiently implanted into portions adjacent to both end portions in the longitudinal direction of the N-type source region constituting the stripe-shaped unit cell. Therefore, the threshold voltage of the portion adjacent to the both ends (long side) in the width direction (short direction) of the source region is the portion adjacent to the both ends (short side) in the longitudinal direction of the source region. The threshold voltage is lower.
  • a current flowing through a channel formed in a portion adjacent to both ends (long sides) in the width direction of the N-type source region is the main component of conduction.
  • the current flowing through the channel formed in the portion adjacent to both ends (short sides) in the longitudinal direction of the N-type source region is taken as a leak current. Then, the element having a large leak current is regarded as a defective product.
  • Patent Document 1 discloses a method of adding ion implantation twice more from the direction in which the substrate is rotated 90 degrees, and a method of implanting ions while rotating the substrate.
  • FIG. 1 is a plan view of a unit cell of a power semiconductor device examined by the present inventor
  • FIG. 2 is a cross-sectional view taken along line X10-X10 of FIG.
  • FIG. 1 illustrates two unit cells 100 formed in a strip shape in plan view.
  • a P-type body region 102 is formed to surround the outer periphery of the N-type source region 101 of the unit cell 100. Therefore, the threshold voltage of a portion adjacent to both ends (short side) in the longitudinal direction of N-type source region 101 and the portion adjacent to both ends (long side) in the width direction of N-type source region 101 And the threshold voltage of the
  • Patent Document 1 neither suggests nor discloses the problem of the leak current IL flowing from both end portions in the longitudinal direction of the unit cell 100 (N-type source region 101). Moreover, in Patent Document 1, the threshold voltage of the portion adjacent to both ends (short side) in the width direction of the N-type source region is set low from the viewpoint of achieving high-speed switching of the power semiconductor device. Therefore, the threshold voltage of the portion adjacent to both ends (short sides) in the longitudinal direction of the N-type source region is also lowered. Therefore, even if ion implantation as described above is performed, as shown in FIG. 1, normal operation is performed through the channels formed in the portions adjacent to both ends (long sides) in the width direction of unit cell 100 during operation of the power MOSFET.
  • plan view means the case of viewing from the direction perpendicular to the main surface of the semiconductor substrate.
  • arrows X and Y in the drawing indicate two directions intersecting (preferably orthogonal) with each other in plan view.
  • the semiconductor device according to the first embodiment is, for example, a switching device (power semiconductor device) having an n-channel vertical double diffused MOSFET (hereinafter, abbreviated as DMOSFET).
  • FIG. 3 is a plan view of an example of a semiconductor chip constituting the semiconductor device of the first embodiment. Although the areas A1 and A2 in FIG. 1 are not actually formed, they are illustrated for the sake of explanation.
  • the semiconductor chip (hereinafter simply referred to as a chip) 1C is formed in, for example, a substantially square shape in a plan view.
  • a termination region (a so-called guard ring region) GA is provided in the outer peripheral edge portion in the main surface of the chip 1C.
  • the termination region GA is formed of, for example, a p-type (second conductivity type) semiconductor region, and has an electric field relaxation function and the like.
  • a p-type impurity such as aluminum (Al) or boron (B) is introduced.
  • the source electrode 2S and the gate electrode 2G of the DMOSFET are provided in a mutually insulated state.
  • the source electrode 2S and the gate electrode 2G are formed, for example, by sequentially stacking a titanium (Ti) film, a titanium nitride (TiN) film, and an aluminum film (Al) from the lower layer.
  • the source electrode 2S and the gate electrode 2G are covered with a surface protection film (not shown) on the main surface of the chip 1C, the source electrode 2S and the gate are formed through an opening formed in part of the surface protection film.
  • a part of the electrode 2G is exposed.
  • a part of the source electrode 2S and the gate electrode 2G exposed from the opening formed in the surface protective film is a source pad and a gate pad.
  • Under the source electrode 2S and the gate electrode 2G a gate electrode made of polycrystalline silicon described later is formed.
  • FIG. 4 is an enlarged plan view of an example of a region A1 surrounded by a broken line in FIG. Note that FIG. 4 shows a state in which the source electrode 2S, the gate electrode 2G, and the gate electrode in the lower layer thereof are removed.
  • An active area ACA is disposed inside the termination area GA in the main surface of the chip 1C.
  • stripe-type unit cells UC constituting a DMOSFET are arranged. That is, in the active area ACA, a plurality of strip-like unit cells UC in which the dimension in the X direction (first direction) in plan view is longer than the dimension in the Y direction (second direction) have predetermined intervals along the Y direction. Is located in
  • the plurality of unit cells UC are electrically connected in parallel.
  • the chip 1C The resistance of the entire DMOSFET can be reduced.
  • the field area FA is disposed between both ends of the unit cell UC in the longitudinal direction (X direction) and the inner periphery of the termination area GA. That is, both ends in the longitudinal direction of each unit cell UC are separated from the inner periphery of the termination area GA.
  • FIG. 5 is an enlarged plan view of an example of a gate electrode made of polycrystalline silicon in a region A2 surrounded by a broken line in FIG. 3
  • FIG. 6 is an enlarged plan view of an example of an active region in a region A2 surrounded by a broken line in FIG. 7 is a cross-sectional view taken along line X1-X1 and line Y1-Y1 of FIG. 5 shows a state in which the source electrode 2S of the chip 1C is removed
  • FIG. 6 shows a state in which the gate electrode layer made of polycrystalline silicon in FIG. 5 is removed.
  • the arrow Z in FIG. 7 indicates a direction intersecting (preferably orthogonal to) the main surface of the chip 1C.
  • the semiconductor substrate 1S constituting the chip 1C is formed of, for example, a wide gap semiconductor such as silicon carbide (SiC).
  • the semiconductor substrate 1S has a substrate layer SB and an epitaxial layer EP formed thereon.
  • the substrate layer SB is made of, for example, n + -type SiC
  • the epitaxial layer EP is made of, for example, n ⁇ -type SiC.
  • an n-type impurity such as nitrogen (N) or phosphorus (P) is introduced.
  • the semiconductor substrate 1S has a main surface (first surface) of the epitaxial layer EP and a main surface (second surface) of the substrate layer SB on the opposite side.
  • the main surface of the epitaxial layer EP corresponds to the main surface of the chip 1C.
  • the drain electrode 3D is formed on the main surface of the substrate layer SB.
  • the drain electrode 3D is formed, for example, by sequentially laminating a Ti film, a TiN film, and an Al film from the lower layer.
  • a p-type buried body region 7B1, an n-type source region 8S, and ap + -type body contact are provided on the main surface side of the epitaxial layer EP of the semiconductor substrate 1S as components of the unit cell UC.
  • a region 9BC, a p-type long side body region 7B2, and a p-type short side body region 7B3 are provided.
  • the p-type buried body region (second semiconductor region) 7B1 is longer than the source region 8S in plan view so as to cover the bottom of the source region 8S of each unit cell UC. It is formed in a strip shape along the direction (X direction). That is, as shown on the right of FIG. 7, both ends in the longitudinal direction (X direction) of the embedded body region 7B1 reach the termination region GA. Further, as shown in the left of FIG. 7, the dimension in the width direction (Y direction) of the embedded body region 7B1 is wider than the dimension in the width direction (Y direction) of the source region 8S. Buried body region 7B1 is formed at a position away from the main surface of epitaxial layer EP (below the bottom of source region 8S).
  • buried body region 7B1 extends from the bottom of source region 8S toward substrate layer SB, and terminates at an intermediate position in the depth direction (Z direction) of epitaxial layer EP without reaching substrate layer SB. There is.
  • p-type impurities such as Al or boron (B) are introduced.
  • n-type (first conductivity type) source region (first semiconductor region) 8S is formed on the p-type buried body region 7B1.
  • the source region 8S is formed in a band shape along the longitudinal direction (X direction) of each unit cell UC in a plan view, as shown in FIG.
  • the source region 8S is disposed in a state of being overlapped with the embedded body region 7B1 so as to be included in each embedded body region 7B1 in plan view.
  • both ends in the longitudinal direction of the source region 8S do not reach the termination region GA, and terminate at a position distant from the termination region GA. Further, as shown in FIG.
  • source region 8S extends from the main surface of epitaxial layer EP toward substrate layer SB and terminates at a position where buried body region 7B1 is reached.
  • an n-type impurity such as nitrogen (N) or phosphorus (P) is introduced.
  • Source electrode 2S is electrically connected to source region 8S through source contact SC.
  • the body contact region 9BC is a conductive region for electrically connecting the source electrode 2S of the DMOSFET and the buried body region 7B1. That is, as shown in FIG. 7, body contact region 9BC extends in the depth direction from the main surface of epitaxial layer EP, and reaches and terminates embedded body region 7B1. Thus, source electrode 2S is electrically connected to embedded body region 7B1 through body contact region 9BC.
  • a p-type impurity such as Al or boron is introduced into the body contact region 9BC, for example.
  • body contact region 9BC is formed, for example, in a substantially rectangular shape in plan view, along the longitudinal direction (X direction) of source region 8S at the central position in the width direction (Y direction) of source region 8S. Are arranged at predetermined intervals. Since the number of unit cells UC that can be arranged in the active area ACA can be increased by reducing the area of the body contact area 9BC as described above, the on-resistance of the DMOSFET can be reduced. However, the number, size, or interval of the body contact regions 9BC can be changed variously. Further, the shape in plan view of the body contact region 9BC can be changed variously, and for example, it may be a strip extending continuously along the longitudinal direction of the source region 8S. In this case, since the resistance between the source electrode 2S and the embedded body region 7B1 can be reduced, the electrical stability of the body region can be improved.
  • a long side body region (third semiconductor region) 7B2 of the die is formed.
  • the long side body region 7B2 extends from the main surface of the epitaxial layer EP toward the substrate layer SB so as to cover the side portions on both long sides of the source region 8S, and reaches the buried body region 7B1 and terminates. ing.
  • a normal channel of the DMOSFET is formed on the surface side of the long side body region 7B2 when the DMOSFET operates.
  • the surface layer of the p-type long side body region 7B2 is inverted to n-type to pass electrons.
  • a p-type impurity such as Al or boron is introduced.
  • a strip-like p-type short side body region (fourth semiconductor in plan view) Region) 7B3 is formed.
  • This short side body region 7B3 extends from the main surface of epitaxial layer EP toward substrate layer SB so as to cover the side portions on both short sides of source region 8S, and reaches embedded body region 7B1 and terminates. ing. Therefore, the entire circumference of the source region 8S is surrounded by the p-type body region (p-type embedded body region 7B1, p-type long side body region 7B2 and p-type short side body region 7B3) .
  • the short side body region 7B3 has a function of suppressing or preventing a leak current from flowing from both ends of the source region 8S in the longitudinal direction during the operation of the DMOSFET.
  • a p-type impurity such as Al or boron is introduced.
  • the concentration of the p-type impurity contained in the short side body region 7B3 is higher than the concentration of the p-type impurity contained in the long side body region 7B2. Therefore, the threshold voltage when the surface layer portion of p-type short side body region 7B3 is inverted to n-type to form a channel during operation of the DMOSFET is the same as that of p-type long side body region 7B2.
  • the current (leakage current) flowing through the p-type short side body region 7B3 can be made extremely smaller than the current flowing through the p-type long side body region 7B2 in the operation of a normal DMOSFET. Therefore, the leakage current flowing from both ends in the longitudinal direction of the source region 8S can be reduced, so that the reliability of the power semiconductor device having the DMOSFET can be improved.
  • the short side body region 7B3 is separated for each unit cell UC.
  • the short side body region 7B3 may be formed so as to cover both end portions in the longitudinal direction of the source region 8S of each unit cell UC in order to suppress or prevent the above-described leakage current.
  • FIG. 8 is a plan view of relevant parts of a semiconductor substrate showing a modification of the short side body region.
  • the short side body regions 7B3 are formed to extend continuously along the Y direction so as to connect the plurality of unit cells UC. As a result, since the dimension of the opening of the mask when forming the short side body region 7B3 can be increased, the short side body region 7B3 can be formed more easily.
  • a gate insulating film (second insulating film) 10a is formed on the main surface of the epitaxial layer EP of such a semiconductor substrate 1S.
  • the gate insulating film 10 a is made of, for example, a silicon oxide film (SiO 2 ).
  • a gate electrode 11G is formed on the gate insulating film 10a.
  • the gate electrode 11G is made of, for example, a low resistance n-type polycrystalline silicon film. Although this gate electrode 11G is formed so as to cover the active area ACA in plan view as shown in FIG. 5, it does not overlap the termination area GA.
  • An opening 12 is formed in a part of the gate electrode 11G to expose a part of each unit cell UC.
  • the opening 12 is formed in a band shape so as to overlap the source region 8S in plan view. A portion of the source region 8S of the unit cell UC and the body contact region 9BC are exposed from the opening 12. Both ends in the width direction and the longitudinal direction of the opening 12 are located in the source region 8S. Therefore, the gate electrode 11G overlaps in plan view with a part inside the outer periphery of the source region 8S, the entire region of the long side body region 7B2 and the entire region 7B3 of the short side body region.
  • the interlayer insulating film 13 is deposited so as to cover the gate electrode 11G.
  • the interlayer insulating film 13 is made of, for example, a silicon oxide film (SiO 2 ).
  • the source electrode 2S and the gate electrode 2G described above are formed on the interlayer insulating film 13.
  • the source electrode 2S and the underlying gate electrode 11G are electrically insulated by an interlayer insulating film 13 provided therebetween.
  • the gate electrode 2G and the gate electrode 11G under the gate electrode 2G are electrically connected through an opening (gate contact; not shown) formed in the interlayer insulating film 13.
  • a source contact SC having an area smaller than that of the opening 12 is opened at a position overlapping the opening 12 of the gate electrode 11G in plan view.
  • a portion of source region 8S and body contact region 9BC are exposed from source contact SC. That is, source electrode 2S is electrically connected to source region 8S and body contact region 9BC of unit cell UC through source contact SC. Therefore, source region 8S and body contact region 9BC are electrically shorted through source electrode 2S.
  • FIG. 9 is a cross-sectional view taken along line Y1-Y1 of FIG.
  • a channel is formed in the surface layer of the p-type long side body region 7B2 in contact with the gate insulating film 10a.
  • electrons flow from the n-type source region 8S to the drain electrode 3D through the channel on the surface layer of the p-type long side body region 7B2. That is, a current Isd flows from the drain electrode 3D to the source electrode 2S through the surface layer channel of the p-type long side body region 7B2.
  • the switching operation is performed by thus applying a voltage to the gate electrode 11G.
  • FIGS. 10 to 20 an example of a method of manufacturing the semiconductor device of the first embodiment will be described with reference to FIGS. 10 to 20.
  • a portion corresponding to the cross section along line X1-X1 of FIG. 6 or the cross section along line Y1-Y1 is illustrated.
  • a plan view is also shown if necessary.
  • FIG. 10 is a cross-sectional view of a portion corresponding to the Y1-Y1 line and the X1-X1 line of FIG. 6 in the step of forming the buried body region constituting the semiconductor device of the first embodiment.
  • an epitaxial layer EP made of n ⁇ -type SiC is formed on the main surface of the substrate layer SB made of n + -type 4H—SiC.
  • the n-type impurity introduced into the substrate layer SB is, for example, nitrogen (N), and the impurity concentration thereof is, for example, in the range of 1 ⁇ 10 18 to 1 ⁇ 10 21 cm ⁇ 3 .
  • the epitaxial layer EP can be formed on the main surface of the substrate layer SB, for example, by an epitaxial method.
  • the epitaxial layer EP has a predetermined thickness and dopant concentration determined by the specifications of the device.
  • the thickness of the epitaxial layer EP is, for example, in the range of 3 to 30 ⁇ m.
  • the n-type dopant added to the epitaxial layer EP is, for example, nitrogen, and the dopant concentration is, for example, in the range of 1 ⁇ 10 14 to 1 ⁇ 10 17 cm ⁇ 3 .
  • a mask material is deposited on the main surface of the n ⁇ -type epitaxial layer EP and patterned to form a mask MA.
  • the shape of the mask MA in a plan view is formed to expose the embedded body region and to cover the rest.
  • a photoresist is used as the material of the mask MA
  • the photoresist is applied and then patterned by a known lithography method to form the mask MA.
  • silicon oxide SiO 2
  • a silicon oxide film is deposited, a photoresist is applied thereon, and a resist pattern is formed by a known lithography method.
  • the silicon oxide film is etched by, eg, reactive ion etching, and then the photoresist is removed to form a mask MA.
  • the thickness of the mask MA is sufficient to shield the ion implantation, and can be, for example, 1.0 to 5.0 ⁇ m.
  • a p-type impurity (second impurity) is implanted into epitaxial layer EP from the main surface side of epitaxial layer EP, from the main surface of epitaxial layer EP in the element formation region of epitaxial layer EP.
  • a p-type embedded body region 7B1 is formed at a distant position.
  • aluminum (Al) or boron (B) can be used as the p-type impurity to be ion implanted.
  • the depth on the bottom side (the depth from the main surface of the epitaxial layer EP) of the buried body region 7B1 can be, for example, about 0.5 to 2.0 ⁇ m.
  • the depth on the main surface side of buried body region 7B1 (the depth from the main surface of epitaxial layer EP) can be, for example, about 0.2 to 0.5 ⁇ m. Further, the concentration of the p-type impurity in the outermost surface (the depth of 0.05 ⁇ m or less from the surface) region of the epitaxial layer EP on the buried body region 7B1 is, for example, 1 ⁇ 10 17 cm ⁇ 3 or less. . . The dopant concentration of the buried body region 7B1 is, for example, in the range of 1 ⁇ 10 16 to 1 ⁇ 10 19 cm ⁇ 3 . After the ion implantation step for forming such embedded body region 7B1, the mask MA is removed. ⁇ Formation of Source Region>
  • FIG. 11 is a cross-sectional view of a portion corresponding to the Y1-Y1 line and the X1-X1 line of FIG. 6 in the process of forming the source region that constitutes the semiconductor device of the first embodiment.
  • another mask MB is formed on the main surface of the epitaxial layer EP.
  • the shape in plan view of the mask MB is formed in a shape that exposes the source region and covers the other.
  • the material and formation method of the mask MB are the same as the mask MA.
  • an n-type impurity (first impurity) is ion-implanted into the epitaxial layer EP from the main surface side of the epitaxial layer EP to form an n-type source region 8S.
  • this n-type impurity for example, nitrogen (N) or phosphorus (P) can be used.
  • the impurity concentration of the source region 8S can be, for example, in the range of 1 ⁇ 10 17 to 1 ⁇ 10 21 cm ⁇ 3 .
  • the depth of the source region 8S (the depth from the main surface of the epitaxial layer EP) is shallower than that of the buried body region 7B1, and can be, for example, about 0.01 to 0.2 ⁇ m.
  • FIG. 12 is a cross-sectional view of a portion corresponding to the Y1-Y1 line of FIG. 6 in the process of forming the long side body region constituting the semiconductor device of the first embodiment.
  • a p-type impurity (third impurity) is implanted obliquely to the main surface of epitaxial layer EP from the main surface side of epitaxial layer EP using the same mask MB as FIG. Do. That is, the p-type impurity is ion-implanted into the epitaxial layer EP from one direction along the Y direction in a state in which the ion implantation angle of the impurity is inclined by the inclination angle ⁇ with respect to the normal to the main surface of the epitaxial layer EP.
  • a p-type impurity is implanted into a part (below the mask MB end) of the part shielded by the mask MB, and a length adjacent to one end (one long side) in the width direction of the source region 8S Side body regions 7B2 can be formed.
  • the p-type impurity for ion implantation can be used as the p-type impurity for ion implantation.
  • the inclination angle ⁇ at the time of ion implantation can be, for example, 15 to 45 degrees.
  • the acceleration energy at the time of ion implantation be, for example, 300 keV to 1500 keV at maximum.
  • the p-type impurity can permeate the mask MB and reach the epitaxial layer EP.
  • the impurity concentration of the long side body region 7B2 is, for example, in the range of 1 ⁇ 10 16 to 5 ⁇ 10 18 cm ⁇ 3 .
  • a p-type impurity (third impurity) is implanted obliquely to the main surface of the epitaxial layer EP using the same mask MB as that of FIG. That is, in a state where the ion implantation angle of the impurity is inclined by the inclination angle ⁇ with respect to the normal to the main surface of the epitaxial layer EP, the p-type impurity is ion implanted into the epitaxial layer EP from the reverse direction to the left in FIG. Do.
  • a p-type impurity is implanted into a part of the portion shielded by the mask MB (below the end of the mask MB), and a portion adjacent to the other end (other long side) in the width direction of the source region 8S.
  • the long side body region 7B2 can be formed.
  • the conditions such as the inclination angle ⁇ , the implanted ion species, the acceleration energy, and the implantation amount are the same except that the impurity implantation direction is different.
  • the implantation depth may differ depending on the crystal orientation of the main surface of epitaxial layer EP. In that case, by changing the implantation conditions such as the inclination angle ⁇ for each impurity implantation direction, each of the two long side body regions 7B2 on both end sides in the width direction of the source region 8S is formed.
  • the channel length and the impurity concentration can be adjusted to be the same.
  • FIG. 13 is a plan view of an essential part of the active region of the semiconductor substrate after the step of forming the long side body region
  • FIG. 14 right and left are cross-sectional views taken along line Y1-Y1 and X1-X1 of FIG.
  • the mask MB (see FIGS. 11 and 12) is removed to form the source region 8S and the long side body region 7B2 on the main surface of the epitaxial layer EP.
  • the long side body regions 7B2 are formed adjacent to both long sides of each source region 8S.
  • the long side body region 7B2 extends from the main surface of the epitaxial layer EP to the buried body region 7B1 so as to cover the side portion on the long side of the source region 8S as shown in the left of FIG. ing.
  • FIG. 15 are cross-sectional views corresponding to the Y1-Y1 line and the X1-X line of FIG. 6 during the process of forming the body contact region constituting the semiconductor device of the first embodiment.
  • the mask MC is formed on the main surface of the epitaxial layer EP.
  • the shape of the mask MC in a plan view is formed to expose the body contact region and cover the other.
  • the material and formation method of the mask MC are the same as the mask MA.
  • p + -type body contact region 9 BC is formed in epitaxial layer EP by ion-implanting p-type impurity in epitaxial layer EP using mask MC as a mask for impurity implantation, and then mask MC is removed.
  • mask MC for impurity implantation
  • aluminum or boron can be used as the p-type impurity to be ion implanted.
  • the p + -type body contact region 9BC extends from the main surface of the epitaxial layer EP to the p-type buried body region 7B1 and terminates.
  • the impurity concentration of the p + -type body contact region 9BC is, for example, in the range of 1 ⁇ 10 19 to 1 ⁇ 10 21 cm ⁇ 3 .
  • the depth of the p + -type body contact region 9BC (the depth from the main surface of the epitaxial layer EP) is, for example, about 0.1 to 0.4 ⁇ m.
  • 16A and 16B are cross-sectional views corresponding to the Y1-Y1 line and the XX line of FIG. 6 in the process of forming the short side body region constituting the semiconductor device of the first embodiment.
  • the mask MD is formed on the main surface of the epitaxial layer EP.
  • the shape in plan view of the mask MD is formed in a shape that exposes the short side body region and covers the other.
  • the material and forming method of the mask MD are the same as the mask MA.
  • p-type impurity (fourth impurity) is ion-implanted into the epitaxial layer EP from the main surface side of the epitaxial layer EP using the mask MD as a mask for impurity implantation, and the p-type short side body region is formed in the epitaxial layer EP.
  • the mask MD is removed.
  • aluminum or boron can be used as the p-type impurity to be ion implanted.
  • the p-type short side body region 7B3 extends from the main surface of the epitaxial layer EP to the buried body region 7B1 and terminates.
  • the impurity concentration of the short side body region 7B3 is higher than the p-type impurity concentration of the long side body region 7B2, and is, for example, in the range of 5 ⁇ 10 16 to 1 ⁇ 10 21 cm ⁇ 3 .
  • FIG. 17 is a cross-sectional view of a portion corresponding to the Y1-Y1 line and the X1-X1 line of FIG. 6 showing a modification of the process of forming the body contact region and the short side body region constituting the semiconductor device of the first embodiment. It is.
  • the p-type short side body region 7B3 and the p + -type body contact region 9BC described above are formed for different functions and purposes, in the above example, the p-type short side body region 7B3 and The case where the p + -type body contact regions 9BC are formed using different masks is shown. Thereby, the setting accuracy of the impurity concentration of each of the p-type short side body region 7B3 and the p + -type body contact region 9BC can be improved.
  • the impurity concentrations of the p-type short side body region 7B3 and the p + -type body contact region 9BC are close to each other, they may be simultaneously formed as long as their respective functions can be achieved. That is, as shown in FIG. 17, on the main surface of epitaxial layer EP, mask ME is formed in which both the p-type short side body region and the p + -type body contact region are exposed and the other is covered. .
  • a p-type impurity is ion-implanted into the epitaxial layer EP using the mask ME as a mask for impurity implantation, thereby collectively forming the p-type short side body region 7B3 and the p + -type body contact region 9BC in the epitaxial layer EP.
  • the mask ME is removed.
  • the concentrations of p-type impurities in the p-type short side body region 7B3 and the p + -type body contact region 9BC are substantially the same.
  • the semiconductor substrate 1S is heat-treated to activate the impurities.
  • a surface covering film (not shown) made of carbon (C) having a thickness of about 0.05 ⁇ m is deposited on the main surface of epitaxial layer EP and the main surface of substrate layer SB. It is good.
  • This surface coating film has an effect of preventing the main surfaces of the epitaxial layer EP and the substrate layer SB from being roughened during the activation heat treatment.
  • the surface coating film is removed by, for example, oxygen plasma treatment after the activation heat treatment.
  • FIG. 18 is a plan view of an essential part of an active region of a semiconductor substrate after a process of forming a body contact region and a short side body region.
  • a plurality of body contact regions 9BC are arranged side by side along the longitudinal direction of source region 8S.
  • short side body regions 7B3 are formed in portions adjacent to both end portions in the longitudinal direction of each source region 8S.
  • the shape of (.) Be a shape that continuously extends along the arrangement direction of the plurality of source regions 8S.
  • FIG. 19 is a cross-sectional view of a portion corresponding to the Y1-Y1 line and the X1-X1 line of FIG. 6 in the step of forming the gate electrode constituting the semiconductor device of the first embodiment.
  • a silicon oxide film for example, is formed on the main surface of the epitaxial layer EP.
  • the gate insulating film 10a is formed by a thermal CVD method or the like.
  • the thickness of the gate insulating film 10a can be, for example, 0.02 to 0.2 ⁇ m.
  • an n-type polycrystalline silicon film 11 for forming a gate electrode is formed on the gate insulating film 10a by a thermal CVD method or the like.
  • the thickness of the polycrystalline silicon film 11 is, for example, about 0.2 to 0.5 ⁇ m.
  • the polycrystalline silicon film 11 may be deposited in a polycrystalline state, or may be polycrystallized by heat treatment after being deposited in an amorphous state.
  • a mask MF is formed on the polycrystalline silicon film 11.
  • the shape of the mask MF in plan view is formed to cover the gate electrode formation region and expose the other regions.
  • the material and forming method of the mask MF are the same as those of the mask MA.
  • FIG. 20 is a cross-sectional view of a portion corresponding to the Y1-Y1 line and the X1-X1 line of FIG. 6 in the manufacturing process of the semiconductor device after the process of FIG.
  • the polycrystalline silicon film 11 is subjected to dry etching to form a gate electrode 11G.
  • An opening 12 is formed in part of the gate electrode 11G.
  • an interlayer insulating film 13 is deposited on the epitaxial layer EP by plasma CVD or the like so as to cover the gate electrode 11G and the gate insulating film 10a, and then a mask MG is formed on the interlayer insulating film 13.
  • the shape of the mask MG in a plan view is formed to expose the source contact region and cover the other.
  • the material and formation method of the mask MG are the same as the mask MA.
  • the source contact SC is formed by removing portions of the interlayer insulating film 13 and the gate insulating film 10a exposed from the mask MG by dry etching using the mask MG as an etching mask, and then the mask MG is removed. A portion of n-type source region 8S and a plurality of p + -type body contact regions 9BC are exposed from source contact SC.
  • the interlayer insulating film 13 is processed by dry etching or the like to partially expose the upper surface of the gate electrode 11G in the interlayer insulating film 13. Form a contact hole (gate contact).
  • a titanium (Ti) film, a titanium nitride (TiN) film, and an aluminum film are sequentially deposited from the lower layer on the epitaxial layer EP of the semiconductor substrate 1S to form a laminated film, and then the laminated film is formed.
  • Source electrode 2S is electrically connected to n type source region 8S and a plurality of p + type body contact regions 9BC through source contact SC.
  • the gate electrode 2G is electrically connected to the gate electrode 11G through the gate contact.
  • drain electrode 3D made of metal is formed on the main surface of the substrate layer SB of the semiconductor substrate 1S.
  • an n-type impurity is heavily implanted into the main surface of substrate layer SB prior to the step of forming drain electrode 3D.
  • a silicide layer can be formed in the high concentration impurity implantation region.
  • the semiconductor substrate 1S is divided into individual chips, whereby the chip 1C having the DMOSFET shown in FIG. 1 can be manufactured.
  • FIG. 21 is an enlarged plan view of an essential part of the active region of the semiconductor device of the second embodiment
  • FIG. 22 is a cross-sectional view taken along the line X1-X1 of FIG.
  • thick field insulating film (first insulating film) 10b is partially provided on epitaxial layer EP in a region adjacent to both ends (short sides) in the longitudinal direction of source region 8S.
  • a gate electrode 11G is provided thereon via a gate insulating film 10a.
  • the field insulating film 10b is made of the same silicon oxide film as the gate insulating film 10a, but the thickness of the field insulating film 10b is, for example, in the range of 200 nm to 5 ⁇ m, and the thickness of the gate insulating film 10a (for example, 0. Thicker than 02 ⁇ m to 0.2 ⁇ m).
  • the gate electrode 11G is disposed via the gate insulating film 10a. That is, in the regions adjacent to both ends (long sides) in the width direction of the source region 8S, the voltage of the gate electrode 11G is affected via the thin gate insulating film 10a.
  • the threshold voltage of the channel formed in the portion adjacent to the both ends (short side) in the longitudinal direction of source region 8S of unit cell UC is the both ends in the width direction of source region 8S of unit cell UC. It is higher than the threshold voltage of the channel formed in the portion adjacent to the long side).
  • a part of the field insulating film 10b overlaps with a part of both end portions in the longitudinal direction of the source region 8S in plan view.
  • the short side body region 7B3 is not formed.
  • both end portions in the longitudinal direction (X direction) of the opening 12 of the gate electrode 11G are located outside the both end portions in the longitudinal direction of the source region 8S of the unit cell UC. That is, the gate electrode 11G is formed at a position apart from both end portions in the longitudinal direction of the source region 8S. Moreover, both end portions in the longitudinal direction of the opening 12 of the gate electrode 11G are formed on the laminated film of the field insulating film 10b and the gate insulating film 10a. That is, the part (short side) adjacent to both ends in the longitudinal direction of source region 8S of unit cell UC is affected by the voltage of gate electrode 11G through the stacked film of thick field insulating film 10b and thin gate insulating film 10a. Receive Thus, the influence of the gate voltage can be further reduced in portions (short sides) adjacent to both ends of the source region 8S of the unit cell UC in the longitudinal direction.
  • both ends in the width direction of the opening 12 of the gate electrode 11G are located inside the both ends in the width direction of the source region 8S of the unit cell UC. Therefore, the gate electrode 11G is provided only at the thin gate insulating film 10a in a portion adjacent to the source region 8S in the width direction. That is, portions (long sides) adjacent to both ends in the width direction of the source region 8S of the unit cell UC are affected by the voltage of the gate electrode 11G only via the thin gate insulating film 10a. As a result, the influence of the gate voltage can be further increased in portions (long sides) adjacent to both ends in the width direction of the source region 8S of the unit cell UC.
  • the threshold voltage of the channel formed in the portion adjacent to both ends (short side) in the longitudinal direction of source region 8S is formed in the portion adjacent to both ends (long side) in the width direction of source region 8S. Higher than the threshold voltage of the channel being
  • the field insulating film 10b when the thickness of the field insulating film 10b is sufficiently thick, the field insulating film 10b is not provided at both ends in the longitudinal direction of the opening 12 of the gate electrode 11G, as in the first embodiment.
  • the opening 12 may be formed to be located inside the source region 8S.
  • the thickness of the field insulating film 10 b is sufficiently thick, the following formula (1) is satisfied. tox1 ⁇ ⁇ NA1> tox2 ⁇ ⁇ NA2 (1)
  • NA1 is a concentration of p-type impurities in a portion adjacent to both ends (short side) in the longitudinal direction of source region 8S, and tox1 is formed on a portion adjacent to both ends (short side) in the longitudinal direction of source region 8S
  • the thickness of the insulating film eg, the sum of the thickness of the field insulating film 10 b and the thickness of the gate insulating film 10 a.
  • NA2 is the concentration of p-type impurities in a portion adjacent to both ends (long side) in the width direction of the source region 8S, and tox2 is on a portion adjacent to both ends (long side) in the width direction of the source region 8S. It is the thickness of the formed insulating film (example: thickness of the gate insulating film 10a).
  • field insulating film 10b is formed to extend continuously along the Y direction so as to connect a plurality of unit cells UC.
  • the dimensions of the mask when forming the field insulating film 10b can be increased, so that the field insulating film 10b can be formed more easily.
  • the field insulating film 10b may be formed to cover both longitudinal ends of the source region 8S of each unit cell UC in order to suppress or prevent the above-described leakage current.
  • FIG. 23 is a plan view of relevant parts of a semiconductor substrate showing a modification of the field insulating film. In FIG. 23, the field insulating film 10b is separated for each unit cell UC.
  • the shape and the arrangement of the opening 12 of the gate electrode 11G may be simply as described above without providing the field insulating film 10b. That is, both end portions in the longitudinal direction (X direction) of the opening 12 of the gate electrode 11G are positioned outside the both ends in the longitudinal direction of the source region 8S, and the width direction (Y direction) of the opening 12 of the gate electrode 11G is Both ends may be located inside the both ends in the width direction of the source region 8S.
  • the threshold voltage of a portion adjacent to both ends (short side) in the longitudinal direction of source region 8S is set to a channel formed in the portion adjacent to both ends (long side) in the width direction of source region 8S. It can be higher than the threshold voltage.
  • the same method as that of the first embodiment can be used up to the step of forming the body contact region (step of FIG. 18) (however, the present embodiment).
  • the short side body region 7B3 is not formed). Therefore, the following steps will be described with reference to FIGS. 24 to 26.
  • FIG. 24 is a cross-sectional view of a portion corresponding to the Y1-Y1 line and the X1-X1 line of FIG. 6 in the step of forming the field insulating film constituting the semiconductor device of the second embodiment.
  • the field insulating film 10b is formed on the epitaxial layer EP by the CVD method or the like.
  • a mask MH is formed on the field insulating film 10b.
  • the mask MH is formed to cover the formation region of the field insulating film 10 b and expose the other regions.
  • the material and formation method of the mask MH are the same as the mask MA.
  • field insulating film 10b exposed from mask MH is etched away to expose a part of the surface of epitaxial layer EP. Thereafter, the mask MH is removed.
  • FIG. 25 is a cross-sectional view of a portion corresponding to the Y1-Y1 line and the X1-X1 line of FIG. 6 during the film formation step of the polycrystalline silicon film constituting the semiconductor device of Embodiment 2 after the step of FIG. is there.
  • the gate insulating film 10a and the polycrystalline silicon film 11 are sequentially deposited from the lower layer by the CVD method or the like on the epitaxial layer EP so as to cover the field insulating film 10b. Subsequently, a mask MJ is formed on the polycrystalline silicon film 11. The mask MJ is formed to cover the formation region of the gate electrode and to expose the other. The material and formation method of the mask MJ are the same as the mask MA.
  • FIG. 26 is a cross-sectional view of a portion corresponding to the Y1-Y1 line and the X1-X1 line of FIG. 6 after the source contact forming step of the semiconductor device of the second embodiment after the step of FIG.
  • the polycrystalline silicon film 11 is processed by dry etching to form the gate electrode 11G, and after the opening 12 is formed, the mask MJ is removed. Do.
  • an interlayer insulating film 13 is formed by, eg, plasma CVD to cover the gate electrode 11G and the gate insulating film 10a, and then a mask (not shown) is formed on the interlayer insulating film 13. Form).
  • a mask (not shown) is formed on the interlayer insulating film 13.
  • interlayer insulating film 13 and gate insulating film 10a are processed by dry etching to form part of the surface of n-type source region 8S and the surface of p + -type body contact region 9BC.
  • An exposed source contact SC is formed.
  • another mask is formed on the interlayer insulating film 13, and this is used as an etching mask to form a gate contact in the interlayer insulating film 13 in which a part of the gate electrode 11G is exposed.
  • FIG. 27 is an enlarged plan view of an essential part of the active region of the semiconductor device according to the third embodiment
  • FIG. 28 is a cross-sectional view taken along line X1-X1 of FIG.
  • the short side body is provided in portions adjacent to both end portions of the source region 8S of the unit cell UC in the longitudinal direction. Region 7B3 is formed.
  • the concentration of the p-type impurity contained in the short side body region 7B3 may not be sufficiently high due to reasons such as the manufacturing process.
  • the thickness of the field insulating film 10b may not be sufficiently thick.
  • the threshold voltage of a portion adjacent to both ends (short side) of source region 8S of unit cell UC is the threshold voltage of a portion adjacent to both ends (long side) of source region 8S in the width direction. Sometimes it can not be higher than the voltage.
  • the threshold voltage of the portion (short side) adjacent to both ends of the source region 8S of the unit cell UC. can be set higher than the threshold voltage of the portion (long side) adjacent to both ends in the width direction of the source region 8S.
  • both end portions in the longitudinal direction of the opening 12 of the gate electrode 11G are located outside the both end portions in the longitudinal direction of the source region 8S. Then, gate electrodes 11G located on both end sides in the longitudinal direction of the source region 8S are formed on the laminated film of the thick field insulating film 10b and the gate insulating film 10a. As a result, the influence of the gate voltage can be further reduced in portions (short sides) adjacent to both ends of the source region 8S of the unit cell UC in the longitudinal direction.
  • both end portions in the width direction of the opening 12 of the gate electrode 11G are located inside the both end portions in the width direction of the source region 8S. Then, gate electrodes 11G located on both end sides in the width direction of the source region 8S are formed on the thin gate insulating film 10a. As a result, the influence of the gate voltage can be further increased in portions (long sides) adjacent to both ends in the width direction of the source region 8S of the unit cell UC.
  • the threshold voltage of the channel (short side) adjacent to both ends in the longitudinal direction of source region 8S of unit cell UC is the portion adjacent to both ends in the width direction of source region 8S of unit cell UC. It can be made higher than the threshold voltage of the (long side) channel.
  • both end portions in the longitudinal direction of the opening 12 of the gate electrode 11G are not provided with the field insulating film 10b.
  • the opening 12 may be formed to be located in the area of 8S.
  • the process of forming the short side body region 7B3 is the same as that of the first embodiment. Further, since the step of forming field insulating film 10b is the same as that of the second embodiment, the example of the method of manufacturing the semiconductor device of the third embodiment is omitted.
  • the present invention is not limited to the above-described embodiment, but includes various modifications.
  • the above-described embodiment has been described in detail in order to explain the invention in an easy-to-understand manner, and is not necessarily limited to one having all the described configurations.
  • part of the configuration of one embodiment can be replaced with the configuration of another embodiment.
  • the functions of the “source” and the “drain” of the transistor may be switched when adopting transistors of different polarities, when the direction of current changes in circuit operation, or the like. Therefore, in the present specification, the terms “source” and “drain” can be used interchangeably.
  • electrode and “wiring” do not functionally limit these components.
  • electrodes may be used as part of “wirings” and vice versa.
  • the terms “electrode” and “wiring” include the case where a plurality of “electrodes” and “wirings” are integrally formed.
  • DMOSFET was illustrated as a switching transistor, it is not limited to this, For example, you may use IGBT (Insulated Gate Bipolar Transistor). Further, for example, the present invention can be applied to an inverter having a switching transistor such as a DMOSFET or an IGBT. Further, for example, the present invention can be applied to a power module having a switching transistor such as a DMOSFET or an IGBT.
  • IGBT Insulated Gate Bipolar Transistor

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Abstract

According to the present invention, the reliability of a semiconductor device is improved. A p-type short side body region 7B3 is formed in a portion adjacent to both end portions in the longitudinal direction of a source region 8S of a unit cell UC of a power semiconductor device so as to cover side portions of both end portions in the longitudinal direction of the source region 8S. Then, the impurity concentration of the p-type short side body region 7B3 is made to be higher than the impurity concentration of a p-type long side body region 7B2. As a result, the threshold voltage of a portion (the p-type short side body region 7B3) adjacent to both end portions in the longitudinal direction of the source region 8S of the unit cell UC of the power semiconductor device is higher than the threshold voltage of a portion (the p-type long side body region 7B2) adjacent to both end portions in the width direction of the source region 8S.

Description

半導体装置およびその製造方法Semiconductor device and method of manufacturing the same
　本発明は、半導体装置およびその製造技術に関し、例えば、パワー半導体装置およびその製造方法に適用して有効な技術に関する。 The present invention relates to a semiconductor device and its manufacturing technology, for example, to a technology effectively applicable to a power semiconductor device and its manufacturing method.
　本技術分野の背景技術として、特開２００４－３９７４４号公報（特許文献１）がある。この公報には、テーパエッチングによりパターン側壁に傾斜が形成されたマスク材を介して、ＳｉＣ基板の法線を軸としてＳｉＣ基板を回転させながら、ＳｉＣ基板の法線方向に対して傾斜させて不純物をイオン注入し、低濃度ベース領域および高濃度ベース領域を形成する技術が記載されている。 As background art of the present technical field, there is JP-A-2004-39744 (Patent Document 1). In this publication, the SiC substrate is inclined relative to the normal direction of the SiC substrate while rotating the SiC substrate around the normal of the SiC substrate through the mask material whose inclination is formed on the pattern sidewall by taper etching. Techniques for implanting low concentration base regions and high concentration base regions are described.
特開２００４－３９７４４号公報JP 2004-39744 A
　ところで、前記特許文献１には、縦型ＭＯＳＦＥＴのソース領域とチャネル領域とを同一のマスクで自己整合的に形成する技術が記載されている。また、特許文献１には、縦型ＭＯＳＦＥＴのストライプ型のセルが例示されている。ストライプ型のセル（ソース領域）は、その平面視での形状が、一方向の長さが、その一方向に直交する他方向の長さよりも長い帯状に形成されている。 Patent Document 1 describes a technique for forming the source region and the channel region of the vertical MOSFET in a self-aligned manner using the same mask. Further, Patent Document 1 exemplifies a stripe type cell of a vertical MOSFET. The stripe type cell (source region) is formed in a strip shape whose length in one direction is longer than the length in the other direction orthogonal to the one direction in the shape in plan view.
　しかし、特許文献１では、ストライプ型のセル（ソース領域）の長手方向の両端部に隣接する部分には、ソース領域に対して逆の導電型の不純物が必ずしも充分に注入されない。このため、ストライプ型のセル（ソース領域）の長手方向の両端部に隣接する部分のしきい値電圧が、ストライプ型のセル（ソース領域）の幅方向（短方向）の両端部に隣接する部分のしきい値電圧とほぼ同じか、または、低くなる。その結果、ストライプ型のセルの長手方向の両端部でリーク電流が生じ、半導体装置の信頼性が低下する課題がある。
　本発明の目的は、半導体装置の信頼性を向上させることが可能な技術を提供することにある。 However, in Patent Document 1, an impurity of the opposite conductivity type to the source region is not necessarily sufficiently injected into portions adjacent to both end portions in the longitudinal direction of the stripe type cell (source region). Therefore, the threshold voltage of a portion adjacent to both ends in the longitudinal direction of the stripe type cell (source region) is a portion adjacent to both ends in the width direction (short direction) of the stripe type cell (source region) Approximately equal to or lower than the threshold voltage of As a result, a leak current is generated at both ends in the longitudinal direction of the stripe type cell, and there is a problem that the reliability of the semiconductor device is lowered.
An object of the present invention is to provide a technology capable of improving the reliability of a semiconductor device.
　上記課題を解決するために、本発明は、半導体基板の第１面に、平面視で第１方向の長さが第１方向に交差する第２方向の長さより長く、かつ、断面視で第１面から半導体基板の深さ方向に延びる第１導電型の第１半導体領域を設けた。また、少なくとも第１半導体領域の第２方向の両端部に隣接する部分上に絶縁膜を介してゲート電極を設けた。そして、平面視で第１半導体領域の第１方向の両端部に隣接する部分のしいき値電圧を、第１半導体領域の第２方向の両端部に隣接する部分のしきい値電圧より高くした。 In order to solve the above problems, according to the present invention, the length of the first direction in plan view is longer than the length in the second direction intersecting with the first direction on the first surface of the semiconductor substrate, and A first semiconductor region of a first conductivity type is provided which extends from one surface in the depth direction of the semiconductor substrate. Further, a gate electrode is provided on portions adjacent to both end portions of at least the first semiconductor region in the second direction via an insulating film. Then, the threshold voltage of a portion adjacent to both ends of the first semiconductor region in the first direction in plan view is made higher than the threshold voltage of a portion adjacent to both ends of the first semiconductor region in the second direction. .
　本発明によれば、半導体装置の信頼性を向上させることができる。
　上記した以外の課題、構成及び効果は、以下の実施の形態の説明により明らかにされる。 According to the present invention, the reliability of the semiconductor device can be improved.
Problems, configurations, and effects other than those described above will be apparent from the description of the embodiments below.
本発明者が検討したパワー半導体装置の単位セルの平面図である。It is a top view of the unit cell of the power semiconductor device which this inventor examined. 図１のＸ１０－Ｘ１０線の断面図である。FIG. 2 is a cross-sectional view taken along line X10-X10 of FIG. 実施の形態１の半導体装置を構成する半導体チップの一例の平面図である。FIG. 1 is a plan view of an example of a semiconductor chip constituting a semiconductor device of a first embodiment. 図３の破線で囲んだ領域Ａ１の一例の拡大平面図である。It is an enlarged plan view of an example of field A1 enclosed with a dashed line of FIG. 図３の破線で囲んだ領域Ａ２の多結晶シリコンからなるゲート電極の一例の拡大平面図である。FIG. 4 is an enlarged plan view of an example of a gate electrode made of polycrystalline silicon in a region A2 surrounded by a broken line in FIG. 3. 図３の破線で囲んだ領域Ａ２の活性領域の一例の拡大平面図である。FIG. 5 is an enlarged plan view of an example of an active region of a region A2 surrounded by a dashed line in FIG. 3; 図６のＸ１－Ｘ１線およびＹ１－Ｙ１線の断面図である。FIG. 7 is a cross-sectional view taken along line X1-X1 and line Y1-Y1 of FIG. 6; 短辺側ボディ領域の変形例を示す半導体基板の要部平面図である。It is a principal part top view of the semiconductor substrate which shows the modification of a short side body field. 図６のＹ１－Ｙ１線の断面図である。FIG. 7 is a cross-sectional view taken along line Y1-Y1 of FIG. 6; 実施の形態１の半導体装置を構成する埋込ボディ領域の形成工程時の図６のＹ１－Ｙ１線およびＸ１－Ｘ１線に相当する箇所の断面図である。FIG. 7 is a cross-sectional view of a portion corresponding to the Y1-Y1 line and the X1-X1 line of FIG. 6 in the step of forming the embedded body region that configures the semiconductor device of the first embodiment. 実施の形態１の半導体装置を構成するソース領域の形成工程時の図６のＹ１－Ｙ１線およびＸ１－Ｘ１線に相当する箇所の断面図である。FIG. 7 is a cross-sectional view of a portion corresponding to the Y1-Y1 line and the X1-X1 line of FIG. 6 in the process of forming the source region that configures the semiconductor device of the first embodiment; 左右は実施の形態１の半導体装置を構成する長辺側ボディ領域の形成工程時の図６のＹ１－Ｙ１線に相当する箇所の断面図である。Left and right are cross-sectional views of a portion corresponding to the Y1-Y1 line of FIG. 6 at the time of the step of forming the long side body region that constitutes the semiconductor device of the first embodiment. 長辺側ボディ領域の形成工程後の半導体基板の活性領域の要部平面図である。It is a principal part top view of an active field of a semiconductor substrate after a formation process of a long side body field. 左は図１３のＹ１－Ｙ１線の断面図、右は図１３のＸ１－Ｘ１線の断面図である。The left is a cross-sectional view taken along line Y1-Y1 of FIG. 13, and the right is a cross-sectional view taken along line X1-X1 of FIG. 左右は実施の形態１の半導体装置を構成するボディコンタクト領域の形成工程時図６のＹ１－Ｙ１線およびＸ１－Ｘ１線に相当する箇所の断面図である。Left and right are cross-sectional views of portions corresponding to the Y1-Y1 line and the X1-X1 line of FIG. 6 during the process of forming the body contact region constituting the semiconductor device of the first embodiment. 左右は実施の形態１の半導体装置を構成する短辺側ボディ領域の形成工程時の図６のＹ１－Ｙ１線およびＸ１－Ｘ１線に相当する箇所の断面図である。Left and right are cross-sectional views of portions corresponding to the Y1-Y1 line and the X1-X1 line of FIG. 6 in the process of forming the short side body region constituting the semiconductor device of the first embodiment. 実施の形態１の半導体装置を構成するボディコンタクト領域および短辺側ボディ領域の形成工程の変形例を示す図６のＹ１－Ｙ１線およびＸ１－Ｘ１線に相当する箇所の断面図である。FIG. 7 is a cross-sectional view of a portion corresponding to the Y1-Y1 line and the X1-X1 line of FIG. 6 showing a modification of the process of forming the body contact region and the short side body region constituting the semiconductor device of the first embodiment; ボディコンタクト領域および短辺側ボディ領域の形成工程後の半導体基板の活性領域の要部平面図である。It is a principal part top view of the active field of a semiconductor substrate after the formation process of a body contact field and a short side body field. 実施の形態１の半導体装置を構成するゲート電極の形成工程時の図６のＹ１－Ｙ１線およびＸ１－Ｘ１線に相当する箇所の断面図である。FIG. 7 is a cross-sectional view of a portion corresponding to the Y1-Y1 line and the X1-X1 line of FIG. 6 in the step of forming the gate electrode constituting the semiconductor device of Embodiment 1; 図１９の工程後の半導体装置の製造工程時の図６のＹ１－Ｙ１線およびＸ１－Ｘ１線に相当する箇所の断面図である。FIG. 20 is a cross-sectional view of a portion corresponding to the Y1-Y1 line and the X1-X1 line of FIG. 6 in the manufacturing process of the semiconductor device after the process of FIG. 19; 実施の形態２の半導体装置の活性領域の要部拡大平面図である。FIG. 16 is an enlarged plan view of a main part of an active region of the semiconductor device of Second Embodiment; 図２１のＸ１－Ｘ１線の断面図である。FIG. 22 is a cross-sectional view taken along line X1-X1 of FIG. フィールド絶縁膜の変形例を示す半導体基板の要部平面図である。It is a principal part top view of the semiconductor substrate which shows the modification of field insulating film. 実施の形態２の半導体装置を構成するフィールド絶縁膜の形成工程時の図６のＹ１－Ｙ１線およびＸ１－Ｘ１線に相当する箇所の断面図である。FIG. 17 is a cross-sectional view of a portion corresponding to the Y1-Y1 line and the X1-X1 line of FIG. 6 in the step of forming the field insulating film that configures the semiconductor device of Second Embodiment; 図２４の工程後の実施の形態２の半導体装置を構成する多結晶シリコン膜の成膜工程時の図６のＹ１－Ｙ１線およびＸ１－Ｘ１線に相当する箇所の断面図である。FIG. 25 is a cross-sectional view of a portion corresponding to the Y1-Y1 line and the X1-X1 line of FIG. 6 in the film formation step of the polycrystalline silicon film constituting the semiconductor device of Embodiment 2 after the step of FIG. 24; 図２５の工程後の実施の形態２の半導体装置を構成するソースコンタクト形成工程後の図６のＹ１－Ｙ１線およびＸ１－Ｘ１線に相当する箇所の断面図である。FIG. 26 is a cross-sectional view of a portion corresponding to the Y1-Y1 line and the X1-X1 line of FIG. 6 after the source contact forming step of the semiconductor device of the second embodiment after the step of FIG. 25; 実施の形態３の半導体装置の活性領域の要部拡大平面図である。FIG. 16 is an enlarged plan view of a main part of an active region of the semiconductor device of the third embodiment. 図２７のＸ１－Ｘ１線の断面図である。FIG. 28 is a cross-sectional view taken along line X1-X1 of FIG.
　以下、実施の形態について図面を用いて説明する。ただし、本発明は以下に示す実施の形態の記載内容に限定して解釈されるものではない。本発明の思想ないし趣旨から逸脱しない範囲で、その具体的構成を変更し得ることは当業者であれば容易に理解される。 Hereinafter, embodiments will be described with reference to the drawings. However, the present invention should not be construed as being limited to the description of the embodiments below. Those skilled in the art can easily understand that the specific configuration can be changed without departing from the spirit or the spirit of the present invention.
　以下に説明する発明の構成において、異なる図面間であっても、同一部分又は同様な機能を有する部分には同一の符号を共通して用い、重複する説明は省略することがある。また、本明細書等における「第１」、「第２」、「第３」などの表記は、構成要素を識別するために付するものであり、必ずしも、数または順序を限定するものではない。 In the structures of the invention described below, the same portions or portions having similar functions may be denoted by the same reference numerals even in different drawings, and overlapping descriptions may be omitted. In addition, the notations such as "first", "second", "third" and the like in the present specification and the like are used to identify components, and are not necessarily limited in number or order. .
　また、図面等において示す各構成の位置、大きさ、形状、範囲などは、発明の理解を容易にするため、実際の位置、大きさ、形状、範囲などを表していない場合がある。このため、本発明は、必ずしも、図面等に開示された位置、大きさ、形状、範囲などに限定されない。 Further, the positions, sizes, shapes, ranges, and the like of the respective components shown in the drawings and the like may not represent actual positions, sizes, shapes, ranges, and the like in order to facilitate understanding of the invention. For this reason, the present invention is not necessarily limited to the position, size, shape, range, etc. disclosed in the drawings and the like.
　本明細書において単数形で表される構成要素は、特段文脈で明らかに示されない限り、複数形を含むものとする。
　＜発明者の検討＞ DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Components which are referred to in the singular will be understood to include the plural unless the context clearly dictates otherwise.
<Investigator's examination>
　近年，エネルギーの有効利用を促進するパワーエレクトロニクスが注目されている。パワーエレクトロニクス機器は，電力の変換や制御を担っており、そのキーとなるパワー半導体装置の性能向上が求められている。 In recent years, power electronics that promote effective use of energy are attracting attention. Power electronics devices are responsible for the conversion and control of power, and there is a need to improve the performance of the key power semiconductor devices.
　パワー半導体装置の基板としては、古くからシリコン（Ｓｉ）基板が用いられてきたが、Ｓｉ系パワー半導体装置の低損失化や性能向上が図られてきた結果、そのデバイス性能がＳｉの材料物性で決まる理論限界に近づきつつあり、今後の更なる性能向上が困難な状況になりつつある。 A silicon (Si) substrate has long been used as a substrate for power semiconductor devices, but as a result of achieving lower loss and improved performance of Si-based power semiconductor devices, the device performance is based on the material properties of Si. It is approaching the theoretical limit to be determined, and it is becoming difficult to further improve performance in the future.
　このような状況の中で、炭化シリコン（ＳｉＣ）や窒化ガリウム（ＧａＮ）等のようなワイドギャップ半導体を用いた低損失パワー半導体装置が盛んに研究されている。ＳｉＣやＧａＮは、Ｓｉと比較して絶縁破壊電界強度が約１桁大きく、ドリフト層を薄くできる。このため、ワイドギャップ半導体を用いたパワー半導体装置は、Ｓｉ系パワー半導体装置と比較して、オン抵抗の低抵抗化、すなわち、低損失化が可能である。 Under such circumstances, low loss power semiconductor devices using wide gap semiconductors such as silicon carbide (SiC) and gallium nitride (GaN) have been actively studied. SiC and GaN have a breakdown electric field strength about one digit larger than that of Si and can make the drift layer thinner. Therefore, in the power semiconductor device using the wide gap semiconductor, the on-resistance can be reduced, that is, the loss can be reduced, as compared with the Si-based power semiconductor device.
　ところで、ＳｉＣ基板を用いたパワーＭＯＳＦＥＴ（Metal Oxide Semiconductor Field Effect Transistor）の製造においては、ｎ型のソース領域およびｐ型のボディ領域等を選択的なイオン注入によって形成している。この不純物イオン注入に際しては、通常、ｎ型のソース領域およびｐ型のボディ領域のそれぞれに対してリソグラフィを行ない、別々のマスクを用いて不純物を注入している。この場合、２回のリソグラフィ工程の各々のマスクの重ね合せが難しく、ステッパを用いた場合、典型的には０．１～０．３μｍ程度の合せずれが生じる。また、露光量や温度の小さな変化によって、現像後に形成されるレジストマスクの寸法がシフトすることもある。チャネル長は通例１μｍ未満であるので、重ね合せずれや寸法シフトによって生じるデバイス性能の変化やばらつきが無視できない。 Incidentally, in the manufacture of a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) using a SiC substrate, an n-type source region, a p-type body region and the like are formed by selective ion implantation. In this impurity ion implantation, usually, lithography is performed on each of the n-type source region and the p-type body region, and impurities are implanted using different masks. In this case, it is difficult to align the masks of each of the two lithography steps, and when using a stepper, misalignment of about 0.1 to 0.3 μm typically occurs. In addition, small changes in exposure dose and temperature may shift the dimensions of the resist mask formed after development. Since the channel length is usually less than 1 μm, changes and variations in device performance caused by misalignment and dimensional shifts can not be ignored.
　また、低いオン抵抗を得るためにはチャネル長を短くするほうが好ましいが、短くなりすぎるとパンチスルーが発生してしまい、所定の耐圧を保持できない。したがって、合せずれによってチャネル長が短くなったとしても、パンチスルーが発生しないように充分なマージンを持ってチャネル長の中心値を設計しておくことが必要であるが、それはオン抵抗やスイッチング損失の増大に繋がる。 Further, in order to obtain a low on-resistance, it is preferable to shorten the channel length, but if it is too short, punch-through occurs and a predetermined breakdown voltage can not be maintained. Therefore, even if the channel length is shortened due to misalignment, it is necessary to design the center value of the channel length with a sufficient margin so that punch-through does not occur, but this is because the on-resistance and switching loss Leading to an increase in
　そこで、上述の重ね合せずれの問題に対して、１回のリソグラフィ工程でソース領域とボディ領域とを形成する、いわゆる自己整合プロセスが提案されている。自己整合プロセスによれば、上記２回の露光により生じる合せずれや寸法シフトの影響を受けずにチャネル長を規定でき、短チャネル、低オン抵抗のパワーＭＯＳＦＥＴを、ばらつき無く製造することができる。 Therefore, in order to solve the above-mentioned misalignment, a so-called self-alignment process has been proposed in which a source region and a body region are formed in one lithography process. According to the self-alignment process, the channel length can be defined without being affected by misalignment or dimensional shift caused by the two exposures, and a short channel, low on-resistance power MOSFET can be manufactured without variation.
　自己整合プロセスの一例として、特許文献１には、縦型ＭＯＳＦＥＴの製造方法において、ソース領域とチャネル領域とを同一のマスクを用いてイオン注入する方法が開示されている。この特許文献１の方法によれば、マスクを形成した基板に対して、基板表面の法線方向からソース領域のＮ型不純物の注入を行ない、さらに、基板法線方向に対して傾斜した角度でＰ型不純物の注入を行なうことでマスクの下にチャネルを形成している。また、特許文献１には、ストライプ状のセルを横切るように斜め方向から２回のイオン注入を行なう方法が開示されている。 As an example of a self-aligned process, Patent Document 1 discloses a method of manufacturing a vertical MOSFET by implanting ions of a source region and a channel region using the same mask. According to the method of Patent Document 1, the n-type impurity of the source region is implanted from the normal direction of the substrate surface to the substrate on which the mask is formed, and further, at an angle inclined to the normal direction of the substrate. A channel is formed under the mask by implanting P-type impurities. Further, Patent Document 1 discloses a method in which ion implantation is performed twice in a diagonal direction so as to cross a stripe-like cell.
　しかし、本発明者が特許文献１について検討したところ、製造したＭＯＳＦＥＴに問題があることが明らかになった。すなわち、特許文献１の方法では、ストライプ状の単位セルを構成するＮ型のソース領域の長手方向の両端部に隣接する部分には、Ｐ型不純物が必ずしも十分に注入されない。そのため、そのソース領域の幅方向（短方向）の両端部（長辺）に隣接する部分のしきい値電圧よりも、そのソース領域の長手方向の両端部（短辺）に隣接する部分のしきい値電圧の方が低くなる。通常は、Ｎ型のソース領域の幅方向の両端部（長辺）に隣接する部分に形成されるチャネルを流れる電流が導通の主成分となる。一方、Ｎ型のソース領域の長手方向の両端部（短辺）に隣接する部分に形成されるチャネルを流れる電流はリーク電流とされる。そして、このリーク電流が多い素子は不良品とされる。 However, when the inventor examined Patent Document 1, it became clear that the manufactured MOSFET had a problem. That is, in the method of Patent Document 1, P-type impurities are not sufficiently implanted into portions adjacent to both end portions in the longitudinal direction of the N-type source region constituting the stripe-shaped unit cell. Therefore, the threshold voltage of the portion adjacent to the both ends (long side) in the width direction (short direction) of the source region is the portion adjacent to the both ends (short side) in the longitudinal direction of the source region. The threshold voltage is lower. In general, a current flowing through a channel formed in a portion adjacent to both ends (long sides) in the width direction of the N-type source region is the main component of conduction. On the other hand, the current flowing through the channel formed in the portion adjacent to both ends (short sides) in the longitudinal direction of the N-type source region is taken as a leak current. Then, the element having a large leak current is regarded as a defective product.
　また、特許文献１には、基板を９０度回転させた方向からさらに２回のイオン注入を追加する方法や、基板を回転させながらイオン注入する方法が開示されている。ここで、図１は本発明者が検討したパワー半導体装置の単位セルの平面図、図２は図１のＸ１０－Ｘ１０線の断面図である。図１には平面視で帯状に形成された２個の単位セル１００が例示されている。特許文献１に記載の上記イオン注入を行った場合、単位セル１００のＮ型のソース領域１０１の外周を取り囲むようにＰ型のボディ領域１０２が形成される。このため、Ｎ型のソース領域１０１の長手方向の両端部（短辺）に隣接する部分のしきい値電圧と、Ｎ型のソース領域１０１の幅方向の両端部（長辺）に隣接する部分のしきい値電圧とをほぼ同じにすることができる。 Further, Patent Document 1 discloses a method of adding ion implantation twice more from the direction in which the substrate is rotated 90 degrees, and a method of implanting ions while rotating the substrate. Here, FIG. 1 is a plan view of a unit cell of a power semiconductor device examined by the present inventor, and FIG. 2 is a cross-sectional view taken along line X10-X10 of FIG. FIG. 1 illustrates two unit cells 100 formed in a strip shape in plan view. When the ion implantation described in Patent Document 1 is performed, a P-type body region 102 is formed to surround the outer periphery of the N-type source region 101 of the unit cell 100. Therefore, the threshold voltage of a portion adjacent to both ends (short side) in the longitudinal direction of N-type source region 101 and the portion adjacent to both ends (long side) in the width direction of N-type source region 101 And the threshold voltage of the
　しかし、特許文献１では、単位セル１００（Ｎ型のソース領域１０１）の長手方向の両端部からリーク電流ＩＬが流れる課題について示唆も開示もされていない。その上、特許文献１では、パワー半導体装置の高速スイッチングを達成する観点等からＮ型のソース領域の幅方向の両端部（短辺）に隣接する部分のしきい値電圧を低く設定しているので、Ｎ型のソース領域の長手方向の両端部（短辺）に隣接する部分のしきい値電圧も低くなる。したがって、たとえ上記のようなイオン注入を行っても、図１に示すように、パワーＭＯＳＦＥＴの動作時に単位セル１００の幅方向の両端部（長辺）に隣接する部分に形成されるチャネルを通じて正規の電流が流れる際に、単位セル１００の長手方向の両端部（短辺）から意図しないリーク電流ＩＬが流れてしまう。その結果、パワー半導体装置の信頼性が低下するという課題がある。しかも特許文献１の場合、２回の追加注入を行なうので、チャネルのイオン注入に２倍の時間がかかり、生産性が低下する。また、基板を回転させながら注入する方法も同様に製造時間を要する上、イオン注入装置の構成が複雑となるという問題もある。つまり、これらの方法は、略正方形状の単位セルをアレイ状に配置する場合には有効であるが、ストライプ型の単位セルに対しては問題がある。
　（実施の形態１）
　＜半導体装置の構成例＞ However, Patent Document 1 neither suggests nor discloses the problem of the leak current IL flowing from both end portions in the longitudinal direction of the unit cell 100 (N-type source region 101). Moreover, in Patent Document 1, the threshold voltage of the portion adjacent to both ends (short side) in the width direction of the N-type source region is set low from the viewpoint of achieving high-speed switching of the power semiconductor device. Therefore, the threshold voltage of the portion adjacent to both ends (short sides) in the longitudinal direction of the N-type source region is also lowered. Therefore, even if ion implantation as described above is performed, as shown in FIG. 1, normal operation is performed through the channels formed in the portions adjacent to both ends (long sides) in the width direction of unit cell 100 during operation of the power MOSFET. When the current flows, an unintended leakage current IL flows from both ends (short sides) in the longitudinal direction of the unit cell 100. As a result, there is a problem that the reliability of the power semiconductor device is reduced. Moreover, in the case of Patent Document 1, since two additional implantations are performed, it takes twice as much time for channel ion implantation, and the productivity is lowered. In addition, the method of implanting while rotating the substrate also requires a manufacturing time, and also has a problem that the configuration of the ion implantation apparatus becomes complicated. That is, although these methods are effective when arranging substantially square unit cells in an array, there is a problem with stripe type unit cells.
Embodiment 1
<Configuration Example of Semiconductor Device>
　本実施の形態１の半導体装置の構成例について図３～図８を参照して説明する。なお、本願明細書において平面視とは、半導体基板の主面に垂直な方向から視た場合を意味する。また、図中の矢印Ｘ，Ｙは、平面視において互いに交差（好ましくは直交）する２つの方向を示している。 A configuration example of the semiconductor device of the first embodiment will be described with reference to FIG. 3 to FIG. In the specification of the present application, the term “plan view” means the case of viewing from the direction perpendicular to the main surface of the semiconductor substrate. Further, arrows X and Y in the drawing indicate two directions intersecting (preferably orthogonal) with each other in plan view.
　本実施の形態１の半導体装置は、例えば、ｎチャネル型の縦型２重拡散ＭＯＳＦＥＴ(Double diffused MOSFET：以下、ＤＭＯＳＦＥＴと略す）を有するスイッチングデバイス（パワー半導体装置）である。図３は本実施の形態１の半導体装置を構成する半導体チップの一例の平面図である。なお、図１の領域Ａ１，Ａ２は、実際に形成されているものではないが、説明上、図示している。 The semiconductor device according to the first embodiment is, for example, a switching device (power semiconductor device) having an n-channel vertical double diffused MOSFET (hereinafter, abbreviated as DMOSFET). FIG. 3 is a plan view of an example of a semiconductor chip constituting the semiconductor device of the first embodiment. Although the areas A1 and A2 in FIG. 1 are not actually formed, they are illustrated for the sake of explanation.
　半導体チップ（以下、単にチップという）１Ｃは、例えば、平面視で略四角形状に形成されている。このチップ１Ｃの主面内において、外周縁部には終端領域（いわゆるガードリング領域）ＧＡが設けられている。終端領域ＧＡは、例えば、ｐ型（第２導電型）の半導体領域で形成されており、電界緩和機能等を有している。この終端領域ＧＡには、例えば、アルミニウム（Ａｌ）またはホウ素（Ｂ）等のようなｐ型不純物が導入されている。 The semiconductor chip (hereinafter simply referred to as a chip) 1C is formed in, for example, a substantially square shape in a plan view. A termination region (a so-called guard ring region) GA is provided in the outer peripheral edge portion in the main surface of the chip 1C. The termination region GA is formed of, for example, a p-type (second conductivity type) semiconductor region, and has an electric field relaxation function and the like. In the termination area GA, for example, a p-type impurity such as aluminum (Al) or boron (B) is introduced.
　チップ１Ｃの主面内において、終端領域ＧＡより内側には、ＤＭＯＳＦＥＴ（スイッチングトランジスタ）のソース電極２Ｓおよびゲート電極２Ｇが互いに絶縁された状態で設けられている。ソース電極２Ｓおよびゲート電極２Ｇは、例えば、チタン（Ｔｉ）膜と、窒化チタン（ＴｉＮ）膜と、アルミニウム膜（Ａｌ）とを下層から順に積層することで形成されている。このソース電極２Ｓおよびゲート電極２Ｇは、チップ１Ｃの主面上の表面保護膜（図示せず）によって覆われているが、表面保護膜の一部に形成された開口部を通じてソース電極２Ｓおよびゲート電極２Ｇの一部が露出されている。その表面保護膜に形成された開口部から露出するソース電極２Ｓおよびゲート電極２Ｇの一部がソースパッドおよびゲートパッドになっている。なお、ソース電極２Ｓおよびゲート電極２Ｇの下層には、後述の多結晶シリコンからなるゲート電極が形成されている。 In the main surface of the chip 1C, inside the termination area GA, the source electrode 2S and the gate electrode 2G of the DMOSFET (switching transistor) are provided in a mutually insulated state. The source electrode 2S and the gate electrode 2G are formed, for example, by sequentially stacking a titanium (Ti) film, a titanium nitride (TiN) film, and an aluminum film (Al) from the lower layer. Although the source electrode 2S and the gate electrode 2G are covered with a surface protection film (not shown) on the main surface of the chip 1C, the source electrode 2S and the gate are formed through an opening formed in part of the surface protection film. A part of the electrode 2G is exposed. A part of the source electrode 2S and the gate electrode 2G exposed from the opening formed in the surface protective film is a source pad and a gate pad. Under the source electrode 2S and the gate electrode 2G, a gate electrode made of polycrystalline silicon described later is formed.
　図４は図３の破線で囲んだ領域Ａ１の一例の拡大平面図である。なお、図４では、ソース電極２Ｓ、ゲート電極２Ｇおよびその下層のゲート電極を取り除いた状態を示している。 FIG. 4 is an enlarged plan view of an example of a region A1 surrounded by a broken line in FIG. Note that FIG. 4 shows a state in which the source electrode 2S, the gate electrode 2G, and the gate electrode in the lower layer thereof are removed.
　チップ１Ｃの主面内において終端領域ＧＡより内側には、アクティブ領域ＡＣＡが配置されている。このアクティブ領域ＡＣＡには、例えば、ＤＭＯＳＦＥＴを構成するストライプ型の単位セルＵＣが配置されている。すなわち、アクティブ領域ＡＣＡには、平面視でＸ方向（第１方向）の寸法がＹ方向（第２方向）の寸法より長い帯状の複数の単位セルＵＣが、Ｙ方向に沿って所定の間隔毎に配置されている。 An active area ACA is disposed inside the termination area GA in the main surface of the chip 1C. In the active area ACA, for example, stripe-type unit cells UC constituting a DMOSFET are arranged. That is, in the active area ACA, a plurality of strip-like unit cells UC in which the dimension in the X direction (first direction) in plan view is longer than the dimension in the Y direction (second direction) have predetermined intervals along the Y direction. Is located in
　この複数の単位セルＵＣは、電気的に並列に接続されている。この単位セルＵＣを並列に接続した数（すなわち、アクティブ領域ＡＣＡ内に敷き詰められた単位セルＵＣの数）を多くし、アクティブ領域ＡＣＡに配置されるチャネルの幅を長くすることで、チップ１Ｃの全体のＤＭＯＳＦＥＴの抵抗を下げることができる。 The plurality of unit cells UC are electrically connected in parallel. By increasing the number of unit cells UC connected in parallel (that is, the number of unit cells UC embedded in the active area ACA) and increasing the width of the channels arranged in the active area ACA, the chip 1C The resistance of the entire DMOSFET can be reduced.
　また、アクティブ領域ＡＣＡ内において、各単位セルＵＣの長手方向（Ｘ方向）の両端部と終端領域ＧＡの内周との間にフィールド領域ＦＡが配置されている。すなわち、各単位セルＵＣの長手方向の両端部は終端領域ＧＡの内周から離れている。 Further, in the active area ACA, the field area FA is disposed between both ends of the unit cell UC in the longitudinal direction (X direction) and the inner periphery of the termination area GA. That is, both ends in the longitudinal direction of each unit cell UC are separated from the inner periphery of the termination area GA.
　図５は図３の破線で囲んだ領域Ａ２の多結晶シリコンからなるゲート電極の一例の拡大平面図、図６は図３の破線で囲んだ領域Ａ２の活性領域の一例の拡大平面図、図７は図６のＸ１－Ｘ１線およびＹ１－Ｙ１線の断面図である。なお、図５はチップ１Ｃのソース電極２Ｓを取り除いた状態を示し、図６は図５の多結晶シリコンからなるゲート電極層を取り除いた状態を示している。また、図７の矢印Ｚはチップ１Ｃの主面に交差（好ましくは直交）する方向を示している。 5 is an enlarged plan view of an example of a gate electrode made of polycrystalline silicon in a region A2 surrounded by a broken line in FIG. 3, FIG. 6 is an enlarged plan view of an example of an active region in a region A2 surrounded by a broken line in FIG. 7 is a cross-sectional view taken along line X1-X1 and line Y1-Y1 of FIG. 5 shows a state in which the source electrode 2S of the chip 1C is removed, and FIG. 6 shows a state in which the gate electrode layer made of polycrystalline silicon in FIG. 5 is removed. Further, the arrow Z in FIG. 7 indicates a direction intersecting (preferably orthogonal to) the main surface of the chip 1C.
　チップ１Ｃを構成する半導体基板１Ｓは、例えば、炭化シリコン（ＳｉＣ）等のようなワイドギャップ半導体で形成されている。この半導体基板１Ｓは、基板層ＳＢと、その上に形成されたエピタキシャル層ＥＰとを有している。基板層ＳＢは、例えば、ｎ＋型のＳｉＣからなり、エピタキシャル層ＥＰは、例えば、ｎ－型のＳｉＣからなる。基板層ＳＢおよびエピタキシャル層ＥＰには、例えば、窒素（Ｎ）またはリン（Ｐ）等のようなｎ型不純物が導入されている。半導体基板１Ｓは、エピタキシャル層ＥＰの主面（第１面）と、その反対側の基板層ＳＢの主面（第２面）とを有している。エピタキシャル層ＥＰの主面がチップ１Ｃの主面に相当している。なお、基板層ＳＢの主面には、ドレイン電極３Ｄが形成されている。ドレイン電極３Ｄは、例えば、Ｔｉ膜と、ＴｉＮ膜と、Ａｌ膜とを下層から順に積層することで形成されている。 The semiconductor substrate 1S constituting the chip 1C is formed of, for example, a wide gap semiconductor such as silicon carbide (SiC). The semiconductor substrate 1S has a substrate layer SB and an epitaxial layer EP formed thereon. The substrate layer SB is made of, for example, n + -type SiC, and the epitaxial layer EP is made of, for example, n − -type SiC. In the substrate layer SB and the epitaxial layer EP, for example, an n-type impurity such as nitrogen (N) or phosphorus (P) is introduced. The semiconductor substrate 1S has a main surface (first surface) of the epitaxial layer EP and a main surface (second surface) of the substrate layer SB on the opposite side. The main surface of the epitaxial layer EP corresponds to the main surface of the chip 1C. The drain electrode 3D is formed on the main surface of the substrate layer SB. The drain electrode 3D is formed, for example, by sequentially laminating a Ti film, a TiN film, and an Al film from the lower layer.
　このような半導体基板１Ｓのエピタキシャル層ＥＰの主面側には、上記単位セルＵＣの構成要素として、ｐ型の埋込ボディ領域７Ｂ１と、ｎ型のソース領域８Ｓと、ｐ＋型のボディコンタクト領域９ＢＣと、ｐ型の長辺側ボディ領域７Ｂ２と、ｐ型の短辺側ボディ領域７Ｂ３とが設けられている。以下、これらの構成について説明する。 A p-type buried body region 7B1, an n-type source region 8S, and ap + -type body contact are provided on the main surface side of the epitaxial layer EP of the semiconductor substrate 1S as components of the unit cell UC. A region 9BC, a p-type long side body region 7B2, and a p-type short side body region 7B3 are provided. Hereinafter, these configurations will be described.
　ｐ型の埋込ボディ領域（第２半導体領域）７Ｂ１は、各単位セルＵＣのソース領域８Ｓの底部を覆うように、各ソース領域８Ｓに平面視で重なった状態で、各ソース領域８Ｓの長手方向（Ｘ方向）に沿って帯状に形成されている。すなわち、図７右に示すように、埋込ボディ領域７Ｂ１の長手方向（Ｘ方向）の両端は、終端領域ＧＡに達している。また、図７左に示すように、埋込ボディ領域７Ｂ１の幅方向（Ｙ方向）の寸法は、ソース領域８Ｓの幅方向（Ｙ方向）の寸法よりも広い。この埋込ボディ領域７Ｂ１は、エピタキシャル層ＥＰの主面から離れた位置（ソース領域８Ｓの底部下）に形成されている。すなわち、埋込ボディ領域７Ｂ１は、ソース領域８Ｓの底部から基板層ＳＢに向かって延び、基板層ＳＢに達することなく、エピタキシャル層ＥＰの深さ方向（Ｚ方向）の途中の位置で終端している。この埋込ボディ領域７Ｂ１には、例えば、Ａｌまたはホウ素（Ｂ）等のようなｐ型不純物が導入されている。 The p-type buried body region (second semiconductor region) 7B1 is longer than the source region 8S in plan view so as to cover the bottom of the source region 8S of each unit cell UC. It is formed in a strip shape along the direction (X direction). That is, as shown on the right of FIG. 7, both ends in the longitudinal direction (X direction) of the embedded body region 7B1 reach the termination region GA. Further, as shown in the left of FIG. 7, the dimension in the width direction (Y direction) of the embedded body region 7B1 is wider than the dimension in the width direction (Y direction) of the source region 8S. Buried body region 7B1 is formed at a position away from the main surface of epitaxial layer EP (below the bottom of source region 8S). In other words, buried body region 7B1 extends from the bottom of source region 8S toward substrate layer SB, and terminates at an intermediate position in the depth direction (Z direction) of epitaxial layer EP without reaching substrate layer SB. There is. In the buried body region 7B1, for example, p-type impurities such as Al or boron (B) are introduced.
　このｐ型の埋込ボディ領域７Ｂ１上には、ｎ型（第１導電型）のソース領域（第１半導体領域）８Ｓが形成されている。このソース領域８Ｓは、図６に示すように、平面視で各単位セルＵＣの長手方向（Ｘ方向）に沿って帯状に形成されている。ソース領域８Ｓは、平面視で各埋込ボディ領域７Ｂ１に内包されるように埋込ボディ領域７Ｂ１に重なった状態で配置されている。ただし、ソース領域８Ｓの長手方向の両端部は、終端領域ＧＡまで達しておらず、終端領域ＧＡから離れた位置で終端している。また、ソース領域８Ｓは、図７に示すように、エピタキシャル層ＥＰの主面から基板層ＳＢに向かって延び、埋込ボディ領域７Ｂ１に達した位置で終端している。このソース領域８Ｓには、例えば、窒素（Ｎ）またはリン（Ｐ）等のようなｎ型不純物が導入されている。このソース領域８Ｓには、ソースコンタクトＳＣを通じてソース電極２Ｓが電気的に接続されている。 An n-type (first conductivity type) source region (first semiconductor region) 8S is formed on the p-type buried body region 7B1. The source region 8S is formed in a band shape along the longitudinal direction (X direction) of each unit cell UC in a plan view, as shown in FIG. The source region 8S is disposed in a state of being overlapped with the embedded body region 7B1 so as to be included in each embedded body region 7B1 in plan view. However, both ends in the longitudinal direction of the source region 8S do not reach the termination region GA, and terminate at a position distant from the termination region GA. Further, as shown in FIG. 7, source region 8S extends from the main surface of epitaxial layer EP toward substrate layer SB and terminates at a position where buried body region 7B1 is reached. In the source region 8S, for example, an n-type impurity such as nitrogen (N) or phosphorus (P) is introduced. Source electrode 2S is electrically connected to source region 8S through source contact SC.
　また、ソース領域８Ｓには、複数のｐ＋型のボディコンタクト領域９ＢＣが配置されている。このボディコンタクト領域９ＢＣは、ＤＭＯＳＦＥＴのソース電極２Ｓと埋込ボディ領域７Ｂ１とを電気的に接続するための導通領域である。すなわち、図７に示すように、ボディコンタクト領域９ＢＣは、エピタキシャル層ＥＰの主面から深さ方向に延び、埋込ボディ領域７Ｂ１に達して終端している。これにより、ソース電極２Ｓは、ボディコンタクト領域９ＢＣを通じて埋込ボディ領域７Ｂ１と電気的に接続されている。このボディコンタクト領域９ＢＣには、例えば、Ａｌまたはホウ素等のようなｐ型不純物が導入されている。 In the source region 8S, a plurality of p + -type body contact regions 9BC are arranged. The body contact region 9BC is a conductive region for electrically connecting the source electrode 2S of the DMOSFET and the buried body region 7B1. That is, as shown in FIG. 7, body contact region 9BC extends in the depth direction from the main surface of epitaxial layer EP, and reaches and terminates embedded body region 7B1. Thus, source electrode 2S is electrically connected to embedded body region 7B1 through body contact region 9BC. A p-type impurity such as Al or boron is introduced into the body contact region 9BC, for example.
　ここでは、ボディコンタクト領域９ＢＣが、例えば、平面視で略四角形状に形成されており、ソース領域８Ｓの幅方向（Ｙ方向）の中央位置に、ソース領域８Ｓの長手方向（Ｘ方向）に沿って所定の間隔毎に配置されている。このようにボディコンタクト領域９ＢＣを小面積にすることでアクティブ領域ＡＣＡ内に配置可能な単位セルＵＣの数を増やすことができるので、ＤＭＯＳＦＥＴのオン抵抗を低減できる。ただし、ボディコンタクト領域９ＢＣの数、大きさ、あるいは間隔は種々変更可能である。また、ボディコンタクト領域９ＢＣの平面視の形状も種々変更可能であり、例えば、ソース領域８Ｓの長手方向に沿って連続的に延びる帯状にしても良い。この場合、ソース電極２Ｓと埋込ボディ領域７Ｂ１との間の抵抗を低減できるので、ボディ領域の電気的安定性を向上させることができる。 Here, body contact region 9BC is formed, for example, in a substantially rectangular shape in plan view, along the longitudinal direction (X direction) of source region 8S at the central position in the width direction (Y direction) of source region 8S. Are arranged at predetermined intervals. Since the number of unit cells UC that can be arranged in the active area ACA can be increased by reducing the area of the body contact area 9BC as described above, the on-resistance of the DMOSFET can be reduced. However, the number, size, or interval of the body contact regions 9BC can be changed variously. Further, the shape in plan view of the body contact region 9BC can be changed variously, and for example, it may be a strip extending continuously along the longitudinal direction of the source region 8S. In this case, since the resistance between the source electrode 2S and the embedded body region 7B1 can be reduced, the electrical stability of the body region can be improved.
　また、図６に示すように、各単位セルＵＣのソース領域８Ｓの幅方向（Ｙ方向）の両端部（両長辺）に隣接する部分（第２部分）には、平面視で帯状のｐ型の長辺側ボディ領域（第３半導体領域）７Ｂ２が形成されている。この長辺側ボディ領域７Ｂ２は、ソース領域８Ｓの両長辺側の側部を覆うように、エピタキシャル層ＥＰの主面から基板層ＳＢに向かって延び、埋込ボディ領域７Ｂ１に達して終端している。この長辺側ボディ領域７Ｂ２の表層側には、ＤＭＯＳＦＥＴの動作時にＤＭＯＳＦＥＴの正規のチャネルが形成される。すなわち、ＤＭＯＳＦＥＴの動作時に、ｐ型の長辺側ボディ領域７Ｂ２の表層はｎ型に反転して電子を通すようになる。この長辺側ボディ領域７Ｂ２には、例えば、Ａｌまたはホウ素等のようなｐ型不純物が導入されている。 Further, as shown in FIG. 6, in a portion (second portion) adjacent to both ends (both long sides) in the width direction (Y direction) of the source region 8S of each unit cell UC, the strip p in plan view A long side body region (third semiconductor region) 7B2 of the die is formed. The long side body region 7B2 extends from the main surface of the epitaxial layer EP toward the substrate layer SB so as to cover the side portions on both long sides of the source region 8S, and reaches the buried body region 7B1 and terminates. ing. A normal channel of the DMOSFET is formed on the surface side of the long side body region 7B2 when the DMOSFET operates. That is, during the operation of the DMOSFET, the surface layer of the p-type long side body region 7B2 is inverted to n-type to pass electrons. In the long side body region 7B2, for example, a p-type impurity such as Al or boron is introduced.
　また、各単位セルＵＣのソース領域８Ｓの長手方向の両端部（両短辺）に隣接する部分（第１部分）には、平面視で帯状のｐ型の短辺側ボディ領域（第４半導体領域）７Ｂ３が形成されている。この短辺側ボディ領域７Ｂ３は、ソース領域８Ｓの両短辺側の側部を覆うように、エピタキシャル層ＥＰの主面から基板層ＳＢに向かって延び、埋込ボディ領域７Ｂ１に達して終端している。このため、ソース領域８Ｓの全周がｐ型のボディ領域（ｐ型の埋込ボディ領域７Ｂ１、ｐ型の長辺側ボディ領域７Ｂ２およびｐ型の短辺側ボディ領域７Ｂ３）で取り囲まれている。 Further, in a portion (first portion) adjacent to both end portions (both short sides) in the longitudinal direction of source region 8S of each unit cell UC, a strip-like p-type short side body region (fourth semiconductor in plan view) Region) 7B3 is formed. This short side body region 7B3 extends from the main surface of epitaxial layer EP toward substrate layer SB so as to cover the side portions on both short sides of source region 8S, and reaches embedded body region 7B1 and terminates. ing. Therefore, the entire circumference of the source region 8S is surrounded by the p-type body region (p-type embedded body region 7B1, p-type long side body region 7B2 and p-type short side body region 7B3) .
　この短辺側ボディ領域７Ｂ３は、ＤＭＯＳＦＥＴの動作時に、ソース領域８Ｓの長手方法の両端部からリーク電流が流れるのを抑制または防止する機能を有している。この短辺側ボディ領域７Ｂ３には、例えば、Ａｌまたはホウ素等のようなｐ型不純物が導入されている。ここでは、短辺側ボディ領域７Ｂ３に含まれるｐ型不純物の濃度は、長辺側ボディ領域７Ｂ２に含まれるｐ型不純物の濃度よりも高くなっている。このため、ＤＭＯＳＦＥＴの動作時に、ｐ型の短辺側ボディ領域７Ｂ３の表層部がｎ型に反転してチャネルが形成されるときのしきい値電圧は、ｐ型の長辺側ボディ領域７Ｂ２の表層部がＮ型に反転してチャネルが形成されるときのしきい値電圧よりも高くなっている。その結果、通常のＤＭＯＳＦＥＴの動作に、ｐ型の短辺側ボディ領域７Ｂ３を通じて流れる電流（リーク電流）を、ｐ型の長辺側ボディ領域７Ｂ２を通じて流れる電流より極めて小さくすることができる。したがって、ソース領域８Ｓの長手方向の両端部から流れるリーク電流を低減できるので、ＤＭＯＳＦＥＴを有するパワー半導体装置の信頼性を向上させることができる。 The short side body region 7B3 has a function of suppressing or preventing a leak current from flowing from both ends of the source region 8S in the longitudinal direction during the operation of the DMOSFET. In this short side body region 7B3, for example, a p-type impurity such as Al or boron is introduced. Here, the concentration of the p-type impurity contained in the short side body region 7B3 is higher than the concentration of the p-type impurity contained in the long side body region 7B2. Therefore, the threshold voltage when the surface layer portion of p-type short side body region 7B3 is inverted to n-type to form a channel during operation of the DMOSFET is the same as that of p-type long side body region 7B2. It is higher than the threshold voltage when the surface layer portion is inverted to N-type to form a channel. As a result, the current (leakage current) flowing through the p-type short side body region 7B3 can be made extremely smaller than the current flowing through the p-type long side body region 7B2 in the operation of a normal DMOSFET. Therefore, the leakage current flowing from both ends in the longitudinal direction of the source region 8S can be reduced, so that the reliability of the power semiconductor device having the DMOSFET can be improved.
　ここでは、図６に示すように、短辺側ボディ領域７Ｂ３が、単位セルＵＣ毎に分離されている。ただし、短辺側ボディ領域７Ｂ３は、上記したリーク電流を抑制または防止すべく各単位セルＵＣのソース領域８Ｓの長手方向の両端部を覆うように形成されていれば良い。図８は短辺側ボディ領域の変形例を示す半導体基板の要部平面図である。図８では、短辺側ボディ領域７Ｂ３が、複数の単位セルＵＣ間を接続するように、Ｙ方向に沿って連続的に延在した状態で形成されている。これにより、短辺側ボディ領域７Ｂ３を形成するときのマスクの開口部の寸法を大きくとれるので、短辺側ボディ領域７Ｂ３をより容易に形成することができる。 Here, as shown in FIG. 6, the short side body region 7B3 is separated for each unit cell UC. However, the short side body region 7B3 may be formed so as to cover both end portions in the longitudinal direction of the source region 8S of each unit cell UC in order to suppress or prevent the above-described leakage current. FIG. 8 is a plan view of relevant parts of a semiconductor substrate showing a modification of the short side body region. In FIG. 8, the short side body regions 7B3 are formed to extend continuously along the Y direction so as to connect the plurality of unit cells UC. As a result, since the dimension of the opening of the mask when forming the short side body region 7B3 can be increased, the short side body region 7B3 can be formed more easily.
　このような半導体基板１Ｓのエピタキシャル層ＥＰの主面上には、図７に示すように、ゲート絶縁膜（第２絶縁膜）１０ａが形成されている。ゲート絶縁膜１０ａは、例えば、酸化シリコン膜（ＳｉＯ２）からなる。ゲート絶縁膜１０ａ上には、ゲート電極１１Ｇが形成されている。ゲート電極１１Ｇは、例えば、低抵抗なｎ型の多結晶シリコン膜からなる。このゲート電極１１Ｇは、図５に示すように、平面視で、アクティブ領域ＡＣＡを覆うように形成されているが、終端領域ＧＡには重なっていない。 As shown in FIG. 7, a gate insulating film (second insulating film) 10a is formed on the main surface of the epitaxial layer EP of such a semiconductor substrate 1S. The gate insulating film 10 a is made of, for example, a silicon oxide film (SiO 2 ). A gate electrode 11G is formed on the gate insulating film 10a. The gate electrode 11G is made of, for example, a low resistance n-type polycrystalline silicon film. Although this gate electrode 11G is formed so as to cover the active area ACA in plan view as shown in FIG. 5, it does not overlap the termination area GA.
　このゲート電極１１Ｇの一部には、各単位セルＵＣの一部が露出される開口部１２が形成されている。開口部１２は、平面視でソース領域８Ｓに重なるように帯状に形成されている。この開口部１２からは単位セルＵＣのソース領域８Ｓの一部およびボディコンタクト領域９ＢＣが露出されている。この開口部１２の幅方向および長手方向の両端部は、ソース領域８Ｓ内に位置している。したがって、ゲート電極１１Ｇは、ソース領域８Ｓの外周より内側の一部分、長辺側ボディ領域７Ｂ２の全域および短辺側ボディ領域の７Ｂ３の全域に平面視で重なっている。 An opening 12 is formed in a part of the gate electrode 11G to expose a part of each unit cell UC. The opening 12 is formed in a band shape so as to overlap the source region 8S in plan view. A portion of the source region 8S of the unit cell UC and the body contact region 9BC are exposed from the opening 12. Both ends in the width direction and the longitudinal direction of the opening 12 are located in the source region 8S. Therefore, the gate electrode 11G overlaps in plan view with a part inside the outer periphery of the source region 8S, the entire region of the long side body region 7B2 and the entire region 7B3 of the short side body region.
　さらに、エピタキシャル層ＥＰの主面上には、ゲート電極１１Ｇを覆うように層間絶縁膜１３が堆積されている。層間絶縁膜１３は、例えば、酸化シリコン膜（ＳｉＯ２）からなる。この層間絶縁膜１３上に上記したソース電極２Ｓおよびゲート電極２Ｇが形成されている。ソース電極２Ｓとその下層のゲート電極１１Ｇとは、それらの間に設けられた層間絶縁膜１３によって電気的に絶縁されている。一方、ゲート電極２Ｇとその下層のゲート電極１１Ｇとは、層間絶縁膜１３に形成された開口部（ゲートコンタクト；図示せず）を通じて電気的に接続されている。 Furthermore, over the main surface of the epitaxial layer EP, the interlayer insulating film 13 is deposited so as to cover the gate electrode 11G. The interlayer insulating film 13 is made of, for example, a silicon oxide film (SiO 2 ). The source electrode 2S and the gate electrode 2G described above are formed on the interlayer insulating film 13. The source electrode 2S and the underlying gate electrode 11G are electrically insulated by an interlayer insulating film 13 provided therebetween. On the other hand, the gate electrode 2G and the gate electrode 11G under the gate electrode 2G are electrically connected through an opening (gate contact; not shown) formed in the interlayer insulating film 13.
　層間絶縁膜１３およびゲート絶縁膜１０ａにおいて、平面視でゲート電極１１Ｇの開口部１２と重なる位置には、開口部１２よりも小面積のソースコンタクトＳＣが開口されている。このソースコンタクトＳＣからは、ソース領域８Ｓの一部およびボディコンタクト領域９ＢＣが露出されている。すなわち、ソース電極２Ｓは、ソースコンタクトＳＣを通じて、単位セルＵＣのソース領域８Ｓおよびボディコンタクト領域９ＢＣと電気的に接続されている。したがって、ソース領域８Ｓおよびボディコンタクト領域９ＢＣは、ソース電極２Ｓを通じて電気的に短絡している。
　＜ＤＭＯＳＦＥＴの動作説明＞ In the interlayer insulating film 13 and the gate insulating film 10a, a source contact SC having an area smaller than that of the opening 12 is opened at a position overlapping the opening 12 of the gate electrode 11G in plan view. A portion of source region 8S and body contact region 9BC are exposed from source contact SC. That is, source electrode 2S is electrically connected to source region 8S and body contact region 9BC of unit cell UC through source contact SC. Therefore, source region 8S and body contact region 9BC are electrically shorted through source electrode 2S.
<Operation explanation of DMOSFET>
　次に、本実施の形態１の半導体装置を構成するＤＭＯＳＦＥＴの動作について図９を参照して説明する。図９は図６のＹ１－Ｙ１線の断面図である。 Next, the operation of the DMOSFET constituting the semiconductor device of the first embodiment will be described with reference to FIG. FIG. 9 is a cross-sectional view taken along line Y1-Y1 of FIG.
　スイッチングデバイス（半導体装置）のゲート電極１１Ｇに正電圧を印加すると、ｐ型の長辺側ボディ領域７Ｂ２の表層においてゲート絶縁膜１０ａが接する部分にチャネルが形成される。これにより、ｎ型のソース領域８Ｓからｐ型の長辺側ボディ領域７Ｂ２の表層のチャネルを通じてドレイン電極３Ｄに電子が流れる。すなわち、ドレイン電極３Ｄからｐ型の長辺側ボディ領域７Ｂ２の表層のチャネルを通じてソース電極２Ｓに電流Ｉｓｄが流れる。このようにゲート電極１１Ｇに電圧を印加することでスイッチング動作を行なう。
　＜半導体装置の製造方法例＞ When a positive voltage is applied to the gate electrode 11G of the switching device (semiconductor device), a channel is formed in the surface layer of the p-type long side body region 7B2 in contact with the gate insulating film 10a. Thereby, electrons flow from the n-type source region 8S to the drain electrode 3D through the channel on the surface layer of the p-type long side body region 7B2. That is, a current Isd flows from the drain electrode 3D to the source electrode 2S through the surface layer channel of the p-type long side body region 7B2. The switching operation is performed by thus applying a voltage to the gate electrode 11G.
<Example of Method of Manufacturing Semiconductor Device>
　次に、本実施の形態１の半導体装置の製造方法の一例について図１０～図２０を参照して説明する。以下の説明に当たっては、図６のＸ１－Ｘ１線の断面、または、Ｙ１－Ｙ１線の断面に対応する部分を図示する。また、必要に応じて平面図も示す。
　＜埋込ボディ領域の形成＞ Next, an example of a method of manufacturing the semiconductor device of the first embodiment will be described with reference to FIGS. 10 to 20. In the following description, a portion corresponding to the cross section along line X1-X1 of FIG. 6 or the cross section along line Y1-Y1 is illustrated. In addition, a plan view is also shown if necessary.
<Formation of an embedded body region>
　図１０は本実施の形態１の半導体装置を構成する埋込ボディ領域の形成工程時の図６のＹ１－Ｙ１線およびＸ１－Ｘ１線に相当する箇所の断面図である。 FIG. 10 is a cross-sectional view of a portion corresponding to the Y1-Y1 line and the X1-X1 line of FIG. 6 in the step of forming the buried body region constituting the semiconductor device of the first embodiment.
　まず、例えば、ｎ＋型の４Ｈ－ＳｉＣからなる基板層ＳＢの主面上に、ｎ－型のＳｉＣからなるエピタキシャル層ＥＰを形成する。基板層ＳＢに導入されたｎ型不純物は、例えば窒素（Ｎ）であり、その不純物濃度は、例えば、１×１０１８～１×１０２１ｃｍ－３の範囲である。 First, for example, on the main surface of the substrate layer SB made of n + -type 4H—SiC, an epitaxial layer EP made of n − -type SiC is formed. The n-type impurity introduced into the substrate layer SB is, for example, nitrogen (N), and the impurity concentration thereof is, for example, in the range of 1 × 10 18 to 1 × 10 21 cm −3 .
　エピタキシャル層ＥＰは、基板層ＳＢの主面上に、例えば、エピタキシャル法によって形成することができる。エピタキシャル層ＥＰは、素子の仕様によって決まる所定の厚さとドーパント濃度とを有している。エピタキシャル層ＥＰの厚さは、例えば、３～３０μｍの範囲である。また、エピタキシャル層ＥＰに添加されているｎ型ドーパントは、例えば窒素であり、そのドーパント濃度は例えば１×１０１４～１×１０１７ｃｍ－３の範囲である。 The epitaxial layer EP can be formed on the main surface of the substrate layer SB, for example, by an epitaxial method. The epitaxial layer EP has a predetermined thickness and dopant concentration determined by the specifications of the device. The thickness of the epitaxial layer EP is, for example, in the range of 3 to 30 μm. The n-type dopant added to the epitaxial layer EP is, for example, nitrogen, and the dopant concentration is, for example, in the range of 1 × 10 14 to 1 × 10 17 cm −3 .
　次いで、ｎ－型のエピタキシャル層ＥＰの主面上にマスク材を堆積し、これをパターニングすることでマスクＭＡを形成する。マスクＭＡの平面視での形状は、埋込ボディ領域を露出させ、それ以外を覆う形状に形成されている。マスクＭＡの材料としてフォトレジストを使用する場合は、フォトレジストを塗布した後、これを公知のリソグラフィ法によってパターニングすることでマスクＭＡを形成する。また、マスクＭＡの材料として酸化シリコン（ＳｉＯ２）を使用する場合は、酸化シリコン膜を堆積した後、その上にフォトレジストを塗布し、公知のリソグラフィ法によってレジストパターンを形成する。続いて、そのレジストパターンをエッチングマスクとして、例えば、反応性イオンエッチング法により酸化シリコン膜をエッチングした後、フォトレジストを除去することでマスクＭＡを形成する。マスクＭＡの厚さは、イオンの注入を遮蔽するために充分な厚さであり、例えば１．０～５．０μｍとすることができる。 Then, a mask material is deposited on the main surface of the n − -type epitaxial layer EP and patterned to form a mask MA. The shape of the mask MA in a plan view is formed to expose the embedded body region and to cover the rest. When a photoresist is used as the material of the mask MA, the photoresist is applied and then patterned by a known lithography method to form the mask MA. When silicon oxide (SiO 2 ) is used as the material of the mask MA, a silicon oxide film is deposited, a photoresist is applied thereon, and a resist pattern is formed by a known lithography method. Subsequently, using the resist pattern as an etching mask, the silicon oxide film is etched by, eg, reactive ion etching, and then the photoresist is removed to form a mask MA. The thickness of the mask MA is sufficient to shield the ion implantation, and can be, for example, 1.0 to 5.0 μm.
　続いて、マスクＭＡをイオン注入マスクとして、エピタキシャル層ＥＰの主面側からエピタキシャル層ＥＰにｐ型不純物（第２不純物）を注入し、エピタキシャル層ＥＰの素子形成領域においてエピタキシャル層ＥＰの主面から離れた位置にｐ型の埋込ボディ領域７Ｂ１を形成する。イオン注入するｐ型不純物としては、例えば、アルミニウム（Ａｌ）またはホウ素（Ｂ）を用いることができる。この埋込ボディ領域７Ｂ１の底面側の深さ（エピタキシャル層ＥＰの主面からの深さ）は、例えば０．５～２．０μｍ程度とすることができる。また、埋込ボディ領域７Ｂ１の主面側の深さ（エピタキシャル層ＥＰの主面からの深さ）は、例えば０．２～０．５μｍ程度とすることができる。また、埋込ボディ領域７Ｂ１上のエピタキシャル層ＥＰの最表面（表面から０．０５μｍ以内の深さ）領域のｐ型不純物の濃度は、例えば、１×１０１７ｃｍ－３以下となるようにする。また、埋込ボディ領域７Ｂ１のドーパント濃度は、例えば、１×１０１６～１×１０１９ｃｍ－３の範囲である。このような埋込ボディ領域７Ｂ１を形成するためのイオン注入工程後、マスクＭＡを除去する。
　＜ソース領域の形成＞ Subsequently, using mask MA as an ion implantation mask, a p-type impurity (second impurity) is implanted into epitaxial layer EP from the main surface side of epitaxial layer EP, from the main surface of epitaxial layer EP in the element formation region of epitaxial layer EP. A p-type embedded body region 7B1 is formed at a distant position. For example, aluminum (Al) or boron (B) can be used as the p-type impurity to be ion implanted. The depth on the bottom side (the depth from the main surface of the epitaxial layer EP) of the buried body region 7B1 can be, for example, about 0.5 to 2.0 μm. The depth on the main surface side of buried body region 7B1 (the depth from the main surface of epitaxial layer EP) can be, for example, about 0.2 to 0.5 μm. Further, the concentration of the p-type impurity in the outermost surface (the depth of 0.05 μm or less from the surface) region of the epitaxial layer EP on the buried body region 7B1 is, for example, 1 × 10 17 cm −3 or less. . The dopant concentration of the buried body region 7B1 is, for example, in the range of 1 × 10 16 to 1 × 10 19 cm −3 . After the ion implantation step for forming such embedded body region 7B1, the mask MA is removed.
<Formation of Source Region>
　図１１は本実施の形態１の半導体装置を構成するソース領域の形成工程時の図６のＹ１－Ｙ１線およびＸ１－Ｘ１線に相当する箇所の断面図である。 FIG. 11 is a cross-sectional view of a portion corresponding to the Y1-Y1 line and the X1-X1 line of FIG. 6 in the process of forming the source region that constitutes the semiconductor device of the first embodiment.
　ここでは、エピタキシャル層ＥＰの主面上に、別のマスクＭＢを形成する。マスクＭＢの平面視での形状は、ソース領域を露出させ、それ以外を覆う形状に形成されている。マスクＭＢの材料や形成方法は、マスクＭＡと同じである。続いて、マスクＭＢをイオン注入マスクとして、エピタキシャル層ＥＰの主面側からエピタキシャル層ＥＰにｎ型不純物（第１不純物）をイオン注入することでｎ型のソース領域８Ｓを形成する。このｎ型不純物としては、例えば、窒素（Ｎ）やリン（Ｐ）を用いることができる。また、このソース領域８Ｓの不純物濃度は、例えば、１×１０１７～１×１０２１ｃｍ－３の範囲とすることができる。また、ソース領域８Ｓの深さ（エピタキシャル層ＥＰの主面からの深さ）は、埋込ボディ領域７Ｂ１より浅く、例えば、０．０１～０．２μｍ程度とすることができる。
　＜長辺側ボディ領域の形成＞ Here, another mask MB is formed on the main surface of the epitaxial layer EP. The shape in plan view of the mask MB is formed in a shape that exposes the source region and covers the other. The material and formation method of the mask MB are the same as the mask MA. Subsequently, using the mask MB as an ion implantation mask, an n-type impurity (first impurity) is ion-implanted into the epitaxial layer EP from the main surface side of the epitaxial layer EP to form an n-type source region 8S. As this n-type impurity, for example, nitrogen (N) or phosphorus (P) can be used. The impurity concentration of the source region 8S can be, for example, in the range of 1 × 10 17 to 1 × 10 21 cm −3 . The depth of the source region 8S (the depth from the main surface of the epitaxial layer EP) is shallower than that of the buried body region 7B1, and can be, for example, about 0.01 to 0.2 μm.
<Formation of long side body region>
　図１２左右は本実施の形態１の半導体装置を構成する長辺側ボディ領域の形成工程時の図６のＹ１－Ｙ１線に相当する箇所の断面図である。 12 is a cross-sectional view of a portion corresponding to the Y1-Y1 line of FIG. 6 in the process of forming the long side body region constituting the semiconductor device of the first embodiment.
　ここでは、図１２左に示すように、図１１と同じマスクＭＢを用いて、エピタキシャル層ＥＰの主面側からエピタキシャル層ＥＰの主面に対して斜めにｐ型不純物（第３不純物）を注入する。すなわち、不純物のイオン注入角度を、エピタキシャル層ＥＰの主面の法線に対して傾斜角度θだけ傾けた状態で、Ｙ方向に沿う一方向からエピタキシャル層ＥＰにｐ型不純物をイオン注入する。これにより、マスクＭＢで遮蔽された部分の一部（マスクＭＢ端部下）にｐ型不純物を注入して、ソース領域８Ｓの幅方向の一端部（一方の長辺）に隣接する部分に、長辺側ボディ領域７Ｂ２を形成することができる。 Here, as shown on the left of FIG. 12, a p-type impurity (third impurity) is implanted obliquely to the main surface of epitaxial layer EP from the main surface side of epitaxial layer EP using the same mask MB as FIG. Do. That is, the p-type impurity is ion-implanted into the epitaxial layer EP from one direction along the Y direction in a state in which the ion implantation angle of the impurity is inclined by the inclination angle θ with respect to the normal to the main surface of the epitaxial layer EP. As a result, a p-type impurity is implanted into a part (below the mask MB end) of the part shielded by the mask MB, and a length adjacent to one end (one long side) in the width direction of the source region 8S Side body regions 7B2 can be formed.
　この際、イオン注入するｐ型不純物としては、例えば、アルミニウムまたはホウ素を用いることができる。イオン注入時の傾斜角度θは、例えば、１５～４５度とすることができる。また、イオン注入時の加速エネルギーは、例えば、最大で３００ｋｅＶ～１５００ｋｅＶとすることが望ましい。これにより、ｐ型不純物は、マスクＭＢを透過してエピタキシャル層ＥＰに到達できる。また、長辺側ボディ領域７Ｂ２の不純物濃度は、例えば、１×１０１６～５×１０１８ｃｍ－３の範囲である。 At this time, for example, aluminum or boron can be used as the p-type impurity for ion implantation. The inclination angle θ at the time of ion implantation can be, for example, 15 to 45 degrees. Also, it is desirable that the acceleration energy at the time of ion implantation be, for example, 300 keV to 1500 keV at maximum. Thereby, the p-type impurity can permeate the mask MB and reach the epitaxial layer EP. The impurity concentration of the long side body region 7B2 is, for example, in the range of 1 × 10 16 to 5 × 10 18 cm −3 .
　続いて、図１２右に示すように、図１１と同じマスクＭＢを用いて、エピタキシャル層ＥＰの主面に対して斜めにｐ型不純物（第３不純物）を注入する。すなわち、不純物のイオン注入角度を、エピタキシャル層ＥＰの主面の法線に対して傾斜角度θだけ傾けた状態で、図１２左とは真逆の方向からエピタキシャル層ＥＰにｐ型不純物をイオン注入する。これにより、マスクＭＢで遮蔽された部分の一部（マスクＭＢの端部下）にｐ型不純物を注入して、ソース領域８Ｓの幅方向の他端部（他方の長辺）に隣接する部分に、長辺側ボディ領域７Ｂ２を形成することができる。 Subsequently, as shown on the right of FIG. 12, a p-type impurity (third impurity) is implanted obliquely to the main surface of the epitaxial layer EP using the same mask MB as that of FIG. That is, in a state where the ion implantation angle of the impurity is inclined by the inclination angle θ with respect to the normal to the main surface of the epitaxial layer EP, the p-type impurity is ion implanted into the epitaxial layer EP from the reverse direction to the left in FIG. Do. As a result, a p-type impurity is implanted into a part of the portion shielded by the mask MB (below the end of the mask MB), and a portion adjacent to the other end (other long side) in the width direction of the source region 8S. The long side body region 7B2 can be formed.
　この２回の不純物注入工程では、不純物の注入方向が異なるだけで、傾斜角度θや注入イオン種、加速エネルギーおよび注入量等の条件は同じである。ただし、エピタキシャル層ＥＰの主面の結晶方位に応じて注入の深さが異なる場合がある。その場合は、不純物の注入方向毎に傾斜角度θ等のような注入条件を変更することで、ソース領域８Ｓの幅方向の両端部側の２つの長辺側ボディ領域７Ｂ２に形成される各々のチャネルの長さや不純物濃度が同じになるように調整することができる。 In the two impurity implantation steps, the conditions such as the inclination angle θ, the implanted ion species, the acceleration energy, and the implantation amount are the same except that the impurity implantation direction is different. However, the implantation depth may differ depending on the crystal orientation of the main surface of epitaxial layer EP. In that case, by changing the implantation conditions such as the inclination angle θ for each impurity implantation direction, each of the two long side body regions 7B2 on both end sides in the width direction of the source region 8S is formed. The channel length and the impurity concentration can be adjusted to be the same.
　図１３は長辺側ボディ領域の形成工程後の半導体基板の活性領域の要部平面図、図１４左右はそれぞれ図１３のＹ１－Ｙ１線およびＸ１－Ｘ１線の断面図である。 FIG. 13 is a plan view of an essential part of the active region of the semiconductor substrate after the step of forming the long side body region, and FIG. 14 right and left are cross-sectional views taken along line Y1-Y1 and X1-X1 of FIG.
　以上の工程後、マスクＭＢ（図１１および図１２参照）を除去することにより、エピタキシャル層ＥＰの主面に、ソース領域８Ｓおよび長辺側ボディ領域７Ｂ２を形成する。長辺側ボディ領域７Ｂ２は、図１３に示すように、各ソース領域８Ｓの両長辺に隣接した状態で形成されている。また、長辺側ボディ領域７Ｂ２は、図１４左に示すように、ソース領域８Ｓの長辺側の側部を覆うように、エピタキシャル層ＥＰの主面から埋込ボディ領域７Ｂ１まで延びて終端している。なお、図１４右に示すように、ソース領域８Ｓの長手方向の両端部（短辺）に隣接する部分側には、エピタキシャル層ＥＰの主面から深さ方向に離れた位置にｐ型の埋込ボディ領域７Ｂ１が形成されている。ただし、この段階では、ソース領域８Ｓの長手方向の両端部（短辺）に隣接する部分において、エピタキシャル層ＥＰの主面から埋込ボディ領域７Ｂ１までの間には、ｐ型不純物がほとんど添加されていない。
　＜ボディコンタクト領域の形成＞ After the above steps, the mask MB (see FIGS. 11 and 12) is removed to form the source region 8S and the long side body region 7B2 on the main surface of the epitaxial layer EP. As shown in FIG. 13, the long side body regions 7B2 are formed adjacent to both long sides of each source region 8S. Further, the long side body region 7B2 extends from the main surface of the epitaxial layer EP to the buried body region 7B1 so as to cover the side portion on the long side of the source region 8S as shown in the left of FIG. ing. As shown in the right side of FIG. 14, p-type buried at a position apart from the main surface of epitaxial layer EP in the depth direction on the side adjacent to both ends (short sides) in the longitudinal direction of source region 8S. An incorporated body region 7B1 is formed. However, at this stage, most of the p-type impurity is added between the main surface of epitaxial layer EP and buried body region 7B1 in portions adjacent to both ends (short sides) in the longitudinal direction of source region 8S. Not.
<Formation of body contact region>
　図１５の左右は本実施の形態１の半導体装置を構成するボディコンタクト領域の形成工程時図６のＹ１－Ｙ１線およびＸ１－Ｘ線に相当する箇所の断面図である。 The left and right sides of FIG. 15 are cross-sectional views corresponding to the Y1-Y1 line and the X1-X line of FIG. 6 during the process of forming the body contact region constituting the semiconductor device of the first embodiment.
　ここでは、エピタキシャル層ＥＰの主面上に、マスクＭＣを形成する。マスクＭＣの平面視での形状は、ボディコンタクト領域を露出させ、それ以外を覆う形状に形成されている。マスクＭＣの材料や形成方法は、マスクＭＡと同じである。 Here, the mask MC is formed on the main surface of the epitaxial layer EP. The shape of the mask MC in a plan view is formed to expose the body contact region and cover the other. The material and formation method of the mask MC are the same as the mask MA.
　続いて、そのマスクＭＣを不純物注入用のマスクとして、エピタキシャル層ＥＰにｐ型不純物をイオン注入することで、エピタキシャル層ＥＰにｐ＋型のボディコンタクト領域９ＢＣを形成した後、マスクＭＣを除去する。イオン注入するｐ型不純物としては、例えば、アルミニウムまたはホウ素を用いることができる。 Then, p + -type body contact region 9 BC is formed in epitaxial layer EP by ion-implanting p-type impurity in epitaxial layer EP using mask MC as a mask for impurity implantation, and then mask MC is removed. . For example, aluminum or boron can be used as the p-type impurity to be ion implanted.
　ｐ＋型のボディコンタクト領域９ＢＣはエピタキシャル層ＥＰの主面からｐ型の埋込ボディ領域７Ｂ１まで延びて終端している。ｐ＋型のボディコンタクト領域９ＢＣの不純物濃度は、例えば１×１０１９～１×１０２１ｃｍ－３の範囲である。また、ｐ＋型のボディコンタクト領域９ＢＣの深さ（エピタキシャル層ＥＰの主面からの深さ）は、例えば０．１～０．４μｍ程度である。
　＜短辺側ボディ領域の形成＞ The p + -type body contact region 9BC extends from the main surface of the epitaxial layer EP to the p-type buried body region 7B1 and terminates. The impurity concentration of the p + -type body contact region 9BC is, for example, in the range of 1 × 10 19 to 1 × 10 21 cm −3 . The depth of the p + -type body contact region 9BC (the depth from the main surface of the epitaxial layer EP) is, for example, about 0.1 to 0.4 μm.
<Formation of short side body region>
　図１６左右は本実施の形態１の半導体装置を構成する短辺側ボディ領域の形成工程時の図６のＹ１－Ｙ１線およびＸ－Ｘ線に相当する箇所の断面図である。 16A and 16B are cross-sectional views corresponding to the Y1-Y1 line and the XX line of FIG. 6 in the process of forming the short side body region constituting the semiconductor device of the first embodiment.
　ここでは、エピタキシャル層ＥＰの主面上に、マスクＭＤを形成する。マスクＭＤの平面視での形状は、短辺側ボディ領域を露出させ、それ以外を覆う形状に形成されている。マスクＭＤの材料や形成方法は、マスクＭＡと同じである。 Here, the mask MD is formed on the main surface of the epitaxial layer EP. The shape in plan view of the mask MD is formed in a shape that exposes the short side body region and covers the other. The material and forming method of the mask MD are the same as the mask MA.
　続いて、マスクＭＤを不純物注入用のマスクとして、エピタキシャル層ＥＰの主面側からエピタキシャル層ＥＰにｐ型不純物（第４不純物）をイオン注入し、エピタキシャル層ＥＰにｐ型の短辺側ボディ領域７Ｂ３を形成した後、マスクＭＤを除去する。イオン注入するｐ型不純物としては、例えば、アルミニウムまたはホウ素を用いることができる。 Subsequently, p-type impurity (fourth impurity) is ion-implanted into the epitaxial layer EP from the main surface side of the epitaxial layer EP using the mask MD as a mask for impurity implantation, and the p-type short side body region is formed in the epitaxial layer EP. After 7B3 is formed, the mask MD is removed. For example, aluminum or boron can be used as the p-type impurity to be ion implanted.
　ｐ型の短辺側ボディ領域７Ｂ３はエピタキシャル層ＥＰの主面から埋込ボディ領域７Ｂ１まで延びて終端している。短辺側ボディ領域７Ｂ３の不純物濃度は、長辺側ボディ領域７Ｂ２のｐ型不純物濃度よりも高く、例えば、５×１０１６～１×１０２１ｃｍ－３の範囲である。
　＜ボディコンタクト領域および短辺側ボディ領域の形成の変形例＞ The p-type short side body region 7B3 extends from the main surface of the epitaxial layer EP to the buried body region 7B1 and terminates. The impurity concentration of the short side body region 7B3 is higher than the p-type impurity concentration of the long side body region 7B2, and is, for example, in the range of 5 × 10 16 to 1 × 10 21 cm −3 .
<Modification of formation of body contact region and short side body region>
　図１７は本実施の形態１の半導体装置を構成するボディコンタクト領域および短辺側ボディ領域の形成工程の変形例を示す図６のＹ１－Ｙ１線およびＸ１－Ｘ１線に相当する箇所の断面図である。 FIG. 17 is a cross-sectional view of a portion corresponding to the Y1-Y1 line and the X1-X1 line of FIG. 6 showing a modification of the process of forming the body contact region and the short side body region constituting the semiconductor device of the first embodiment. It is.
　上記したｐ型の短辺側ボディ領域７Ｂ３およびｐ＋型のボディコンタクト領域９ＢＣは互いに異なる機能や目的のために形成されるものなので、上記の例では、ｐ型の短辺側ボディ領域７Ｂ３とｐ＋型のボディコンタクト領域９ＢＣとを、それぞれ別のマスクを用いて形成する場合を示した。これにより、ｐ型の短辺側ボディ領域７Ｂ３およびｐ＋型のボディコンタクト領域９ＢＣの各々の不純物濃度の設定精度を向上させることができる。 Since the p-type short side body region 7B3 and the p + -type body contact region 9BC described above are formed for different functions and purposes, in the above example, the p-type short side body region 7B3 and The case where the p + -type body contact regions 9BC are formed using different masks is shown. Thereby, the setting accuracy of the impurity concentration of each of the p-type short side body region 7B3 and the p + -type body contact region 9BC can be improved.
　ただし、ｐ型の短辺側ボディ領域７Ｂ３とｐ＋型のボディコンタクト領域９ＢＣとの不純物濃度は近いので、それぞれの機能が達成される範囲であれば同時に形成しても良い。すなわち、図１７に示すように、エピタキシャル層ＥＰの主面上に、ｐ型の短辺側ボディ領域およびｐ＋型のボディコンタクト領域の両方が露出され、それ以外が覆われるマスクＭＥを形成する。続いて、マスクＭＥを不純物注入用のマスクとしてエピタキシャル層ＥＰにｐ型不純物をイオン注入することで、エピタキシャル層ＥＰにｐ型の短辺側ボディ領域７Ｂ３およびｐ＋型のボディコンタクト領域９ＢＣを一括して形成した後、マスクＭＥを除去する。この場合、ｐ型の短辺側ボディ領域７Ｂ３とｐ＋型のボディコンタクト領域９ＢＣとのｐ型不純物の濃度は、ほぼ同じになる。このようにｐ型の短辺側ボディ領域７Ｂ３およびｐ＋型のボディコンタクト領域９ＢＣを同時に形成することにより、パワー半導体装置の製造プロセスの簡略化および製造工程数の削減を実現できる。したがって、パワー半導体装置の生産性を向上させることができる。 However, since the impurity concentrations of the p-type short side body region 7B3 and the p + -type body contact region 9BC are close to each other, they may be simultaneously formed as long as their respective functions can be achieved. That is, as shown in FIG. 17, on the main surface of epitaxial layer EP, mask ME is formed in which both the p-type short side body region and the p + -type body contact region are exposed and the other is covered. . Subsequently, a p-type impurity is ion-implanted into the epitaxial layer EP using the mask ME as a mask for impurity implantation, thereby collectively forming the p-type short side body region 7B3 and the p + -type body contact region 9BC in the epitaxial layer EP. Then, the mask ME is removed. In this case, the concentrations of p-type impurities in the p-type short side body region 7B3 and the p + -type body contact region 9BC are substantially the same. By thus simultaneously forming the p-type short side body region 7B3 and the p + -type body contact region 9BC, simplification of the manufacturing process of the power semiconductor device and reduction of the number of manufacturing steps can be realized. Therefore, the productivity of the power semiconductor device can be improved.
　上記のようにして短辺側ボディ領域７Ｂ３およびボディコンタクト領域９ＢＣを形成した後、半導体基板１Ｓに対して熱処理を施すことで不純物を活性化する。この活性化熱処理の前にエピタキシャル層ＥＰの主面および基板層ＳＢの主面上に、例えば、厚さ０．０５μｍ程度の炭素（Ｃ）からなる表面被覆膜（図示せず）を堆積しても良い。この表面被覆膜は、活性化熱処理の際にエピタキシャル層ＥＰや基板層ＳＢの主面が荒れるのを防止する効果がある。表面被覆膜は、活性化熱処理後に、例えば、酸素プラズマ処理によって除去される。 After the short side body region 7B3 and the body contact region 9BC are formed as described above, the semiconductor substrate 1S is heat-treated to activate the impurities. Before this activation heat treatment, for example, a surface covering film (not shown) made of carbon (C) having a thickness of about 0.05 μm is deposited on the main surface of epitaxial layer EP and the main surface of substrate layer SB. It is good. This surface coating film has an effect of preventing the main surfaces of the epitaxial layer EP and the substrate layer SB from being roughened during the activation heat treatment. The surface coating film is removed by, for example, oxygen plasma treatment after the activation heat treatment.
　図１８はボディコンタクト領域および短辺側ボディ領域の形成工程後の半導体基板の活性領域の要部平面図である。各ソース領域８Ｓの幅方向の中央には、複数のボディコンタクト領域９ＢＣがソース領域８Ｓの長手方向に沿って並んで配置されている。また、各ソース領域８Ｓの長手方向の両端部に隣接する部分には、短辺側ボディ領域７Ｂ３が形成されている。上記図８に示したＹ方向に長い短辺側ボディ領域７Ｂ３を形成する場合は、図１６や図１７に示したマスクＭＤ，ＭＥにおいて短辺側ボディ領域が露出される開口部の平面視での形状を、複数のソース領域８Ｓの配置方向に沿って連続的に延在する形状にすれば良い。
　＜電極の形成、その他＞ FIG. 18 is a plan view of an essential part of an active region of a semiconductor substrate after a process of forming a body contact region and a short side body region. At the center in the width direction of each source region 8S, a plurality of body contact regions 9BC are arranged side by side along the longitudinal direction of source region 8S. Further, short side body regions 7B3 are formed in portions adjacent to both end portions in the longitudinal direction of each source region 8S. When the short side body region 7B3 long in the Y direction shown in FIG. 8 is formed, the planar view of the opening where the short side body region is exposed in the masks MD and ME shown in FIGS. It is preferable that the shape of (.) Be a shape that continuously extends along the arrangement direction of the plurality of source regions 8S.
<Formation of electrodes, others>
　図１９は本実施の形態１の半導体装置を構成するゲート電極の形成工程時の図６のＹ１－Ｙ１線およびＸ１－Ｘ１線に相当する箇所の断面図である。 FIG. 19 is a cross-sectional view of a portion corresponding to the Y1-Y1 line and the X1-X1 line of FIG. 6 in the step of forming the gate electrode constituting the semiconductor device of the first embodiment.
　ここでは、半導体基板１Ｓのエピタキシャル層ＥＰにおいて各チップ領域の外周縁部に選択的に不純物を注入して終端領域ＧＡを形成した後、エピタキシャル層ＥＰの主面上に、例えば、酸化シリコン膜からなるゲート絶縁膜１０ａを熱ＣＶＤ法等により形成する。ゲート絶縁膜１０ａの厚さは、例えば、０．０２～０．２μｍとすることができる。 Here, after the impurity is selectively implanted into the outer peripheral portion of each chip region in the epitaxial layer EP of the semiconductor substrate 1S to form the termination region GA, a silicon oxide film, for example, is formed on the main surface of the epitaxial layer EP. The gate insulating film 10a is formed by a thermal CVD method or the like. The thickness of the gate insulating film 10a can be, for example, 0.02 to 0.2 μm.
　続いて、ゲート絶縁膜１０ａ上に、例えば、ゲート電極形成用のｎ型の多結晶シリコン膜１１を熱ＣＶＤ法等により形成する。この多結晶シリコン膜１１の厚さは、例えば、０．２～０．５μｍ程度である。多結晶シリコン膜１１は、多結晶状態で堆積しても良いし、アモルファス状態で堆積した後に熱処理によって多結晶化させても良い。 Subsequently, for example, an n-type polycrystalline silicon film 11 for forming a gate electrode is formed on the gate insulating film 10a by a thermal CVD method or the like. The thickness of the polycrystalline silicon film 11 is, for example, about 0.2 to 0.5 μm. The polycrystalline silicon film 11 may be deposited in a polycrystalline state, or may be polycrystallized by heat treatment after being deposited in an amorphous state.
　その後、多結晶シリコン膜１１上に、マスクＭＦを形成する。マスクＭＦの平面視での形状は、ゲート電極形成領域を覆い、それ以外を露出させる形状に形成されている。マスクＭＦの材料や形成方法は、マスクＭＡと同じである。 Thereafter, a mask MF is formed on the polycrystalline silicon film 11. The shape of the mask MF in plan view is formed to cover the gate electrode formation region and expose the other regions. The material and forming method of the mask MF are the same as those of the mask MA.
　次いで、マスクＭＦをエッチングマスクとして、多結晶シリコン膜１１に対してドライエッチング処理を施した後、マスクＭＦを除去する。図２０は図１９の工程後の半導体装置の製造工程時の図６のＹ１－Ｙ１線およびＸ１－Ｘ１線に相当する箇所の断面図である。多結晶シリコン膜１１に対してドライエッチング処理を施すことによりゲート電極１１Ｇを形成する。ゲート電極１１Ｇの一部には、開口部１２が形成されている。 Next, dry etching is performed on the polycrystalline silicon film 11 using the mask MF as an etching mask, and then the mask MF is removed. FIG. 20 is a cross-sectional view of a portion corresponding to the Y1-Y1 line and the X1-X1 line of FIG. 6 in the manufacturing process of the semiconductor device after the process of FIG. The polycrystalline silicon film 11 is subjected to dry etching to form a gate electrode 11G. An opening 12 is formed in part of the gate electrode 11G.
　次いで、ゲート電極１１Ｇおよびゲート絶縁膜１０ａを覆うように、エピタキシャル層ＥＰ上に、プラズマＣＶＤ法等により層間絶縁膜１３を堆積した後、層間絶縁膜１３上にマスクＭＧを形成する。マスクＭＧの平面視での形状は、ソースコンタクト領域を露出させ、それ以外を覆う形状に形成されている。マスクＭＧの材料や形成方法は、マスクＭＡと同じである。 Then, an interlayer insulating film 13 is deposited on the epitaxial layer EP by plasma CVD or the like so as to cover the gate electrode 11G and the gate insulating film 10a, and then a mask MG is formed on the interlayer insulating film 13. The shape of the mask MG in a plan view is formed to expose the source contact region and cover the other. The material and formation method of the mask MG are the same as the mask MA.
　続いて、マスクＭＧをエッチングマスクとして、マスクＭＧから露出する層間絶縁膜１３およびゲート絶縁膜１０ａの一部分をドライエッチングにより除去することで、ソースコンタクトＳＣを形成した後、マスクＭＧを除去する。ソースコンタクトＳＣからは、ｎ型のソース領域８Ｓの一部および複数のｐ＋型のボディコンタクト領域９ＢＣが露出されている。 Subsequently, the source contact SC is formed by removing portions of the interlayer insulating film 13 and the gate insulating film 10a exposed from the mask MG by dry etching using the mask MG as an etching mask, and then the mask MG is removed. A portion of n-type source region 8S and a plurality of p + -type body contact regions 9BC are exposed from source contact SC.
　次いで、図示は省略するが、層間絶縁膜１３上に別のマスクを形成し、層間絶縁膜１３をドライエッチング法等により加工して、層間絶縁膜１３にゲート電極１１Ｇの上面一部が露出するコンタクトホール（ゲートコンタクト）を形成する。 Next, although not shown, another mask is formed on the interlayer insulating film 13, and the interlayer insulating film 13 is processed by dry etching or the like to partially expose the upper surface of the gate electrode 11G in the interlayer insulating film 13. Form a contact hole (gate contact).
　続いて、半導体基板１Ｓのエピタキシャル層ＥＰ上に、例えば、チタン（Ｔｉ）膜と、窒化チタン（ＴｉＮ）膜と、アルミニウム膜とを下層から順に堆積して積層膜を形成した後、その積層膜をエッチング法により加工して、ソース電極２Ｓおよびゲート電極２Ｇ（図１参照）を形成する。ソース電極２Ｓは、ソースコンタクトＳＣを通じて、ｎ型のソース領域８Ｓおよび複数のｐ＋型のボディコンタクト領域９ＢＣと電気的に接続されている。また、ゲート電極２Ｇは、上記ゲートコンタクトを通じてゲート電極１１Ｇと電気的に接続されている。 Subsequently, for example, a titanium (Ti) film, a titanium nitride (TiN) film, and an aluminum film are sequentially deposited from the lower layer on the epitaxial layer EP of the semiconductor substrate 1S to form a laminated film, and then the laminated film is formed. Are processed by the etching method to form the source electrode 2S and the gate electrode 2G (see FIG. 1). Source electrode 2S is electrically connected to n type source region 8S and a plurality of p + type body contact regions 9BC through source contact SC. The gate electrode 2G is electrically connected to the gate electrode 11G through the gate contact.
　その後、半導体基板１Ｓの基板層ＳＢの主面に、金属からなるドレイン電極３Ｄを形成する。なお、ドレイン電極３Ｄと基板層ＳＢの主面との電気的接触を取るために、ドレイン電極３Ｄの形成工程に先立って基板層ＳＢの主面に、ｎ型の不純物を高濃度に注入した後、その高濃度不純物注入領域にシリサイド層を形成しておくこともできる。 Thereafter, the drain electrode 3D made of metal is formed on the main surface of the substrate layer SB of the semiconductor substrate 1S. In order to electrically contact drain electrode 3D with the main surface of substrate layer SB, an n-type impurity is heavily implanted into the main surface of substrate layer SB prior to the step of forming drain electrode 3D. Alternatively, a silicide layer can be formed in the high concentration impurity implantation region.
　以上の工程を経た後、半導体基板１Ｓを個々のチップに分割することで、図１に示したＤＭＯＳＦＥＴを有するチップ１Ｃを製造することができる。 After the above steps, the semiconductor substrate 1S is divided into individual chips, whereby the chip 1C having the DMOSFET shown in FIG. 1 can be manufactured.
　以上のように本実施の形態１では、短辺側ボディ領域７Ｂ３の形成のためのイオン注入が１回追加されるだけである。また、イオン注入時に半導体基板１Ｓを回転させることもない。このため、特許文献１の場合よりもパワー半導体装置の製造時間を短縮でき、パワー半導体装置の生産性を向上させることができる。また、イオン注入時に半導体基板１Ｓを回転させることもないので、イオン注入装置の構成を簡単化できる。
　（実施の形態２）
　＜実施の形態２の半導体装置の構成例＞ As described above, in the first embodiment, only one ion implantation for forming the short side body region 7B3 is added. In addition, the semiconductor substrate 1S is not rotated at the time of ion implantation. For this reason, the manufacturing time of a power semiconductor device can be shortened compared with the case of patent document 1, and the productivity of a power semiconductor device can be improved. In addition, since the semiconductor substrate 1S is not rotated at the time of ion implantation, the configuration of the ion implantation apparatus can be simplified.
Second Embodiment
<Configuration Example of Semiconductor Device of Second Embodiment>
　図２１は本実施の形態２の半導体装置の活性領域の要部拡大平面図、図２２は図２１のＸ１－Ｘ１線の断面図である。 FIG. 21 is an enlarged plan view of an essential part of the active region of the semiconductor device of the second embodiment, and FIG. 22 is a cross-sectional view taken along the line X1-X1 of FIG.
　本実施の形態２では、ソース領域８Ｓの長手方向の両端部(短辺)に隣接する領域のエピタキシャル層ＥＰ上に、厚いフィールド絶縁膜（第１絶縁膜）１０ｂが部分的に設けられており、さらにその上にゲート絶縁膜１０ａを介してゲート電極１１Ｇが設けられている。フィールド絶縁膜１０ｂは、ゲート絶縁膜１０ａと同じ酸化シリコン膜からなるが、フィールド絶縁膜１０ｂの厚さは、例えば、２００ｎｍ～５μｍの範囲であり、ゲート絶縁膜１０ａの厚さ（例えば、０．０２μｍ～０．２μｍ）よりも厚い。これにより、ゲート電極１１Ｇに電圧を印加した際に、ソース領域８Ｓの長手方向の両端部(短辺)に隣接する領域では、エピタキシャル層ＥＰの表面に及ぼされる電界強度が弱められる。 In the second embodiment, thick field insulating film (first insulating film) 10b is partially provided on epitaxial layer EP in a region adjacent to both ends (short sides) in the longitudinal direction of source region 8S. Further, a gate electrode 11G is provided thereon via a gate insulating film 10a. The field insulating film 10b is made of the same silicon oxide film as the gate insulating film 10a, but the thickness of the field insulating film 10b is, for example, in the range of 200 nm to 5 μm, and the thickness of the gate insulating film 10a (for example, 0. Thicker than 02 μm to 0.2 μm). Thereby, when a voltage is applied to the gate electrode 11G, the electric field intensity exerted on the surface of the epitaxial layer EP is weakened in the regions adjacent to both ends (short sides) in the longitudinal direction of the source region 8S.
　これに対して、ソース領域８Ｓの幅方向の両端部(長辺)に隣接する領域においてエピタキシャル層ＥＰ（ｐ型の長辺側ボディ領域７Ｂ２）上には、前記実施の形態１と同様に、ゲート絶縁膜１０ａを介してゲート電極１１Ｇが配置されている。すなわち、ソース領域８Ｓの幅方向の両端部(長辺)に隣接する領域では、薄いゲート絶縁膜１０ａを介してゲート電極１１Ｇの電圧の影響を受ける。 On the other hand, on the epitaxial layer EP (p-type long side body region 7B2) in the regions adjacent to both ends (long sides) in the width direction of the source region 8S, as in the first embodiment, The gate electrode 11G is disposed via the gate insulating film 10a. That is, in the regions adjacent to both ends (long sides) in the width direction of the source region 8S, the voltage of the gate electrode 11G is affected via the thin gate insulating film 10a.
　このため、単位セルＵＣのソース領域８Ｓの長手方向の両端部（短辺）に隣接する部分に形成されるチャネルのしきい値電圧は、単位セルＵＣのソース領域８Ｓの幅方向の両端部（長辺）に隣接する部分に形成されるチャネルのしきい値電圧より高くなっている。なお、ここでは、フィールド絶縁膜１０ｂの一部が平面視でソース領域８Ｓの長手方向の両端部の一部と重なっている。また、本実施の形態２では、短辺側ボディ領域７Ｂ３が形成されていない。 Therefore, the threshold voltage of the channel formed in the portion adjacent to the both ends (short side) in the longitudinal direction of source region 8S of unit cell UC is the both ends in the width direction of source region 8S of unit cell UC. It is higher than the threshold voltage of the channel formed in the portion adjacent to the long side). Here, a part of the field insulating film 10b overlaps with a part of both end portions in the longitudinal direction of the source region 8S in plan view. Further, in the second embodiment, the short side body region 7B3 is not formed.
　また、本実施の形態２では、ゲート電極１１Ｇの開口部１２の長手方向（Ｘ方向）の両端部が、単位セルＵＣのソース領域８Ｓの長手方向の両端部より外側に位置している。すなわち、ゲート電極１１Ｇは、ソース領域８Ｓの長手方向の両端部から離れた位置に形成されている。しかも、ゲート電極１１Ｇの開口部１２の長手方向の両端部がフィールド絶縁膜１０ｂおよびゲート絶縁膜１０ａの積層膜上に形成されている。すなわち、単位セルＵＣのソース領域８Ｓの長手方向の両端部に隣接する部分（短辺側）は厚いフィールド絶縁膜１０ｂと薄いゲート絶縁膜１０ａとの積層膜を介してゲート電極１１Ｇの電圧の影響を受ける。これにより、単位セルＵＣのソース領域８Ｓの長手方向の両端部に隣接する部分（短辺側）では、ゲート電圧の影響をより一層小さくすることができる。 Further, in the second embodiment, both end portions in the longitudinal direction (X direction) of the opening 12 of the gate electrode 11G are located outside the both end portions in the longitudinal direction of the source region 8S of the unit cell UC. That is, the gate electrode 11G is formed at a position apart from both end portions in the longitudinal direction of the source region 8S. Moreover, both end portions in the longitudinal direction of the opening 12 of the gate electrode 11G are formed on the laminated film of the field insulating film 10b and the gate insulating film 10a. That is, the part (short side) adjacent to both ends in the longitudinal direction of source region 8S of unit cell UC is affected by the voltage of gate electrode 11G through the stacked film of thick field insulating film 10b and thin gate insulating film 10a. Receive Thus, the influence of the gate voltage can be further reduced in portions (short sides) adjacent to both ends of the source region 8S of the unit cell UC in the longitudinal direction.
　一方、ゲート電極１１Ｇの開口部１２の幅方向の両端部は、単位セルＵＣのソース領域８Ｓの幅方向の両端部より内側に位置している。このため、ソース領域８Ｓの幅方向に隣接する部分では、薄いゲート絶縁膜１０ａのみを介してゲート電極１１Ｇが設けられている。すなわち、単位セルＵＣのソース領域８Ｓの幅方向の両端部に隣接する部分（長辺側）は薄いゲート絶縁膜１０ａのみを介してゲート電極１１Ｇの電圧の影響を受ける。これにより、単位セルＵＣのソース領域８Ｓの幅方向の両端部に隣接する部分（長辺側）では、ゲート電圧の影響をより大きくすることができる。 On the other hand, both ends in the width direction of the opening 12 of the gate electrode 11G are located inside the both ends in the width direction of the source region 8S of the unit cell UC. Therefore, the gate electrode 11G is provided only at the thin gate insulating film 10a in a portion adjacent to the source region 8S in the width direction. That is, portions (long sides) adjacent to both ends in the width direction of the source region 8S of the unit cell UC are affected by the voltage of the gate electrode 11G only via the thin gate insulating film 10a. As a result, the influence of the gate voltage can be further increased in portions (long sides) adjacent to both ends in the width direction of the source region 8S of the unit cell UC.
　したがって、ソース領域８Ｓの長手方向の両端部（短辺）に隣接する部分に形成されるチャネルのしきい値電圧が、ソース領域８Ｓの幅方向の両端部（長辺）に隣接する部分に形成されるチャネルのしきい値電圧よりさらに高くなっている。 Therefore, the threshold voltage of the channel formed in the portion adjacent to both ends (short side) in the longitudinal direction of source region 8S is formed in the portion adjacent to both ends (long side) in the width direction of source region 8S. Higher than the threshold voltage of the channel being
　ただし、フィールド絶縁膜１０ｂの厚さが充分に厚い場合は、前記実施の形態１と同様に、ゲート電極１１Ｇの開口部１２の長手方向の両端部が、フィールド絶縁膜１０ｂが設けられていない、ソース領域８Ｓの内側に位置するように、開口部１２を形成しても良い。ここで、フィールド絶縁膜１０ｂの厚さが充分に厚いという場合は、下記の式（１）を満たしている。
　　　　　ｔｏｘ１×√ＮＡ１＞ｔｏｘ２×√ＮＡ２　　　　　（１） However, when the thickness of the field insulating film 10b is sufficiently thick, the field insulating film 10b is not provided at both ends in the longitudinal direction of the opening 12 of the gate electrode 11G, as in the first embodiment. The opening 12 may be formed to be located inside the source region 8S. Here, in the case where the thickness of the field insulating film 10 b is sufficiently thick, the following formula (1) is satisfied.
tox1 × √NA1> tox2 × √NA2 (1)
　ＮＡ１はソース領域８Ｓの長手方向に両端部（短辺）に隣接する部分のｐ型不純物の濃度、ｔｏｘ１はソース領域８Ｓの長手方向に両端部（短辺）に隣接する部分の上に形成された絶縁膜の厚さ（例：フィールド絶縁膜１０ｂの厚さとゲート絶縁膜１０ａの厚さとの和）である。また、ＮＡ２はソース領域８Ｓの幅方向に両端部（長辺）に隣接する部分のｐ型不純物の濃度、ｔｏｘ２はソース領域８Ｓの幅方向に両端部（長辺）に隣接する部分の上に形成された絶縁膜の厚さ（例：ゲート絶縁膜１０ａの厚さ）である。 NA1 is a concentration of p-type impurities in a portion adjacent to both ends (short side) in the longitudinal direction of source region 8S, and tox1 is formed on a portion adjacent to both ends (short side) in the longitudinal direction of source region 8S The thickness of the insulating film (eg, the sum of the thickness of the field insulating film 10 b and the thickness of the gate insulating film 10 a). Also, NA2 is the concentration of p-type impurities in a portion adjacent to both ends (long side) in the width direction of the source region 8S, and tox2 is on a portion adjacent to both ends (long side) in the width direction of the source region 8S. It is the thickness of the formed insulating film (example: thickness of the gate insulating film 10a).
　ここでは、図２１に示すように、フィールド絶縁膜１０ｂが、複数の単位セルＵＣを接続するようにＹ方向に沿って連続的に延在した状態で形成されている。これにより、フィールド絶縁膜１０ｂを形成するときのマスクの寸法を大きくとれるので、フィールド絶縁膜１０ｂをより容易に形成することができる。ただし、フィールド絶縁膜１０ｂは、上記したリーク電流を抑制または防止すべく各単位セルＵＣのソース領域８Ｓの長手方向の両端部を覆うように形成されていれば良い。図２３はフィールド絶縁膜の変形例を示す半導体基板の要部平面図である。図２３では、フィールド絶縁膜１０ｂが、単位セルＵＣ毎に分離されている。 Here, as shown in FIG. 21, field insulating film 10b is formed to extend continuously along the Y direction so as to connect a plurality of unit cells UC. As a result, the dimensions of the mask when forming the field insulating film 10b can be increased, so that the field insulating film 10b can be formed more easily. However, the field insulating film 10b may be formed to cover both longitudinal ends of the source region 8S of each unit cell UC in order to suppress or prevent the above-described leakage current. FIG. 23 is a plan view of relevant parts of a semiconductor substrate showing a modification of the field insulating film. In FIG. 23, the field insulating film 10b is separated for each unit cell UC.
　また、ここでは、フィールド絶縁膜１０ｂを設ける場合について説明したが、フィールド絶縁膜１０ｂを設けないで、ゲート電極１１Ｇの開口部１２の形状や配置を上記のようにするだけでも良い。すなわち、ゲート電極１１Ｇの開口部１２の長手方向（Ｘ方向）の両端部をソース領域８Ｓの長手方向の両端部より外側に位置させ、ゲート電極１１Ｇの開口部１２の幅方向（Ｙ方向）の両端部をソース領域８Ｓの幅方向の両端部より内側に位置させても良い。これにより、ソース領域８Ｓの長手方向の両端部（短辺）に隣接する部分のしきい値電圧を、ソース領域８Ｓの幅方向の両端部（長辺）に隣接する部分に形成されるチャネルのしきい値電圧より高くすることができる。
　＜実施の形態２の半導体装置の製造方法例＞ Although the case where the field insulating film 10b is provided is described here, the shape and the arrangement of the opening 12 of the gate electrode 11G may be simply as described above without providing the field insulating film 10b. That is, both end portions in the longitudinal direction (X direction) of the opening 12 of the gate electrode 11G are positioned outside the both ends in the longitudinal direction of the source region 8S, and the width direction (Y direction) of the opening 12 of the gate electrode 11G is Both ends may be located inside the both ends in the width direction of the source region 8S. Thus, the threshold voltage of a portion adjacent to both ends (short side) in the longitudinal direction of source region 8S is set to a channel formed in the portion adjacent to both ends (long side) in the width direction of source region 8S. It can be higher than the threshold voltage.
<Example of Method of Manufacturing Semiconductor Device of Embodiment 2>
　本実施の形態２の半導体装置例の製造においては、上記ボディコンタクト領域の形成工程（図１８の工程）までは、実施の形態１と同様の方法を用いることができる（ただし、本実施の形態２では短辺側ボディ領域７Ｂ３が形成されていない）。したがって、ここでは、それ以降の工程について図２４～図２６を参照して説明する。 In the manufacture of the semiconductor device example of the second embodiment, the same method as that of the first embodiment can be used up to the step of forming the body contact region (step of FIG. 18) (however, the present embodiment). In No. 2, the short side body region 7B3 is not formed). Therefore, the following steps will be described with reference to FIGS. 24 to 26.
　図２４は本実施の形態２の半導体装置を構成するフィールド絶縁膜の形成工程時の図６のＹ１－Ｙ１線およびＸ１－Ｘ１線に相当する箇所の断面図である。 FIG. 24 is a cross-sectional view of a portion corresponding to the Y1-Y1 line and the X1-X1 line of FIG. 6 in the step of forming the field insulating film constituting the semiconductor device of the second embodiment.
　まず、エピタキシャル層ＥＰの上に、フィールド絶縁膜１０ｂをＣＶＤ法等により成膜する。続いて、フィールド絶縁膜１０ｂ上に、マスクＭＨを形成する。マスクＭＨは、フィールド絶縁膜１０ｂの形成領域を覆い、それ以外が露出されるように形成されている。マスクＭＨの材料や形成方法は、マスクＭＡと同じである。その後、マスクＭＨをエッチングマスクとして、マスクＭＨから露出するフィールド絶縁膜１０ｂをエッチング除去してエピタキシャル層ＥＰの表面の一部を露出させる。その後、マスクＭＨを除去する。 First, the field insulating film 10b is formed on the epitaxial layer EP by the CVD method or the like. Subsequently, a mask MH is formed on the field insulating film 10b. The mask MH is formed to cover the formation region of the field insulating film 10 b and expose the other regions. The material and formation method of the mask MH are the same as the mask MA. Thereafter, using mask MH as an etching mask, field insulating film 10b exposed from mask MH is etched away to expose a part of the surface of epitaxial layer EP. Thereafter, the mask MH is removed.
　図２５は図２４の工程後の本実施の形態２の半導体装置を構成する多結晶シリコン膜の成膜工程時の図６のＹ１－Ｙ１線およびＸ１－Ｘ１線に相当する箇所の断面図である。 FIG. 25 is a cross-sectional view of a portion corresponding to the Y1-Y1 line and the X1-X1 line of FIG. 6 during the film formation step of the polycrystalline silicon film constituting the semiconductor device of Embodiment 2 after the step of FIG. is there.
　ここでは、フィールド絶縁膜１０ｂを覆うように、エピタキシャル層ＥＰ上にゲート絶縁膜１０ａおよび多結晶シリコン膜１１をＣＶＤ法等により下層から順に堆積する。続いて、多結晶シリコン膜１１上に、マスクＭＪを形成する。マスクＭＪは、ゲート電極の形成領域を覆い、それ以外が露出されるように形成されている。マスクＭＪの材料や形成方法は、マスクＭＡと同じである。 Here, the gate insulating film 10a and the polycrystalline silicon film 11 are sequentially deposited from the lower layer by the CVD method or the like on the epitaxial layer EP so as to cover the field insulating film 10b. Subsequently, a mask MJ is formed on the polycrystalline silicon film 11. The mask MJ is formed to cover the formation region of the gate electrode and to expose the other. The material and formation method of the mask MJ are the same as the mask MA.
　図２６は図２５の工程後の本実施の形態２の半導体装置を構成するソースコンタクト形成工程後の図６のＹ１－Ｙ１線およびＸ１－Ｘ１線に相当する箇所の断面図である。 FIG. 26 is a cross-sectional view of a portion corresponding to the Y1-Y1 line and the X1-X1 line of FIG. 6 after the source contact forming step of the semiconductor device of the second embodiment after the step of FIG.
　ここでは、上記マスクＭＪ（図２５参照）をエッチングマスクとして、多結晶シリコン膜１１をドライエッチング法により加工して、ゲート電極１１Ｇを形成するとともに、開口部１２を形成した後、マスクＭＪを除去する。 Here, using the mask MJ (see FIG. 25) as an etching mask, the polycrystalline silicon film 11 is processed by dry etching to form the gate electrode 11G, and after the opening 12 is formed, the mask MJ is removed. Do.
　次いで、前記実施の形態１と同様に、ゲート電極１１Ｇおよびゲート絶縁膜１０ａを覆うように、例えば、プラズマＣＶＤ法により層間絶縁膜１３を形成した後、層間絶縁膜１３上にマスク（図示せず）を形成する。続いて、そのマスクをエッチングマスクとして、層間絶縁膜１３およびゲート絶縁膜１０ａをドライエッチングにより加工して、ｎ型のソース領域８Ｓの表面の一部およびｐ＋型のボディコンタクト領域９ＢＣの表面が露出するソースコンタクトＳＣを形成する。また、前記実施の形態１と同様に、層間絶縁膜１３上に別のマスクを形成し、これをエッチングマスクとして、層間絶縁膜１３にゲート電極１１Ｇの一部が露出するゲートコンタクトを形成する。 Next, as in the first embodiment, an interlayer insulating film 13 is formed by, eg, plasma CVD to cover the gate electrode 11G and the gate insulating film 10a, and then a mask (not shown) is formed on the interlayer insulating film 13. Form). Subsequently, using the mask as an etching mask, interlayer insulating film 13 and gate insulating film 10a are processed by dry etching to form part of the surface of n-type source region 8S and the surface of p + -type body contact region 9BC. An exposed source contact SC is formed. Further, as in the first embodiment, another mask is formed on the interlayer insulating film 13, and this is used as an etching mask to form a gate contact in the interlayer insulating film 13 in which a part of the gate electrode 11G is exposed.
　これ以降は、前記実施の形態１と同様にして、ソース電極２Ｓ、ゲート電極２Ｇおよびドレイン電極３Ｄを形成して、図２１および図２２に示した本実施の形態２の半導体装置を製造する。
　（実施の形態３）
　＜半導体装置の構成例＞ After this, the source electrode 2S, the gate electrode 2G and the drain electrode 3D are formed in the same manner as in the first embodiment, and the semiconductor device of the second embodiment shown in FIGS. 21 and 22 is manufactured.
Third Embodiment
<Configuration Example of Semiconductor Device>
　図２７は本実施の形態３の半導体装置の活性領域の要部拡大平面図、図２８は図２７のＸ１－Ｘ１線の断面図である。 FIG. 27 is an enlarged plan view of an essential part of the active region of the semiconductor device according to the third embodiment, and FIG. 28 is a cross-sectional view taken along line X1-X1 of FIG.
　本実施の形態３では、前記実施の形態２で説明した構造において、前記実施の形態１と同様に、単位セルＵＣのソース領域８Ｓの長手方向の両端部に隣接する部分に、短辺側ボディ領域７Ｂ３が形成されている。 In the third embodiment, in the structure described in the second embodiment, as in the first embodiment, the short side body is provided in portions adjacent to both end portions of the source region 8S of the unit cell UC in the longitudinal direction. Region 7B3 is formed.
　前記実施の形態１では、製造工程上の理由等により短辺側ボディ領域７Ｂ３に含まれるｐ型不純物の濃度を充分に高くできない場合がある。また、前記実施の形態２では、フィールド絶縁膜１０ｂの厚さを充分に厚くできない場合がある。それらの場合、単位セルＵＣのソース領域８Ｓの両端部（短辺）に隣接する部分のしきい値電圧が、ソース領域８Ｓの幅方向の両端部（長辺）に隣接する部分のしきい値電圧より高くできない場合がある。 In the first embodiment, the concentration of the p-type impurity contained in the short side body region 7B3 may not be sufficiently high due to reasons such as the manufacturing process. In the second embodiment, the thickness of the field insulating film 10b may not be sufficiently thick. In those cases, the threshold voltage of a portion adjacent to both ends (short side) of source region 8S of unit cell UC is the threshold voltage of a portion adjacent to both ends (long side) of source region 8S in the width direction. Sometimes it can not be higher than the voltage.
　そこで、その場合は、短辺側ボディ領域７Ｂ３と厚いフィールド絶縁膜１０ｂとの両方を設けることにより、単位セルＵＣのソース領域８Ｓの両端部に隣接する部分（短辺側）のしきい値電圧を、ソース領域８Ｓの幅方向の両端部に隣接する部分（長辺側）のしきい値電圧より高くすることができる。 Therefore, in this case, by providing both the short side body region 7B3 and the thick field insulating film 10b, the threshold voltage of the portion (short side) adjacent to both ends of the source region 8S of the unit cell UC. Can be set higher than the threshold voltage of the portion (long side) adjacent to both ends in the width direction of the source region 8S.
　また、本実施の形態３でも、前記実施の形態２と同様に、ゲート電極１１Ｇの開口部１２の長手方向の両端部がソース領域８Ｓの長手方向の両端部より外側に位置している。そして、ソース領域８Ｓの長手方向の両端部側に位置するゲート電極１１Ｇが厚いフィールド絶縁膜１０ｂおよびゲート絶縁膜１０ａの積層膜上に形成されている。これにより、単位セルＵＣのソース領域８Ｓの長手方向の両端部に隣接する部分（短辺側）ではゲート電圧の影響をより小さくすることができる。 Further, also in the third embodiment, as in the second embodiment, both end portions in the longitudinal direction of the opening 12 of the gate electrode 11G are located outside the both end portions in the longitudinal direction of the source region 8S. Then, gate electrodes 11G located on both end sides in the longitudinal direction of the source region 8S are formed on the laminated film of the thick field insulating film 10b and the gate insulating film 10a. As a result, the influence of the gate voltage can be further reduced in portions (short sides) adjacent to both ends of the source region 8S of the unit cell UC in the longitudinal direction.
　一方、前記実施の形態２と同様に、ゲート電極１１Ｇの開口部１２の幅方向の両端部が、ソース領域８Ｓの幅方向の両端部より内側に位置している。そして、ソース領域８Ｓの幅方向の両端部側に位置するゲート電極１１Ｇが薄いゲート絶縁膜１０ａ上に形成されている。これにより、単位セルＵＣのソース領域８Ｓの幅方向の両端部に隣接する部分（長辺側）ではゲート電圧の影響をより大きくすることができる。 On the other hand, as in the second embodiment, both end portions in the width direction of the opening 12 of the gate electrode 11G are located inside the both end portions in the width direction of the source region 8S. Then, gate electrodes 11G located on both end sides in the width direction of the source region 8S are formed on the thin gate insulating film 10a. As a result, the influence of the gate voltage can be further increased in portions (long sides) adjacent to both ends in the width direction of the source region 8S of the unit cell UC.
　したがって、単位セルＵＣのソース領域８Ｓの長手方向の両端部に隣接する部分（短辺側）のチャネルのしきい値電圧を、単位セルＵＣのソース領域８Ｓの幅方向の両端部に隣接する部分（長辺側）のチャネルのしきい値電圧よりさらに高くすることができる。 Therefore, the threshold voltage of the channel (short side) adjacent to both ends in the longitudinal direction of source region 8S of unit cell UC is the portion adjacent to both ends in the width direction of source region 8S of unit cell UC. It can be made higher than the threshold voltage of the (long side) channel.
　本実施の形態３においても、ｔｏｘ１×√ＮＡ１＞ｔｏｘ２×√ＮＡ２（上記式（１））を満たしていれば良い。 Also in the third embodiment, it suffices to satisfy tox1 × √NA1> tox2 × NA2 (the above equation (1)).
　ただし、フィールド絶縁膜１０ｂの厚さや短辺側ボディ領域７Ｂ３の効果が充分な場合は、ゲート電極１１Ｇの開口部１２の長手方向の両端部が、フィールド絶縁膜１０ｂが設けられていない、ソース領域８Ｓの領域内に位置するように、開口部１２を形成しても良い。 However, when the thickness of the field insulating film 10b and the effect of the short side body region 7B3 are sufficient, both end portions in the longitudinal direction of the opening 12 of the gate electrode 11G are not provided with the field insulating film 10b. The opening 12 may be formed to be located in the area of 8S.
　短辺側ボディ領域７Ｂ３の形成工程は前記実施の形態１と同じである。また、フィールド絶縁膜１０ｂの形成工程は前記実施の形態２と同じなので、本実施の形態３の半導体装置の製造方法例は省略する。 The process of forming the short side body region 7B3 is the same as that of the first embodiment. Further, since the step of forming field insulating film 10b is the same as that of the second embodiment, the example of the method of manufacturing the semiconductor device of the third embodiment is omitted.
　なお、本発明は上記した実施の形態に限定されるものではなく、様々な変形例が含まれる。例えば、上記した実施の形態は発明を分かりやすく説明するために詳細に説明したものであり、必ずしも説明した全ての構成を備えるものに限定されるものではない。また、ある実施の形態の構成の一部を他の実施の形態の構成に置き換えることが可能である。また、ある実施の形態の構成に他の実施の形態の構成を加えることも可能である。また、各実施の形態の構成の一部について、他の構成の追加・削除・置換をすることが可能である。 The present invention is not limited to the above-described embodiment, but includes various modifications. For example, the above-described embodiment has been described in detail in order to explain the invention in an easy-to-understand manner, and is not necessarily limited to one having all the described configurations. In addition, part of the configuration of one embodiment can be replaced with the configuration of another embodiment. In addition, it is possible to add the configuration of another embodiment to the configuration of one embodiment. In addition, with respect to a part of the configuration of each embodiment, it is possible to add, delete, and replace other configurations.
　また、トランジスタの「ソース」や「ドレイン」の機能は、異なる極性のトランジスタを採用する場合や、回路動作において電流の方向が変化する場合等には入れ替わることがある。このため、本明細書においては、「ソース」や「ドレイン」の用語は、入れ替えて用いることができる。 In addition, the functions of the “source” and the “drain” of the transistor may be switched when adopting transistors of different polarities, when the direction of current changes in circuit operation, or the like. Therefore, in the present specification, the terms "source" and "drain" can be used interchangeably.
　また、本明細書において「電極」や「配線」の用語は、これらの構成要素を機能的に限定するものではない。例えば、「電極」は「配線」の一部として用いられることがあり、その逆もまた同様である。さらに、「電極」や「配線」の用語は、複数の「電極」や「配線」が一体となって形成されている場合等も含む。 Further, in the present specification, the terms "electrode" and "wiring" do not functionally limit these components. For example, "electrodes" may be used as part of "wirings" and vice versa. Furthermore, the terms “electrode” and “wiring” include the case where a plurality of “electrodes” and “wirings” are integrally formed.
　また、前記実施の形態では、スイッチングトランジスタとして、ＤＭＯＳＦＥＴを例示したが、これに限定されるものではなく、例えば、ＩＧＢＴ（Insulated Gate Bipolar Transistor）を用いても良い。また、例えば、ＤＭＯＳＦＥＴやＩＧＢＴ等のようなスイッチングトランジスタを有するインバータに適用できる。また、例えば、ＤＭＯＳＦＥＴやＩＧＢＴ等のようなスイッチングトランジスタを有するパワーモジュールに適用できる。 Moreover, in the said embodiment, although DMOSFET was illustrated as a switching transistor, it is not limited to this, For example, you may use IGBT (Insulated Gate Bipolar Transistor). Further, for example, the present invention can be applied to an inverter having a switching transistor such as a DMOSFET or an IGBT. Further, for example, the present invention can be applied to a power module having a switching transistor such as a DMOSFET or an IGBT.
　１Ｃ　半導体チップ
　１Ｓ　半導体基板
　２Ｓ　ソース電極
　２Ｇ　ゲート電極
　３Ｄ　ドレイン電極
　７Ｂ１　埋込ボディ領域
　７Ｂ２　長辺側ボディ領域
　７Ｂ３　短辺側ボディ領域
　８Ｓ　ソース領域
　９ＢＣ　ボディコンタクト領域
　１０ａ　ゲート絶縁膜
　１０ｂ　フィールド絶縁膜
　１１　多結晶シリコン膜
　１１Ｇ　ゲート電極
　１２　開口部
　１３　層間絶縁膜
　ＥＰ　エピタキシャル層
　ＳＢ　基板層
　ＡＣＡ　活性領域
　ＵＣ　単位セル
　ＦＡ　フィールド領域
　ＧＡ　終端領域
　ＳＣ　ソースコンタクト 1C semiconductor chip 1S semiconductor substrate 2S source electrode 2G gate electrode 3D drain electrode 7B1 embedded body region 7B2 long side body region 7B3 short side body region 8S source region 9BC body contact region 10a gate insulating film 10b field insulating film 11 polycrystal Silicon film 11G Gate electrode 12 Opening 13 Interlayer dielectric EP EP layer SB Substrate layer ACA Active area UC Unit cell FA Field area GA Termination area SC Source contact

Claims (15)

  1. 　第１面と、前記第１面の反対側の第２面とを有する第１導電型の半導体基板と、
    　前記半導体基板の前記第１面に設けられ、平面視で第１方向の長さが前記第１方向に交差する第２方向の長さより長く、かつ、断面視で前記第１面から前記半導体基板の深さ方向に延びる第１導電型の第１半導体領域と、
    　前記半導体基板に設けられ、平面視で前記第１半導体領域を覆い、かつ、断面視で前記第１半導体領域の底部から前記半導体基板の深さ方向に延びる、前記第１導電型とは逆の第２導電型の第２半導体領域と、
    　前記半導体基板の前記第１面に設けられ、平面視で前記第１半導体領域の前記第２方向の両端部に隣接し、かつ、断面視で前記第１面から前記第２半導体領域に達するように延びる第２導電型の第３半導体領域と、
    　前記半導体基板の前記第１面上に絶縁膜を介して設けられたゲート電極と、
    　を備え、
    　前記第１半導体領域の前記第１方向の両端部に隣接する第１部分のしきい値電圧は、前記第１半導体領域の前記第２方向の両端部に隣接する第２部分のしきい値電圧より高い、半導体装置。     A semiconductor substrate of a first conductivity type having a first surface and a second surface opposite to the first surface;
    The semiconductor substrate is provided on the first surface of the semiconductor substrate, and the length in the first direction is longer than the length in the second direction intersecting the first direction in a plan view, and the semiconductor substrate from the first surface in a cross sectional view A first semiconductor region of a first conductivity type extending in the depth direction of
    Reverse to the first conductivity type, provided on the semiconductor substrate, covering the first semiconductor region in plan view, and extending in the depth direction of the semiconductor substrate from the bottom of the first semiconductor region in cross section A second semiconductor region of a second conductivity type,
    Provided on the first surface of the semiconductor substrate, adjacent to both ends of the first semiconductor region in the second direction in a plan view, and reaching the second semiconductor region from the first surface in a cross sectional view A third semiconductor region of the second conductivity type extending
    A gate electrode provided via an insulating film on the first surface of the semiconductor substrate;
    Equipped with
    The threshold voltage of a first portion adjacent to both ends of the first semiconductor region in the first direction is the threshold voltage of a second portion adjacent to both ends of the first semiconductor region in the second direction. Higher semiconductor devices.
  2. 　請求項１記載の半導体装置において、
    　前記第１部分に、前記第１半導体領域の前記第１方向の両端部の側部を覆うように、前記第１面から前記第２半導体領域に達するように延びる第２導電型の第４半導体領域を設け、
    　前記第４半導体領域の第２導電型の不純物の濃度は、前記第３半導体領域の第２導電型の不純物の濃度より高い、半導体装置。     In the semiconductor device according to claim 1,
    A fourth semiconductor of a second conductivity type that extends from the first surface to the second semiconductor region so as to cover side portions of both ends of the first semiconductor region in the first direction in the first portion. Set the area,
    The semiconductor device, wherein the concentration of the second conductivity type impurity of the fourth semiconductor region is higher than the concentration of the second conductivity type impurity of the third semiconductor region.
  3. 　請求項２記載の半導体装置において、
    　前記絶縁膜は、前記第１部分上に形成された第１絶縁膜と、前記第２部分上に形成された第２絶縁膜とを備え、
    　前記第１絶縁膜の厚さは、前記第２絶縁膜より厚い、半導体装置。     In the semiconductor device according to claim 2,
    The insulating film includes a first insulating film formed on the first portion and a second insulating film formed on the second portion,
    The thickness of the said 1st insulating film is a semiconductor device thicker than the said 2nd insulating film.
  4. 　請求項３記載の半導体装置において、
    　前記第１半導体領域の前記第１方向の両端部側に位置する前記ゲート電極は、前記第１半導体領域の前記第１方向の両端部から離れており、
    　前記第１半導体領域の前記第２方向の両端部側に位置する前記ゲート電極は、前記第３半導体領域に平面視で重なっている、半導体装置。     In the semiconductor device according to claim 3,
    The gate electrodes positioned on both end sides in the first direction of the first semiconductor region are apart from both ends in the first direction of the first semiconductor region,
    A semiconductor device, wherein the gate electrodes positioned on both end sides in the second direction of the first semiconductor region overlap the third semiconductor region in plan view.
  5. 　請求項１記載の半導体装置において、
    　前記第１部分の第２導電型の不純物の濃度をＮＡ１、前記絶縁膜のうち、前記第１部分上に形成された第１絶縁膜の厚さをｔｏｘ１とし、
    　前記第２部分の第２導電型の不純物の濃度をＮＡ２、前記絶縁膜のうち、前記第２部分上に形成された第２絶縁膜の厚さをｔｏｘ２としたときに、
    　ｔｏｘ１×√ＮＡ１＞ｔｏｘ２×√ＮＡ２
    　の関係を満たす、半導体装置。     In the semiconductor device according to claim 1,
    The concentration of the second conductivity type impurity of the first portion is NA1, and the thickness of the first insulating film formed on the first portion of the insulating film is tox1.
    Assuming that the concentration of the second conductivity type impurity of the second portion is NA2, and the thickness of the second insulating film formed on the second portion of the insulating film is tox2.
    tox1 × √NA1> tox2 × √NA2
    A semiconductor device that satisfies the relationship of
  6. 　請求項１記載の半導体装置において、
    　前記絶縁膜は、前記第１部分上に形成された第１絶縁膜と、前記第２部分上に形成された第２絶縁膜とを有し、
    　前記第１絶縁膜の厚さは、前記第２絶縁膜より厚い、半導体装置。     In the semiconductor device according to claim 1,
    The insulating film includes a first insulating film formed on the first portion and a second insulating film formed on the second portion,
    The thickness of the said 1st insulating film is a semiconductor device thicker than the said 2nd insulating film.
  7. 　請求項６記載の半導体装置において、
    　前記第１半導体領域の前記第１方向の両端部側に位置する前記ゲート電極は、前記第１半導体領域の前記第１方向の両端部から離れた状態で前記第１絶縁膜上に設けられ、
    　前記第１半導体領域の前記第２方向の両端部側に位置する前記ゲート電極は、前記第３半導体領域に平面視で重なった状態で前記第２絶縁膜上に設けられている、半導体装置。     In the semiconductor device according to claim 6,
    The gate electrodes located on both end sides of the first semiconductor region in the first direction are provided on the first insulating film in a state of being separated from both ends of the first semiconductor region in the first direction,
    The semiconductor device, wherein the gate electrodes located on both end sides in the second direction of the first semiconductor region are provided on the second insulating film in a state of being overlapped with the third semiconductor region in plan view.
  8. 　請求項１記載の半導体装置において、
    　前記ゲート電極には、前記第１半導体領域に平面視で重なる開口部が設けられ、
    　前記開口部の前記第１方向の両端部は、前記第１半導体領域の前記第１方向の両端部より外側に位置し、
    　前記開口部の前記第２方向の両端部は、前記第１半導体領域の前記第２方向の両端部より内側に位置する、半導体装置。     In the semiconductor device according to claim 1,
    The gate electrode is provided with an opening overlapping with the first semiconductor region in plan view,
    Both ends of the opening in the first direction are located outside of both ends of the first semiconductor region in the first direction,
    The both ends of the said 2nd direction of the said opening part are the semiconductor devices located inside the both ends of the said 2nd direction of a said 1st semiconductor region.
  9. 　請求項１記載の半導体装置において、
    　前記半導体基板は、炭化シリコンからなる、半導体装置。     In the semiconductor device according to claim 1,
    The semiconductor device, wherein the semiconductor substrate is made of silicon carbide.
  10. 　（ａ）第１面と、前記第１面の反対側の第２面とを有する第１導電型の半導体基板の前記第１面側から第１不純物を導入し、前記第１面に、平面視で第１方向の長さが前記第１方向に交差する第２方向の長さより長く、かつ、断面視で前記第１面から前記半導体基板の深さ方向に延びる第１導電型の第１半導体領域を形成する工程、
    　（ｂ）前記第１面側から第２不純物を導入し、前記第１半導体領域の底部側に、平面視で前記第１半導体領域を覆い、かつ、断面視で前記第１半導体領域の底部から前記半導体基板の深さ方向に延びる、前記第１導電型とは逆の第２導電型の第２半導体領域を形成する工程、
    　（ｃ）前記第１面側から第３不純物を導入し、平面視で前記第１半導体領域の前記第２方向の両端部に隣接する部分に、断面視で前記第１面から前記第２半導体領域に達するように延びる第２導電型の第３半導体領域を形成する工程、
    　（ｄ）前記第１面側から第４不純物を導入し、平面視で前記第１半導体領域の前記第１方向の両端部に隣接する部分に、断面視で前記第１面から前記第２半導体領域に達するように延びる第２導電型の第４半導体領域を形成する工程、
    　（ｅ）前記半導体基板の前記第１面上に絶縁膜を形成する工程、
    　（ｆ）前記絶縁膜上にゲート電極を形成する工程、
    　を有し、
    　前記（ｃ）工程は、
    　（ｃ１）前記（ａ）工程で用いたマスクを用いて、断面視で前記第１面の法線に対して斜めの方向から平面視で前記第１半導体領域の前記第２方向の一端部に隣接する部分に前記第３不純物を導入する工程、
    　（ｃ２）前記（ａ）工程で用いたマスクを用いて、断面視で前記第１面の法線に対して斜めの方向から平面視で前記第１半導体領域の前記第２方向の他端部に隣接する部分に前記第３不純物を導入する工程、
    　を有する、半導体装置の製造方法。     (A) introducing a first impurity from the first surface side of the semiconductor substrate of the first conductivity type having a first surface and a second surface opposite to the first surface, and forming a plane on the first surface A first conductive type first of a first conductivity type, wherein a length of a first direction in a view is longer than a length of a second direction intersecting the first direction, and extends in a depth direction of the semiconductor substrate from the first surface in a cross sectional view Forming a semiconductor region,
    (B) introducing a second impurity from the first surface side, covering the first semiconductor region in plan view on the bottom side of the first semiconductor region, and from the bottom of the first semiconductor region in cross section Forming a second semiconductor region of a second conductivity type opposite to the first conductivity type extending in a depth direction of the semiconductor substrate;
    (C) A third impurity is introduced from the first surface side, and a portion adjacent to both ends of the first semiconductor region in the second direction in the plan view is the second semiconductor from the first surface in the cross sectional view Forming a third semiconductor region of the second conductivity type extending to reach the region;
    (D) A fourth impurity is introduced from the first surface side, and a portion adjacent to both ends of the first semiconductor region in the first direction in the plan view is the second semiconductor from the first surface in the cross sectional view Forming a fourth semiconductor region of the second conductivity type extending to reach the region;
    (E) forming an insulating film on the first surface of the semiconductor substrate;
    (F) forming a gate electrode on the insulating film;
    Have
    In the step (c),
    (C1) using the mask used in the step (a), at one end of the first semiconductor region in the second direction in plan view from a direction oblique to the normal to the first surface in cross section Introducing the third impurity into an adjacent portion;
    (C2) Using the mask used in the step (a), the other end of the first semiconductor region in the second direction in plan view from a direction oblique to the normal to the first surface in cross section Introducing the third impurity into a portion adjacent to
    A method of manufacturing a semiconductor device, comprising:
  11. 　請求項１０記載の半導体装置の製造方法において、
    　前記（ｅ）工程は、
    　（ｅ１）前記第１半導体領域の前記第１方向の両端部に隣接する第１部分上に第１絶縁膜を形成する工程、
    　（ｅ２）前記第１半導体領域の前記第２方向の両端部に隣接する第２部分上に第２絶縁膜を形成する工程、
    　を有し、
    　前記第１絶縁膜の厚さは、前記第２絶縁膜の厚さより厚い、半導体装置の製造方法。     In the method of manufacturing a semiconductor device according to claim 10,
    In the step (e),
    (E1) forming a first insulating film on first portions adjacent to both end portions in the first direction of the first semiconductor region;
    (E2) forming a second insulating film on second portions adjacent to both end portions of the first semiconductor region in the second direction,
    Have
    A method of manufacturing a semiconductor device, wherein a thickness of the first insulating film is thicker than a thickness of the second insulating film.
  12. 　請求項１１記載の半導体装置の製造方法において、
    　前記（ｆ）工程は、
    　（ｆ１）前記絶縁膜上に多結晶シリコン膜を堆積する工程、
    　（ｆ２）前記多結晶シリコン膜を加工し、前記ゲート電極を形成する工程、
    　を有し、
    　前記第１半導体領域の前記第１方向の両端部側に位置する前記ゲート電極は、前記第１半導体領域の前記第１方向の両端部から離れており、
    　前記第１半導体領域の前記第２方向の両端部側に位置する前記ゲート電極は、前記第３半導体領域に平面視で重なっている、半導体装置の製造方法。     In the method of manufacturing a semiconductor device according to claim 11,
    In the step (f),
    (F1) depositing a polycrystalline silicon film on the insulating film;
    (F2) processing the polycrystalline silicon film to form the gate electrode;
    Have
    The gate electrodes positioned on both end sides in the first direction of the first semiconductor region are apart from both ends in the first direction of the first semiconductor region,
    The method for manufacturing a semiconductor device, wherein the gate electrodes located on both end sides in the second direction of the first semiconductor region overlap the third semiconductor region in plan view.
  13. 　請求項１１記載の半導体装置の製造方法において、
    　前記第１部分の第２導電型の不純物の濃度をＮＡ１、前記絶縁膜のうち、前記第１半導体領域の前記第１方向の両端部に隣接する第１部分上に形成された第１絶縁膜の厚さをｔｏｘ１とし、
    　前記第２部分の第２導電型の不純物の濃度をＮＡ２、前記絶縁膜のうち、前記第１半導体領域の前記第２方向の両端部に隣接する第２部分上に形成された第２絶縁膜の厚さをｔｏｘ２としたときに、
    　ｔｏｘ１×√ＮＡ１＞ｔｏｘ２×√ＮＡ２
    　の関係を満たす、半導体装置の製造方法。     In the method of manufacturing a semiconductor device according to claim 11,
    A first insulating film formed on the first portion adjacent to both ends of the first semiconductor region in the first direction of the first conductive region, wherein the concentration of the second conductivity type impurity of the first portion is NA1. Let the thickness of be tox1,
    A second insulating film formed on the second portion adjacent to both ends of the first semiconductor region in the second direction in the insulating film, wherein the concentration of the second conductivity type impurity of the second portion is NA 2. When the thickness of is tox2,
    tox1 × √NA1> tox2 × √NA2
    A method of manufacturing a semiconductor device, which satisfies the following relationship:
  14. 　（ａ）第１面と、前記第１面の反対側の第２面とを有する第１導電型の半導体基板の前記第１面側から第１不純物を導入し、前記第１面に、平面視で第１方向の長さが前記第１方向に交差する第２方向の長さより長く、かつ、断面視で前記第１面から前記半導体基板の深さ方向に延びる第１導電型の第１半導体領域を形成する工程、
    　（ｂ）前記第１面側から第２不純物を導入し、前記第１半導体領域の底部側に、平面視で前記第１半導体領域を覆い、かつ、断面視で前記第１半導体領域の底部から前記半導体基板の深さ方向に延びる、前記第１導電型とは逆の第２導電型の第２半導体領域を形成する工程、
    　（ｃ）前記第１面側から第３不純物を導入し、平面視で前記第１半導体領域の前記第２方向の両端部に隣接する部分に、断面視で前記第１面から前記第２半導体領域に達するように延びる第２導電型の第３半導体領域を形成する工程、
    　（ｄ）前記半導体基板の前記第１面上に絶縁膜を形成する工程、
    　（ｅ）前記絶縁膜上にゲート電極を形成する工程、
    　を有し、
    　前記（ｄ）工程は、
    　（ｄ１）前記第１半導体領域の前記第１方向の両端部に隣接する第１部分上に第１絶縁膜を形成する工程、
    　（ｄ２）前記第１半導体領域の前記第２方向の両端部に隣接する第２部分上に第２絶縁膜を形成する工程、
    　を有し、
    　前記第１絶縁膜の厚さは、前記第２絶縁膜の厚さより厚い、半導体装置の製造方法。     (A) introducing a first impurity from the first surface side of the semiconductor substrate of the first conductivity type having a first surface and a second surface opposite to the first surface, and forming a plane on the first surface A first conductive type first of a first conductivity type, wherein a length of a first direction in a view is longer than a length of a second direction intersecting the first direction, and extends in a depth direction of the semiconductor substrate from the first surface in a cross sectional view Forming a semiconductor region,
    (B) introducing a second impurity from the first surface side, covering the first semiconductor region in plan view on the bottom side of the first semiconductor region, and from the bottom of the first semiconductor region in cross section Forming a second semiconductor region of a second conductivity type opposite to the first conductivity type extending in a depth direction of the semiconductor substrate;
    (C) A third impurity is introduced from the first surface side, and a portion adjacent to both ends of the first semiconductor region in the second direction in the plan view is the second semiconductor from the first surface in the cross sectional view Forming a third semiconductor region of the second conductivity type extending to reach the region;
    (D) forming an insulating film on the first surface of the semiconductor substrate;
    (E) forming a gate electrode on the insulating film;
    Have
    In the step (d),
    (D1) forming a first insulating film on first portions adjacent to both end portions in the first direction of the first semiconductor region;
    (D2) forming a second insulating film on second portions adjacent to both end portions of the first semiconductor region in the second direction,
    Have
    A method of manufacturing a semiconductor device, wherein a thickness of the first insulating film is thicker than a thickness of the second insulating film.
  15. 　請求項１４記載の半導体装置の製造方法において、
    　前記（ｅ）工程は、
    　（ｅ１）前記絶縁膜上に多結晶シリコン膜を堆積する工程、
    　（ｅ２）前記多結晶シリコン膜を加工し、前記ゲート電極を形成する工程、
    　を有し、
    　前記第１半導体領域の前記第１方向の両端部側に位置する前記ゲート電極は、前記第１半導体領域の前記第１方向の両端部から離れた状態で前記第１絶縁膜上に形成され、
    　前記第１半導体領域の前記第２方向の両端部側に位置する前記ゲート電極は、前記第３半導体領域に平面視で重なった状態で前記第２絶縁膜上に形成されている、半導体装置の製造方法。     In the method of manufacturing a semiconductor device according to claim 14,
    In the step (e),
    (E1) depositing a polycrystalline silicon film on the insulating film;
    (E2) processing the polycrystalline silicon film to form the gate electrode;
    Have
    The gate electrodes positioned on both end sides of the first semiconductor region in the first direction are formed on the first insulating film in a state of being separated from both ends of the first semiconductor region in the first direction,
    In the semiconductor device, the gate electrodes located on both end sides in the second direction of the first semiconductor region are formed on the second insulating film in a state of being overlapped with the third semiconductor region in plan view. Production method.
PCT/JP2018/020457 2017-07-18 2018-05-29 Semiconductor device and manufacturing method thereof WO2019017076A1 (en)

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