JP2013026488A - Insulation gate type semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem that, in a case where a guard ring is diffused deeply to improve voltage resistance, a lateral diffusion of the guard ring causes a source region of a transistor cell near the guard ring to overlap with the guard ring.SOLUTION: The insulation gate type semiconductor device includes a one conductive type semiconductor layer 2, an inverse conductive type channel layer 4 provided on the surface of the one conductive type semiconductor layer 2, a plurality of trenches 7 provided at the one conductive type semiconductor layer 2, an insulating film 11 provided in the trench 7, a gate electrode 13 embedded in the trench 7, a one conductive type source region 15 provided on the surface of the channel layer 4, and an inverse conductive type impurity region 25 of high concentration which is provided on the surface of the one conductive type semiconductor layer 2 so as to surround the outside of the channel layer 4. At least a trench 7o at the outermost part of the trench 7 contacts to the inverse conductive type impurity region 25 by at least one side wall, with no source region 15 being arranged.

Description

  The present invention relates to an insulated gate semiconductor device and a method for manufacturing the same, and more particularly to an insulated gate semiconductor device that can be manufactured by changing a plurality of masks with less withstand voltage and a method for manufacturing the same.

  In a conventional insulated gate semiconductor device (eg, MOSFET), a peripheral region surrounding the outside of an element region in which a transistor cell is provided (channel layer end portion) is provided with a guard ring having the same conductivity type as the channel layer, and a peripheral end portion of the element region. (See, for example, Patent Document 1).

  A conventional insulated gate semiconductor device and a method for manufacturing the same will be described with reference to FIGS. FIG. 9A is a plan view showing the entire final structure (semiconductor chip) of the MOSFET, and FIGS. 9B and 10 are cross-sectional views illustrating an example of a method for manufacturing the MOSFET. It is sectional drawing of the bb line of 9 (A).

  9A, the chip of MOSFET 100 includes an element region 121 and a peripheral region 122 surrounding the element region 121. In the element region 121, for example, a transistor cell of a trench type MOSFET is disposed and covers the surface. A source electrode 117 is disposed. In the peripheral region 122, a guard ring 125 is disposed on the surface of the substrate SB, and a conductive layer 113c, a gate wiring 118, and a gate pad electrode 119 are disposed on the substrate SB.

  Referring to FIG. 9B, MOSFET 100 is manufactured by preparing substrate SB in which n − type semiconductor layer 102 is laminated on the surface of n + type semiconductor substrate 101, and a mask (not shown) from which a guard ring formation region is exposed. ) And p-type impurities (for example, B) are ion-implanted, and then the p-type impurities are diffused. Thereby, an annular guard ring 125 is formed in the vicinity of the outer periphery of the n − type semiconductor layer 102. The formation depth of the guard ring 125 is 3 μm, for example.

  Next, the mask of the transistor cell formation region is removed, and p-type impurities are implanted and diffused to form the channel layer 104. Thereafter, a trench 108 penetrating the channel layer 104 is formed, and the entire surface is thermally oxidized to form a gate insulating film 111 on the inner wall of the trench 108. A polysilicon layer is deposited on the entire surface and etched back, and a polysilicon layer is buried in the trench 108 to form the gate electrode 113. At the same time, a conductive layer 113 c is formed on the guard ring 125 through an insulating film 130. The conductive layer 113c leads the gate electrode 113 around the surface of the substrate SB and is electrically connected to the gate pad electrode 119.

  Referring to FIG. 10A, a mask M31 from which a body region formation region is exposed is provided, and p + type impurities are selectively implanted into the surface of the channel layer 104, and the mask M31 is removed.

  Referring to FIG. 10B, a mask M32 that exposes the formation region of the source region adjacent to all the trenches 108 is provided, and n + type impurities are selectively ion-implanted into the surface of the channel layer 104, and the mask M32 is formed. Remove.

  Referring to FIG. 10C, an insulating film is provided on the entire surface, and n + type impurities and p + type impurities are diffused by reflow at this time to form source region 115 and body region 114. Further, contact holes from which these are exposed are formed in the insulating film, and an interlayer insulating film 116 covering the gate electrode 113 is formed. A source electrode 117 covering the entire surface of the element region 121 is formed, and a gate wiring 118 extending to the peripheral region 122 and a gate pad electrode (not shown) connected thereto are formed.

JP 2004-31386 A (page 8, FIG. 4)

  One method for increasing the breakdown voltage in the MOSFET shown in FIG. 10C is to control the guard ring 125. For example, in a MOSFET having the same conductivity type (n-channel type), the breakdown voltage can be increased by increasing the diffusion depth of the guard ring 125.

  FIG. 11 is a cross-sectional view of MOSFET 100 ′ when the pattern of element region 121 (formation position of source region 115, body region 114, etc.) is maintained and the diffusion depth of guard ring 125 in FIG. 10C is increased. is there.

  The guard ring 125 is an impurity diffusion region. When the diffusion depth is increased, horizontal diffusion (so-called lateral diffusion) also proceeds on the main surface of the substrate SB. In this case, when the distance from the guard ring 125 to the nearest source region (the outermost source region formed in a later process) 115 is small, the guard region 125 overlaps with the source region 115. Specifically, if the distance from the guard ring 125 to the outermost trench 108 is 4 μm, for example, if the guard ring 125 is diffused deeply (4 μm) in order to increase the breakdown voltage, it is diffused 4 μm in the lateral direction as well. It overlaps with the source region 115.

  If the guard ring 125 overlaps or comes into contact with a part of the source region 115, that is, the transistor cell, there is a possibility that normal transistor operation may not be performed. There is a problem that the operation of the transistor cells in the column becomes unstable or non-uniform.

  For this reason, in a method of manufacturing a MOSFET 100, the element region 121 (transistor cell) is formed so as not to come into contact with the guard ring 125 (to ensure a predetermined distance from the end of the guard ring 125) in response to the change in breakdown voltage. It was necessary to change the formation area. That is, a mask for forming the source region 115 (and the body region 114, the channel layer 104, etc.) corresponding to each of them is necessary.

  SUMMARY OF THE INVENTION The present invention has been made in view of such a problem. First, a one-conductivity-type semiconductor layer, a reverse-conductivity-type channel layer provided on the surface of the one-conductivity-type semiconductor layer, and the one-conductivity-type semiconductor layer are provided. Surrounding a plurality of trenches, an insulating film provided in the trenches, a gate electrode embedded in the trenches, a one-conductivity type source region provided on the surface of the channel layer, and the outside of the channel layer A high-concentration reverse-conductivity type impurity region provided on the surface of the one-conductivity type semiconductor layer, and at least one outermost trench among the trenches is solved by having at least one side wall in contact with the reverse-conductivity type impurity region To do.

  Second, a step of preparing one conductivity type semiconductor layer and forming a high concentration reverse conductivity type impurity region on the surface of the peripheral region of the one conductivity type semiconductor layer, and the one conductivity type inside the reverse conductivity type impurity region. Forming a reverse conductivity type channel layer on the surface of the type semiconductor layer, forming a plurality of trenches in the one conductivity type semiconductor layer, covering the trench with an insulating film, and forming a gate in the trench A step of burying an electrode; and a step of forming a source region of one conductivity type on the surface of the channel layer, wherein at least one of the outermost trenches has at least one sidewall of the opposite conductivity type impurity region. It is solved by being formed in contact.

  According to the insulated gate semiconductor device of the present invention, the source region and the guard ring in the transistor cell close to the guard ring (end portion of the element region), even if the guard ring is deeply formed to improve the breakdown voltage. Can be avoided, and the transistor operation can be stabilized.

  Further, according to the method of manufacturing an insulated gate semiconductor device of the present invention, when forming the guard ring deeply in order to improve the breakdown voltage, the source region and the guard in the transistor cell close to the guard ring (end portion of the element region). A method of manufacturing a semiconductor device that avoids contact with the ring can be provided.

  Furthermore, even when the withstand voltage is changed, it is possible to cope with a small mask change, and even when a semiconductor device having a plurality of series is manufactured, an increase in the mask change is prevented, and the manufacturing cost is reduced.

1A is a plan view and FIG. 1B is a cross-sectional view illustrating an insulated gate semiconductor device according to a first embodiment of the present invention. It is sectional drawing explaining the manufacturing method of the insulated gate semiconductor device of the 1st Embodiment of this invention. It is sectional drawing explaining the manufacturing method of the insulated gate semiconductor device of the 1st Embodiment of this invention. It is sectional drawing explaining the manufacturing method of the insulated gate semiconductor device of the 1st Embodiment of this invention. It is sectional drawing explaining the insulated gate semiconductor device of the 2nd Embodiment of this invention. It is sectional drawing explaining the insulated gate semiconductor device of embodiment of this invention. It is sectional drawing explaining the manufacturing method of the insulated gate semiconductor device of embodiment of this invention. It is sectional drawing explaining the manufacturing method of the insulated gate semiconductor device of embodiment of this invention. It is (A) top view and (B) sectional drawing explaining the conventional insulated gate semiconductor device and its manufacturing method. It is sectional drawing explaining the manufacturing method of the conventional insulated gate semiconductor device. It is sectional drawing explaining the conventional insulated gate semiconductor device.

  The embodiment of the present invention will be described with reference to FIGS. 1 to 8 by taking the case of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) as an example.

  First, a first embodiment of the present invention will be described with reference to FIGS. FIG. 1 shows the structure of the MOSFET 50 of the first embodiment. 1A is a plan view of the entire chip, and FIG. 1B is a cross-sectional view taken along the line aa in FIG.

  Referring to FIG. 1A, the chip of MOSFET 50 is provided with an element region 21 and a peripheral region 22 surrounding it on the surface of a substrate SB constituting the chip.

  In the element region 21, a large number of MOSFET transistor cells C are arranged in a stripe pattern, for example. The source electrode 17 is provided so as to cover the entire surface of the element region 21 and is connected to a source region (not shown) of the element region 21.

  A guard ring 25 that is a high-concentration p-type impurity diffusion region is provided on the surface of the substrate SB in the peripheral region 22. The guard ring 25 is provided in an annular shape that surrounds the outside of the element region 21. A conductive layer 13 c is provided on the guard ring 25 so as to overlap therewith. Conductive layer 13 c is connected to gate electrode 8 in element region 21. A gate wiring 18 is provided so as to overlap with the conductive layer 13c. The gate wiring 18 is connected to the gate electrode 13 through the conductive layer 13c. The gate wiring 18 is connected to a gate pad electrode 19 provided on the surface of the substrate SB.

  Referring to FIG. 1B, a substrate SB is formed by laminating an n− type semiconductor layer 2 on an n + type silicon semiconductor substrate 1. The n− type semiconductor layer 2 is, for example, a silicon semiconductor layer formed on the n + type silicon semiconductor substrate 1 by epitaxial growth.

  A p-type channel layer 4 is provided on the surface of the n − -type semiconductor layer 2. A guard ring 25 that is a p + type impurity diffusion region deeper than the channel layer 4 and surrounded by the periphery of the channel layer 4 is provided to relax the curvature of the depletion layer at the peripheral edge of the channel layer 4 to concentrate the electric field. Suppressed.

  The n − type semiconductor layer 2 is etched to provide a plurality of trenches 7. The first trench 71 is provided by etching the n − type semiconductor layer 2 in the element region 20, and both side walls are adjacent to the channel layer 4. A plurality of first trenches 71 are provided to constitute a transistor cell C having a known trench structure.

  Here, the second trench 72 is the outermost trench (outermost trench 7 o) among the plurality of trenches 7. In the second trench 72, one side wall (here, the right side wall) is in contact with the guard ring 25, and the other side wall (here, the left side wall) is adjacent to the channel layer 4.

  A gate insulating film 11 made of a thermal oxide film or the like is provided inside the trench 7 and a gate electrode 13 is embedded. The gate electrode 13 is a polysilicon layer into which impurities are introduced. On the surface of the channel layer 4 adjacent to the first trench 71, the source region 15 which is an n + type impurity region is disposed. A body region 14 which is a p + type impurity region is disposed on the surface of the channel layer 4 between the source regions 15.

  The source region 15 is provided on the surface of the channel layer 4. The second trench 72 (outermost trench 7 o) disposed at the end of the element region 21 has one side wall in contact with the guard ring 25 and the source region 15 is not disposed, but the other side wall on the element region 21 side. A source region 15 is disposed on the substrate. In the present embodiment, the body region 14 and the channel layer 4 are arranged on the guard ring 25 side, but these may not be arranged on the guard ring 25 side.

  A transistor cell C is formed in a region surrounded by the first trench 71 and the second trench 72. The source region 15 is disposed on both side walls of the first trench 71, and a channel (inversion region) of the MOS transistor is formed along both side walls. That is, the first trench 71 operates as a transistor on both sides with the gate electrode 13 interposed therebetween. On the other hand, in FIG. 1B where the source region 15 is disposed, the second trench 72 operates as a transistor by forming a channel of a MOS transistor along the side wall on one side (left half side). The half side does not operate as a transistor.

  That is, the second trench 72 in which the transistor cell C is disposed along only one side wall of the first trench 71 in which the transistor cell C is disposed along both side walls is formed from the inside of the element region 21.

  In the present embodiment, the region where the source region 15 is disposed, that is, the region where the transistor cell C performing the transistor operation is disposed is referred to as an element region 21. That is, in FIG. 1B, the region on the left side of the broken line is the element region 21, and the second trench 72 constitutes the end of the element region 21.

  The gate electrode 13 is covered with an interlayer insulating film 16, and a part of the source region 15 and the body region 14 are exposed from a contact hole CH provided in the interlayer insulating film 16. These are in contact with the source electrode 17 provided so as to cover the entire surface of the element region 21 through the contact hole CH.

  The gate electrode 13 is drawn to the surface of the substrate SB in the peripheral region 22 by the conductive layer 13c. The conductive layer 13c is a polysilicon layer made of the same material as that of the gate electrode 13, and extends to the surface of the substrate SB so as to surround, for example, the outside of the element region 21, and is connected to, for example, one end of a protection diode (not shown).

  A gate wiring 18 is provided on the conductive layer 13c so as to overlap and be electrically connected. The gate wiring 18 is connected to the gate pad electrode 19 and applies a gate voltage to the MOSFET.

  The source electrode 17, the gate wiring 18, and the gate pad electrode 19 are provided on the entire surface of the semiconductor substrate SB as the same metal layer by sputtering of a metal such as aluminum, and are patterned into a predetermined shape.

  The source electrode 17 is provided so as to cover all the trenches 8, and in this embodiment, the inner peripheral end portion (end portion on the element region 21 side) of the guard ring 25 is disposed below the source electrode 17.

  A drain electrode 20 is provided on the back surface of the n + type silicon semiconductor substrate 1 by a vapor deposition metal layer or the like.

  In this embodiment, a plurality of (striped) trenches 7 are provided in the n − type semiconductor layer 2, and at least the outermost trench 7 o (here, the second trench 72) has at least one side wall (here, the right side trench). (Side wall) is in contact with the guard ring 25. Further, the source region 15 is not disposed on one side wall of the second trench 72, and the source region 15 is disposed only on the other side wall (here, the left side wall). That is, the source region 15 is formed using a mask that covers the side wall of the second trench 72 in contact with the guard ring 25 (which has no opening) (this will be described later).

  Thereby, even if it is transistor cell C (transistor cell C between 1st trench 71 and 2nd trench 72) of the edge part of element region 21, it can avoid that guard ring 25 and source region 15 overlap, and it is stable transistor The action can be performed.

  1B shows a case where the guard ring 25 has reached the vicinity of the center of the second trench 72, but the position where the end of the guard ring 25 reaches is not limited to this. The guard ring 25 is designed in accordance with the withstand voltage. For example, the end of the guard ring 25 may substantially coincide with the right side wall portion of the second trench 72.

  Next, a method for manufacturing the MOSFET 50 of the first embodiment will be described with reference to FIGS.

  First, referring to FIG. 2A, a substrate SB in which an n− type semiconductor layer 2 is stacked on an n + type silicon semiconductor substrate 1 is prepared. As an example, the n − type semiconductor layer 2 is stacked on the n + type silicon semiconductor substrate 1 by epitaxial growth or the like.

The entire surface of the substrate is thermally oxidized (for example, about 1000 ° C.), an oxide film (not shown) is formed on the surface of the n − type semiconductor layer 2, and a guard ring formation region is exposed by a photolithography process. Using this as a mask, a p-type impurity (for example, boron (B)) is ion-implanted. As an example, the implantation energy is 50 keV, and the dose is 1 × 10 ¹⁴ / cm ² .

  Thereafter, heat treatment (1000 ° C. to 1200 ° C.) is performed to diffuse the implanted p-type impurity. Thereby, an annular guard ring 25 is formed near the outer periphery of the n − type semiconductor layer 2 (see FIG. 1A). These formation depths are 4 micrometers-5 micrometers, for example.

Next, an oxide film (not shown) is provided again on the entire surface, and the channel layer forming region is exposed by a photolithography process. Using this as a mask, a p-type impurity (for example, B) is ion-implanted over the entire surface. The implantation energy is, for example, 120 keV to 450 keV, and the dose amount is, for example, 2 × 10 ¹² / cm ² . Thereafter, p-type impurities are diffused by heat treatment (1100 ° C.) to form the p-type channel layer 4.

  Referring to FIG. 2B, an NSG (Non-Doped Silicate Glass) CVD oxide film (not shown) is formed on the entire surface by CVD. Thereafter, a mask made of a resist film is formed except for the opening of the trench. The CVD oxide film is partially removed by dry etching to form a trench opening in which the channel layer 4 is exposed.

  Using the CVD oxide film as a mask, the n − type semiconductor layer 2 in the trench opening is dry-etched with CF-based gas and HBr-based gas to form a plurality of trenches 7 (first trench 71 and second trench 72). The first trench 71 passes through the channel layer 4 and reaches the n − type semiconductor layer 2. That is, both side walls of the first trench 71 are in contact with the channel layer 4. The second trench 72 is the outermost trench 7 o and has one side wall in contact with the channel layer 4 and the other side wall in contact with the guard ring 25.

  Dummy oxidation is performed to form an oxide film (not shown) on the inner wall of the trench 7 and the surface of the channel layer 4 to remove etching damage during dry etching, and then the oxide film and the CVD oxide film are removed by etching. .

  Further, the entire surface is oxidized to form a gate oxide film 11 on the inner wall of the trench 7 with a thickness of, for example, about 300 to 700 mm according to the driving voltage.

  Thereafter, a polysilicon layer containing impurities is deposited on the entire surface. The polysilicon layer may be a layer in which polysilicon containing impurities is deposited, or impurities may be introduced after depositing non-doped polysilicon.

  Subsequently, dry etching is performed by providing a mask such that a polysilicon layer having a desired shape remains on the surface of the substrate SB in the peripheral region 22. Thereby, the gate electrode 13 embedded in the trench 7 is formed. At the same time, the gate electrode 13 is drawn out to the surface of the substrate SB, and a conductive layer 13c extending to the surface of the substrate SB in the peripheral region 22 is formed. In this cross section, the conductive layer 13c is formed on the insulating film 30 such as the CVD oxide film or the gate oxide film 11 (remaining) formed (remaining) in the peripheral region 22 in the steps so far. A polysilicon layer constituting a protection diode (not shown) is formed as necessary.

Referring to FIG. 3A, a mask M11 made of a resist film exposing a portion to be a body region is provided, and a p-type impurity (for example, boron (B)) is selectively applied, for example, at a dose of 2.0 × 10 ^15. Ion implantation at / cm ² .

With reference to FIG. 3B, a new resist film mask M12 exposing a portion to be a source region is provided, and an n-type impurity (for example, arsenic (As)) is selectively doped with, for example, a dose of 5.0 × 10. Ion implantation is performed at about ¹⁵ / cm ² .

  At this time, the opening of the mask M12 (that is, the region where the source region is formed) is provided only inside the second trench 72. That is, unlike the conventional mask in which the regions adjacent to all the trenches are opened, the mask M12 of the present embodiment has an opening for forming the source region in the region from the second trench 72 to the guard ring 25. Is not provided.

  Note that the ion implantation step for forming the source region may be performed prior to the ion implantation step for forming the body region.

  Referring to FIG. 4A, the mask M12 is removed, and an NSG or PSG (not shown) and BPSG (Boron Phosphorus Silicate Glass) layer insulating film 16 'is deposited on the entire surface by CVD. By the heat treatment at this time, the p-type impurity and the n-type impurity implanted in the respective formation regions of the body region and the source region are diffused to form the body region 14 and the source region 15.

  The source region 15 and the body region 14 are not formed on one side wall (here, the right side) of the second trench 72 adjacent to the guard ring 25, and the guard ring 25 and these regions can be prevented from overlapping.

  As a result, a region surrounded by the trench 8 becomes a transistor cell C, and an element region 21 in which a large number of MOSFET transistor cells C are arranged is formed.

  Referring to FIG. 4B, a mask (not shown) made of a resist film is provided and the insulating film 16 ′ is etched to form an interlayer insulating film 16 that covers the gate electrode 13 and a part of the source region 15. A contact hole CH exposing the body region 14 is formed.

  Thereafter, aluminum or the like is deposited on the entire surface by a sputtering apparatus and patterned into a desired shape, covering the entire surface of the element region 21 and forming a source electrode 17 in contact with the source region 15 and the body region 14. The source electrode 17 covers a part of the guard ring 25 and the second trench 72 near the end of the element region 21.

  Further, a drain electrode is formed on the back surface of the n + -type silicon semiconductor substrate 1 by metal vapor deposition or the like to obtain the final structure shown in FIG.

  In the MOSFET of the present invention, at least the outermost trench 7o among the plurality of trenches 7 has at least one side wall in contact with the guard ring 25, and the source region 15 is not disposed on the one side wall. As a result, the transistor operation is not performed on the side wall portion of the trench 7o, and an unstable operation can be avoided even when it is in contact with the guard ring 25. Therefore, the outermost trench 7o is not limited to the above configuration.

  FIG. 5 is a diagram showing a second embodiment of the present invention, which corresponds to a cross section taken along the line aa in FIG. As shown in FIG. 5A, the outermost trench 7 o may be in contact with the guard ring 25 on both side walls. That is, the third trench 73 that becomes the outermost trench 7 o may be provided outside the second trench 72. The guard ring 25 reaches the second trench 72, and the third trench 73 is located between the outer peripheral end and the inner peripheral end of the guard ring 25, that is, the third trench 73 is in contact with the guard ring 25 at both side walls. . In this case, the source region 15 is not disposed on both side walls of the third trench 73. The third trench 73 is also covered with an insulating film (gate insulating film 11) and a polysilicon layer (gate electrode 13) is buried, but since the source region 15 is not disposed on both side walls, no transistor operation is performed.

  That is, from the inside of the element region 21, the second trench 72 in which the transistor cell C is disposed along only one side wall of the first trench 71 in which the transistor cell C is disposed along both side walls, and the transistor cell C in both side walls. A third trench 73 in which no is disposed is formed. The source electrode 17 also covers the third trench 73. A plurality of third trenches 73 that do not perform transistor operation may be provided.

  By providing the third trench 73 in which the source region 15 is not formed on the side wall, the guard ring 25 can be formed deeper (wider). In this case, as a mask for forming the source region 15, a mask in which both side walls of the third trench 73 and one side wall of the second trench 72 are covered is used.

  5B, the end of the guard ring 25 may be located between the trenches 7. In this case, the trench 7 which is not in contact with the end portion of the guard ring 25 but is close to the trench 7 may be the first trench 71 in which the source regions 15 are provided on both side walls thereof and perform transistor operation. The source region 15 may be provided only on the side wall that is not adjacent to the second trench 72 and the transistor operation may be performed only on one side. That is, the dashed source region 15 indicates that the presence or absence of formation is arbitrary. If a sufficient distance from the end of the guard ring 25 to the nearest source region 15 can be secured, the first trench 71 may be used, and if the distance is insufficient, the second trench 72 may be used. Here, a plurality of third trenches 73 in the guard ring 25 are shown, but there may be one.

  If the source region 15 is not provided, transistor operation is not performed in that region (side wall), and unstable operation due to contact with the guard ring 25 can be avoided. That is, the mask for forming the channel layer 4, the trench 7, and the body region 14 uses the conventional mask, and there is no problem even if these are formed in contact with or overlapping the guard ring 25. By changing the pattern only for the mask M22 for forming the source region 15, the change of the mask pattern can be minimized. The present invention does not exclude the formation of the channel layer 4 and the body region 14 in a region where the transistor operation is not performed.

  Thus, the arrangement of the source region 15 can be selected by the mask pattern for forming the source region 15. That is, when manufacturing MOSFETs with different breakdown voltages, the pattern of the element region 21 can be dealt with only by changing the mask of the mask for forming the source region 15 according to the diffusion width of the guard ring 25. Hereinafter, the manufacturing method of the present embodiment will be described with reference to FIGS.

  6 is a cross-sectional view showing MOSFETs having different breakdown voltages, and FIG. 6A is a MOSFET having a breakdown voltage of 100 V to 150 V (hereinafter referred to as a low breakdown voltage MOSFET 51) of the first embodiment (FIG. 1B), for example. (B) is, for example, a MOSFET having a breakdown voltage of 200 V to 250 V (hereinafter referred to as a high breakdown voltage MOSFET 52) of the second embodiment (FIG. 5A). The same applies to FIGS. 7 and 8 below.

  Comparing these, since the high breakdown voltage MOSFET 52 of FIG. 6B has a high breakdown voltage, the guard ring 25 is formed deeper than the low breakdown voltage MOSFET 51 of FIG. Therefore, by changing only the pattern (formation region) of the source region 15 in the element region 21, a mask other than the formation of the source region 15 can be shared in the manufacturing process of the two breakdown voltage MOSFETs. The mask for forming the body region 14 and the channel layer 4 may be changed according to the formation region of the guard ring 25. However, by changing only the mask of the source region 15, the number of mask pattern changes can be minimized. it can.

  7 and 8 mainly show the steps of forming the source region and the body region, and the other manufacturing steps are the same as those in the first embodiment. Further, the low breakdown voltage MOSFET 51 (FIG. 7A) and the high breakdown voltage MOSFET 52 (FIG. 7B) are shown side by side (also in FIG. 8), but it is possible to share a mask. It is not that they are manufactured at the same time.

  Referring to FIG. 7, p-type impurities are ion-implanted under a condition corresponding to each breakdown voltage, using the oxide film from which the guard ring formation region is exposed as a mask.

  Next, a channel layer 4 is formed by providing a mask (not shown) and ion-implanting and diffusing p-type impurities.

  Thereafter, the same process as in the first embodiment is performed to form the trench 7 (first trench 71, second trench 72, third trench 73), gate insulating film 11 and gate electrode 13 (conductive layer 13c).

  Thereafter, a mask M21 in which the formation region of the body region is exposed is provided, and p-type impurities are ion-implanted. Thus, the mask for forming the channel layer 4, the trench 7 and the body region 14 can be shared.

  Referring to FIG. 8, new masks M22a and M22b in which the formation region of the source region is exposed are provided, and n-type impurities are ion-implanted. At this time, since the low breakdown voltage MOSFET 51 and the high breakdown voltage MOSFET 52 are different in the formation region of the source region 15, different masks M22a and M22b are used.

  As described above, in the present invention, it is possible to change the number of masks for MOSFETs having different breakdown voltages (in this embodiment, only the mask for forming the source is changed). Therefore, even with a MOSFET manufacturing method (series) corresponding to a plurality of breakdown voltages, the mask change can be reduced and the manufacturing cost can be reduced.

  As described above, the n-channel MOSFET has been described as an example in the embodiment of the present invention. However, a p-channel MOSFET having a reversed conductivity type can be implemented in the same manner, and the same effect can be obtained. The present invention is not limited to the MOSFET, and can be similarly applied to an insulated gate semiconductor device such as an IGBT (Insulated Gate Bipolar Transistor) in which a p-type semiconductor layer is disposed under the n + -type silicon semiconductor substrate 1 of the MOSFET. An effect is obtained.

1 n + type silicon semiconductor substrate
2 n-type semiconductor layer
4 channel layer
8 Gate electrode
14 Body region
15 Source region
17 Source electrode
25 Guard ring

Claims (6)

One conductivity type semiconductor layer;
A reverse conductivity type channel layer provided on the surface of the one conductivity type semiconductor layer;
A plurality of trenches provided in the one conductivity type semiconductor layer;
An insulating film provided in the trench;
A gate electrode embedded in the trench;
A source region of one conductivity type provided on the surface of the channel layer;
A high-concentration reverse conductivity type impurity region provided on the surface of the one conductivity type semiconductor layer surrounding the outside of the channel layer,
The insulated gate semiconductor device according to claim 1, wherein at least one sidewall of at least the outermost trench is in contact with the reverse conductivity type impurity region.   2. The insulated gate semiconductor device according to claim 1, wherein the source region is not disposed in a region adjacent to the one side wall.   3. The insulated gate semiconductor device according to claim 1, wherein a transistor operation is not performed on the one side wall.   4. The outermost trench has another side wall that is not in contact with the opposite conductivity type impurity region, and the source region is provided on the other side wall. Insulated gate type semiconductor device. Preparing one conductivity type semiconductor layer and forming a high concentration reverse conductivity type impurity region on the surface of the peripheral region of the one conductivity type semiconductor layer;
Forming a reverse conductivity type channel layer on the surface of the one conductivity type semiconductor layer inside the reverse conductivity type impurity region;
Forming a plurality of trenches in the one conductivity type semiconductor layer;
A step of covering the trench with an insulating film, a step of burying a gate electrode in the trench,
Forming a source region of one conductivity type on the surface of the channel layer;
Comprising
At least the outermost trench among the trenches is formed such that at least one side wall is in contact with the reverse conductivity type impurity region.   6. The method of manufacturing an insulated gate semiconductor device according to claim 5, wherein, in the impurity implantation step of the source region, the upper side of the one side wall is covered with a mask.

Images