WO2018210335A1 - 膜层的掺杂方法、薄膜晶体管及其制作方法 - Google Patents

膜层的掺杂方法、薄膜晶体管及其制作方法 Download PDF

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WO2018210335A1
WO2018210335A1 PCT/CN2018/087484 CN2018087484W WO2018210335A1 WO 2018210335 A1 WO2018210335 A1 WO 2018210335A1 CN 2018087484 W CN2018087484 W CN 2018087484W WO 2018210335 A1 WO2018210335 A1 WO 2018210335A1
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region
layer
ion beam
barrier layer
substrate
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French (fr)
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王学伟
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BOE Technology Group Co Ltd
Ordos Yuansheng Optoelectronics Co Ltd
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BOE Technology Group Co Ltd
Ordos Yuansheng Optoelectronics Co Ltd
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    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
    • H10D30/6715—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes characterised by the doping profiles, e.g. having lightly-doped source or drain extensions
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
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    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/013—Manufacturing their source or drain regions, e.g. silicided source or drain regions
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0231—Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks
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    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
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    • H10P14/65—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials
    • H10P14/6516—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials
    • H10P14/6536—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials by exposure to radiation, e.g. visible light
    • H10P14/6539—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials by exposure to radiation, e.g. visible light by exposure to corpuscular radiation, e.g. exposure to electrons, alpha-particles, protons or ions
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    • H10P30/202—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials
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    • H10P30/204—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials into Group IV semiconductors
    • H10P30/2042—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials into Group IV semiconductors into crystalline silicon carbide
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    • H10P30/202—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials
    • H10P30/204—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials into Group IV semiconductors
    • H10P30/2044—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials into Group IV semiconductors into semiconducting carbon, e.g. diamond or semiconducting diamond-like carbon
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    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/21—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically active species
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    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/22—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping using masks
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    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/22—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping using masks
    • H10P30/221—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping using masks characterised by the angle between the ion beam and the mask
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    • H10P30/222—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the angle between the ion beam and the crystal planes or the main crystal surface
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Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a doping method of a film layer, a thin film transistor, and a method of fabricating the same.
  • the active matrix organic light emitting diode (AMOLED) backplane technology and the semiconductor device process, it is generally required to perform multiple different ions and different doses on the semiconductor layer. Doping to improve the electrical properties of its Thin Film Transistor (TFT).
  • TFT Thin Film Transistor
  • the film layer comprising a first region, a second region and a third region, wherein the first region is located in an intermediate region of the film layer, a third zone is located in an edge region of the film layer, and the second zone is located between the first zone and the third zone;
  • first barrier layer and a second barrier layer for blocking the ion beam on the film layer by a patterning process, the orthographic projection area of the first barrier layer on the film layer just covering the first region
  • the orthographic projection area of the second barrier layer on the film layer covers the first region and the second region;
  • the substrate substrate is rotated by a predetermined angle in a direction parallel to the ion beam such that the second barrier layer does not block the second region, using the ions Performing a second doping of the film layer to complete doping of the second region comprises:
  • L represents a length value of the second region in a predetermined direction
  • H1 represents a thickness value of the film layer
  • H2 represents a thickness value of the first barrier layer.
  • the materials of the first barrier layer and the second barrier layer are the same.
  • the method further includes: removing the first barrier layer and the second barrier layer to form a doping After the film layer.
  • the dose of the second doped dopant ions is less than the dose of the first doped dopant ions
  • the embodiment of the present disclosure further provides a method for fabricating a thin film transistor, including a gate, a source, a drain, and a semiconductor active layer, wherein: the fabrication of the semiconductor active layer includes:
  • the semiconductor layer Forming a semiconductor layer on a base substrate by a patterning process, the semiconductor layer including a first region, a second region, and a third region, the first region being located in an intermediate region of the semiconductor layer, the third region being located in the semiconductor An edge region of the layer, the second region being located between the first region and the third region;
  • first barrier layer and a second barrier layer for blocking the ion beam on the semiconductor layer by a patterning process, the orthographic projection area of the first barrier layer on the semiconductor layer just covering the first region
  • the orthographic projection area of the second barrier layer on the semiconductor layer covers the first region and the second region;
  • the semiconductor layer is first doped with an ion beam perpendicular to the substrate;
  • the method before the semiconductor layer is formed on the substrate by a patterning process, the method further includes:
  • a light shielding layer and a buffer layer are formed on the base substrate by a patterning process.
  • the forming the first barrier layer and the second barrier layer for blocking the ion beam sequentially by the patterning process on the semiconductor layer comprises:
  • the method further includes:
  • the second barrier layer is removed, and a source and a drain are formed on the semiconductor active layer by a patterning process.
  • L represents a length value of the second region in a predetermined direction
  • H1 represents a thickness value of the semiconductor layer
  • H2 represents a thickness value of a portion of the insulating layer directly above the second region
  • H3 represents The thickness value of the gate.
  • the method before the semiconductor layer is formed on the substrate by the patterning process, the method further includes:
  • a gate electrode and an insulating layer are sequentially formed on the base substrate by a patterning process.
  • the method further includes:
  • the first barrier layer and the second barrier layer are removed, and a source and a drain are formed on the semiconductor active layer by a patterning process.
  • L represents a length value of the second region in a predetermined direction
  • H1 represents a thickness value of the semiconductor layer
  • H2 represents a thickness value of the first barrier layer.
  • the materials of the first barrier layer and the second barrier layer are the same.
  • the dose of the second doped dopant ions is less than the dose of the first dopant doped ions.
  • the substrate substrate is rotated by a predetermined angle in a direction parallel to the ion beam such that the second barrier layer does not block the second region, using the ions
  • the second doping of the semiconductor layer by the beam to form a semiconductor active layer includes:
  • the embodiment of the present disclosure further provides a thin film transistor which is formed by the above manufacturing method.
  • 1 is a partial structural view of a known thin film transistor
  • FIG. 2 is a flow chart of a doping method of a film layer according to an embodiment of the present disclosure
  • 4, 5a and 5b are schematic structural views of different stages of a film doping process provided by an embodiment of the present disclosure
  • FIG. 6 is a flow chart of a method for fabricating a thin film transistor according to an embodiment of the present disclosure
  • FIG. 7 is a flow chart of a method for fabricating a top gate thin film transistor according to an embodiment of the present disclosure
  • 9a, 9b, and 10 are schematic structural diagrams of different stages of a fabrication process of a top-gate thin film transistor according to an embodiment of the present disclosure
  • FIG. 11 is a flow chart of a method for fabricating a bottom gate thin film transistor according to an embodiment of the present disclosure
  • FIG 12, 13a, 13b and 14 are schematic structural views of different stages of a fabrication process of a bottom-gate thin film transistor according to an embodiment of the present disclosure.
  • the top gate thin film transistor includes a light shielding layer 12, a buffer layer 11, a semiconductor active layer 13, an insulating layer 14, a gate electrode 15, and a source and a drain which are sequentially disposed on the base substrate 10.
  • the semiconductor active layer 13 includes an undoped region 131, a lightly doped region 132, and a heavily doped region 133.
  • the undoped region 131 corresponds to the channel region of the semiconductor active layer 13, and the heavily doped region 133 and the lightly doped region 132 correspond to the ohmic contact region of the semiconductor active layer 13.
  • the lightly doped region 132 is a Lightly Doped Drain (LDD), which acts to reduce the electric field in the drain region and prevent the degradation of the hot electrons.
  • LDD Lightly Doped Drain
  • the semiconductor active layer 13 when the semiconductor active layer 13 is doped, first, a photoresist layer 16 is covered on the gate electrode 15, and the positive projection area of the photoresist layer 16 on the substrate substrate 10 is just right. The undoped region 131 and the lightly doped region 132 of the semiconductor active layer 13 are covered. Next, the heavily doped region 133 of the semiconductor active layer 13 is doped with a larger dose by an ion beam, and the direction of the ion beam is perpendicular to the substrate 10 (in the direction indicated by the arrow in the figure), thereby forming a semiconductor. The heavily doped region 133 of the source layer 13. Next, a light dose doping of the lightly doped region 132 of the semiconductor active layer 13 with an ion beam is required.
  • the photoresist layer 16 covers the lightly doped region 132 to block the doping ions, it is necessary to remove the photoresist layer in the portion, that is, to remove the photoresist layer in the dotted frame in the figure. After the removal, a smaller dose of doping is performed to form the lightly doped region 132 of the semiconductor active layer 13.
  • a portion of the photoresist layer needs to be removed by exposure and etching processes during different dose doping, such as removing the photoresist layer in the dashed box in FIG.
  • the parameter control of Ashing is difficult, resulting in the length of the lightly doped region cannot be effectively defined, and the key electrical parameters such as leakage current are affected.
  • the photoresist residue is easily generated, thereby causing various defects in the latter stage process, which not only reduces the yield but also reduces the productivity.
  • Embodiments of the present disclosure provide a doping method of a film layer, a thin film transistor, and a manufacturing method thereof, which are used to simplify a process flow, increase productivity, and improve product yield.
  • a specific embodiment of the present disclosure provides a method for doping a film layer, including:
  • S201 forming a layer of a film to be doped on the substrate by a first patterning process, the film layer comprising a first region, a second region, and a third region, wherein the first region is located in a middle region of the film layer
  • the third zone is located at an edge region of the film layer, and the second zone is located between the first zone and the third zone;
  • S203 performing first doping of the film layer by using an ion beam perpendicular to the substrate substrate to complete doping of the third region;
  • the first region is a non-doped region of the film layer
  • the second region is a lightly doped region of the film layer
  • the third region is a heavily doped region of the film layer.
  • the exact coverage here means that the two are completely coincident.
  • the positive projection area of the first barrier layer on the film layer just covering the first region means that the orthographic projection area of the first barrier layer on the film layer completely coincides with the first region of the film layer.
  • the specific embodiment of the present disclosure rotates the substrate substrate in a direction parallel to the ion beam by a predetermined angle such that the second barrier layer does not block the second region, and the second layer is doped by the ion beam.
  • Miscellaneous, complete the doping of the second region specifically including:
  • a film layer 31 to be doped is formed on the base substrate 10 by a patterning process, and the film layer 31 includes a first region 311, a second region 313, and a third region 312, and the first region 311 Located in the middle region of the film layer 31, the third region 312 is located at the edge region of the film layer 31, and the second region 313 is located between the first region 311 and the third region 312.
  • the first region 311 corresponds to the undoped region of the film layer 31
  • the third region 312 corresponds to the heavily doped region of the film layer 31
  • the second region 313 corresponds to the lightly doped region of the film layer 31.
  • the patterning process in a specific embodiment of the present disclosure includes coating, exposure, development, etching of a photoresist, and part or all of the process of removing the photoresist.
  • the base substrate 10 in the specific embodiment of the present disclosure may be a glass substrate, or may be other types of substrates, such as a quartz substrate.
  • the film layer 31 in a specific embodiment of the present disclosure may be a semiconductor film layer.
  • a first barrier layer 41 and a second barrier layer 42 for blocking the ion beam, the orthographic projection area of the first barrier layer 41 on the film layer 31 are sequentially formed on the film layer 31 by a patterning process.
  • the first region 311 is covered, and the orthographic projection area of the second barrier layer 42 on the film layer 31 covers the first region 311 and the second region 313.
  • the first barrier layer 41 and the second barrier layer 42 formed by the specific embodiments of the present disclosure are the same material.
  • the first barrier layer 41 and the second barrier layer 42 may select a photoresist layer.
  • other types of barrier film layers may be selected in the actual production process, as long as the ions implanted in the ion doping process can be blocked. The role can be.
  • the film layer 31 is doped for the first time by using an ion beam perpendicular to the base substrate 10 (the direction indicated by the arrow in the ion beam injection direction), and the film layer 31 is completed. Doping of the three regions 312. In the first doping, since the first region 311 and the second region 313 are blocked by the first barrier layer 41 and the second barrier layer 42, the first region 311 and the second region 313 of the film layer 31 are first doped. There is no doping in the impurity process.
  • the dose of the ion beam implanted with the dopant ions is relatively large, such as an n-type dopant ion or a p-type dopant ion having a larger implantation dose.
  • the substrate substrate 10 is rotated clockwise by a predetermined angle A in a direction parallel to the ion beam, so that the second barrier layer 42 does not block the second region 313, and the film layer 31 is processed by the ion beam.
  • the second doping completes the doping of the second region 313 under the first region 311.
  • the dose of the ion beam implanted dopant ions is small, and the preset angle A of rotation in the specific embodiment of the present disclosure needs to satisfy: the substrate substrate 10 is parallel to the ion beam.
  • the second zone 313 can be exposed after the direction is rotated by the preset angle A.
  • L indicates that the second region 313 is in a preset direction (eg, the second region 313 is in a direction parallel to the base substrate 10).
  • the length value, H1 represents the thickness value of the film layer 31, and H2 represents the thickness value of the first barrier layer 41.
  • the substrate substrate 10 is rotated counterclockwise in a direction parallel to the ion beam by a predetermined angle A, and the film layer 31 is again doped by the ion beam to complete the first region 311. Doping of the second region 313.
  • the first doping and the second doping in the specific embodiments of the present disclosure may be completed in an ion beam implantation apparatus, and the substrate substrate in the specific embodiment of the present disclosure may be placed in the ion beam implantation device.
  • the platform of the ion beam implantation device itself can be rotated at multiple angles, and it is not necessary to separately set the rotation axis, and the influence of the ion implantation depth caused by the change of the distance between the ion beam and the substrate substrate after the substrate substrate is rotated, It can be controlled according to the setting of the ion acceleration voltage, and can be experimentally compared with the electrical characteristics of the normal vertical injection mode.
  • the ion implantation region after the rotation of the base substrate is a trapezoidal body region, and there is one less triangular region than the rectangular parallelepiped region of the normal vertical injection mode.
  • the ion implantation dose can be adjusted to achieve electrical matching with the normal vertical injection mode. .
  • the specific embodiment of the present disclosure further includes: removing the first barrier layer and the second barrier layer to form a doped film layer.
  • the specific embodiment of the present disclosure may remove the first barrier layer and the second barrier layer by using an ashing process and a dry etching process, or may remove the first barrier layer and the second barrier layer by a lift-off process.
  • the doping method of the above film layer used in the specific embodiment of the present disclosure can achieve doping of the heavily doped region and the lightly doped region simultaneously in the same ion beam implantation device, and does not need to do the doping in the heavily doped region. Then, the substrate is further placed in an etching device to remove the barrier layer at a position directly above the lightly doped region, and then placed in the ion beam implantation device to complete doping of the lightly doped region. Therefore, the specific embodiment of the present disclosure It simplifies the process, increases productivity and improves product yield.
  • a specific embodiment of the present disclosure further provides a method for fabricating a thin film transistor, as shown in FIG. 6, including a gate, a source, a drain, and a semiconductor active layer, wherein the semiconductor active layer
  • the production includes:
  • S601 manufacturing a semiconductor layer on a base substrate by a first patterning process, the semiconductor layer including a first region, a second region, and a third region, the first region being located in an intermediate region of the semiconductor layer, the third a region is located in an edge region of the semiconductor layer, and the second region is located between the first region and the third region;
  • S603 performing first doping of the semiconductor layer by using an ion beam perpendicular to the substrate.
  • the first region is an undoped region of the semiconductor layer
  • the second region is a lightly doped region of the semiconductor layer
  • the third region is a heavily doped region of the semiconductor layer.
  • the thin film transistor formed by the specific embodiment of the present disclosure may be a top gate type thin film transistor or a bottom gate type thin film transistor, and may of course be other types of thin film transistors, such as a side gate type thin film transistor.
  • a method for fabricating a thin film transistor according to a specific embodiment of the present disclosure includes:
  • S702 forming a semiconductor layer on the buffer layer by a first patterning process, the semiconductor layer comprising a first region, a second region, and a third region, wherein the first region is located in an intermediate region of the semiconductor layer, a third zone is located in an edge region of the semiconductor layer, and the second zone is located between the first zone and the third zone;
  • S705 performing first doping of the semiconductor layer by using an ion beam perpendicular to the substrate.
  • the specific embodiment of the present disclosure rotates the substrate substrate in a direction parallel to the ion beam by a predetermined angle, so that the second barrier layer does not block the second region, and the semiconductor layer is doped for a second time by using an ion beam to form a semiconductor.
  • the active layer specifically includes:
  • the light shielding layer 12 and the buffer layer 11 are formed on the base substrate 10 by a patterning process.
  • the specific manufacturing methods of the light shielding layer 12 and the buffer layer 11 in the specific embodiment of the present disclosure are the same as those in the prior art. I won't go into details here.
  • a semiconductor layer 71 is formed on the buffer layer 11 by a patterning process.
  • the semiconductor layer 71 includes a first region 711, a second region 713, and a third region 712.
  • the first region 711 is located in an intermediate region of the semiconductor layer 71, and the third region 712 Located in the edge region of the semiconductor layer 71, the second region 713 is located between the first region 711 and the third region 712, the first region 711 corresponds to the undoped region of the semiconductor layer 71, and the third region 712 corresponds to the re-doping of the semiconductor layer 71.
  • the second region 713 corresponds to the lightly doped region of the semiconductor layer 71.
  • the specific fabrication method of the semiconductor layer 71 in the specific embodiment of the present disclosure is similar to the prior art, and details are not described herein again.
  • the insulating layer 14 and the gate electrode 15 are sequentially formed on the semiconductor layer 71 by a patterning process.
  • the specific fabrication methods of the insulating layer 14 and the gate electrode 15 in the embodiment of the present disclosure are the same as those in the prior art, and are not described herein again.
  • the gate 15 in the particular embodiment shown in Figure 7 acts as a barrier during subsequent doping.
  • a second barrier layer 72 is formed on the gate 15 by a patterning process.
  • the second barrier layer 72 may select a photoresist layer, and the second barrier layer 72 is on the semiconductor layer 71.
  • the orthographic projection area covers exactly the first area 711 and the second area 713.
  • the semiconductor layer 71 is doped first by using an ion beam perpendicular to the substrate 10, and the first region 711 and the second region 713 are gated 15 by the first doping.
  • the second barrier layer 72 is occluded, so the first region 711 and the second region 713 of the semiconductor layer 71 are not doped during the first doping process, and the ion beam implantation is performed during the first doping of the embodiment of the present disclosure.
  • the dose of the doping ions is relatively large, such as an n-type dopant ion or a p-type dopant ion having a larger implantation dose.
  • the substrate substrate 10 is rotated clockwise by a predetermined angle A in a direction parallel to the ion beam, so that the second barrier layer 72 does not block the second region 713, and the semiconductor layer 71 is subjected to ion beam irradiation.
  • the second doping, the second doping of the embodiment of the present disclosure, the dose of the ion beam implanted dopant ions is small, and the preset angle A of the rotation in the specific embodiment of the present disclosure needs to satisfy: the substrate substrate 10 is The second region 713 can be exposed after rotating the predetermined angle A parallel to the direction of the ion beam to enable the ion beam to dope the second region 713.
  • L indicates that the second region of the semiconductor layer is in a preset direction (eg, the second region is in a direction parallel to the base substrate 10)
  • H1 represents the thickness value of the semiconductor layer 71
  • H2 represents the thickness value of the portion of the insulating layer 14 located directly above the second region 713
  • H3 represents the thickness value of the gate electrode 15.
  • the second region of the semiconductor layer has a length value of 0.25 m in a direction parallel to the substrate substrate 10
  • the semiconductor layer 71 has a thickness of 500 ⁇ .
  • the thickness of the insulating layer 14 is
  • the thickness value of the gate 15 is
  • the preset angle A calculated according to the above formula is 33°.
  • the base substrate 10 is rotated counterclockwise in a direction parallel to the ion beam by a predetermined angle A, and the semiconductor layer 71 is again doped second by an ion beam to form a semiconductor active layer.
  • the first doping and the second doping in the specific embodiments of the present disclosure may be completed in an ion beam implantation apparatus, and the substrate substrate in the specific embodiment of the present disclosure may be placed in the ion beam implantation device.
  • the platform of the ion beam injection device itself can be rotated at multiple angles without the need to separately set the rotating shaft. It is realized that the ion beam can be implanted not only in the direction of the vertical substrate but also at an angle to the substrate.
  • the embodiment of the present disclosure does not need to pass through when the semiconductor layer is doped to form the semiconductor active layer.
  • the doping ions can also be implanted into the lightly doped region, which improves the controllability of the process and various parameters, and eliminates the denaturation due to the photoresist.
  • the problem of photoresist residue that occurs can simplify the process, increase productivity, increase ion implantation efficiency, and increase product yield.
  • the second barrier layer is removed, and the source 92 and the drain 93 are formed on the semiconductor active layer 91 by a patterning process.
  • the specific fabrication method of the source 92 and the drain 93 in the specific embodiment of the present disclosure Same as the prior art, and will not be described here.
  • the specific embodiment of the present disclosure may remove the second barrier layer by an ashing process and an etching process, or may remove the second barrier layer by a lift-off process.
  • the specific embodiment of the present disclosure when the thin film transistor is fabricated by the above method, in the case of fabricating the semiconductor active layer, after the first doping of the semiconductor layer, the specific embodiment of the present disclosure does not require the lining after the first doping.
  • the bottom substrate is transported to the etching device for etching the barrier layer directly above the lightly doped region.
  • the specific embodiment of the present disclosure may retain the second barrier layer. At this time, the substrate substrate may be rotated at a predetermined angle to complete the light blending.
  • the doping of the impurity region, the specific embodiment of the present disclosure can realize that the heavily doped region and the lightly doped region are completed in one time in the same ion beam implantation device, and no additional ashing and etching processes are needed.
  • a method for fabricating a thin film transistor according to a specific embodiment of the present disclosure includes:
  • S1101 forming a gate electrode and an insulating layer on a base substrate by a seventh patterning process and fabricating a semiconductor layer by a first patterning process, the semiconductor layer including a first region, a second region, and a third region, the first region Located in an intermediate region of the film layer, the third region is located at an edge region of the film layer, and the second region is located between the first region and the third region;
  • S1103 performing first doping of the semiconductor layer by using an ion beam perpendicular to the substrate.
  • S1104 rotating the substrate substrate in a direction parallel to the ion beam by a predetermined angle, such that the second barrier layer does not block the second region, and using the ion beam to perform the second layer on the semiconductor layer Sub-doping, forming a semiconductor active layer; a dose of the second doped dopant ions is less than a dose of the first doped dopant ions;
  • the specific embodiment of the present disclosure rotates the substrate substrate in a direction parallel to the ion beam by a predetermined angle, so that the second barrier layer does not block the second region, and the semiconductor layer is doped for a second time by using an ion beam to form a semiconductor.
  • the active layer specifically includes:
  • a gate electrode 15, an insulating layer 14, and a semiconductor layer 71 are sequentially formed on a base substrate 10 by a patterning process, and the semiconductor layer 71 includes a first region 711, a second region 713, and a third region 712.
  • the first region 711 is located at an intermediate portion of the semiconductor layer 71
  • the third region 712 is located at an edge region of the semiconductor layer 71
  • the second region 713 is located between the first region 711 and the third region 712
  • the first region 711 corresponds to the semiconductor layer 71.
  • the undoped region, the third region 712 corresponds to the heavily doped region of the semiconductor layer 71
  • the second region 713 corresponds to the lightly doped region of the semiconductor layer 71.
  • the gate electrode 15, the insulating layer 14 and the semiconductor layer in the embodiment of the present disclosure The specific manufacturing method of 71 is similar to the prior art, and will not be described here.
  • a first barrier layer 111 and a second barrier layer 112 are sequentially formed on the semiconductor layer 71 by a patterning process, and the orthographic projection area of the first barrier layer 111 on the semiconductor layer 71 covers the first region 711.
  • the orthographic projection area of the second barrier layer 112 on the semiconductor layer 71 covers the first region 711 and the second region 713.
  • the first barrier layer 111 and the second barrier layer 112 are formed of the same material in a specific embodiment of the present disclosure.
  • the first barrier layer 111 and the second barrier layer 112 may select a photoresist layer. .
  • the semiconductor layer 71 is first doped with an ion beam perpendicular to the substrate 10, and the first region 711 and the second region 713 are first blocked.
  • the layer 111 and the second barrier layer 112 are occluded, so that the first region 711 and the second region 713 of the semiconductor layer 71 are not doped during the first doping process, and the ions are implanted for the first time in the specific embodiment of the present disclosure.
  • the dose of the implanted dopant ions is larger, such as a larger dose of n-type dopant ions or p-type dopant ions.
  • the substrate substrate 10 is rotated clockwise by a predetermined angle A in a direction parallel to the ion beam, so that the second barrier layer 112 does not block the second region 713, and the semiconductor layer 71 is irradiated with an ion beam.
  • the second doping when the second doping of the embodiment of the present disclosure, the dose of the ion beam implanted dopant ions is small, and the preset angle A of the rotation in the specific embodiment of the present disclosure needs to satisfy: the substrate substrate 10 is to be The second zone 713 can be exposed after rotating the predetermined angle A parallel to the direction of the ion beam.
  • L represents that the second region of the semiconductor layer is in a predetermined direction (eg, the second region is in a direction parallel to the substrate 10)
  • the length value H1 represents the thickness value of the semiconductor layer 71, and H2 represents the thickness value of the first barrier layer 111.
  • the substrate substrate 10 is rotated counterclockwise in a direction parallel to the ion beam by a predetermined angle A, and the semiconductor layer 71 is again doped second by an ion beam to form a semiconductor active layer 91. .
  • the first doping and the second doping in the specific embodiments of the present disclosure may be completed in an ion beam implantation apparatus, and the substrate substrate in the specific embodiment of the present disclosure may be placed in the ion beam implantation device.
  • the platform of the ion beam injection device itself can be rotated at multiple angles without the need to separately set the rotating shaft.
  • the first barrier layer and the second barrier layer are removed, and the source 92 and the drain 93 are formed on the semiconductor active layer 91 by a patterning process.
  • the source 92 and the drain are The specific manufacturing method of 93 is the same as the prior art, and will not be described again here.
  • the specific embodiment of the present disclosure may remove the first barrier layer and the second barrier layer by an ashing process and an etching process, and may also remove the first barrier layer and the second barrier layer by a lift-off process.
  • a specific embodiment of the present disclosure further provides a thin film transistor formed by the above-described fabrication method in the specific embodiment of the present disclosure.
  • a specific embodiment of the present disclosure provides a method for doping a film layer, comprising: forming a film layer to be doped by a patterning process on a substrate, the film layer comprising a first region and a second layer a region and a third region, the first region is located in an intermediate region of the film layer, the third region is located at an edge region of the film layer, and the second region is located between the first region and the third region; Forming a first barrier layer and a second barrier layer for blocking the ion beam, the orthographic projection area of the first barrier layer on the film layer just covering the first region, and the orthographic projection area of the second barrier layer on the film layer covers exactly a region and a second region; performing a first doping of the film layer by using an ion beam perpendicular to the substrate, completing doping of the third region; rotating the substrate substrate in a direction parallel to the ion beam by a predetermined angle, So that the second barrier layer does not block the second region, and the second layer is do
  • the doping method of the above film layer used in the specific embodiment of the present disclosure can achieve the doping of the second region and the third region simultaneously in the same ion beam implantation device, and does not need to be lining after the doping of the third region is completed.
  • the bottom substrate is further placed in the etching device to remove the barrier layer at a position directly above the second region. Therefore, the specific embodiment of the present disclosure can simplify the process flow, increase productivity, and improve product yield.

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Abstract

公开了一种膜层的掺杂方法、薄膜晶体管及其制作方法。膜层的掺杂方法包括：在衬底基板上通过第一构图工艺制作一层待掺杂的膜层，该膜层包括第一区、第二区和第三区，第一区位于中间区，第三区位于边缘区，第二区位于第一区和第三区之间；在膜层上通过第二构图工艺依次形成第一阻挡层和第二阻挡层，第一阻挡层在膜层上的正投影区域恰好覆盖第一区，第二阻挡层在膜层上的正投影区域恰好覆盖第一区和第二区；采用与衬底基板垂直的离子束对膜层进行第一次掺杂，完成第三区的掺杂；将衬底基板沿平行于离子束的方向旋转预设角度，使得第二阻挡层不遮挡第二区，采用离子束对膜层进行第二次掺杂，完成第二区的掺杂。

Description

膜层的掺杂方法、薄膜晶体管及其制作方法
相关专利申请
本申请主张于2017年5月19日提交的中国专利申请No.201710357418.1的优先权，其全部内容通过引用结合于此。
技术领域
本公开涉及显示技术领域，尤其涉及膜层的掺杂方法、薄膜晶体管及其制作方法。
背景技术
液晶显示器(Liquid Crystal Display，LCD)、有源矩阵有机发光二极管(Active Matrix Organic Light Emitting Diode，AMOLED)背板技术以及半导体器件工艺制程中，一般需要对半导体层进行多次不同离子、不同剂量的掺杂，以改善其薄膜晶体管(Thin Film Transistor，TFT)电学特性。
发明内容
本公开实施例提供的一种膜层的掺杂方法，包括：
在衬底基板上通过构图工艺制作一层待掺杂的膜层，该膜层包括第一区、第二区和第三区，所述第一区位于该膜层的中间区域，所述第三区位于该膜层的边缘区域，所述第二区位于所述第一区和所述第三区之间；
在所述膜层上通过构图工艺依次形成用于阻挡离子束的第一阻挡层和第二阻挡层，所述第一阻挡层在所述膜层上的正投影区域恰好覆盖所述第一区，所述第二阻挡层在所述膜层上的正投影区域恰好覆盖所述第一区和所述第二区；
采用与所述衬底基板垂直的离子束对所述膜层进行第一次掺杂，完成所述第三区的掺杂；
将所述衬底基板沿平行于所述离子束的方向旋转预设角度，使得所述第二阻挡层不遮挡所述第二区，采用所述离子束对所述膜层进行第二次掺杂，完成所述第二区的掺杂。
在一个或多个实施例中，所述将所述衬底基板沿平行于所述离子束的方向旋转预设角度，使得所述第二阻挡层不遮挡所述第二区，采用所述离子束对所述膜层进行第二次掺杂，完成所述第二区的掺杂，包括：
将所述衬底基板沿平行于所述离子束的方向顺时针旋转预设角度，使得所述第二阻挡层不遮挡所述第二区，采用所述离子束对所述膜层进行第二次掺杂，以及，将所述衬底基板沿平行于所述离子束的方向逆时针旋转预设角度，使得所述第二阻挡层不遮挡所述第二区，采用所述离子束对所述膜层再次进行第二次掺杂，完成所述第二区的掺杂。
在一个或多个实施例中，所述预设角度A满足：tanA＝L/(H1+H2)；其中：
L表示所述第二区在预设方向上的长度值，H1表示所述膜层的厚度值，H2表示所述第一阻挡层的厚度值。
在一个或多个实施例中，所述第一阻挡层和所述第二阻挡层的材料相同。
在一个或多个实施例中，所述采用所述离子束对所述膜层进行第二次掺杂之后，还包括：去除所述第一阻挡层和所述第二阻挡层，形成掺杂后的膜层。
在一个或多个实施例中，所述第二次掺杂的掺杂离子的剂量小于所述第一次掺杂的掺杂离子的剂量
本公开实施例还提供了一种薄膜晶体管的制作方法，包括栅极、源极、漏极和半导体有源层的制作，其中：所述半导体有源层的制作包括：
在衬底基板上通过构图工艺制作半导体层，所述半导体层包括第一区、第二区和第三区，所述第一区位于该半导体层的中间区域，所述第三区位于该半导体层的边缘区域，所述第二区位于所述第一区和所述第三区之间；
在所述半导体层上通过构图工艺依次形成用于阻挡离子束的第一阻挡层和第二阻挡层，所述第一阻挡层在所述半导体层上的正投影区域恰好覆盖所述第一区，所述第二阻挡层在所述半导体层上的正投影区域恰好覆盖所述第一区和所述第二区；
采用与所述衬底基板垂直的离子束对所述半导体层进行第一次掺 杂；
将所述衬底基板沿平行于所述离子束的方向旋转预设角度，使得所述第二阻挡层不遮挡所述第二区，采用所述离子束对所述半导体层进行第二次掺杂，形成半导体有源层。
在一个或多个实施例中，所述在衬底基板上通过构图工艺制作半导体层之前，还包括：
在所述衬底基板上通过构图工艺制作遮光层和缓冲层。
在一个或多个实施例中，所述在所述半导体层上通过构图工艺依次形成用于阻挡离子束的第一阻挡层和第二阻挡层，包括：
在所述半导体层上通过构图工艺依次制作绝缘层和栅极，所述栅极作为第一阻挡层，所述栅极在所述半导体层上的正投影区域恰好覆盖所述第一区；
在所述栅极上通过构图工艺形成用于阻挡离子束的第二阻挡层，所述第二阻挡层在所述半导体层上的正投影区域恰好覆盖所述第一区和所述第二区。
在一个或多个实施例中，所述形成半导体有源层之后，该方法还包括：
去除所述第二阻挡层，在所述半导体有源层上通过构图工艺制作源极和漏极。
在一个或多个实施例中，所述预设角度A满足：tanA＝L/(H1+H2+H3)；其中：
L表示所述第二区在预设方向上的长度值，H1表示所述半导体层的厚度值，H2表示所述绝缘层的位于所述第二区正上方的部分的厚度值，H3表示所述栅极的厚度值。
在一个或多个实施例中，所述衬底基板上通过构图工艺制作半导体层之前，还包括：
在所述衬底基板上通过构图工艺依次制作栅极和绝缘层。
在一个或多个实施例中，所述形成半导体有源层之后，该方法还包括：
去除所述第一阻挡层和所述第二阻挡层，在所述半导体有源层上通过构图工艺制作源极和漏极。
在一个或多个实施例中，所述预设角度A满足：tanA＝L/(H1+H2)； 其中：
L表示所述第二区在预设方向上的长度值，H1表示所述半导体层的厚度值，H2表示所述第一阻挡层的厚度值。
在一个或多个实施例中，所述第一阻挡层和所述第二阻挡层的材料相同。
在一个或多个实施例中，所述第二次掺杂的掺杂离子的剂量小于所述第一次掺杂的掺杂离子的剂量。
在一个或多个实施例中，所述将所述衬底基板沿平行于所述离子束的方向旋转预设角度，使得所述第二阻挡层不遮挡所述第二区，采用所述离子束对所述半导体层进行第二次掺杂，形成半导体有源层，包括：
将所述衬底基板沿平行于所述离子束的方向顺时针旋转预设角度，使得所述第二阻挡层不遮挡所述第二区，采用所述离子束对所述半导体层进行第二次掺杂，以及，将所述衬底基板沿平行于所述离子束的方向逆时针旋转预设角度，使得所述第二阻挡层不遮挡所述第二区，采用所述离子束对所述半导体层再次进行第二次掺杂，形成半导体有源层。
本公开实施例还提供了一种薄膜晶体管，该薄膜晶体管采用上述制作方法制作形成。
附图说明
图1为已知薄膜晶体管的部分结构示意图；
图2为本公开实施例提供的一种膜层的掺杂方法流程图；
图3、4、5a和5b为本公开实施例提供的膜层掺杂过程的不同阶段的结构示意图；
图6为本公开实施例提供的一种薄膜晶体管的制作方法流程图；
图7为本公开实施例提供的顶栅型薄膜晶体管的制作方法流程图；
图8、9a、9b和10为本公开实施例提供的顶栅型薄膜晶体管制作过程的不同阶段的结构示意图；
图11为本公开实施例提供的底栅型薄膜晶体管的制作方法流程图；以及
图12、13a、13b和14为本公开实施例提供的底栅型薄膜晶体管 制作过程的不同阶段的结构示意图。
具体实施方式
如图1所示，顶栅型薄膜晶体管包括依次位于衬底基板10上的遮光层12、缓冲层11、半导体有源层13、绝缘层14、栅极15、以及源极和漏极(图中未示出)。半导体有源层13包括非掺杂区131、轻掺杂区132和重掺杂区133。非掺杂区131对应半导体有源层13的沟道区，重掺杂区133和轻掺杂区132对应半导体有源层13的欧姆接触区。轻掺杂区132即轻掺杂漏结构(Lightly Doped Drain，LDD)，作用是减弱漏区电场，防止热电子退化效应。
如图1所示，在对半导体有源层13进行掺杂时，首先，在栅极15上覆盖一层光刻胶层16，光刻胶层16在衬底基板10上的正投影区域恰好覆盖半导体有源层13的非掺杂区131和轻掺杂区132。接着，采用离子束对半导体有源层13的重掺杂区133进行较大剂量的掺杂，离子束的方向与衬底基板10垂直(如图中箭头所示的方向)，形成了半导体有源层13的重掺杂区133。接着，需要采用离子束对半导体有源层13的轻掺杂区132进行较小剂量的掺杂。此时由于光刻胶层16覆盖了轻掺杂区132而对掺杂离子起到了阻挡作用，因此需要去除该部分的光刻胶层，即去除图中虚线框内的光刻胶层。去除之后再进行较小剂量的掺杂，形成半导体有源层13的轻掺杂区132。
综上所述，不同剂量掺杂时需要通过曝光及刻蚀工艺去除部分光刻胶层，例如去除图1中虚线框内的光刻胶层。这使得不仅工艺繁琐，各项参数控制难度较大，例如灰化(Ashing)的参数控制较难，导致轻掺杂区长度不能有效定义，影响漏电流等关键电学特性参数。并且在去除光刻胶的剥离工艺中容易产生光刻胶残留，进而引发后段工艺的多种不良，不仅降低了良率，也降低了产能。
本公开实施例提供了一种膜层的掺杂方法、薄膜晶体管及其制作方法，用以简化工艺流程，提高产能，提升产品良率。
为了使本公开的目的、技术方案和优点更加清楚，下面将结合附图对本公开作进一步地详细描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其它实 施例，都属于本公开保护的范围。
下面结合附图详细介绍本公开具体实施例提供的膜层的掺杂方法。
附图中各膜层厚度和区域大小、形状不反应各膜层的真实比例，目的只是示意说明本公开内容。
如图2所示，本公开具体实施例提供了一种膜层的掺杂方法，包括：
S201、在衬底基板上通过第一构图工艺制作一层待掺杂的膜层，该膜层包括第一区、第二区和第三区，所述第一区位于该膜层的中间区域，所述第三区位于该膜层的边缘区域，所述第二区位于所述第一区和所述第三区之间；
S202、在所述膜层上通过第二构图工艺依次形成用于阻挡离子束的第一阻挡层和第二阻挡层，所述第一阻挡层在所述膜层上的正投影区域恰好覆盖所述第一区，所述第二阻挡层在所述膜层上的正投影区域恰好覆盖所述第一区和所述第二区；
S203、采用与所述衬底基板垂直的离子束对所述膜层进行第一次掺杂，完成所述第三区的掺杂；
S204、将所述衬底基板沿平行于所述离子束的方向旋转预设角度，使得所述第二阻挡层不遮挡所述第二区，采用所述离子束对所述膜层进行第二次掺杂，完成所述第二区的掺杂；所述第二次掺杂的掺杂离子的剂量小于所述第一次掺杂的掺杂离子的剂量。
具体地，第一区为膜层的非掺杂区，第二区为膜层的轻掺杂区，第三区为膜层的重掺杂区。此处的恰好覆盖是指二者完全重合。例如，第一阻挡层在膜层上的正投影区域恰好覆盖第一区是指第一阻挡层在膜层上的正投影区域与膜层的第一区完全重合。
具体地，本公开具体实施例将衬底基板沿平行于离子束的方向旋转预设角度，使得所述第二阻挡层不遮挡所述第二区，采用离子束对膜层进行第二次掺杂，完成第二区的掺杂，具体包括：
将衬底基板沿平行于离子束的方向顺时针旋转预设角度，使得第二阻挡层不遮挡第二区，采用离子束对膜层进行第二次掺杂，以及，将衬底基板沿平行于离子束的方向逆时针旋转预设角度，使得第二阻挡层不遮挡第二区，采用离子束对膜层再次进行第二次掺杂，完成第二区的掺杂。
下面结合附图详细介绍本公开具体实施例对膜层进行掺杂的具体过程。
如图3所示，在衬底基板10上通过构图工艺制作一层待掺杂的膜层31，该膜层31包括第一区311、第二区313和第三区312，第一区311位于该膜层31的中间区域，第三区312位于该膜层31的边缘区域，第二区313位于第一区311和第三区312之间。第一区311对应膜层31的非掺杂区，第三区312对应膜层31的重掺杂区，第二区313对应膜层31的轻掺杂区。本公开具体实施例中的构图工艺包括光刻胶的涂覆、曝光、显影、刻蚀，以及去除光刻胶的部分或全部过程。本公开具体实施例中的衬底基板10可以为玻璃基板，也可以为其它类型的基板，如可以为石英基板。本公开具体实施例中的膜层31可以为半导体膜层。
如图4所示，接着，在膜层31上通过构图工艺依次形成用于阻挡离子束的第一阻挡层41和第二阻挡层42，第一阻挡层41在膜层31上的正投影区域恰好覆盖第一区311，第二阻挡层42在膜层31上的正投影区域恰好覆盖第一区311和第二区313。在示例性实施例中，本公开具体实施例形成的第一阻挡层41和第二阻挡层42的材料相同。具体实施时，第一阻挡层41和第二阻挡层42可以选择光刻胶层，当然实际生产过程中还可以选择其它类型的阻挡膜层，只要能够起到阻挡离子掺杂过程中注入的离子的作用即可。
接着，如图4所示，采用与衬底基板10垂直的离子束(离子束注入方向如图中的箭头所示的方向)对膜层31进行第一次掺杂，完成膜层31的第三区312的掺杂。第一次掺杂时，由于第一区311和第二区313被第一阻挡层41和第二阻挡层42遮挡，因此膜层31的第一区311和第二区313在第一次掺杂过程中没有被掺杂。本公开具体实施例第一次掺杂时，离子束注入的掺杂离子的剂量较大，如：注入剂量较大的n型掺杂离子或p型掺杂离子。
接着，如图5a所示，将衬底基板10沿平行于离子束的方向顺时针旋转预设角度A，使得第二阻挡层42不遮挡第二区313，采用离子束对膜层31进行第二次掺杂，完成第一区311下方的第二区313的掺杂。本公开具体实施例第二次掺杂时，离子束注入的掺杂离子的剂量较小，本公开具体实施例中旋转的预设角度A需要满足：将衬底基板 10沿平行于离子束的方向旋转预设角度A后能够暴露第二区313。具体实施时，预设角度A满足：tanA＝L/(H1+H2)；其中：L表示第二区313在预设方向(如第二区313在平行于衬底基板10的方向)上的长度值，H1表示膜层31的厚度值，H2表示第一阻挡层41的厚度值。
同样地，如图5b所示，将衬底基板10沿平行于离子束的方向逆时针旋转预设角度A，再次采用离子束对膜层31进行第二次掺杂，完成第一区311上方的第二区313的掺杂。
具体实施时，本公开具体实施例中的第一次掺杂和第二次掺杂均可以在离子束注入设备中完成，可以将本公开具体实施例中的衬底基板放置在离子束注入设备的平台上，离子束注入设备的平台本身可以进行多角度旋转，不需要单独设置旋转轴，衬底基板旋转后因离子束与衬底基板的距离产生的变化带来的离子注入深度的影响，可根据离子加速电压的设置来控制，具体可对比正常垂直注入模式的电学特性做实验测试。衬底基板旋转后的离子注入区域为梯形体区域，相比正常垂直注入模式的长方体区域会少一个三角形区域，具体实施时可通过调整离子注入剂量来实现与正常垂直注入模式的电学特性的匹配。
最后，本公开具体实施例在采用离子束对膜层进行第二次掺杂之后，还包括：去除第一阻挡层和第二阻挡层，形成掺杂后的膜层。具体实施时，本公开具体实施例可以采用灰化工艺和干法刻蚀工艺去除第一阻挡层和第二阻挡层，也可以采用剥离工艺去除第一阻挡层和第二阻挡层。
本公开具体实施例采用的以上膜层的掺杂方法，可以实现在同一离子束注入设备中同时完成重掺杂区和轻掺杂区的掺杂，不需要在完成重掺杂区的掺杂后将衬底基板再放入刻蚀设备中去除轻掺杂区正上方位置处的阻挡层，然后再放入离子束注入设备中完成轻掺杂区的掺杂，因此，本公开具体实施例能够简化工艺流程，提高产能，提升产品良率。
基于同一发明构思，本公开具体实施例还提供了一种薄膜晶体管的制作方法，如图6所示，包括栅极、源极、漏极和半导体有源层的制作，其中，半导体有源层的制作包括：
S601、在衬底基板上通过第一构图工艺制作半导体层，所述半导体层包括第一区、第二区和第三区，所述第一区位于该半导体层的中 间区域，所述第三区位于该半导体层的边缘区域，所述第二区位于所述第一区和所述第三区之间；
S602、在所述半导体层上通过第二构图工艺依次形成用于阻挡离子束的第一阻挡层和第二阻挡层，所述第一阻挡层在所述半导体层上的正投影区域恰好覆盖所述第一区，所述第二阻挡层在所述半导体层上的正投影区域恰好覆盖所述第一区和所述第二区；
S603、采用与所述衬底基板垂直的离子束对所述半导体层进行第一次掺杂；
S604、将所述衬底基板沿平行于所述离子束的方向旋转预设角度，使得所述第二阻挡层不遮挡所述第二区，采用所述离子束对所述半导体层进行第二次掺杂，形成半导体有源层；所述第二次掺杂的掺杂离子的剂量小于所述第一次掺杂的掺杂离子的剂量。
具体地，第一区为半导体层的非掺杂区、第二区为半导体层的轻掺杂区、第三区为半导体层的重掺杂区。
本公开具体实施例制作形成的薄膜晶体管可以为顶栅型的薄膜晶体管，也可以为底栅型的薄膜晶体管，当然还可以为其它类型的薄膜晶体管，如：可以为侧栅型的薄膜晶体管。
下面分别以顶栅型的薄膜晶体管和底栅型的薄膜晶体管为例，详细介绍本公开具体实施例制作薄膜晶体管的方法。
如图7所示，本公开具体实施例的薄膜晶体管的制作方法包括：
S701、在衬底基板上通过第三构图工艺制作遮光层和缓冲层；
S702、在所述缓冲层上通过第一构图工艺制作半导体层，所述半导体层包括第一区、第二区和第三区，所述第一区位于该半导体层的中间区域，所述第三区位于该半导体层的边缘区域，所述第二区位于所述第一区和所述第三区之间；
S703、在所述半导体层上通过第四构图工艺依次制作绝缘层和栅极，所述栅极作为第一阻挡层，所述栅极在所述半导体层上的正投影区域恰好覆盖所述第一区；
S704、在所述栅极上通过第五构图工艺形成用于阻挡离子束的第二阻挡层，所述第二阻挡层在所述半导体层上的正投影区域恰好覆盖所述第一区和所述第二区；
S705、采用与所述衬底基板垂直的离子束对所述半导体层进行第 一次掺杂；
S706、将所述衬底基板沿平行于所述离子束的方向旋转预设角度，使得所述第二阻挡层不遮挡所述第二区，采用所述离子束对所述半导体层进行第二次掺杂，形成半导体有源层；所述第二次掺杂的掺杂离子的剂量小于所述第一次掺杂的掺杂离子的剂量；
S707、去除所述第二阻挡层，在所述半导体有源层上通过构图工艺制作源极和漏极。
具体地，本公开具体实施例将衬底基板沿平行于离子束的方向旋转预设角度，使得第二阻挡层不遮挡第二区，采用离子束对半导体层进行第二次掺杂，形成半导体有源层，具体包括：
将衬底基板沿平行于离子束的方向顺时针旋转预设角度，使得第二阻挡层不遮挡第二区，采用离子束对半导体层进行第二次掺杂，以及，将衬底基板沿平行于离子束的方向逆时针旋转预设角度，使得第二阻挡层不遮挡第二区，采用离子束对半导体层再次进行第二次掺杂，形成半导体有源层。
下面结合附图详细介绍图7所示具体实施例的薄膜晶体管的具体制作过程。
如图8所示，首先，在衬底基板10上通过构图工艺制作遮光层12和缓冲层11，本公开具体实施例中的遮光层12和缓冲层11的具体制作方法与已有技术相同，这里不再赘述。接着，在缓冲层11上通过构图工艺制作半导体层71，半导体层71包括第一区711、第二区713和第三区712，第一区711位于半导体层71的中间区域，第三区712位于半导体层71的边缘区域，第二区713位于第一区711和第三区712之间，第一区711对应半导体层71的非掺杂区、第三区712对应半导体层71的重掺杂区，第二区713对应半导体层71的轻掺杂区，本公开具体实施例中的半导体层71的具体制作方法与已有技术类似，这里不再赘述。接着，在半导体层71上通过构图工艺依次制作绝缘层14和栅极15，本公开具体实施例中的绝缘层14和栅极15的具体制作方法与已有技术相同，这里不再赘述，图7所示具体实施例中的栅极15在后续掺杂过程中作为阻挡层。
如图8所示，接着，在栅极15上通过构图工艺形成第二阻挡层72，具体实施时，第二阻挡层72可以选择光刻胶层，第二阻挡层72在半 导体层71上的正投影区域恰好覆盖第一区711和第二区713。
如图8所示，接着，采用与衬底基板10垂直的离子束对半导体层71进行第一次掺杂，第一次掺杂时，由于第一区711和第二区713被栅极15和第二阻挡层72遮挡，因此半导体层71的第一区711和第二区713在第一次掺杂过程中没有被掺杂，本公开具体实施例第一次掺杂时，离子束注入的掺杂离子的剂量较大，如：注入剂量较大的n型掺杂离子或p型掺杂离子。
接着，如图9a所示，将衬底基板10沿平行于离子束的方向顺时针旋转预设角度A，使得第二阻挡层72不遮挡第二区713，采用离子束对半导体层71进行第二次掺杂，本公开具体实施例第二次掺杂时，离子束注入的掺杂离子的剂量较小，本公开具体实施例中旋转的预设角度A需要满足：将衬底基板10沿平行于离子束的方向旋转预设角度A后能够暴露出第二区713，以使得离子束能够对第二区713进行掺杂。
具体实施时，预设角度A满足：tanA＝L/(H1+H2+H3)；其中：L表示半导体层的第二区在预设方向(如第二区在平行于衬底基板10的方向)上的长度值，H1表示半导体层71的厚度值，H2表示绝缘层14的位于第二区713正上方的部分的厚度值，H3表示栅极15的厚度值。例如：本公开具体实施例中半导体层的第二区在平行于衬底基板10的方向上的长度值为0.25m，半导体层71的厚度值为500埃
Figure PCTCN2018087484-appb-000001
绝缘层14的厚度值为
Figure PCTCN2018087484-appb-000002
栅极15的厚度值为
Figure PCTCN2018087484-appb-000003
根据以上公式计算得到的预设角度A为33°。
同样地，如图9b所示，将衬底基板10沿平行于离子束的方向逆时针旋转预设角度A，再次采用离子束对半导体层71进行第二次掺杂，形成半导体有源层。
具体实施时，本公开具体实施例中的第一次掺杂和第二次掺杂均可以在离子束注入设备中完成，可以将本公开具体实施例中的衬底基板放置在离子束注入设备的平台上，离子束注入设备的平台本身可以进行多角度旋转，不需要单独设置旋转轴。实现了离子束不仅能在垂直衬底基板的方向注入，而且能在与衬底基板成一定角度的方向注入，本公开具体实施例在对半导体层掺杂形成半导体有源层时，不需要通过灰化、刻蚀工艺去除轻掺杂区上方的阻挡层的情况下，同样能够使掺杂离子注入到轻掺杂区，提高了工艺及各项参数的管控能力，消除 了因光刻胶变性发生的光刻胶残留问题，进而能够简化工艺、提升产能、提高离子注入效率以及提升产品良率。
最后，如图10所示，去除第二阻挡层，在半导体有源层91上通过构图工艺制作源极92和漏极93，本公开具体实施例中源极92和漏极93的具体制作方法与、已有技术相同，这里不再赘述。具体实施时，本公开具体实施例可以通过灰化工艺和刻蚀工艺去除第二阻挡层，也可以通过剥离工艺去除第二阻挡层。
本公开具体实施例采用以上方法制作薄膜晶体管时，在制作半导体有源层时，在对半导体层进行第一次掺杂后，本公开具体实施例不需要将经过第一次掺杂后的衬底基板搬送到刻蚀设备进行轻掺杂区正上方阻挡层的刻蚀，本公开具体实施例可以保留第二阻挡层，此时将衬底基板按照预设角度旋转一定角度就可以完成轻掺杂区的掺杂，本公开具体实施例能够实现重掺杂区和轻掺杂区在同一离子束注入设备实现一次性完成，无需再增加灰化、刻蚀工艺过程。
如图11所示，本公开具体实施例的薄膜晶体管的制作方法包括：
S1101、在衬底基板上通过第七构图工艺制作栅极和绝缘层并且通过第一构图工艺制作半导体层，所述半导体层包括第一区、第二区和第三区，所述第一区位于该膜层的中间区域，所述第三区位于该膜层的边缘区域，所述第二区位于所述第一区和所述第三区之间；
S1102、在所述半导体层上通过第二构图工艺依次形成用于阻挡离子束的第一阻挡层和第二阻挡层，所述第一阻挡层在所述半导体层上的正投影区域恰好覆盖所述第一区，所述第二阻挡层在所述半导体层上的正投影区域恰好覆盖所述第一区和所述第二区；
S1103、采用与所述衬底基板垂直的离子束对所述半导体层进行第一次掺杂；
S1104、将所述衬底基板沿平行于所述离子束的方向旋转预设角度，使得所述第二阻挡层不遮挡所述第二区，采用所述离子束对所述半导体层进行第二次掺杂，形成半导体有源层；所述第二次掺杂的掺杂离子的剂量小于所述第一次掺杂的掺杂离子的剂量；
S1105、去除所述第一阻挡层和所述第二阻挡层，在所述半导体有源层上通过第八构图工艺制作源极和漏极。
具体地，本公开具体实施例将衬底基板沿平行于离子束的方向旋 转预设角度，使得第二阻挡层不遮挡第二区，采用离子束对半导体层进行第二次掺杂，形成半导体有源层，具体包括：
将衬底基板沿平行于离子束的方向顺时针旋转预设角度，使得第二阻挡层不遮挡第二区，采用离子束对半导体层进行第二次掺杂，以及，将衬底基板沿平行于离子束的方向逆时针旋转预设角度，使得第二阻挡层不遮挡第二区，采用离子束对半导体层再次进行第二次掺杂，形成半导体有源层。
下面结合附图详细介绍本公开具体实施例薄膜晶体管的具体制作过程。
如图12所示，首先，在衬底基板10上通过构图工艺依次制作栅极15、绝缘层14和半导体层71，半导体层71包括第一区711、第二区713和第三区712，第一区711位于半导体层71的中间区域，第三区712位于半导体层71的边缘区域，第二区713位于第一区711和第三区712之间，第一区711对应半导体层71的非掺杂区、第三区712对应半导体层71的重掺杂区，第二区713对应半导体层71的轻掺杂区，本公开具体实施例中的栅极15、绝缘层14和半导体层71的具体制作方法与已有技术类似，这里不再赘述。
接着，如图12所示，在半导体层71上通过构图工艺依次形成第一阻挡层111和第二阻挡层112，第一阻挡层111在半导体层71上的正投影区域恰好覆盖第一区711，第二阻挡层112在半导体层71上的正投影区域恰好覆盖第一区711和第二区713。在示例性实施例中，本公开具体实施例形成的第一阻挡层111和第二阻挡层112的材料相同，具体实施时，第一阻挡层111和第二阻挡层112可以选择光刻胶层。
如图12所示，接着，采用与衬底基板10垂直的离子束对半导体层71进行第一次掺杂，第一次掺杂时，由于第一区711和第二区713被第一阻挡层111和第二阻挡层112遮挡，因此半导体层71的第一区711和第二区713在第一次掺杂过程中没有被掺杂，本公开具体实施例第一次掺杂时，离子束注入的掺杂离子的剂量较大，如：注入剂量较大的n型掺杂离子或p型掺杂离子。
接着，如图13a所示，将衬底基板10沿平行于离子束的方向顺时针旋转预设角度A，使得第二阻挡层112不遮挡第二区713，采用离子束对半导体层71进行第二次掺杂，本公开具体实施例第二次掺杂时， 离子束注入的掺杂离子的剂量较小，本公开具体实施例中旋转的预设角度A需要满足：将衬底基板10沿平行于离子束的方向旋转预设角度A后能够暴露第二区713。具体实施时，预设角度A满足：tanA＝L/(H1+H2)；其中：L表示半导体层的第二区在预设方向(如第二区在平行于衬底基板10的方向)上的长度值，H1表示半导体层71的厚度值，H2表示第一阻挡层111的厚度值。
同样地，如图13b所示，将衬底基板10沿平行于离子束的方向逆时针旋转预设角度A，再次采用离子束对半导体层71进行第二次掺杂，形成半导体有源层91。
具体实施时，本公开具体实施例中的第一次掺杂和第二次掺杂均可以在离子束注入设备中完成，可以将本公开具体实施例中的衬底基板放置在离子束注入设备的平台上，离子束注入设备的平台本身可以进行多角度旋转，不需要单独设置旋转轴。
最后，如图14所示，去除第一阻挡层和第二阻挡层，在半导体有源层91上通过构图工艺制作源极92和漏极93，本公开具体实施例中源极92和漏极93的具体制作方法与已有技术相同，这里不再赘述。具体实施时，本公开具体实施例可以通过灰化工艺和刻蚀工艺去除第一阻挡层和第二阻挡层，也可以通过剥离工艺去除第一阻挡层和第二阻挡层。
基于同一发明构思，本公开具体实施例还提供了一种薄膜晶体管，该薄膜晶体管采用本公开具体实施例中的上述制作方法制作形成。
综上所述，本公开具体实施例提供一种膜层的掺杂方法，包括：在衬底基板上通过构图工艺制作一层待掺杂的膜层，该膜层包括第一区、第二区和第三区，第一区位于该膜层的中间区域，第三区位于该膜层的边缘区域，第二区位于第一区和第三区之间；在膜层上通过构图工艺依次形成用于阻挡离子束的第一阻挡层和第二阻挡层，第一阻挡层在膜层上的正投影区域恰好覆盖第一区，第二阻挡层在膜层上的正投影区域恰好覆盖第一区和第二区；采用与衬底基板垂直的离子束对膜层进行第一次掺杂，完成第三区的掺杂；将衬底基板沿平行于离子束的方向旋转预设角度，使得第二阻挡层不遮挡第二区，采用离子束对膜层进行第二次掺杂，完成第二区的掺杂；第二次掺杂的掺杂离子的剂量小于第一次掺杂的掺杂离子的剂量。本公开具体实施例采用 的以上膜层的掺杂方法，可以实现在同一离子束注入设备中同时完成第二区和第三区的掺杂，不需要在完成第三区的掺杂后将衬底基板再放入刻蚀设备中去除第二区正上方位置处的阻挡层，因此，本公开具体实施例能够简化工艺流程，提高产能，提升产品良率。
显然，本领域的技术人员可以对本公开进行各种改动和变型而不脱离本公开的精神和范围。这样，倘若本公开的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (17)

  1. 一种膜层的掺杂方法，包括：
    在衬底基板上通过第一构图工艺制作一层待掺杂的膜层，该膜层包括第一区、第二区和第三区，所述第一区位于该膜层的中间区域，所述第三区位于该膜层的边缘区域，所述第二区位于所述第一区和所述第三区之间：
    在所述膜层上通过第二构图工艺依次形成用于阻挡离子束的第一阻挡层和第二阻挡层，所述第一阻挡层在所述膜层上的正投影区域恰好覆盖所述第一区，所述第二阻挡层在所述膜层上的正投影区域恰好覆盖所述第一区和所述第二区；
    采用与所述衬底基板垂直的离子束对所述膜层进行第一次掺杂，完成所述第三区的掺杂；
    将所述衬底基板沿平行于所述离子束的方向旋转预设角度，使得所述第二阻挡层不遮挡所述第二区，采用所述离子束对所述膜层进行第二次掺杂，完成所述第二区的掺杂。
  2. 根据权利要求1所述的掺杂方法，其中所述将所述衬底基板沿平行于所述离子束的方向旋转预设角度，使得所述第二阻挡层不遮挡所述第二区，采用所述离子束对所述膜层进行第二次掺杂，完成所述第二区的掺杂，包括：
    将所述衬底基板沿平行于所述离子束的方向顺时针旋转预设角度，使得所述第二阻挡层不遮挡所述第二区，采用所述离子束对所述膜层进行第二次掺杂，以及，将所述衬底基板沿平行于所述离子束的方向逆时针旋转预设角度，使得所述第二阻挡层不遮挡所述第二区，采用所述离子束对所述膜层再次进行第二次掺杂，完成所述第二区的掺杂。
  3. 根据权利要求2所述的掺杂方法，其中所述预设角度A满足：tanA＝L/(H1+H2)；其中：
    L表示所述第二区在预设方向上的长度值，H1表示所述膜层的厚度值，H2表示所述第一阻挡层的厚度值。
  4. 根据权利要求1所述的掺杂方法，其中所述第一阻挡层和所述第二阻挡层的材料相同。
  5. 根据权利要求1所述的掺杂方法，其中所述采用所述离子束对 所述膜层进行第二次掺杂之后，还包括：去除所述第一阻挡层和所述第二阻挡层，形成掺杂后的膜层。
  6. 根据权利要求1—5中任意一项所述的掺杂方法，其中所述第二次掺杂的掺杂离子的剂量小于所述第一次掺杂的掺杂离子的剂量。
  7. 一种薄膜晶体管的制作方法，包括栅极、源极、漏极和半导体有源层的制作，其中所述半导体有源层的制作包括：
    在衬底基板上通过第一构图工艺制作半导体层，所述半导体层包括第一区、第二区和第三区，所述第一区位于该半导体层的中间区域，所述第三区位于该半导体层的边缘区域，所述第二区位于所述第一区和所述第三区之间：
    在所述半导体层上通过第二构图工艺依次形成用于阻挡离子束的第一阻挡层和第二阻挡层，所述第一阻挡层在所述半导体层上的正投影区域恰好覆盖所述第一区，所述第二阻挡层在所述半导体层上的正投影区域恰好覆盖所述第一区和所述第二区；
    采用与所述衬底基板垂直的离子束对所述半导体层进行第一次掺杂；
    将所述衬底基板沿平行于所述离子束的方向旋转预设角度，使得所述第二阻挡层不遮挡所述第二区，采用所述离子束对所述半导体层进行第二次掺杂，形成半导体有源层。
  8. 根据权利要求7所述的制作方法，其中所述在衬底基板上通过第一构图工艺制作半导体层之前，还包括：
    在所述衬底基板上通过第三构图工艺制作遮光层和缓冲层。
  9. 根据权利要求8所述的制作方法，其中所述在所述半导体层上通过第二构图工艺依次形成用于阻挡离子束的第一阻挡层和第二阻挡层，包括：
    在所述半导体层上通过第四构图工艺依次制作绝缘层和栅极，所述栅极作为第一阻挡层，所述栅极在所述半导体层上的正投影区域恰好覆盖所述第一区；
    在所述栅极上通过第五构图工艺形成用于阻挡离子束的第二阻挡层，所述第二阻挡层在所述半导体层上的正投影区域恰好覆盖所述第一区和所述第二区。
  10. 根据权利要求9所述的制作方法，其中所述形成半导体有源 层之后，该方法还包括：
    去除所述第二阻挡层，在所述半导体有源层上通过第六构图工艺制作源极和漏极。
  11. 根据权利要求10所述的制作方法，其中所述预设角度A满足：tanA＝L/(H1+H2+H3)；其中：
    L表示所述第二区在预设方向上的长度值，H1表示所述半导体层的厚度值，H2表示所述绝缘层的位于所述第二区正上方的部分的厚度值，H3表示所述栅极的厚度值。
  12. 根据权利要求7所述的制作方法，其中所述在衬底基板上通过第一构图工艺制作半导体层之前，还包括：
    在所述衬底基板上通过第七构图工艺依次制作栅极和绝缘层。
  13. 根据权利要求12所述的制作方法，其中所述形成半导体有源层之后，该方法还包括：
    去除所述第一阻挡层和所述第二阻挡层，在所述半导体有源层上通过第八构图工艺制作源极和漏极。
  14. 根据权利要求13所述的制作方法，其中所述预设角度A满足：tanA＝L/(H1+H2)；其中：
    L表示所述第二区在预设方向上的长度值，H1表示所述半导体层的厚度值，H2表示所述第一阻挡层的厚度值，所述第一阻挡层和所述第二阻挡层的材料相同。
  15. 根据权利要求7所述的制作方法，其中所述第二次掺杂的掺杂离子的剂量小于所述第一次掺杂的掺杂离子的剂量。
  16. 根据权利要求7—15任一项所述的制作方法，其中所述将所述衬底基板沿平行于所述离子束的方向旋转预设角度，使得所述第二阻挡层不遮挡所述第二区，采用所述离子束对所述半导体层进行第二次掺杂，形成半导体有源层，包括：
    将所述衬底基板沿平行于所述离子束的方向顺时针旋转预设角度，使得所述第二阻挡层不遮挡所述第二区，采用所述离子束对所述半导体层进行第二次掺杂，以及，将所述衬底基板沿平行于所述离子束的方向逆时针旋转预设角度，使得所述第二阻挡层不遮挡所述第二区，采用所述离子束对所述半导体层再次进行第二次掺杂，形成半导体有源层。
  17. 一种薄膜晶体管，采用权利要求7—16任一项所述的制作方法制作形成。
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