WO2018205569A1 - 显示基板及其制备方法、显示面板和显示装置 - Google Patents

显示基板及其制备方法、显示面板和显示装置 Download PDF

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Publication number
WO2018205569A1
WO2018205569A1 PCT/CN2017/114294 CN2017114294W WO2018205569A1 WO 2018205569 A1 WO2018205569 A1 WO 2018205569A1 CN 2017114294 W CN2017114294 W CN 2017114294W WO 2018205569 A1 WO2018205569 A1 WO 2018205569A1
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Prior art keywords
substrate
insulating layer
signal line
display
layer
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PCT/CN2017/114294
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English (en)
French (fr)
Inventor
崔晓晨
栗鹏
朴正淏
金在光
李哲
李晓吉
赵冬兴
Original Assignee
京东方科技集团股份有限公司
重庆京东方光电科技有限公司
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Priority to US16/068,297 priority Critical patent/US11209709B2/en
Publication of WO2018205569A1 publication Critical patent/WO2018205569A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/136295—Materials; Compositions; Manufacture processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133357—Planarisation layers

Definitions

  • At least one embodiment of the present disclosure is directed to a display substrate, a method of fabricating the same, a display panel, and a display device.
  • At least one embodiment of the present disclosure provides a display substrate including: a substrate substrate, at least one first signal line disposed on the substrate substrate, and a first insulating layer disposed in parallel with the first signal line, wherein a surface of the first insulating layer remote from the substrate and a surface of the first signal line remote from the substrate are parallel to the substrate and substantially in the same continuous plane.
  • the display substrate provided by at least one embodiment of the present disclosure may further include: a second insulating layer disposed on the base substrate; wherein the second insulating layer covers the first signal line and the first Insulation.
  • the display substrate provided by at least one embodiment of the present disclosure may further include: a first electrode or a semiconductor layer disposed on a side of the second insulating layer away from the substrate.
  • the first signal line includes at least one or a combination of a gate line, a data line, and a common electrode line.
  • the first signal line is a common electrode line
  • the first insulating layer is a gate insulating layer
  • the display substrate is an array substrate.
  • At least one embodiment of the present disclosure provides a display panel including any of the above display substrates.
  • At least one embodiment of the present disclosure provides a display device including any of the above display panels.
  • At least one embodiment of the present disclosure provides a method of fabricating a display substrate, including: providing a substrate; forming at least one first signal line on the substrate; forming the first on the substrate a first insulating layer in which the signal lines are juxtaposed; wherein a surface of the first insulating layer remote from the substrate substrate and a surface of the first signal line remote from the substrate substrate are parallel to the substrate basically in the same continuous plane.
  • forming at least one first signal line on the base substrate may include: providing a first mask; depositing a conductive layer film on the substrate And coating a first photoresist layer on the conductive layer film; exposing the first photoresist layer through the first mask to develop the exposed first photoresist layer To obtain a first photoresist pattern, the conductive layer film is patterned using the first photoresist pattern to form at least one of the first signal lines.
  • forming the first insulating layer disposed on the substrate substrate in parallel with the first signal line may include: in a direction perpendicular to the substrate substrate Depositing a first insulating layer film substantially the same as the thickness of the first signal line on the base substrate on which at least one of the first signal lines is formed; coating the first insulating layer film Coating a second photoresist layer; exposing the second photoresist layer through the first mask plate on a side of the second photoresist layer away from the substrate substrate. The second photoresist layer is developed to obtain a second photoresist pattern, and the first insulating layer film is patterned using the second photoresist pattern to form the first insulating layer.
  • the first photoresist layer is a positive photoresist layer
  • the second photoresist layer is a negative photoresist layer
  • the first photoresist layer is a negative photoresist layer
  • the second photoresist layer is a positive photoresist layer.
  • Forming the first insulating layer disposed side by side with the first signal line may include: depositing on the substrate substrate on which at least one of the first signal lines is formed in a direction perpendicular to the substrate substrate a first insulating layer film substantially the same as a thickness of the first signal line; coating a third photoresist layer on the first gate insulating layer film; away from the first On one side of the signal line, the third photoresist layer is exposed by using the first signal line as a mask, and the exposed third photoresist layer is developed to obtain a third photoresist pattern. And patterning the first insulating layer film using the third photoresist pattern to form the first insulating layer.
  • the third photoresist layer is a negative photoresist layer.
  • the preparation method provided by at least one embodiment of the present disclosure may further include: forming a second insulating layer on the base substrate on which the first signal line and the first insulating layer are formed; wherein the second insulation A layer covers the first signal line and the first insulating layer.
  • 1 is a schematic structural view of a display substrate
  • FIG. 2 is a schematic structural diagram of a display substrate according to an embodiment of the present disclosure
  • FIG. 3 is a schematic structural diagram of another display substrate according to an embodiment of the present disclosure.
  • FIG. 3b is another schematic structural diagram of a display substrate according to an embodiment of the present disclosure.
  • FIG. 4 is a graph showing light transmittance of a display substrate provided by an embodiment of the present disclosure.
  • FIG. 5 is a simulation diagram of light transmittance of a display substrate according to an embodiment of the present disclosure
  • 6a to 6i, 7a to 7d, and 8 to 13 are diagrams showing a process of preparing a display substrate according to an embodiment of the present disclosure.
  • the signal line disposed in the display substrate may cause a step difference at the edge of the display region in the pixel region, which may cause unevenness of the structure of each layer disposed on the display substrate, resulting in poor display of image sticking or the like.
  • the design thickness of the signal line is usually limited, but the functionality of the signal line may be poor, such as high resistivity, small strength, easy breakage, or flattening layer to flatten the surface of the display substrate, but This may increase the thickness of the display display substrate, which is disadvantageous for thinning.
  • FIG. 1 is a schematic structural view of a display substrate.
  • a first signal line 210 an insulating layer 300 , a second signal line 220 , an interlayer dielectric layer 400 , and a first electrode 500 are disposed on the substrate substrate 100 .
  • the first electrode 500 corresponds to the pixel region.
  • Display area B Due to the setting of the first signal line 210, there is a step area B3 near the edge of the display area.
  • the display substrate is an array substrate
  • the first signal line 210 is a gate line
  • the insulating layer 300 is a gate insulating layer
  • the second signal line 220 is a data line.
  • the display substrate shown in FIG. 1 as an example for a liquid crystal display panel, it is necessary to provide an alignment layer 600 on the surface of the display substrate by an alignment process to pre-orient the liquid crystal molecules, but at the step region B3, the intensity of the alignment layer 600
  • the direction and the flat area are different, so that the initial alignment of the liquid crystal molecules is disordered, causing the liquid crystal molecules at the step region B3 and the liquid crystal molecules at the flat region to be in an operating state.
  • the step difference is such that the thickness of the liquid crystal molecules on the region B1 and the liquid crystal molecules on the region B2 are different, and thus the liquid crystal molecules and the region B2 on the region B1
  • the degree of deflection of the liquid crystal molecules Display panel is located at work In the state of the state, the degree of deflection of the liquid crystal molecules on the step region B3, the region B1, and the region B2 is different. For example, the dark state cannot be simultaneously reached in a short period of time, resulting in display failure such as image sticking and contrast reduction.
  • the display failure caused by the step difference on the surface of the display substrate is not limited to the above.
  • the display substrate may be an array substrate, and in the actual production process, a signal line is also prepared when preparing a thin film transistor in the array substrate, because the preparation process of the thin film transistor is complicated, in the process of forming each layer structure in the thin film transistor. Because the step difference is too large, the number of slopes generated in the formation process of each layer structure in the thin film transistor may increase, resulting in, for example, an increase in parasitic capacitance.
  • At least one embodiment of the present disclosure provides a display substrate and a method of fabricating the same, a display panel, and a display device, which can eliminate or reduce a step difference on a display substrate.
  • At least one embodiment of the present disclosure provides a display substrate including: a substrate substrate, at least one first signal line disposed on the substrate substrate, and a first insulating layer, wherein the first insulating layer is away from the substrate
  • the surface of the substrate and the surface of the first signal line remote from the substrate substrate are both parallel to the substrate substrate and substantially in the same continuous plane.
  • the first insulating layer disposed in parallel with the first signal line can improve the flatness of the surface of the display substrate, and avoid problems such as poor display due to excessive step difference in the structure disposed on the display substrate.
  • the relationship between the first signal line and the first insulating layer is expressed in a matching manner, and the layer in which the first signal line and the first insulating layer are disposed in the display substrate is planarized Settings.
  • a plurality of signal lines may be disposed on the display substrate, and the signal lines may be one type of signal lines or a plurality of types of signal lines.
  • the signal lines may be located on the same layer of the display substrate or on different layers of the display substrate.
  • the signal line includes a plurality of signal lines located in different layers, as long as one of the layers (for example, the layer in which the first signal line is located) is provided with the first insulating layer, and the surface of the first insulating layer away from the substrate is The surface of the first signal line in the layer remote from the substrate substrate is substantially in the same continuous plane, thereby improving the flatness of the surface of the display substrate.
  • FIG. 2 is a schematic structural view of a display substrate according to an embodiment of the present disclosure.
  • the display substrate may include a base substrate 100 , a first signal line 210 disposed on the base substrate 100 , and a first insulating layer 310 .
  • the surface of the first insulating layer 310 remote from the substrate 100 is substantially in the same continuous plane as the surface of the first signal line 210 remote from the substrate 100.
  • the surface of the first insulating layer 310 remote from the substrate 100 and the surface of the first signal line 210 remote from the substrate 100 may be parallel to the substrate 100.
  • the thickness of the first insulating layer 310 is close to or equal to the thickness of the first signal line 210.
  • the surface flatness of the structural layer of the display substrate on which the first signal line 210 is disposed is improved as compared with the display substrate shown in FIG.
  • the display substrate may further include a second insulating layer 320 disposed on the base substrate 100, and the second insulating layer 320 may cover the first signal line 210 and The first insulating layer 310.
  • the display substrate is provided with a structural layer (for example, the first electrode 500 and the second insulating layer 320) of the insulating substrate 300 (for example, the first electrode 500 and the alignment layer) as compared with the display substrate shown in FIG. The surface flatness of 600, etc. is improved.
  • the display substrate may further include a first electrode 500 disposed on a side of the second insulating layer 320 away from the substrate 100.
  • the first electrode 500 may be a pixel electrode and/or a common electrode.
  • the flatness of the surface of the second insulating layer 320 away from the substrate 100 side is improved, and the flatness at the display region B corresponding to the first electrode 500 is also improved as compared with the display substrate shown in FIG.
  • the display substrate may further include an alignment layer 600 disposed on the second insulating layer 320.
  • the flatness of the surface of the second insulating layer 320 away from the substrate 100 side is improved, and the flatness of the alignment layer 600 at the display region B is also improved, that is, the display region, compared with the display substrate shown in FIG.
  • the intensity and direction distribution of the alignment layer 600 at B is uniform, and in the operating state, the liquid crystal molecules at the display region B can reach a state of synchronous deflection.
  • the alignment layer 600 may be a polyimide layer and subjected to a rubbing treatment.
  • the display substrate is not limited to improving display failure problems in the field of liquid crystal display.
  • the display substrate may be an organic light emitting diode display substrate, and the organic light emitting device
  • the parameters such as the flatness of the organic light-emitting layer directly affect the performance of the organic light-emitting device.
  • the display substrate can flatten the structure of each layer in the display substrate, reduce the step difference, and accordingly, can improve the flatness of the light-emitting layer and the like, and improve the performance of the organic light-emitting device.
  • the signal line 200 may be at least one or a combination of a gate line, a data line, a common electrode line, and the like.
  • the signal line 200 includes a first signal line 210 and a second signal line 220.
  • the first signal line 210 may be a common electrode line
  • the second signal line 220 may be For the data line.
  • the type of the signal line 200 is not limited as long as the setting of the signal line 200 causes a step difference in the surface of the display substrate.
  • first signal line 210 as a common electrode line
  • second signal line 220 as a data line
  • the display substrate may be an array substrate or other substrate.
  • the display substrate may also be a touch substrate formed with a touch electrode, a lead, or the like.
  • the type of display substrate is not limited.
  • the technical solution in the following embodiments of the present disclosure will be described by taking a display substrate as an array substrate as an example.
  • the display substrate is an array substrate, and a plurality of thin film transistors may be disposed in the array substrate.
  • the display substrate may further include an active layer disposed on a side of the second insulating layer 320 away from the substrate 100.
  • the first signal line 210 may be a common electrode line, and the common electrode line 210 may be in the same layer and the same material as the gate electrode in the thin film transistor (for example, the two may pass through the same conductive material film).
  • the first insulating layer 310 and/or the second insulating layer 320 may also be disposed in the same layer and the same material as the gate insulating layer in the thin film transistor.
  • the second signal line 220 may be a data line
  • the data line 220 may be disposed in the same layer and the same material as the source or drain electrode in the thin film transistor.
  • An interlayer dielectric layer 400 may be disposed between the first electrode 500 and the data line 220.
  • an insulating layer matching the signal line 200 may be disposed in the layer in which the signal line 200 is disposed in the display substrate.
  • the relationship between the insulating layer and the signal line 200 may be as shown in FIG. 2 .
  • the related description of the relationship between the first signal line 210 and the first insulating layer 310 is not described herein.
  • FIG. 3 is a schematic structural diagram of another display substrate according to an embodiment of the present disclosure.
  • a first interlayer dielectric layer 410 may be disposed on the layer where the second signal line 220 is located.
  • the first interlayer dielectric layer 410 is matched with the second signal line 220, that is, the surface of the first interlayer dielectric layer 410 away from the substrate 100 and the second signal line 220.
  • the surfaces away from the substrate 100 are substantially in the same continuous plane.
  • the surface flatness of the display substrate shown in Fig. 3a is further improved as compared with the display substrate of the embodiment shown in Fig. 2.
  • the insulating layer that matches the signal line is not limited to the layer where the signal line is located, and the structure that can cause the surface of the display substrate to be uneven may be matched.
  • the insulating layer further improves the surface flatness of the display substrate.
  • FIG. 3b is another schematic structural diagram of a display substrate according to an embodiment of the present disclosure.
  • the first layer in the layer where the first electrode 500 is located, the first layer may also be disposed.
  • the electrode 500 is matched to the third insulating layer 510 such that the surface of the first electrode 500 remote from the substrate 100 is substantially in the same continuous plane as the surface of the third insulating layer 510 remote from the substrate 100.
  • the surface flatness of the display substrate shown in Fig. 3b is further improved as compared with the display substrate shown in Fig. 3a.
  • FIG. 4 is a graph of light transmittance simulated by the display substrate provided by the embodiment of the present disclosure.
  • the display substrate in the above embodiment is separately simulated by the Techwiz 3D simulation software, with the center of the second signal line 220 as the origin, the plane where the substrate 100 is located is the horizontal plane, and the abscissa represents The distance from the origin in the horizontal direction, the ordinate represents the light transmittance; and, in the embodiment of the present disclosure, only the display substrate portion in the positive axis direction of the abscissa is a serious light leakage region, and the negative axis direction of the abscissa is not Consider (it is considered that there is no step difference in the surface of the substrate).
  • the horizontal axis coordinate 10um is the edge position of the second signal line 220
  • D1 represents the simulation result of the current display substrate shown in FIG.
  • the light transmittance falling speed in D2 is significantly higher than the light transmittance falling speed in D1.
  • FIG. 5 is a simulation diagram of light transmittance of a display substrate according to an embodiment of the present disclosure.
  • E1 represents the light leakage area in D1
  • E2 represents the light leakage area in D2.
  • the rate of decrease of the light transmittance of D2 is significantly greater than the rate of decrease of the light transmittance of D1.
  • Table 1 shows the change of light transmittance in D1 and D2 at the position of 10.8978 on the abscissa with time. law.
  • the light transmittance in D1 decreased from 0.363574 to 0.31212, a decrease of 0.051454; the light transmittance in D2 decreased from 0.354803 to 0.165622, a decrease of 0.189181.
  • the decrease of the light transmittance in D2 is greater than the decrease of the light transmittance in D1, that is, the decrease of the light transmittance in D2 is faster.
  • FIG. 4, FIG. 5 and Table 1 According to the display substrate provided by the embodiment of the present disclosure, by improving the surface flatness of the display substrate, display defects such as afterimages can be improved, and the flatness of the surface of the display substrate is improved, and the residual is improved. The better the effect of showing bad images, etc.
  • At least one embodiment of the present disclosure provides a display panel, which may include the display substrate in any of the above embodiments.
  • the display panel may be a liquid crystal display panel, and may include an array substrate and a counter substrate opposite to each other to form a liquid crystal cell filled with a liquid crystal material.
  • the opposite substrate is, for example, a color filter substrate.
  • the pixel electrode of each pixel unit of the array substrate is used to apply an electric field to control the degree of rotation of the liquid crystal material to perform a display operation.
  • the display panel may be an organic light emitting diode (OLED) display panel, wherein the display panel includes an array substrate on which a stack of organic light emitting functional materials may be formed, each pixel
  • OLED organic light emitting diode
  • the display panel includes an array substrate on which a stack of organic light emitting functional materials may be formed, each pixel
  • the anode or cathode of the unit is used to drive the organic luminescent material to illuminate for display operations.
  • the display panel may be an electronic paper display panel, wherein an electronic ink layer is formed on the array substrate of the display panel, and the pixel electrode of each pixel unit is used as a driving driver.
  • the charged microparticles in the electronic ink move to perform the voltage of the display operation.
  • At least one embodiment of the present disclosure provides a display device, which may include the above A display panel in any of the embodiments.
  • the display device may be any product or component having a display function such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, or a navigator.
  • At least one embodiment of the present disclosure provides a method of fabricating a display substrate, the method comprising: providing a substrate; forming at least one signal line on the substrate; forming a first insulating layer on the substrate; wherein A surface of the insulating layer remote from the substrate substrate and a surface of the signal line remote from the substrate substrate are parallel to the substrate and substantially lie in the same continuous plane.
  • FIG. 6a to 6i, 7a to 7d, and 8 to 13 are diagrams showing a process of preparing a display substrate according to an embodiment of the present disclosure.
  • the display substrate shown in FIG. 3a is prepared as an example, and the method for preparing the display substrate in at least one embodiment of the present disclosure may be Including the following process:
  • a base substrate 100 is provided, a conductive layer film is deposited on the base substrate 100 and patterned to form a first signal line 210.
  • the type of material of the first signal line 210 is not limited.
  • the material of the first signal line 210 may include a copper-based metal such as copper (Cu), copper-molybdenum alloy (Cu/Mo), copper-titanium alloy (Cu/Ti), copper-molybdenum-titanium alloy (Cu/Mo/Ti) Copper-molybdenum-tungsten alloy (Cu/Mo/W), copper-molybdenum-niobium alloy (Cu/Mo/Nb), etc.; the material of the first signal line 210 may also include a chromium-based metal, for example, a chromium-molybdenum alloy (Cr/ Mo), chrome-titanium alloy (Cr/Ti), chrome-molybdenum-titanium alloy (Cr/Mo/Ti), etc.; the material of the first signal line 210 may further include aluminum or aluminum alloy.
  • a copper-based metal such as copper (Cu), copper-molybden
  • the patterning process may be, for example, a photolithographic patterning process, which may include, for example, coating a photoresist layer on a structural layer that needs to be patterned, and using a mask to polish the photoresist layer. Exposure, developing the exposed photoresist layer to obtain a photoresist pattern, etching the structural layer using the photoresist pattern as a mask, and then optionally removing the photoresist pattern.
  • a photolithographic patterning process may include, for example, coating a photoresist layer on a structural layer that needs to be patterned, and using a mask to polish the photoresist layer. Exposure, developing the exposed photoresist layer to obtain a photoresist pattern, etching the structural layer using the photoresist pattern as a mask, and then optionally removing the photoresist pattern.
  • FIGS. 6b-6f are specific process diagrams for preparing the first signal line 210 on the base substrate 100 shown in FIG. 6a. As shown in FIGS. 6b-6f, in one example of an embodiment of the present disclosure, forming the first signal line 210 on the base substrate 100 may include the following process:
  • a base substrate 100 is provided, deposited on the base substrate 100 (first signal)
  • the conductive layer film 201 is coated and the first photoresist layer 202 is coated on the conductive layer film 201.
  • a first mask 203 is provided, and the first photoresist layer 202 is exposed through the first mask 203.
  • the exposed first photoresist layer 202 is developed to obtain a first photoresist pattern 204.
  • the conductive layer film 201 is etched using the first photoresist pattern 204 to form at least one first signal line 210.
  • the first photoresist pattern on the first signal line 210 is removed.
  • the material of the first photoresist layer 202 is a negative photoresist, and the transparent portion A of the first mask plate 203. Corresponding to the location where the first signal line 210 is located. However, in the embodiment of the present disclosure, the material of the first photoresist layer 202 may also be a positive photoresist, and the light shielding portion of the mask for exposure corresponds to the position where the first signal line 210 is located. After the positive photoresist is exposed, the exposed portion becomes soluble, is removed after development, and the unexposed portion is used to form a photoresist pattern; in contrast, the negative photoresist is exposed. Thereafter, the unexposed portion becomes soluble, is removed after development, and the exposed portion is used to form a photoresist pattern.
  • FIG. 6g-6i are process diagrams for preparing a first signal line 210 on a substrate substrate 100 according to another example of an embodiment of the present disclosure.
  • the first photoresist layer is passed through the second mask 205.
  • the exposure is performed at 202, and the light shielding portion C of the second mask 205 corresponds to the position where the first signal line 210 is located.
  • the process of preparing the first signal line 210 on the substrate substrate 100 after the first photoresist layer 202 is exposed may refer to the related description in the embodiment shown in FIG. 6d to FIG. 6f, and details are not described herein.
  • the first photoresist layer 202 is a positive photoresist.
  • the technical solution in the following embodiments of the present disclosure will be described by taking the material of the first photoresist layer 202 as a negative photoresist as an example.
  • a first insulating layer film having substantially the same thickness as the first signal line 210 is deposited on the base substrate 100, and the first insulating layer film is patterned to form the first insulating layer 310. .
  • FIGS. 6b-6f are specific process diagrams for preparing the first signal line 210 on the base substrate 100 shown in FIG. 6a. As shown in FIGS. 6b-6f, in one example of an embodiment of the present disclosure, on a substrate Forming the at least one first signal line 210 on the substrate 100 may include the following process:
  • a first insulating layer film 301 having substantially the same thickness as that of the first signal line 210 is deposited on the base substrate 100 on which the first signal line 210 is formed, and then coated on the first insulating layer film 301.
  • the second photoresist layer 302 is coated, wherein the first insulating film 301 is substantially the same thickness as the first signal line 210 in a direction perpendicular to the substrate 100.
  • substantially the same for example, the difference between the two is within ⁇ 10%, preferably the difference between the two is within ⁇ 5%.
  • the second photoresist layer 302 is exposed through the first mask 203.
  • the second photoresist layer 302 may be, for example, a positive photoresist, and the exposed second photoresist layer 302 is developed to obtain a second photoresist pattern, and the first photoresist pattern is used to insulate the first photoresist.
  • the layer film 301 is patterned to form the first insulating layer 310 as shown in FIG. 7a. It should be noted that, in the process of processing the display substrate of FIG. 7c to obtain the display substrate as shown in FIG. 7a, reference may be made to the related description of forming the first signal line 210 as shown in FIG. 6c to FIG. 6f in the above embodiment. I will not repeat them here.
  • the properties of the first photoresist layer 202 and the second photoresist layer 302 are opposite.
  • the second photoresist layer 302 is a negative photoresist; in the case where the first photoresist layer 202 is a negative photoresist Next, the second photoresist layer 302 is a positive photoresist.
  • the portion where the first signal line 210 and the first insulating layer 310 are in contact may not be in a flat state in a strict sense, and a slight depression or convexity may occur.
  • the surface flatness of the display substrate in the embodiment of the present disclosure is still significantly improved, and the above-mentioned causes of the unevenness of the contact portion of the first signal line 210 and the first insulating layer 310 (for example, The step difference is very small, so the unevenness at that place can be ignored.
  • the technical solution in the embodiment of the present disclosure will be described by taking a portion in which the first signal line 210 and the first insulating layer 310 are in contact as a continuous plane.
  • the manner in which the first insulating layer 310 is formed on the base substrate 100 is not limited to the above method.
  • the first insulating layer 310 matching the first signal line 310 may be formed on the base substrate 100 without using the first mask 203.
  • FIG. 7b and FIG. 7d are the first to be prepared on the substrate substrate 100 according to an embodiment of the present disclosure.
  • a first insulating layer film 301 having substantially the same thickness as that of the first signal line 210 is deposited on the base substrate 100 on which the first signal line 210 is formed, and then coated on the first insulating layer film 301.
  • the third photoresist layer 303 is coated, wherein the first insulating layer film 301 and the first signal line 210 have substantially the same thickness in a direction perpendicular to the substrate 100.
  • the third photoresist layer 303 is made of the first signal line 310 as a mask. After exposure, the exposed third photoresist layer 303 is developed to obtain a third photoresist pattern, and the first insulating layer film 301 is patterned using the third photoresist pattern to form the first insulating layer 310.
  • the first signal line 210 may be an opaque or translucent conductive material.
  • the display substrate shown in FIG. 7d is processed to obtain a display substrate as shown in FIG. 7a, and reference may be made to the above embodiment as shown in FIGS. 6d to 6f. The related description of the formation of the first signal line 210 will not be repeated here.
  • the third photoresist layer 303 is a negative photoresist layer.
  • a second insulating layer 320 is formed on the base substrate 100 on which the first signal line 210 and the first insulating layer 310 are formed, and the second insulating layer 320 covers the first signal line 210 and the first insulating layer 310.
  • the second insulating layer 320 For the description of the second insulating layer 320, reference may be made to the related content in the first embodiment, and details are not described herein.
  • the material of the first insulating layer 310 and/or the second insulating layer 320 may be the same as the material of the gate insulating layer, and may include silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride. (SiNxOy), alumina (Al 2 O 3 ), aluminum nitride (AlN) or other suitable materials.
  • the first insulating layer 310 and/or the second insulating layer 320 may be deposited by chemical vapor deposition (CVD) or the like.
  • a conductive layer film is deposited on the second insulating layer 320 and patterned to form a second signal line 220.
  • the second signal line 220 reference may be made to the related content in the first embodiment, and details are not described herein.
  • the second signal line 220 can be a data line.
  • the preparation material of the second signal line 220 may include a metal material such as molybdenum, titanium, copper, and chromium or
  • the alloy material formed by the metal for example, the copper-based alloy material includes copper-molybdenum alloy (CuMo), copper-titanium alloy (CuTi), copper-molybdenum-titanium alloy (CuMoTi), copper-molybdenum-tungsten alloy (CuMoW), copper-molybdenum-niobium alloy (CuMoNb)
  • the chromium-based alloy materials include chromium molybdenum alloy (CrMo), chromium titanium alloy (CrTi), chromium molybdenum titanium alloy (CrMoTi), and the like.
  • an interlayer dielectric layer film having substantially the same thickness as the second signal line 220 is deposited on the base substrate 100, and the interlayer dielectric layer film is patterned to form the first interlayer dielectric layer 410.
  • the first interlayer dielectric layer 410 is deposited on the base substrate 100, and the interlayer dielectric layer film is patterned to form the first interlayer dielectric layer 410.
  • a second interlayer dielectric layer 420 is formed on the second signal line 220 and the first interlayer dielectric layer 410.
  • the material of the interlayer dielectric layer 400 may include an inorganic insulating material such as silicon nitride or silicon oxide in the embodiment of the present disclosure. It is an organic insulating material.
  • a thin film of a conductive layer is deposited on the interlayer dielectric layer 400 and patterned to form a first electrode 500.
  • the first electrode 500 may be a pixel electrode.
  • the material of the first electrode 500 may include indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium oxide (IGO), gallium zinc oxide (GZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ). , aluminum zinc oxide (AZO) and carbon nanotubes.
  • the first electrode 500 may be an anode or a cathode of an organic light emitting diode.
  • the preparation material may be a transparent conductive material or a metal material.
  • the material forming the first electrode 500 includes indium tin oxide (ITO), indium zinc oxide (IZO), and indium gallium oxide (IGO).
  • the preparation material may be silver, A metal such as aluminum, calcium, indium, lithium or magnesium or an alloy thereof (for example, a magnesium-silver alloy).
  • the first electrode 500 may be a pixel electrode
  • an alignment film 600 is formed on the surface of the display substrate.
  • the alignment film 600 reference may be made to the relevant one in the first embodiment. Rong, do not repeat here.
  • Embodiments of the present disclosure provide a display substrate, a method of fabricating the same, a display panel, and a display device, and may have at least one of the following beneficial effects:
  • At least one embodiment of the present disclosure provides a display substrate in which a layer of a signal line in a display substrate is provided with a first insulating layer disposed in parallel with the signal line, which can improve the flatness of the surface of the display substrate and avoid subsequent
  • the structure provided on the display substrate has problems such as poor display due to excessive step difference.
  • the surface flatness of the display substrate is increased, and the limitation of the thickness of the signal line at the time of design can be reduced or released.
  • the planarization of the layers in the display substrate can also reduce the number of slopes generated in the formation process of each layer structure, and reduce the parasitic capacitance in the thin film transistor.

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Abstract

一种显示基板及其制备方法、显示面板和显示装置。该显示基板包括：衬底基板(100)、设置于衬底基板(100)上的至少一条第一信号线(201)以及第一绝缘层(310)，其中，第一绝缘层(310)的远离衬底基板(100)的表面与第一信号线(201)的远离衬底基板(100)的表面与衬底基板(100)平行且基本上位于同一个连续的平面内。与第一信号线(201)并列设置的第一绝缘层(310)可以提高显示基板的表面的平坦度，避免后续设置于显示基板上的结构因段差过大导致的显示不良等问题。

Description

显示基板及其制备方法、显示面板和显示装置
本申请要求于2017年5月10日递交的中国专利申请第201710327060.8号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开至少一个实施例涉及一种显示基板及其制备方法、显示面板和显示装置。
背景技术
随着生活水平的提高，当前用户对显示产品的要求也越来越高，尤其是在显示画面的质量提升方面。但是，因受传统工艺的限制，显示基板的表面平坦度不高，显示基板表面上的某些区域存在的段差(step)会引起例如残影等显示不良。因此，如何有效改善显示基板表面的平坦度成为当前各厂家面临的难题。
发明内容
本公开至少一个实施例提供一种显示基板，包括：衬底基板、设置于所述衬底基板上的至少一条第一信号线以及与所述第一信号线并列设置的第一绝缘层，其中，所述第一绝缘层的远离所述衬底基板的表面和所述第一信号线的远离所述衬底基板的表面与所述衬底基板平行且基本上位于同一个连续的平面内。
例如，本公开至少一个实施例提供的显示基板还可以包括：设置于所述衬底基板上的第二绝缘层；其中，所述第二绝缘层覆盖所述第一信号线和所述第一绝缘层。
例如，本公开至少一个实施例提供的显示基板还可以包括：设置于所述第二绝缘层的远离所述衬底基板一侧的第一电极或半导体层。
例如，在本公开至少一个实施例提供的显示基板中，所述第一信号线包括栅线、数据线和公共电极线中的至少一种或组合。
例如，在本公开至少一个实施例提供的显示基板中，所述第一信号线为公共电极线，所述第一绝缘层为栅绝缘层。
例如，在本公开至少一个实施例提供的显示基板中，所述显示基板为阵列基板。
本公开至少一个实施例提供一种显示面板，包括上述任一的显示基板。
本公开至少一个实施例提供一种显示装置，包括上述任一的显示面板。
本公开至少一个实施例提供一种显示基板的制备方法，包括：提供衬底基板；在所述衬底基板上形成至少一条第一信号线；在所述衬底基板上形成与所述第一信号线并列的第一绝缘层；其中，所述第一绝缘层的远离所述衬底基板的表面和所述第一信号线的远离所述衬底基板的表面与所述衬底基板平行且基本上位于同一个连续的平面内。
例如，在本公开至少一个实施例提供的制备方法中，在所述衬底基板上形成至少一条第一信号线可以包括：提供第一掩膜板；在所述衬底基板上沉积导电层薄膜以及在所述导电层薄膜上涂覆第一光刻胶层；通过所述第一掩膜板对所述第一光刻胶层进行曝光，将曝光后的所述第一光刻胶层显影以得到第一光刻胶图案，使用所述第一光刻胶图案对所述导电层薄膜进行图案化处理以形成至少一条所述第一信号线。
例如，在本公开至少一个实施例提供的制备方法中，在所述衬底基板上形成与所述第一信号线并列设置的第一绝缘层可以包括：在垂直于所述衬底基板的方向上，在形成有至少一条所述第一信号线的所述衬底基板上沉积与所述第一信号线的厚度基本上相同的第一绝缘层薄膜；在所述第一绝缘层薄膜上涂覆第二光刻胶层；在所述第二光刻胶层的远离所述衬底基板的一侧，通过所述第一掩膜板对所述第二光刻胶层进行曝光，将曝光后的所述第二光刻胶层显影以得到第二光刻胶图案，使用所述第二光刻胶图案对所述第一绝缘层薄膜进行图案化处理以形成所述第一绝缘层。
例如，在本公开至少一个实施例提供的制备方法中，所述第一光刻胶层为正性光刻胶层，所述第二光刻胶层为负性光刻胶层；或所述第一光刻胶层为负性光刻胶层，所述第二光刻胶层为正性光刻胶层。
例如，在本公开至少一个实施例提供的制备方法中，在所述衬底基板 上形成与所述第一信号线并列设置的第一绝缘层可以包括：在垂直于所述衬底基板的方向上，在形成有至少一条所述第一信号线的所述衬底基板上沉积与所述第一信号线的厚度基本上相同的第一绝缘层薄膜；在所述第一栅绝缘层薄膜上涂覆第三光刻胶层；在所述衬底基板的远离所述第一信号线的一侧，以所述第一信号线为掩膜板对所述第三光刻胶层进行曝光，将曝光后的所述第三光刻胶层显影以得到第三光刻胶图案，使用所述第三光刻胶图案对所述第一绝缘层薄膜进行图案化处理以形成所述第一绝缘层。
例如，在本公开至少一个实施例提供的制备方法中，所述第三光刻胶层为负性光刻胶层。
例如，本公开至少一个实施例提供的制备方法还可以包括：在形成有所述第一信号线和所述第一绝缘层的衬底基板上形成第二绝缘层；其中，所述第二绝缘层覆盖所述第一信号线和所述第一绝缘层。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例，而非对本发明的限制。
图1为一种显示基板的结构示意图；
图2为本公开实施例提供的显示基板的一种结构示意图；
图3a为本公开实施例提供的显示基板的另一种结构示意图；
图3b为本公开实施例提供的显示基板的另一种结构示意图；
图4为对本公开实施例提供的显示基板进行模拟的光透过率的曲线图；
图5为本公开实施例提供的显示基板的光透过率的模拟图；以及
图6a～图6i、图7a～图7d、图8～图13为本公开实施例提供的一种显示基板的制备过程图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。 基于所描述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
显示基板中设置的信号线可能使得像素区域中的显示区域的边缘处存在段差，该段差会导致设置于显示基板上的各层结构的不平，造成残影等显示不良。为避免段差过大，通常会限制信号线的设计厚度，但是会造成信号线的功能性不良例如电阻率大、强度较小容易断裂等；或者使用平坦化层来将显示基板表面平坦化，但是这可能增加显示显示基板的厚度，不利于轻薄化。
图1为一种显示基板的结构示意图。如图1所示，衬底基板100上依次设置有第一信号线210、绝缘层300、第二信号线220、层间介质层400以及第一电极500，第一电极500对应于像素区域的显示区域B。因第一信号线210的设置，在显示区域的边缘附近会存在段差区域B3。例如，该显示基板为阵列基板，第一信号线210为栅线，绝缘层300为栅绝缘层，第二信号线220为数据线。
以图1所示的显示基板用于液晶显示面板为例，需要通过配向工艺在显示基板的表面上设置配向层600以对液晶分子进行预取向，但是在段差区域B3处，配向层600的强度和方向与平坦区域(图中未示出，包括区域B1和区域B2)处会有不同，使得液晶分子的初始配向紊乱，导致段差区域B3处的液晶分子和平坦区域处的液晶分子在工作状态下不同步；并且，平坦区域中的区域B1和区域B2之间也存在段差，段差使得区域B1上的液晶分子和区域B2上的液晶分子的厚度不同，因而区域B1上的液晶分子和区域B2上的液晶分子的偏转程度也存在差异。显示面板在位于工 作状态下时，段差区域B3、区域B1和区域B2上的液晶分子的偏转程度存在差异，例如不能在较短的时间内同步达到暗态，导致出现残影、对比度下降等显示不良。
需要说明的是，显示基板表面存在段差导致的显示不良不限于上述所述情况。例如，该显示基板可以为阵列基板，在实际生产过程中，在制备阵列基板中的薄膜晶体管时还制备信号线，因薄膜晶体管的制备工艺复杂，在形成薄膜晶体管中的各层结构的过程中，因为段差过大，可能会增加薄膜晶体管中的各层结构在形成过程中产生的坡角数量，导致例如寄生电容的增加。例如，在将阵列基板和对置基板对盒以得到显示面板的过程中，因段差的存在，液晶分子的扩散受到不利影响，使得液晶层中容易产生气泡等不良，由此需要进行长时间的真空对合和热处理，造成产能降低。
本公开至少一个实施例提供一种显示基板及其制备方法、显示面板和显示装置，可以消除或减小显示基板上的段差。
本公开至少一个实施例提供一种显示基板，该显示基板包括：衬底基板、设置于衬底基板上的至少一条第一信号线以及第一绝缘层，其中，第一绝缘层的远离衬底基板的表面和第一信号线的远离衬底基板的表面都与衬底基板平行且基本上位于同一个连续的平面内。与第一信号线并列设置的第一绝缘层可以提高显示基板的表面的平坦度，避免后续设置于显示基板上的结构因段差过大导致的显示不良等问题。例如，在本公开的实施例中，以相匹配来表述第一信号线和第一绝缘层之间的关系，并且显示基板中设置有上述第一信号线和第一绝缘层的层为平坦化设置。
需要说明的是，在本公开的实施例中，显示基板上可以设置有多种信号线，该信号线可以为一种信号线也可以为多种信号线。例如，当信号线为多种信号线的情况下，这些信号线可以位于显示基板的同一层上也可以位于显示基板的不同层。当信号线包括位于不同层的多种信号线时，只要其中一层(例如第一信号线所在的层)中设置有第一绝缘层，并且该第一绝缘层的远离衬底基板的表面与该层中的第一信号线的远离衬底基板的表面基本上位于同一个连续的平面内，即可提高显示基板的表面的平坦度。
下面，以信号线中的至少第一信号线所在的层上设置有与其相匹配的第一绝缘层为例，结合附图说明对根据本公开至少一个实施例中的显示基板及其制备方法、显示面板和显示装置进行说明。
本公开至少一个实施例提供一种显示基板，图2为本公开实施例提供的显示基板的一种结构示意图。例如，如图2所示，在本公开一个实施例中，该显示基板可以包括：衬底基板100、设置于衬底基板100上的第一信号线210以及第一绝缘层310。第一绝缘层310的远离衬底基板100的表面与第一信号线210的远离衬底基板100的表面基本上位于同一个连续的平面内。例如，第一绝缘层310的远离衬底基板100的表面和第一信号线210的远离衬底基板100的表面都可以与衬底基板100平行。例如，在垂直于衬底基板100的方向上，第一绝缘层310的厚度与第一信号线210的厚度相近或相等。如此，与图1中所示的显示基板相比，显示基板的设置有第一信号线210的结构层的表面平坦度提高。第一绝缘层210的具体形成方式可以参考下述实施例(关于显示基板的制备方法的实施例)的相关说明，本公开在此不做赘述。
例如，在本公开至少一个实施例中，如图2所示，该显示基板还可以包括设置在衬底基板100上的第二绝缘层320，第二绝缘层320可以覆盖第一信号线210和第一绝缘层310。如此，与图1中所示的显示基板相比，显示基板的设置有绝缘层300(例如可以包括第一绝缘层310和第二绝缘层320)的结构层(例如第一电极500、配向层600等)的表面平坦度提高。
例如，在本公开至少一个实施例中，如图2所示，该显示基板还可以包括设置于第二绝缘层320的远离衬底基板100一侧的第一电极500。例如，第一电极500可以为像素电极和/或公共电极。第二绝缘层320的远离衬底基板100一侧的表面的平坦度提高，与图1中所示的显示基板相比，第一电极500所对应的显示区域B处的平坦度也得以提高。
例如，在本公开至少一个实施例中，如图2所示，该显示基板还可以包括设置于第二绝缘层320上的配向层600。第二绝缘层320的远离衬底基板100一侧的表面的平坦度提高，与图1中所示的显示基板相比，显示区域B处的配向层600的平坦度也得以提高，即显示区域B处配向层600的强度和方向分布均匀，在工作状态下，显示区域B处的液晶分子可以达到同步偏转的状态。例如，该配向层600可以为聚酰亚胺层，并且经过摩擦处理。
需要说明的是在，该显示基板不限于改善液晶显示领域中的显示不良问题。例如，该显示基板可以为有机发光二极管显示基板，有机发光器件 中的有机发光层的平坦度等参数直接影响有机发光器件的性能。该显示基板可以平坦化显示基板中的各层结构，减小段差，相应地，也可以改善发光层等的平坦度，提升有机发光器件的性能。
例如，在本公开至少一个实施例中，信号线200可以为栅线、数据线和公共电极线等中的至少一种或组合。例如，如图2所示，在本公开的一个实施例中，信号线200包括第一信号线210和第二信号线220，第一信号线210可以为公共电极线，第二信号线220可以为数据线。在本公开的实施例中，对信号线200的种类不做限制，只要信号线200的设置会导致显示基板的表面出现段差即可。
下面，以第一信号线210为公共电极线，第二信号线220为数据线为例，对本公开下述实施例中的技术方案进行说明。
例如，在本公开至少一个实施例中，显示基板可以为阵列基板或其它基板，例如显示基板也可以为形成有触控电极、引线等的触控基板等，在本公开的实施例中，对显示基板的类型不做限制。下面，以显示基板为阵列基板为例对本公开下述实施例中的技术方案进行说明。
例如，在本公开至少一个实施例中，如图2所示，该显示基板为阵列基板，阵列基板中可以设置有多个薄膜晶体管。例如，在本公开实施例中，显示基板还可以包括设置于第二绝缘层320的远离衬底基板100一侧的有源层。例如，在本公开实施例中，该第一信号线210可以为公共电极线，公共电极线210可以与薄膜晶体管中的栅电极同层且同材料设置(例如二者可以由同一导电材料薄膜经过构图工艺形成)，则第一绝缘层310和/或第二绝缘层320也可以与薄膜晶体管中的栅绝缘层同层且同材料设置。例如，在本公开实施例中，第二信号线220可以为数据线，数据线220可以与薄膜晶体管中的源电极或漏电极同层且同材料设置。第一电极500与数据线220之间可以设置层间介质层400。
为进一步提高显示基板表面的平坦度，可以在显示基板中设置有信号线200的层中都设置有与信号线200相匹配的绝缘层，该绝缘层与信号线200的关系可以参考如图2所示的第一信号线210和第一绝缘层310之间关系的相关说明，在此不做赘述。
图3a为本公开实施例提供的显示基板的另一种结构示意图。例如图3a所示，在本公开实施例的一个示例中，在第二信号线220所在的层上， 可以设置有第一层间介质层410，第一层间介质层410与第二信号线220相匹配，即第一层间介质层410的远离衬底基板100的表面与第二信号线220的远离衬底基板100的表面基本上位于同一个连续的平面内。与图2所示的实施例的显示基板相比，图3a中所示的显示基板的表面平坦度进一步提高。
需要说明的是，在本公开提供的实施例中，不限于只对信号线所在的层设置与信号线相匹配的绝缘层，对于其它可以引起显示基板表面不平的结构，也可以设置与其相匹配的绝缘层，从而进一步提高显示基板的表面平坦度。图3b为本公开实施例提供的显示基板的另一种结构示意图，例如图3b所示，在本公开实施例的一个示例中，在第一电极500所在的层中，也可以设置与第一电极500匹配的第三绝缘层510，以使得第一电极500的远离衬底基板100的表面与第三绝缘层510的远离衬底基板100的表面基本上位于同一个连续的平面内。与图3a所示的显示基板相比，图3b中所示的显示基板的表面平坦度进一步提高。
本公开至少一个实施例通过软件模拟，以验证上述实施例中的显示基板可以改善残影等显示不良，图4为对本公开实施例提供的显示基板进行模拟的光透过率的曲线图。在本公开实施例中，通过Techwiz 3D模拟软件对上述实施例中的显示基板分别进行模拟，以第二信号线220的中心为原点，以衬底基板100所在的平面为水平面，横坐标代表在水平面方向上距离原点的距离，纵坐标代表光透过率；并且，在本公开实施例中，只考虑横坐标的正轴方向的显示基板部分为漏光严重区域，对于横坐标的负轴方向不作考虑(认为该部分显示基板的表面不存在段差)。横轴坐标10um处为第二信号线220的边缘位置，D1代表对图1所示当前的显示基板的模拟结果；D2代表图2所示本公开实施例提供过的显示基板的模拟结果。
如图4所示，在加载同样电压的条件下，在0毫秒(ms)～6毫秒(ms)的过程中，D2中的光透过率下降速度明显大于D1中的光透过率下降速度。
图5为本公开实施例提供的显示基板的光透过率的模拟图。其中E1代表D1中的漏光区域；E2代表D2中的漏光区域。在2ms至6ms的时间范围内，由图5可以看出，D2的光透过率的下降速度明显大于D1中的光透过率的下降速度。
表1为横坐标10.8978位置处的D1和D2中的光透过率随时间的变化 规律。
表1
时间 D1 D2
0ms 0.364642 0.365618
2ms 0.363574 0.354803
4ms 0.31212 0.165622
6ms 0.066362 0.022991
如表1所示，在2ms至4ms的过程中，D1中的光透过率由0.363574下降至0.31212，下降了0.051454；D2中的光透过率由0.354803下降至0.165622，下降了0.189181。在2ms至4ms的时间段内，D2中的光透过率的下降幅度都大于D1中的光透过率的下降幅度，即D2中的光透过率的下降速度更快。
由图4、图5和表1可以验证，本公开实施例提供的显示基板，通过提高显示基板的表面平坦度，可以改善残影等显示不良，并且显示基板表面的平坦度越高，改善残影等显示不良的效果越好。
本公开至少一个实施例提供一种显示面板，该显示面板可以包括上述任一实施例中的显示基板。
例如，在本公开实施例的一个示例中，该显示面板可以为液晶显示面板，可以包括阵列基板和对置基板，二者彼此对置以形成液晶盒，在液晶盒中填充有液晶材料。该对置基板例如为彩膜基板。阵列基板的每个像素单元的像素电极用于施加电场以对液晶材料的旋转的程度进行控制从而进行显示操作。
例如，在本公开实施例的另一个示例中，该显示面板可以为有机发光二极管(OLED)显示面板，其中，该显示面板包括的阵列基板上可以形成有机发光功能材料的叠层，每个像素单元的阳极或阴极用于驱动有机发光材料发光以进行显示操作。
例如，在本公开实施例的再一个示例中，该显示面板可以为电子纸显示面板，其中，该显示面板的阵列基板上形成有电子墨水层，每个像素单元的像素电极作为用于施加驱动电子墨水中的带电微颗粒移动以进行显示操作的电压。
本公开至少一个实施例提供一种显示装置，该显示装置可以包括上述 任一实施例中的显示面板。例如，在本公开实施例的一个示例中，该显示装置可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框或导航仪等任何具有显示功能的产品或部件。
本公开至少一个实施例提供一种显示基板的制备方法，该方法包括：提供衬底基板；在衬底基板上形成至少一条信号线；在衬底基板上形成第一绝缘层；其中，第一绝缘层的远离衬底基板的表面和信号线的远离衬底基板的表面与所述衬底基板平行且基本上位于同一个连续的平面内。
需要说明是，由本公开实施例的制备方法制备的显示基板的具体结构，可以参考前述实施例(关于显示基板的实施例)中的显示基板的相关说明，在此不做赘述。
图6a～图6i、图7a～图7d、图8～图13为本公开实施例提供的一种显示基板的制备过程图。下面，如图6a～图6i、图7a～图7d、图8～图13所示，以制备如图3a所示的显示基板为例，本公开至少一个实施例中的显示基板的制备方法可以包括如下过程：
如图6a所示，提供衬底基板100，在衬底基板100上沉积一层导电层薄膜并对其进行构图工艺处理以形成第一信号线210。
在本公开实施例中，对第一信号线210的材料的类型不做限制。例如，第一信号线210的材料可以包括铜基金属，例如，铜(Cu)、铜钼合金(Cu/Mo)、铜钛合金(Cu/Ti)、铜钼钛合金(Cu/Mo/Ti)、铜钼钨合金(Cu/Mo/W)、铜钼铌合金(Cu/Mo/Nb)等；该第一信号线210的材料也可以包括铬基金属，例如，铬钼合金(Cr/Mo)、铬钛合金(Cr/Ti)、铬钼钛合金(Cr/Mo/Ti)等；该第一信号线210的材料还可以包括铝或铝合金等。
在本公开的至少一个实施例中，构图工艺例如可以为光刻构图工艺，其例如可以包括：在需要被构图的结构层上涂覆光刻胶层，使用掩膜板对光刻胶层进行曝光，对曝光的光刻胶层进行显影以得到光刻胶图案，使用光刻胶图案作为掩模对结构层进行蚀刻，然后可选地去除光刻胶图案。
图6b～图6f为图6a所示的在衬底基板100上制备第一信号线210的具体过程图。如图6b～图6f所示，在本公开实施例的一个示例中，在衬底基板100上形成第一信号线210可以包括如下过程：
如图6b所示，提供衬底基板100，在衬底基板100上沉积(第一信号 线)导电层薄膜201以及在导电层薄膜201上涂覆第一光刻胶层202。
如图6c所示，提供第一掩膜板203，通过第一掩膜板203对第一光刻胶层202进行曝光。
如图6d所示，将曝光后的第一光刻胶层202显影以得到第一光刻胶图案204。
如图6e所示，使用第一光刻胶图案204对导电层薄膜201进行刻蚀以形成至少一条第一信号线210。
如图6f所示，去除第一信号线210上的第一光刻胶图案。
需要说明是，在图6b～图6f所示的第一信号线210的制备过程中，第一光刻胶层202的材料为负性光刻胶，第一掩膜板203的透光部分A对应第一信号线210所在的位置。但是，本公开实施例中，第一光刻胶层202的材料也可以为正性光刻胶，用于曝光的掩膜板的遮光部分对应第一信号线210所在的位置。正性光刻胶经过曝光后，被曝光的部分变得可溶，经显影后被去除，而未被曝光的部分则用于形成光刻胶图案；与此相反，负性光刻胶经过曝光后，未被曝光的部分变得可溶，经显影后被去除，而被曝光的部分则用于形成光刻胶图案。
图6g～图6i为本公开实施例的另一个示例提供的在衬底基板100上制备第一信号线210的过程图。如图6g～图6i所示，在衬底基板100上形成(第一信号线)导电层薄膜201以及第一光刻胶层202之后，通过第二掩膜板205对第一光刻胶层202进行曝光，第二掩膜板205的遮光部分C对应第一信号线210所在的位置。在对第一光刻胶层202曝光之后，在衬底基板100上制备第一信号线210的过程可以参考上述图6d～图6f所示的实施例中的相关说明，在此不做赘述。例如，在本示例中，第一光刻胶层202为正性光刻胶。
下面，以第一光刻胶层202的材料为负性光刻胶为例，对本公开下述实施例中的技术方案进行说明。
如图7a所示，在衬底基板100上沉积一层与第一信号线210的厚度基本上相同的第一绝缘层薄膜，对该第一绝缘层薄膜进行构图工艺以形成第一绝缘层310。
图7b～图7c为图6a所示的在衬底基板100上制备第一信号线210的具体过程图。如图6b～图6f所示，在本公开实施例的一个示例中，在衬底 基板100上形成至少一个第一信号线210可以包括如下过程：
如图7b所示，在形成有第一信号线210的衬底基板100上沉积与第一信号线210的厚度基本上相同的第一绝缘层薄膜301，然后在第一绝缘层薄膜301上涂覆第二光刻胶层302，其中，在垂直于衬底基板100的方向上，第一绝缘层薄膜301与第一信号线210的厚度基本相同。这里，“基本相同”例如二者差值在±10％内，优选地二者差值在±5％内。
如图7c所示，在第二光刻胶层302的远离衬底基板100的一侧(例如图7c中的S1处)，通过第一掩膜板203对第二光刻胶层302进行曝光，这里第二光刻胶层302例如可以为正性光刻胶，将曝光后的第二光刻胶层302显影以得到第二光刻胶图案，使用第二光刻胶图案对第一绝缘层薄膜301进行图案化处理以形成如图7a所示的第一绝缘层310。需要说明的是，对图7c的显示基板进行处理以获得如图7a所示的显示基板的过程，可以参考上述实施例中如图6c～图6f所示的形成第一信号线210的相关说明，在此不做赘述。
例如，在本公开实施例中，在通过第一掩膜板203形成第一绝缘层310的情况下，第一光刻胶层202和第二光刻胶层302的性质相反。例如，在第一光刻胶层202为正性光刻胶的情况下，第二光刻胶层302为负性光刻胶；在第一光刻胶层202为负性光刻胶的情况下，第二光刻胶层302为正性光刻胶。
需要说明的是，在实际工艺中，因受设备精度等的限制，第一信号线210和第一绝缘层310接触的部分可能不会处于严格意义上的平坦状态，会出现微小的凹陷或者凸起。但是，与当前的显示基板结构相比，本公开实施例中的显示基板的表面平坦度仍有明显改善，且上述原因造成的第一信号线210和第一绝缘层310接触部分的不平(例如段差)非常小，所以该处的不平可以忽略。下面，在本公开所有实施例中，以第一信号线210和第一绝缘层310接触的部分为连续的平面为例，对本公开实施例中的技术方案进行说明。
在衬底基板100上形成第一绝缘层310的方式不限于上述所述方法。例如，在本公开实施例的另一个示例中，不需要使用第一掩膜板203即可在衬底基板100上形成与第一信号线310匹配的第一绝缘层310。
图7b和图7d为本公开实施例提供的一种在衬底基板100上制备第一 绝缘层310的过程图。如图7b和图7d所示，本公开实施例的另一个示例所示的在衬底基板100上制备第一绝缘层310可以包括如下过程：
如图7b所示，在形成有第一信号线210的衬底基板100上沉积与第一信号线210的厚度基本上相同的第一绝缘层薄膜301，然后在第一绝缘层薄膜301上涂覆第三光刻胶层303，其中，在垂直于衬底基板100的方向上，第一绝缘层薄膜301与第一信号线210的厚度基本相同。
如图7d所示，从衬底基板100的远离第一信号线210的一侧(例如图7d中的S2位置)，以第一信号线310为掩膜板对第三光刻胶层303进行曝光，将曝光后的第三光刻胶层303显影以得到第三光刻胶图案，使用第三光刻胶图案对第一绝缘层薄膜301进行图案化处理以形成第一绝缘层310。
需要说明的是，在本示例中，第一信号线210可以为不透明或半透明的导电材料。在对第三光刻胶层303进行曝光之后，对图7d所示的显示基板进行处理以获得如图7a所示的显示基板的过程，可以参考上述实施例中如图6d～图6f所示的形成第一信号线210的相关说明，在此不做赘述。
例如，在本公开实施例中，在以第一信号线310为掩膜板形成第一绝缘层310的情况下，第三光刻胶层303为负性光刻胶层。
如图8所示，在形成有第一信号线210和第一绝缘层310的衬底基板100上形成第二绝缘层320，第二绝缘层320覆盖第一信号线210和第一绝缘层310。关于第二绝缘层320的说明可以参考实施例一中的相关内容，在此不做赘述。
例如，在本示例中，第一绝缘层310和/或第二绝缘层320的材料可以与栅绝缘层的材料相同，可以包括氮化硅(SiNx)、氧化硅(SiOx)、氧氮化硅(SiNxOy)、氧化铝(Al2O3)、氮化铝(AlN)或其他适合的材料等。例如，可以采用化学气相沉积(CVD)等方式沉积上述第一绝缘层310和/或第二绝缘层320。
如图9所示，在第二绝缘层320上沉积一层导电层薄膜并对其进行构图工艺以形成第二信号线220。关于第二信号线220的说明可以参考实施例一中的相关内容，在此不做赘述。
例如，在本公开至少一个实施例中，第二信号线220可以为数据线。第二信号线220的制备材料可以包括钼、钛、铜和铬等金属材料或者由上 述金属形成的合金材料，例如，铜基合金材料包括铜钼合金(CuMo)、铜钛合金(CuTi)、铜钼钛合金(CuMoTi)、铜钼钨合金(CuMoW)、铜钼铌合金(CuMoNb)等，铬基合金材料包括铬钼合金(CrMo)、铬钛合金(CrTi)、铬钼钛合金(CrMoTi)等。
如图10所示，在衬底基板100上沉积与第二信号线220的厚度基本上相同的层间介质层薄膜，对该层间介质层薄膜进行构图工艺以形成第一层间介质层410。在衬底基板100上形成第一层间介质层410的方法可以参考如图6b～图6f所示的制备第一绝缘层310的相关说明，本公开在此不做赘述。
如图11所示，在第二信号线220和第一层间介质层410上形成第二层间介质层420。
在本公开实施例中，关于第一层间介质层410和第二层间介质层420的说明可以参考实施例一中的相关内容，在此不做赘述。例如，在本公开实施例中层间介质层400(例如可以包括第一层间介质层410和第二层间介质层420)的材料可以包括氮化硅、氧化硅等无机绝缘材料，也可以为有机绝缘材料。
如图12所示，在层间介质层400上沉积导电层薄膜并对其进行构图工艺以形成第一电极500。
例如，在本公开实施例的一个示例中，第一电极500可以为像素电极。第一电极500的材料可以包括氧化铟锡(ITO)、氧化铟锌(IZO)、氧化铟镓(IGO)、氧化镓锌(GZO)、氧化锌(ZnO)、氧化铟(In2O3)、氧化铝锌(AZO)和碳纳米管等。
例如，在本公开实施例的另一个示例中，第一电极500可以为有机发光二极管的阳极或阴极。第一电极500作为阳极时，其制备材料可以为透明导电材料或金属材料，例如，形成该第一电极500的材料包括氧化铟锡(ITO)、氧化铟锌(IZO)、氧化铟镓(IGO)、氧化镓锌(GZO)氧化锌(ZnO)、氧化铟(In2O3)、氧化铝锌(AZO)和碳纳米管等；第一电极500作为阴极时，其制备材料可以为银、铝、钙、铟、锂或镁等金属或它们的合金来(例如镁银合金)。
如图13所示，第一电极500可以为像素电极时，在显示基板的表面上形成配向膜600。关于配向膜600的说明可以参考实施例一中的相关内 容，在此不做赘述。
本公开的实施例提供一种显示基板及其制备方法、显示面板和显示装置，并且可以具有以下至少一项有益效果：
(1)本公开至少一个实施例提供一种显示基板，显示基板中的信号线所在的层中设置有与信号线并列设置的第一绝缘层，可以提高显示基板的表面的平坦度，避免后续设置于显示基板上的结构因段差过大导致的显示不良等问题。
(2)在本公开至少一个实施例提供的显示基板中，显示基板的表面平坦度提高，可以降低或解除信号线在设计时对其厚度的限制。
(3)在本公开至少一个实施例提供的显示基板中，显示基板中的各层的平坦化也可以降低各层结构在形成过程中产生的坡角数量，降低薄膜晶体管中的寄生电容。
对于本公开，还有以下几点需要说明：
(1)本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)为了清晰起见，在用于描述本公开的实施例的附图中，层或区域的厚度被放大或缩小，即这些附图并非按照实际的比例绘制。
(3)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (15)

  1. 一种显示基板，包括：
    衬底基板；
    设置于所述衬底基板上的至少一条第一信号线以及第一绝缘层；
    其中，所述第一绝缘层的远离所述衬底基板的表面和所述第一信号线的远离所述衬底基板的表面与所述衬底基板平行且基本上位于同一个连续的平面内。
  2. 根据权利要求1所述的显示基板，还包括：
    设置于所述衬底基板上的第二绝缘层；
    其中，所述第二绝缘层覆盖所述第一信号线和所述第一绝缘层。
  3. 根据权利要求2所述的显示基板，还包括：
    设置于所述第二绝缘层的远离所述衬底基板一侧的第一电极或半导体层。
  4. 根据权利要求1-3任一所述的显示基板，其中，
    所述第一信号线包括栅线、数据线和公共电极线中的至少一种或组合。
  5. 根据权利要求1-4任一所述的显示基板，其中，
    所述第一信号线为公共电极线，所述第一绝缘层为栅绝缘层。
  6. 根据权利要求1-5任一所述的显示基板，其中，所述显示基板为阵列基板。
  7. 一种显示面板，包括如权利要求1-6任一项所述的显示基板。
  8. 一种显示装置，包括如权利要求7所述的显示面板。
  9. 一种显示基板的制备方法，包括：
    提供衬底基板；
    在所述衬底基板上形成至少一条第一信号线；
    在所述衬底基板上形成与所述第一信号线并列设置的第一绝缘层；
    其中，所述第一绝缘层的远离所述衬底基板的表面和所述第一信号线的远离所述衬底基板的表面与所述衬底基板平行且基本上位于同一个连续的平面内。
  10. 根据权利要求9所述的制备方法，其中，所述在所述衬底基板上 形成至少一条第一信号线包括：
    提供第一掩膜板；
    在所述衬底基板上沉积导电层薄膜以及在所述导电层薄膜上涂覆第一光刻胶层；
    通过所述第一掩膜板对所述第一光刻胶层进行曝光，将曝光后的所述第一光刻胶层显影以得到第一光刻胶图案，使用所述第一光刻胶图案对所述导电层薄膜进行图案化处理以形成至少一条所述第一信号线。
  11. 根据权利要求10所述的制备方法，其中，所述在所述衬底基板上形成与所述第一信号线并列设置的第一绝缘层包括：
    在垂直于所述衬底基板的方向上，在形成有至少一条所述第一信号线的所述衬底基板上沉积与所述第一信号线的厚度基本上相同的第一绝缘层薄膜；
    在所述第一绝缘层薄膜上涂覆第二光刻胶层；
    在所述第二光刻胶层的远离所述衬底基板的一侧，通过所述第一掩膜板对所述第二光刻胶层进行曝光，将曝光后的所述第二光刻胶层显影以得到第二光刻胶图案，使用所述第二光刻胶图案对所述第一绝缘层薄膜进行图案化处理以形成所述第一绝缘层。
  12. 根据权利要求11所述的制备方法，其中
    所述第一光刻胶层为正性光刻胶层，所述第二光刻胶层为负性光刻胶层；或
    所述第一光刻胶层为负性光刻胶层，所述第二光刻胶层为正性光刻胶层。
  13. 根据权利要求10所述的制备方法，其中，在所述衬底基板上形成与所述第一信号线并列设置的第一绝缘层包括：
    在垂直于所述衬底基板的方向上，在形成有至少一条所述第一信号线的所述衬底基板上沉积与所述第一信号线的厚度基本上相同的第一绝缘层薄膜；
    在所述第一栅绝缘层薄膜上涂覆第三光刻胶层；
    在所述衬底基板的远离所述第一信号线的一侧，以所述第一信号线为掩膜板对所述第三光刻胶层进行曝光，将曝光后的所述第三光刻胶层显影以得到第三光刻胶图案，使用所述第三光刻胶图案对所述第一绝缘层薄膜 进行图案化处理以形成所述第一绝缘层。
  14. 根据权利要求13所述的制备方法，其中，
    所述第三光刻胶层为负性光刻胶层。
  15. 根据权利要求9-14任一所述的制备方法，还包括：
    在形成有所述第一信号线和所述第一绝缘层的衬底基板上形成第二绝缘层；
    其中，所述第二绝缘层覆盖所述第一信号线和所述第一绝缘层。
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CN107065356A (zh) * 2017-05-10 2017-08-18 京东方科技集团股份有限公司 显示基板及其制备方法、显示面板和显示装置
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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007193200A (ja) * 2006-01-20 2007-08-02 Fujitsu Ltd 半導体装置の製造方法及び反射型液晶表示装置の製造方法
US20080023697A1 (en) * 2006-07-28 2008-01-31 Seung Hwan Cho Organic thin film transistor substrate and method of manufacturing the same
CN101807585A (zh) * 2009-02-18 2010-08-18 北京京东方光电科技有限公司 Tft-lcd阵列基板及其制造方法
JP2011221116A (ja) * 2010-04-06 2011-11-04 Seiko Epson Corp 電気光学装置の製造方法
CN104733477A (zh) * 2015-04-01 2015-06-24 上海天马微电子有限公司 阵列基板及其制作方法、显示面板、显示装置
CN205581480U (zh) * 2016-05-05 2016-09-14 鄂尔多斯市源盛光电有限责任公司 阵列基板、显示面板和显示装置
CN107065356A (zh) * 2017-05-10 2017-08-18 京东方科技集团股份有限公司 显示基板及其制备方法、显示面板和显示装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4670097A (en) * 1985-12-23 1987-06-02 Gte Products Corporation Method for patterning transparent layers on a transparent substrate
DE102006033496A1 (de) 2006-07-19 2008-01-31 Siemens Ag Strahlungsdetektor für Röntgen- oder Gammastrahlen
CN100541277C (zh) * 2006-08-17 2009-09-16 胜华科技股份有限公司 液晶显示器
CN103779202B (zh) * 2014-01-27 2016-12-07 深圳市华星光电技术有限公司 像素结构及其制作方法和显示面板
CN205591480U (zh) 2016-04-28 2016-09-21 广东省第一建筑工程有限公司 一种运动场馆的地板结构

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007193200A (ja) * 2006-01-20 2007-08-02 Fujitsu Ltd 半導体装置の製造方法及び反射型液晶表示装置の製造方法
US20080023697A1 (en) * 2006-07-28 2008-01-31 Seung Hwan Cho Organic thin film transistor substrate and method of manufacturing the same
CN101807585A (zh) * 2009-02-18 2010-08-18 北京京东方光电科技有限公司 Tft-lcd阵列基板及其制造方法
JP2011221116A (ja) * 2010-04-06 2011-11-04 Seiko Epson Corp 電気光学装置の製造方法
CN104733477A (zh) * 2015-04-01 2015-06-24 上海天马微电子有限公司 阵列基板及其制作方法、显示面板、显示装置
CN205581480U (zh) * 2016-05-05 2016-09-14 鄂尔多斯市源盛光电有限责任公司 阵列基板、显示面板和显示装置
CN107065356A (zh) * 2017-05-10 2017-08-18 京东方科技集团股份有限公司 显示基板及其制备方法、显示面板和显示装置

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