WO2018157751A1 - 起始信号生成电路、驱动方法和显示装置 - Google Patents

起始信号生成电路、驱动方法和显示装置 Download PDF

Info

Publication number
WO2018157751A1
WO2018157751A1 PCT/CN2018/076976 CN2018076976W WO2018157751A1 WO 2018157751 A1 WO2018157751 A1 WO 2018157751A1 CN 2018076976 W CN2018076976 W CN 2018076976W WO 2018157751 A1 WO2018157751 A1 WO 2018157751A1
Authority
WO
WIPO (PCT)
Prior art keywords
pull
node
level
control
input terminal
Prior art date
Application number
PCT/CN2018/076976
Other languages
English (en)
French (fr)
Inventor
栗峰
王宝强
苏秋杰
Original Assignee
京东方科技集团股份有限公司
北京京东方显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 北京京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/077,992 priority Critical patent/US11158224B2/en
Publication of WO2018157751A1 publication Critical patent/WO2018157751A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present disclosure relates to the field of display driving technologies, and in particular, to an initial signal generating circuit, a driving method, and a display device.
  • the existing GOA (Gate On Array) circuit requires a separate trace for the gate drive unit to provide the start signal STV on the array substrate, and the existing trace cannot be used as the gate.
  • the pole drive unit provides a start signal, so that there is an additional start signal output to provide the start signal, so that the corresponding start signal trace needs to be added, and an additional start signal output is added. The space from which the signal is routed.
  • some embodiments of the present disclosure provide a start signal generation circuit for providing a start signal to a GOA circuit, the GOA circuit and 2N clock signal inputs, a first level input, and a The two-level input terminal is connected, N is an integer greater than 1, and the start signal generating circuit comprises: a pull-down node control unit, respectively connected to the pull-down node and the pull-up node, for controlling under the control of the pull-up node a potential of the pull-down node; a pull-up control node control unit, respectively connected to the first clock signal input end, the second clock signal input end, and the 2n clock signal input end and the pull-up control node, for the first Controlling a potential of the pull-up control node under control of a clock signal input terminal, a second clock signal input terminal, and a 2nth clock signal input terminal; and a pull-up node control unit, respectively, and the pull-up node and the pull-up control node And the pull-down node is connected to
  • the period T of the clock signal input by each clock signal input terminal is equal during each frame display period, and the adjacent one clock signal is delayed by T/ from the adjacent previous clock signal period. 2N.
  • the pull-down node control unit is further connected to the first level input end and the second level input end, respectively, for specifically controlling when the potential of the pull-up node is at a first level.
  • the pull-down node is connected to the second level input terminal, and controls the pull-down node to be connected to the first level input terminal when the potential of the pull-up node is at a second level;
  • the pull-up control node control unit And being connected to the second level input end, specifically for controlling the input of the first level when the first clock signal input end is input, and the second clock signal input end and the 2nth clock signal input end are both inputting the second level a pull-up control node is connected to the first clock signal input end, and is configured to control the pull-up control when the second clock signal input end inputs a first level and/or the 2n clock signal input end inputs a first level A node is coupled to the second level input.
  • the pull-down node control unit includes: a first pull-down node control transistor, a gate connected to the pull-up node, a first pole connected to the pull-down control node, and a second pole and the a second level input terminal is connected; a second pull-down node controls the transistor, a gate is connected to the pull-up node, a first pole is connected to the pull-down node, and a second pole is connected to the second level input end; a three pull-down node control transistor, the gate and the first pole are both connected to the first level input terminal, the second pole is connected to the pull-down control node; and the fourth pull-down node controls the transistor, the gate and the pull-down The control node is connected, the first pole is connected to the first level input terminal, and the second pole is connected to the pulldown node.
  • the pull-up control node control unit includes: a pull-up control transistor, the gate and the first pole are both connected to the first clock signal input end, and the second pole and the pull-up a control node is connected; the first pull-up control node controls the transistor, the gate is connected to the second clock signal input end, the first pole is connected to the pull-up control node, and the second pole and the second level input end Connecting; and, the nth pull-up control node controls the transistor, the gate is connected to the second nth clock signal input end, the first pole is connected to the pull-up control node, and the second pole and the second level input end connection.
  • the pull-up node control unit is further connected to the first level input end and the second level input end respectively, specifically for when the potential of the pull-up control node Controlling, when the first level is connected, the pull-up node is connected to the first level input terminal, and the potential of the pull-down node is a first level and/or the second clock signal input end is inputting a first level.
  • the pull-up node is connected to the second level input terminal; the start signal output unit is specifically configured to control the start signal output end and the The first level input terminal is connected, and controls the start signal output end and the second power when the potential of the pull-down node is a first level and/or the second clock signal input end inputs a first level Flat input connection.
  • the pull-up node control unit includes: a first pull-up node control transistor, a gate connected to the pull-up control node, and a first pole connected to the first level input terminal a second pole is connected to the pull-up node; a second pull-up node controls a transistor, a gate is connected to the pull-down node, a first pole is connected to the pull-up node, and a second pole is connected to the second level The input terminal is connected; and the third pull-up node controls the transistor, the gate is connected to the second clock signal input end, the first pole is connected to the pull-up node, and the second pole and the second level input end connection.
  • the start signal output unit includes: a first start signal output transistor, a gate connected to the pull-up node, and a first pole connected to the first level input end, a second pole is connected to the start signal output end; a second start signal output transistor, a gate connected to the pull-down node, a first pole connected to the start signal output end, a second pole and the second pole a level input terminal is connected; and a third start signal output transistor, a gate connected to the second clock signal input end, a first pole connected to the start signal output end, and a second pole and the second pole The level inputs are connected.
  • the present disclosure also provides a driving method of a start signal generating circuit, which is applied to the above-mentioned start signal generating circuit, the start signal generating circuit is configured to provide a start signal for a GOA circuit, and the GOA circuit respectively Connected to the 2N clock signal input terminal, the first level input terminal and the second level input terminal, N is an integer greater than 1;
  • the driving method includes: when the first clock signal input terminal inputs the first level and When both the clock signal input end and the 2n clock signal input end are input to the second level, the pull-up control node control unit controls the pull-up control node to be connected to the first clock signal input end, and the pull-up node control unit is on the Controlling, by the control of the pull control node, the potential of the pull-up node is a first level; under the control of the pull-up node, the pull-down node control unit controls the potential of the pull-down node to be a second level; the start signal output unit is at the Controlling the start signal output
  • the present disclosure also provides a gate driving apparatus including a GOA circuit, further comprising the above-described start signal generating circuit; the start signal generating circuit is connected to the GOA circuit for providing a start for the GOA circuit signal.
  • the start signal generating circuit, the driving method and the display device of the present disclosure can provide a start signal by using a terminal required for the operation of the GOA circuit on the existing array substrate, thereby saving an additional start.
  • FIG. 1 is a structural diagram of a start signal generating circuit according to an embodiment of the present disclosure
  • FIG. 3 is a structural diagram of a start signal generating circuit according to another embodiment of the present disclosure.
  • FIG. 4 is a timing chart showing an operation of a start signal generating circuit according to an embodiment of the present disclosure
  • Figure 5 is a circuit diagram of a specific embodiment of the start signal generating circuit of the present disclosure.
  • the transistors employed in all embodiments of the present disclosure may each be a thin film transistor or a field effect transistor or other device having the same characteristics.
  • one of the poles is referred to as a first pole, and the other pole is referred to as a second pole.
  • the first pole may be a drain, and the second pole may be a source; or the first pole may be a source, and the second pole may be a drain .
  • the start signal generating circuit of the embodiment of the present disclosure is configured to provide a start signal for the GOA circuit, and the GOA circuit is respectively connected to 2N clock signal input ends, a first level input end, and a second level input end. , N is an integer greater than one.
  • the start signal generating circuit includes: a pull-down node control unit, respectively connected to the pull-down node and the pull-up node, for controlling the potential of the pull-down node under the control of the pull-up node; and pulling up the control node control unit, And respectively connected to the first clock signal input end, the second clock signal input end, and the 2nth clock signal input end and the pull-up control node, for the first clock signal input end, the second clock signal input end, and the 2n Controlling a potential of the pull-up control node under control of a clock signal input; a pull-up node control unit, respectively, with the pull-up node, the pull-up control node, the pull-down node, and the second clock signal input end a connection for controlling a potential of the pull-up node under control of the pull-up control node, the pull-down node, and the second clock signal input terminal; a storage unit connected to the pull-up node and starting Between the signal output terminals; and a start signal output
  • the initial signal generating circuit can generate a terminal required for the operation of the GOA circuit existing on the existing array substrate: a clock signal input terminal, a first level input terminal, and a second level input terminal.
  • the initial start signal is solved, thereby solving the problem in the related art that an additional start signal output is required in order to provide the start signal, so that the corresponding start signal trace needs to be increased.
  • the initial signal generating circuit of the embodiment of the present disclosure can provide a start signal by using a terminal required for the operation of the GOA circuit on the existing array substrate, thereby saving an additional initial signal output end and an initial signal trace. space.
  • the start signal generating circuit of the embodiment of the present disclosure is configured to provide a start signal for the GOA circuit, and the GOA circuit is respectively connected to the six clock signal input ends, the first level input end and the second level input end. .
  • the start signal generating circuit includes: a pull-down node control unit 11 connected to the pull-down node PD and the pull-up node PU, respectively, for controlling the pull-down node under the control of the pull-up node PU The potential of the PD; the pull-up control node control unit 12, respectively, with the first clock signal input terminal CLK1, the second clock signal input terminal CLK2, the fourth clock signal input terminal CLK4, the sixth clock signal input terminal CLK6, and the pull-up control node a PUCN connection for controlling the potential of the pull-up control node PUCN under the control of the first clock signal input terminal CLK1, the second clock signal input terminal CLK2, the fourth clock signal input terminal CLK4, and the sixth clock signal input terminal CLK6 a pull-up node
  • the start signal generating circuit of the embodiment of the present disclosure when the start signal generating circuit of the embodiment of the present disclosure includes transistors that are all n-type transistors, the first level is a high level, and the second level is a low level; When the start signal generating circuit of the embodiment of the present disclosure includes transistors which are all p-type transistors, the first level is a low level and the second level is a high level.
  • the period T of the clock signal input by each clock signal input terminal is equal, and the adjacent one clock signal is delayed by T/2N from the adjacent previous clock signal period.
  • the vertical axis is voltage and the horizontal axis is time.
  • N equal to 3, but is not limited thereto. In some optional embodiments, N may be any integer greater than or equal to 2.
  • the pull-down node control unit is further connected to the first level input end and the second level input end, respectively, for specifically controlling when the potential of the pull-up node is at a first level.
  • the pull-down node is connected to the second level input terminal, and controls the pull-down node to be connected to the first level input terminal when the potential of the pull-up node is at a second level;
  • the pull-up control node control unit And being connected to the second level input end, specifically for controlling the input of the first level when the first clock signal input end is input, and the second clock signal input end and the 2nth clock signal input end are both inputting the second level a pull-up control node is connected to the first clock signal input end, and is configured to control the pull-up control when the second clock signal input end inputs a first level and/or the 2n clock signal input end inputs a first level A node is coupled to the second level input.
  • the pull-up node control unit is further connected to the first level input end and the second level input end respectively, specifically for when the potential of the pull-up control node Controlling, when the first level is connected, the pull-up node is connected to the first level input terminal, and the potential of the pull-down node is a first level and/or the second clock signal input end is inputting a first level.
  • the pull-up node is connected to the second level input terminal; the start signal output unit is specifically configured to control the start signal output end and the The first level input terminal is connected, and controls the start signal output end and the second power when the potential of the pull-down node is a first level and/or the second clock signal input end inputs a first level Flat input connection.
  • the pull-down node control unit 11 is also connected to the first level input terminal VI1 and the second level input terminal VI2, respectively. Specifically, when the potential of the pull-up node PU is at a first level, the pull-down node PD is controlled to be connected to the second level input terminal VI2, and when the potential of the pull-up node PU is at a second level, the control station is The pull-down node PD is connected to the first level input terminal VI1; the pull-up control node control unit 12 is also connected to the second level input terminal VI2, specifically for inputting at the first clock signal input terminal CLK1.
  • the terminal CLK1 is connected, and is configured to control the pull-up control node PUCN when at least one of the second clock signal input terminal CLK2, the fourth clock signal input terminal CLK4, and the sixth clock signal input terminal CLK6 inputs a first level
  • the second level input The terminal of the pull-up control node is connected to the first level input terminal VI1 and the second level input terminal VI2, specifically for when the potential of the pull-up control node PUCN is Controlling, by the first level, the pull-up node PU is connected to the first level input terminal VI1, and the potential of the pull-down node PD is a first level and/or the second clock signal input end CLK2 is input first Level-time controlling the pull-up node PU to be connected to the second level input terminal VI2; the start signal output
  • the embodiment of the initial signal generating circuit shown in FIG. 3 of the present disclosure is in operation (assuming that the first level is a high level and the second level is a low level),
  • the pull-up control node control unit 12 controls The pull-up control node PUCN is connected to the first clock signal input terminal CLK1 such that the potential of the PUCN is at a high level, and the pull-up node control unit 13 controls the pull-up node PU under the control of the pull-up control node PUCN
  • the potential is a high level; under the control of the pull-up node PU, the pull-down node control unit 11 controls the potential of the pull-down node PD to be a low level;
  • the start signal output unit 15 is at the pull-up node PU and the pull-down
  • the control start signal output terminal STV_OUT outputs a high level under the control of the node PD.
  • the pull-up control node control unit 12 controls the pull-up control node PUCN to be connected to the second level input terminal VI2, so that the potential of the PUCN is low.
  • the pull-up node control unit 13 controls the potential of the pull-up node PU to be low under the control of the pull-up control node PUCN and the second clock signal input terminal CLK2, and the pull-down node control unit 11 is in the Controlling the potential of the pull-down node PD to be a high level under the control of the pull-up node PU, the start signal output unit 15 controlling the start under the control of the pull-up node PU and the pull-down node PD
  • the signal output terminal STV_OUT outputs a low level.
  • the pull-up control node control unit 12 continues to control the pull-up control node PUCN and the second level input terminal.
  • VI2 is connected such that the potential of the PUCN is at a low level, and the pull-up node control unit 13 controls the potential of the pull-up node PU to be maintained at a low level under the control of the pull-up control node PUCN, and the pull-down node control unit 11 Controlling the potential of the pull-down node PD to be high under the control of the pull-up node PU, and the start signal output unit 15 controls the control under the control of the pull-up node PU and the pull-down node PD
  • the start signal output terminal STV_OUT outputs a low level.
  • the pull-down node control unit may include: a first pull-down node control transistor, a gate connected to the pull-up node, a first pole connected to the pull-down control node, a second pole and the second level input
  • the second pull-down node controls the transistor, the gate is connected to the pull-up node, the first pole is connected to the pull-down node, the second pole is connected to the second level input terminal, and the third pull-down node controls the transistor a gate and a first pole are both connected to the first level input terminal, a second pole is connected to the pull-down control node; and a fourth pull-down node controls the transistor, and the gate is connected to the pull-down control node, One pole is coupled to the first level input and a second pole is coupled to the pull down node.
  • the pull-up control node control unit may include: a pull-up control transistor, the gate and the first pole are both connected to the first clock signal input end, and the second pole is connected to the pull-up control node; a pull-up control node control transistor, a gate connected to the second clock signal input terminal, a first pole connected to the pull-up control node, and a second pole connected to the second level input terminal; and, The n pull-up control node controls the transistor, the gate is connected to the second n-clock signal input terminal, the first pole is connected to the pull-up control node, and the second pole is connected to the second level input terminal.
  • the pull-up node control unit may include: a first pull-up node control transistor, a gate connected to the pull-up control node, a first pole connected to the first level input end, and a second pole
  • the pull-up node is connected;
  • the second pull-up node controls the transistor, the gate is connected to the pull-down node, the first pole is connected to the pull-up node, and the second pole is connected to the second level input;
  • the third pull-up node controls the transistor, the gate is connected to the second clock signal input terminal, the first pole is connected to the pull-up node, and the second pole is connected to the second level input terminal.
  • the start signal output unit may include: a first start signal output transistor, a gate connected to the pull-up node, a first pole connected to the first level input end, a second pole and the a start signal output terminal is connected; a second start signal output transistor, a gate connected to the pull-down node, a first pole connected to the start signal output end, and a second pole connected to the second level input end And a third start signal output transistor, the gate is connected to the second clock signal input end, the first pole is connected to the start signal output end, and the second pole is connected to the second level input end; .
  • the start signal generating unit of the present disclosure will be described below by way of a specific embodiment.
  • a specific embodiment of the start signal generating unit of the present disclosure includes a pull-down node control unit, a pull-up control node control unit, a pull-up node control unit, a storage unit, and a start signal output unit.
  • the pull-down node control unit includes: a first pull-down node control transistor MDC1, a gate connected to the pull-up node PU, a drain connected to the pull-down control node PDCN, and a source connected to the low-level input terminal VSS;
  • the pull-down node controls the transistor MDC2, the gate is connected to the pull-up node PU, the drain is connected to the pull-down node PD, the source is connected to the low-level input terminal VSS, and the third pull-down node controls the transistor MDC3, the gate and the drain
  • the pole is connected to the high level input terminal VGH, the source is connected to the pull-down control node PDCN; and the fourth pull-down node controls the transistor MDC4, the gate is connected to the pull-down control node PDCN, and the drain and the high level input The terminal VGH is connected, and the source is connected to the pull-down node PD.
  • the pull-up control node control unit may include: a pull-up control transistor M120, the gate and the drain are both connected to the first clock signal input terminal CLK1, and the source is connected to the pull-up control node PUCN;
  • the pull control node controls the transistor M121, the gate is connected to the second clock signal input terminal CLK2, the drain is connected to the pull-up control node PUCN, and the source is connected to the low level input terminal VSS;
  • the second pull-up control node a control transistor M122, a gate connected to the fourth clock signal input terminal CLK4, a drain connected to the pull-up control node PUCN, a source connected to the low level input terminal VSS, and a third pull-up control node control
  • the transistor M123 has a gate connected to the sixth clock signal input terminal CLK6, a drain connected to the pull-up control node PUCN, and a source connected to the low level input terminal VSS.
  • the pull-up node control unit includes: a first pull-up node control transistor MUC1, a gate connected to the pull-up control node PUCN, a drain connected to a high-level input terminal VGH, a source and the pull-up node PU Connecting; the second pull-up node controls the transistor MUC2, the gate is connected to the pull-down node PD, the drain is connected to the pull-up node PU, the source is connected to the low-level input terminal VSS; and the third pull-up node a control transistor MUC3, a gate connected to the second clock signal input terminal CLK2, a drain connected to the pull-up node PU, and a source connected to the low-level input terminal VSS;
  • the start signal output unit includes: a first start signal output transistor MO1, a gate connected to the pull-up node PU, a drain connected to the high-level input terminal VGH, a source and the start signal output terminal STV_OUT Connected; a second start signal output transistor MO2, a gate connected to the pull-down node PD, a drain connected to the start signal output terminal STV_OUT, a source connected to the low-level input terminal VSS; and, the third The start signal output transistor MO3 has a gate connected to the second clock signal input terminal CLK2, a drain connected to the start signal output terminal STV_OUT, and a source connected to the low level input terminal VSS; the storage unit includes: The storage capacitor C1 is connected between the pull-up node PU and the start signal output terminal STV_OUT.
  • all of the transistors are n-type transistors.
  • the transistors may also be p-type transistors, and only the timing of each clock signal needs to be inverted. Set the first level to low and the second level to high.
  • the MDC3 and MDC4 are turned on before the CLK1 is input to the high level, and the potential of the PDCN and the potential of the PD are high.
  • the potential of the start signal of STV_OUT output will be high level, that is, the time when each frame is turned on;
  • the potential of the pull-up node PU of the first row of GOA units included in the GOA circuit that accesses the start signal is pulled high to ensure normal output of the GOA circuit.
  • the first clock signal accessed by the first row of GOA units and the potential of the pull-up node PU in the first row of GOA units simultaneously become high level, and the gate drive signal outputted by the first row of GOA units is maintained.
  • the first row of GOA units can be set to the Dummy (pseudo) GOA unit, that is, the first The row GOA unit does not drive the gate line.
  • the driving method of the initial signal generating circuit is applied to the above-described start signal generating circuit, and the start signal generating circuit is configured to provide a start signal for the GOA circuit, and the GOA circuit is respectively associated with 2N
  • the clock signal input terminal, the first level input terminal and the second level input terminal are connected, and N is an integer greater than 1; the driving method comprises the following steps.
  • the pull-up control node control unit controls the pull-up control node and the first clock a signal input terminal is connected, and the pull-up node control unit controls the potential of the pull-up node to be a first level under the control of the pull-up control node; under the control of the pull-up node, the pull-down node control unit controls the pull-down node The potential is a second level; the start signal output unit controls the start signal output end to output the first level under the control of the pull-up node and the pull-down node;
  • the pull-up control node control unit controls the pull-up control node to be connected to the second level input terminal, and the pull-up node control unit controls the pull-up
  • the potential of the pull-up node is controlled to be a second level under control of the node and the second clock signal input end
  • the pull-down node control unit controls the potential of the pull-down node to be the first power under the control of the pull-up node Pinging
  • the start signal output unit controls the start signal output end to output a second level under the control of the pull-up node and the pull-down node;
  • the pull-up control node control unit continues to control the pull-up control node to be connected to the second level input terminal, and the pull-up node control unit is in the pull-up Controlling, by the control node, the potential of the pull-up node is maintained at a second level, and the pull-down node control unit controls the potential of the pull-down node to be a first level under the control of the pull-up node, the start The signal output unit controls the start signal output terminal to output a second level under the control of the pull-up node and the pull-down node.
  • n is an integer greater than 1 and less than or equal to N.
  • the gate driving device of the embodiment of the present disclosure includes a GOA circuit, and further includes the above-mentioned start signal generating circuit; the start signal generating circuit is connected to the GOA circuit for providing a start for the GOA circuit signal.

Abstract

一种起始信号生成电路、驱动方法和显示装置。起始信号生成电路包括：下拉节点控制单元（11）；上拉控制节点控制单元（12），用于在第一时钟信号输入端、第二时钟信号输入端和第2n时钟信号输入端的控制下控制上拉控制节点（PUCN）的电位；上拉节点控制单元（13）；存储单元（14），连接于上拉节点（PU）与起始信号输出端（STV_OUT）之间；以及，起始信号输出单元（15）；n为大于1而小于等于N的整数，N为大于1的整数。

Description

起始信号生成电路、驱动方法和显示装置
相关申请的交叉引用
本申请主张在2017年3月2日在中国提交的中国专利申请号No.201710119977.9的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示驱动技术领域，尤其涉及一种起始信号生成电路、驱动方法和显示装置。
背景技术
现有的GOA(Gate On Array，阵列基板行驱动)电路需要在阵列基板上单独设置一根为栅极驱动单元提供起始信号STV的走线，而无法利用现有的走线既可以为栅极驱动单元提供起始信号，从而存在为了提供起始信号还需设置额外的起始信号输出端，从而需要增加相应的起始信号走线的问题，增加了额外的起始信号输出端和起始信号走线的空间。
发明内容
一方面，本公开一些实施例中提供了一种起始信号生成电路，用于为GOA电路提供起始信号，所述GOA电路分别与2N个时钟信号输入端、第一电平输入端和第二电平输入端连接，N为大于1的整数，所述起始信号生成电路包括：下拉节点控制单元，分别与下拉节点和上拉节点连接，用于在所述上拉节点的控制下控制所述下拉节点的电位；上拉控制节点控制单元，分别与第一时钟信号输入端、第二时钟信号输入端和第2n时钟信号输入端和上拉控制节点连接，用于在所述第一时钟信号输入端、第二时钟信号输入端和第2n时钟信号输入端的控制下控制所述上拉控制节点的电位；上拉节点控制单元，分别与所述上拉节点、所述上拉控制节点、所述下拉节点和所述第二时钟信号输入端连接，用于在所述上拉控制节点、所述下拉节点和所述第二时钟信号输入端的控制下，控制所述上拉节点的电位；存储单元，连接于 所述上拉节点与起始信号输出端之间；以及，起始信号输出单元，分别与所述上拉节点、所述下拉节点、所述第二时钟信号输入端、起始信号输出端、所述第一电平输入端和所述第二电平输入端连接，用于在所述上拉节点、所述下拉节点和所述第二时钟信号输入端的控制下，控制所述起始信号输出端与所述第一电平输入端连接或控制所述起始信号输出端与所述第二电平输入端连接；n为大于1而小于等于N的整数。
在一些可选的实施例中，在每一帧显示时间段内，每个时钟信号输入端输入的时钟信号的周期T相等，相邻后一个时钟信号比相邻前一个时钟信号周期延迟T/2N。
在一些可选的实施例中，所述下拉节点控制单元还分别与第一电平输入端和第二电平输入端连接，具体用于当所述上拉节点的电位为第一电平时控制所述下拉节点与第二电平输入端连接，当所述上拉节点的电位为第二电平时控制所述下拉节点与所述第一电平输入端连接；所述上拉控制节点控制单元还与所述第二电平输入端连接，具体用于在第一时钟信号输入端输入第一电平而第二时钟信号输入端和第2n时钟信号输入端都输入第二电平时控制所述上拉控制节点与所述第一时钟信号输入端连接，并用于当所述第二时钟信号输入端输入第一电平和/或第2n时钟信号输入端输入第一电平时控制所述上拉控制节点与所述第二电平输入端连接。
在一些可选的实施例中，所述下拉节点控制单元包括：第一下拉节点控制晶体管，栅极与所述上拉节点连接，第一极与下拉控制节点连接，第二极与所述第二电平输入端连接；第二下拉节点控制晶体管，栅极与所述上拉节点连接，第一极与所述下拉节点连接，第二极与所述第二电平输入端连接；第三下拉节点控制晶体管，栅极和第一极都与所述第一电平输入端连接，第二极与所述下拉控制节点连接；以及，第四下拉节点控制晶体管，栅极与所述下拉控制节点连接，第一极与所述第一电平输入端连接，第二极与所述下拉节点连接。
在一些可选的实施例中，所述上拉控制节点控制单元包括：上拉控制晶体管，栅极和第一极都与所述第一时钟信号输入端连接，第二极与所述上拉控制节点连接；第一上拉控制节点控制晶体管，栅极与所述第二时钟信号输 入端连接，第一极与所述上拉控制节点连接，第二极与所述第二电平输入端连接；以及，第n上拉控制节点控制晶体管，栅极与所述第2n时钟信号输入端连接，第一极与所述上拉控制节点连接，第二极与所述第二电平输入端连接。
在一些可选的实施例中，所述上拉节点控制单元还分别与所述第一电平输入端和所述第二电平输入端连接，具体用于当所述上拉控制节点的电位为第一电平时控制所述上拉节点与所述第一电平输入端连接，并所述下拉节点的电位为第一电平和/或所述第二时钟信号输入端输入第一电平时控制所述上拉节点与所述第二电平输入端连接；所述起始信号输出单元具体用于当所述上拉节点的电位为第一电平时控制所述起始信号输出端与所述第一电平输入端连接，并当所述下拉节点的电位为第一电平和/或所述第二时钟信号输入端输入第一电平时控制所述起始信号输出端与所述第二电平输入端连接。
在一些可选的实施例中，所述上拉节点控制单元包括：第一上拉节点控制晶体管，栅极与所述上拉控制节点连接，第一极与所述第一电平输入端连接，第二极与所述上拉节点连接；第二上拉节点控制晶体管，栅极与所述下拉节点连接，第一极与所述上拉节点连接，第二极与所述第二电平输入端连接；以及，第三上拉节点控制晶体管，栅极与所述第二时钟信号输入端连接，第一极与所述上拉节点连接，第二极与所述第二电平输入端连接。
在一些可选的实施例中，所述起始信号输出单元包括：第一起始信号输出晶体管，栅极与所述上拉节点连接，第一极与所述第一电平输入端连接，第二极与所述起始信号输出端连接；第二起始信号输出晶体管，栅极与所述下拉节点连接，第一极与所述起始信号输出端连接，第二极与所述第二电平输入端连接；以及，第三起始信号输出晶体管，栅极与所述第二时钟信号输入端连接，第一极与所述起始信号输出端连接，第二极与所述第二电平输入端连接。
本公开还提供了一种起始信号生成电路的驱动方法，应用于上所述的起始信号生成电路，所述起始信号生成电路用于为GOA电路提供起始信号，所述GOA电路分别与2N个时钟信号输入端、第一电平输入端和第二电平输入端连接，N为大于1的整数；所述驱动方法包括：当第一时钟信号输入端输 入第一电平并第二时钟信号输入端和第2n时钟信号输入端都输入第二电平时，上拉控制节点控制单元控制上拉控制节点与所述第一时钟信号输入端连接，上拉节点控制单元在所述上拉控制节点的控制下控制上拉节点的电位为第一电平；在所述上拉节点的控制下，下拉节点控制单元控制下拉节点的电位为第二电平；起始信号输出单元在所述上拉节点和所述下拉节点的控制下控制起始信号输出端输出第一电平；当第二时钟信号输入端输入第一电平时，所述上拉控制节点控制单元控制所述上拉控制节点与所述第二电平输入端连接，上拉节点控制单元在所述上拉控制节点和所述第二时钟信号输入端的控制下控制所述上拉节点的电位为第二电平，下拉节点控制单元在所述上拉节点的控制下控制所述下拉节点的电位为第一电平，所述起始信号输出单元在所述上拉节点和所述下拉节点的控制下控制所述起始信号输出端输出第二电平；当第2n时钟信号输入端输入第一电平时，所述上拉控制节点控制单元继续控制所述上拉控制节点与所述第二电平输入端连接，上拉节点控制单元在所述上拉控制节点的控制下控制所述上拉节点的电位维持为第二电平，下拉节点控制单元在所述上拉节点的控制下控制所述下拉节点的电位为第一电平，所述起始信号输出单元在所述上拉节点和所述下拉节点的控制下控制所述起始信号输出端输出第二电平；n为大于1而小于等于N的整数。
本公开还提供了一种栅极驱动装置，包括GOA电路，还包括上述的起始信号生成电路；所述起始信号生成电路与所述GOA电路连接，用于为所述GOA电路提供起始信号。
与相关技术相比，本公开所述的起始信号生成电路、驱动方法和显示装置通过现有的阵列基板上已经存在GOA电路工作需要的端子即可提供起始信号，节省了额外的起始信号输出端和起始信号走线的空间。
附图说明
图1是本公开实施例所述的起始信号生成电路的结构图；
图2是当N等于3时各个时钟信号的时序图；
图3是本公开另一实施例所述的起始信号生成电路的结构图；
图4是本公开实施例所述的起始信号生成电路的工作时序图；
图5是本公开所述的起始信号生成电路的一具体实施例的电路图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
本公开所有实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件。在本公开实施例中，为区分晶体管除栅极之外的两极，将其中一极称为第一极，另一极称为第二极。在一些可选的实施例中，所述第一极可以为漏极，所述第二极可以为源极；或者，所述第一极可以为源极，所述第二极可以为漏极。
除非另作定义，此处使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开专利申请说明书以及权利要求书中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”或者“一”等类似词语也不表示数量限制，而是表示存在至少一个。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也相应地改变。
本公开实施例所述的起始信号生成电路，用于为GOA电路提供起始信号，所述GOA电路分别与2N个时钟信号输入端、第一电平输入端和第二电平输入端连接，N为大于1的整数。所述起始信号生成电路包括：下拉节点控制单元，分别与下拉节点和上拉节点连接，用于在所述上拉节点的控制下控制所述下拉节点的电位；上拉控制节点控制单元，分别与第一时钟信号输入端、第二时钟信号输入端和第2n时钟信号输入端和上拉控制节点连接，用于在所述第一时钟信号输入端、第二时钟信号输入端和第2n时钟信号输入端的控制下控制所述上拉控制节点的电位；上拉节点控制单元，分别与所述上拉节点、所述上拉控制节点、所述下拉节点和所述第二时钟信号输入端连接，用于在 所述上拉控制节点、所述下拉节点和所述第二时钟信号输入端的控制下，控制所述上拉节点的电位；存储单元，连接于所述上拉节点与起始信号输出端之间；以及，起始信号输出单元，分别与所述上拉节点、所述下拉节点、所述第二时钟信号输入端、起始信号输出端、所述第一电平输入端和所述第二电平输入端连接，用于在所述上拉节点、所述下拉节点和所述第二时钟信号输入端的控制下，控制所述起始信号输出端与所述第一电平输入端连接或控制所述起始信号输出端与所述第二电平输入端连接；n为大于1而小于等于N的整数。
本公开实施例所述的起始信号生成电路通过现有的阵列基板上存在的GOA电路工作需要的端子：时钟信号输入端、第一电平输入端和第二电平输入端，即可生成起始起始信号，从而解决了相关技术中为了提供起始信号还需设置额外的起始信号输出端，从而需要增加相应的起始信号走线的问题。
本公开实施例所述的起始信号生成电路通过现有的阵列基板上已经存在GOA电路工作需要的端子即可提供起始信号，节省了额外的起始信号输出端和起始信号走线的空间。
下面以N等于3为例结合附图来说明本公开实施例所述的起始信号生成电路。
本公开实施例所述的起始信号生成电路，用于为GOA电路提供起始信号，所述GOA电路分别与6个时钟信号输入端、第一电平输入端和第二电平输入端连接。如图1所示，所述起始信号生成电路包括：下拉节点控制单元11，分别与下拉节点PD和上拉节点PU连接，用于在所述上拉节点PU的控制下控制所述下拉节点PD的电位；上拉控制节点控制单元12，分别与第一时钟信号输入端CLK1、第二时钟信号输入端CLK2、第四时钟信号输入端CLK4、第六时钟信号输入端CLK6和上拉控制节点PUCN连接，用于在第一时钟信号输入端CLK1、第二时钟信号输入端CLK2、第四时钟信号输入端CLK4和第六时钟信号输入端CLK6的控制下控制所述上拉控制节点PUCN的电位；上拉节点控制单元13，分别与所述上拉节点PU、所述上拉控制节点PUCN、所述下拉节点PD和所述第二时钟信号输入端CLK2连接，用于在所述上拉控制节点PUCN、所述下拉节点PD和所述第二时钟信号输入端CLK3的控制 下，控制所述上拉节点PU的电位；存储单元14，连接于所述上拉节点PU与起始信号输出端STV_OUT之间；以及，起始信号输出单元15，分别与所述上拉节点PU、所述下拉节点PD、所述第二时钟信号输入端CLK2、起始信号输出端STV_OUT、第一电平输入端VI1和第二电平输入端VI2连接，用于在所述上拉节点PU、所述下拉节点PD和所述第二时钟信号输入端CLK2的控制下，控制所述起始信号输出端STV_OUT与所述第一电平输入端VI1连接或控制所述起始信号输出端STV_OUT与所述第二电平输入端VI2连接。
在一些可选的实施例中，当本公开实施例所述的起始信号生成电路包括的晶体管都是n型晶体管时，第一电平为高电平，第二电平为低电平；当本公开实施例所述的起始信号生成电路包括的晶体管都是p型晶体管时，第一电平为低电平，第二电平为高电平。
具体的，在每一帧显示时间段内，每个时钟信号输入端输入的时钟信号的周期T相等，相邻后一个时钟信号比相邻前一个时钟信号周期延迟T/2N。
当N等于3时，CLK1、CLK2、CLK3、CLK4、CLK5和CLK6的波形如图2所示；在每一帧显示时间段内，CLK1和CLK4反相，CLK2和CLK5反相，CLK3和CLK6反相，CLK1的周期、CLK2的周期、CLK3的周期、CLK4的周期、CLK5的周期和CLK6的周期都为T，CLK2比CLK1推迟T/6，CLK3比CLK2推迟T/6，CLK4比CLK3推迟T/6，CLK5比CLK4推迟T/6，CLK6比CLK5推迟T/6。
在图2所示的时钟信号的波形图中，纵轴为电压，横轴为时间。
本公开实施例以N等于3举例说明，但不以此为限，在一些可选的实施例中，N可以为大于或等于2的任何整数。
在一些可选的实施例中，所述下拉节点控制单元还分别与第一电平输入端和第二电平输入端连接，具体用于当所述上拉节点的电位为第一电平时控制所述下拉节点与第二电平输入端连接，当所述上拉节点的电位为第二电平时控制所述下拉节点与所述第一电平输入端连接；所述上拉控制节点控制单元还与所述第二电平输入端连接，具体用于在第一时钟信号输入端输入第一电平而第二时钟信号输入端和第2n时钟信号输入端都输入第二电平时控制所述上拉控制节点与所述第一时钟信号输入端连接，并用于当所述第二时钟 信号输入端输入第一电平和/或第2n时钟信号输入端输入第一电平时控制所述上拉控制节点与所述第二电平输入端连接。
在一些可选的实施例中，所述上拉节点控制单元还分别与所述第一电平输入端和所述第二电平输入端连接，具体用于当所述上拉控制节点的电位为第一电平时控制所述上拉节点与所述第一电平输入端连接，并所述下拉节点的电位为第一电平和/或所述第二时钟信号输入端输入第一电平时控制所述上拉节点与所述第二电平输入端连接；所述起始信号输出单元具体用于当所述上拉节点的电位为第一电平时控制所述起始信号输出端与所述第一电平输入端连接，并当所述下拉节点的电位为第一电平和/或所述第二时钟信号输入端输入第一电平时控制所述起始信号输出端与所述第二电平输入端连接。
如图3所示，在图2所示的起始信号生成电路的实施例的基础上，所述下拉节点控制单元11还分别与第一电平输入端VI1和第二电平输入端VI2连接，具体用于当所述上拉节点PU的电位为第一电平时控制所述下拉节点PD与第二电平输入端VI2连接，当所述上拉节点PU的电位为第二电平时控制所述下拉节点PD与所述第一电平输入端VI1连接；所述上拉控制节点控制单元12还与所述第二电平输入端VI2连接，具体用于在第一时钟信号输入端CLK1输入第一电平而第二时钟信号输入端CLK2、第四时钟信号输入端CLK4和第六时钟信号输入端CLK6都输入第二电平时控制所述上拉控制节点PUCN与所述第一时钟信号输入端CLK1连接，并用于当所述第二时钟信号输入端CLK2、第四时钟信号输入端CLK4、第六时钟信号输入端CLK6中的至少一个输入第一电平时控制所述上拉控制节点PUCN与所述第二电平输入端VI2连接；所述上拉节点控制单元13还分别与所述第一电平输入端VI1和所述第二电平输入端VI2连接，具体用于当所述上拉控制节点PUCN的电位为第一电平时控制所述上拉节点PU与所述第一电平输入端VI1连接，并所述下拉节点PD的电位为第一电平和/或所述第二时钟信号输入端CLK2输入第一电平时控制所述上拉节点PU与所述第二电平输入端VI2连接；所述起始信号输出单元15具体用于当所述上拉节点PU的电位为第一电平时控制所述起始信号输出端STV_OUT与所述第一电平输入端VI1连接，并当所述下拉节点PD的电位为第一电平和/或所述第二时钟信号输入端CLK2输入第 一电平时控制所述起始信号输出端STV_OUT与所述第二电平输入端VI2连接。
如图4所示，本公开如图3所示的起始信号生成电路的实施例在工作时(假设第一电平为高电平，第二电平为低电平)，
当第一时钟信号输入端CLK1输入高电平并第二时钟信号输入端CLK2、第四时钟信号输入端CLK4和第六时钟信号输入端CLK6都输入低电平时，上拉控制节点控制单元12控制上拉控制节点PUCN与所述第一时钟信号输入端CLK1连接，从而使得PUCN的电位为高电平，上拉节点控制单元13在所述上拉控制节点PUCN的控制下控制上拉节点PU的电位为高电平；在所述上拉节点PU的控制下，下拉节点控制单元11控制下拉节点PD的电位为低电平；起始信号输出单元15在所述上拉节点PU和所述下拉节点PD的控制下控制起始信号输出端STV_OUT输出高电平。
当第二时钟信号输入端CLK2输入高电平时，所述上拉控制节点控制单元12控制所述上拉控制节点PUCN与所述第二电平输入端VI2连接，以使得PUCN的电位为低电平，上拉节点控制单元13在所述上拉控制节点PUCN和所述第二时钟信号输入端CLK2的控制下控制所述上拉节点PU的电位为低电平，下拉节点控制单元11在所述上拉节点PU的控制下控制所述下拉节点PD的电位为高电平，所述起始信号输出单元15在所述上拉节点PU和所述下拉节点PD的控制下控制所述起始信号输出端STV_OUT输出低电平。
当第四时钟信号输入端CLK4和/或第六时钟信号输入端CLK6输入高电平时，所述上拉控制节点控制单元12继续控制所述上拉控制节点PUCN与所述第二电平输入端VI2连接，以使得PUCN的电位为低电平，上拉节点控制单元13在所述上拉控制节点PUCN的控制下控制所述上拉节点PU的电位维持为低电平，下拉节点控制单元11在所述上拉节点PU的控制下控制所述下拉节点PD的电位为高电平，所述起始信号输出单元15在所述上拉节点PU和所述下拉节点PD的控制下控制所述起始信号输出端STV_OUT输出低电平。
具体的，所述下拉节点控制单元可以包括：第一下拉节点控制晶体管，栅极与所述上拉节点连接，第一极与下拉控制节点连接，第二极与所述第二电平 输入端连接；第二下拉节点控制晶体管，栅极与所述上拉节点连接，第一极与所述下拉节点连接，第二极与所述第二电平输入端连接；第三下拉节点控制晶体管，栅极和第一极都与所述第一电平输入端连接，第二极与所述下拉控制节点连接；以及，第四下拉节点控制晶体管，栅极与所述下拉控制节点连接，第一极与所述第一电平输入端连接，第二极与所述下拉节点连接。
具体的，所述上拉控制节点控制单元可以包括：上拉控制晶体管，栅极和第一极都与所述第一时钟信号输入端连接，第二极与所述上拉控制节点连接；第一上拉控制节点控制晶体管，栅极与所述第二时钟信号输入端连接，第一极与所述上拉控制节点连接，第二极与所述第二电平输入端连接；以及，第n上拉控制节点控制晶体管，栅极与所述第2n时钟信号输入端连接，第一极与所述上拉控制节点连接，第二极与所述第二电平输入端连接。
具体的，所述上拉节点控制单元可以包括：第一上拉节点控制晶体管，栅极与所述上拉控制节点连接，第一极与所述第一电平输入端连接，第二极与所述上拉节点连接；第二上拉节点控制晶体管，栅极与所述下拉节点连接，第一极与所述上拉节点连接，第二极与所述第二电平输入端连接；以及，第三上拉节点控制晶体管，栅极与所述第二时钟信号输入端连接，第一极与所述上拉节点连接，第二极与所述第二电平输入端连接。
具体的，所述起始信号输出单元可以包括：第一起始信号输出晶体管，栅极与所述上拉节点连接，第一极与所述第一电平输入端连接，第二极与所述起始信号输出端连接；第二起始信号输出晶体管，栅极与所述下拉节点连接，第一极与所述起始信号输出端连接，第二极与所述第二电平输入端连接；以及，第三起始信号输出晶体管，栅极与所述第二时钟信号输入端连接，第一极与所述起始信号输出端连接，第二极与所述第二电平输入端连接。
下面通过一具体实施例来说明本公开所述的起始信号生成单元。
如图5所示，本公开所述的起始信号生成单元的一具体实施例包括下拉节点控制单元、上拉控制节点控制单元、上拉节点控制单元、存储单元和起始信号输出单元。
所述下拉节点控制单元包括：第一下拉节点控制晶体管MDC1，栅极与所述上拉节点PU连接，漏极与下拉控制节点PDCN连接，源极与低电平输 入端VSS连接；第二下拉节点控制晶体管MDC2，栅极与所述上拉节点PU连接，漏极与所述下拉节点PD连接，源极与低电平输入端VSS连接；第三下拉节点控制晶体管MDC3，栅极和漏极都与高电平输入端VGH连接，源极与所述下拉控制节点PDCN连接；以及，第四下拉节点控制晶体管MDC4，栅极与所述下拉控制节点PDCN连接，漏极与高电平输入端VGH连接，源极与所述下拉节点PD连接。
所述上拉控制节点控制单元可以包括：上拉控制晶体管M120，栅极和漏极都与所述第一时钟信号输入端CLK1连接，源极与所述上拉控制节点PUCN连接；第一上拉控制节点控制晶体管M121，栅极与所述第二时钟信号输入端CLK2连接，漏极与所述上拉控制节点PUCN连接，源极与低电平输入端VSS连接；第二上拉控制节点控制晶体管M122，栅极与所述第四时钟信号输入端CLK4连接，漏极与所述上拉控制节点PUCN连接，源极与低电平输入端VSS连接；以及，第三上拉控制节点控制晶体管M123，栅极与所述第六时钟信号输入端CLK6连接，漏极与所述上拉控制节点PUCN连接，源极与低电平输入端VSS连接。
所述上拉节点控制单元包括：第一上拉节点控制晶体管MUC1，栅极与所述上拉控制节点PUCN连接，漏极与高电平输入端VGH连接，源极与所述上拉节点PU连接；第二上拉节点控制晶体管MUC2，栅极与所述下拉节点PD连接，漏极与所述上拉节点PU连接，源极与低电平输入端VSS连接；以及，第三上拉节点控制晶体管MUC3，栅极与所述第二时钟信号输入端CLK2连接，漏极与所述上拉节点PU连接，源极与低电平输入端VSS连接；
所述起始信号输出单元包括：第一起始信号输出晶体管MO1，栅极与所述上拉节点PU连接，漏极与高电平输入端VGH连接，源极与所述起始信号输出端STV_OUT连接；第二起始信号输出晶体管MO2，栅极与所述下拉节点PD连接，漏极与所述起始信号输出端STV_OUT连接，源极与低电平输入端VSS连接；以及，第三起始信号输出晶体管MO3，栅极与所述第二时钟信号输入端CLK2连接，漏极与所述起始信号输出端STV_OUT连接，源极与低电平输入端VSS连接；所述存储单元包括：存储电容C1，连接于上拉节点PU与起始信号输出端STV_OUT之间。
在如图5所示的具体实施例中，所有的晶体管都为n型晶体管，在一些可选的实施例中，该晶体管也可以为p型晶体管，仅需将各时钟信号的时序反相，并将第一电平设置为低电平，将第二电平设置为高电平即可。
如图4所示，本公开如图5所示的起始信号生成电路的具体实施例在工作时，在CLK1输入高电平之前，MDC3和MDC4开启，PDCN的电位和PD的电位为高电平，MU2和MO2开启，PU的电位为低电平，STV_OUT输出低电平；当CLK1输入高电平，CLK2、CLK4和CLK6都输入低电平时，M120和MU1都开启，PU的电位变为高电平，MDC1和MDC2都开启，PDCN的电位和PD的电位都变为低电平，MO1开启，STV_OUT输出高电平；STV_OUT开始输出高电平的时间为一帧开启的时间；当CLK2输入高电平时，M121、MU3和MO3都开启，PUCN的电位、PU的电位都为低电平，STV_OUT输出低电平，MDC1和MDC2都关闭，PD的电位恢复为高电平，继续对PU和STV_OUT进行复位，防止STV_OUT输出高电平；当CLK4输入高电平时，M122开启，对PUCN的电位进行拉低，防止CLK1输入高电平时开启MU1，从而使得STV_OUT输出低电平；当CLK6输入高电平时，M123开启，对PUCN的电位进行拉低，防止CLK1输入高电平时开启MU1，从而使得STV_OUT输出低电平；到下一帧显示开始时，重复上述时序。
由上可知，只有在CLK1输入高电平，而CLK2、CLK4和CLK6都输入低电平时，STV_OUT输出的起始信号的电位才会为高电平，即每一帧开启的时间；当起始信号为高电平时，接入该起始信号的GOA电路包括的第一行GOA单元的上拉节点PU的电位被拉高，保证GOA电路正常输出。值得注意的是，第一行GOA单元接入的第一时钟信号和第一行GOA单元中的上拉节点PU的电位同时变为高电平，第一行GOA单元输出的栅极驱动信号维持为高电平的时间会增加，但不会影响后面行GOA单元的正常输出，在一些可选的实施例中，可以将第一行GOA单元设置为Dummy(伪)GOA单元，也即第一行GOA单元并不驱动栅线。
本公开实施例所述的起始信号生成电路的驱动方法，应用于上述的起始信号生成电路，所述起始信号生成电路用于为GOA电路提供起始信号，所述GOA电路分别与2N个时钟信号输入端、第一电平输入端和第二电平输入端 连接，N为大于1的整数；所述驱动方法包括以下步骤。
当第一时钟信号输入端输入第一电平并第二时钟信号输入端和第2n时钟信号输入端都输入第二电平时，上拉控制节点控制单元控制上拉控制节点与所述第一时钟信号输入端连接，上拉节点控制单元在所述上拉控制节点的控制下控制上拉节点的电位为第一电平；在所述上拉节点的控制下，下拉节点控制单元控制下拉节点的电位为第二电平；起始信号输出单元在所述上拉节点和所述下拉节点的控制下控制起始信号输出端输出第一电平；
当第二时钟信号输入端输入第一电平时，所述上拉控制节点控制单元控制所述上拉控制节点与所述第二电平输入端连接，上拉节点控制单元在所述上拉控制节点和所述第二时钟信号输入端的控制下控制所述上拉节点的电位为第二电平，下拉节点控制单元在所述上拉节点的控制下控制所述下拉节点的电位为第一电平，所述起始信号输出单元在所述上拉节点和所述下拉节点的控制下控制所述起始信号输出端输出第二电平；
当第2n时钟信号输入端输入第一电平时，所述上拉控制节点控制单元继续控制所述上拉控制节点与所述第二电平输入端连接，上拉节点控制单元在所述上拉控制节点的控制下控制所述上拉节点的电位维持为第二电平，下拉节点控制单元在所述上拉节点的控制下控制所述下拉节点的电位为第一电平，所述起始信号输出单元在所述上拉节点和所述下拉节点的控制下控制所述起始信号输出端输出第二电平。
其中，n为大于1而小于等于N的整数。
本公开实施例所述的栅极驱动装置，包括GOA电路，还包括上述的起始信号生成电路；所述起始信号生成电路与所述GOA电路连接，用于为所述GOA电路提供起始信号。
以上所述是本公开的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (10)

  1. 一种起始信号生成电路，用于为GOA电路提供起始信号，所述GOA电路分别与2N个时钟信号输入端、第一电平输入端和第二电平输入端连接，N为大于1的整数，其中，所述起始信号生成电路包括：
    下拉节点控制单元，分别与下拉节点和上拉节点连接，用于在所述上拉节点的控制下控制所述下拉节点的电位；
    上拉控制节点控制单元，分别与第一时钟信号输入端、第二时钟信号输入端和第2n时钟信号输入端和上拉控制节点连接，用于在所述第一时钟信号输入端、第二时钟信号输入端和第2n时钟信号输入端的控制下控制所述上拉控制节点的电位；
    上拉节点控制单元，分别与所述上拉节点、所述上拉控制节点、所述下拉节点和所述第二时钟信号输入端连接，用于在所述上拉控制节点、所述下拉节点和所述第二时钟信号输入端的控制下，控制所述上拉节点的电位；
    存储单元，连接于所述上拉节点与起始信号输出端之间；以及，
    起始信号输出单元，分别与所述上拉节点、所述下拉节点、所述第二时钟信号输入端、起始信号输出端、所述第一电平输入端和所述第二电平输入端连接，用于在所述上拉节点、所述下拉节点和所述第二时钟信号输入端的控制下，控制所述起始信号输出端与所述第一电平输入端连接或控制所述起始信号输出端与所述第二电平输入端连接；
    n为大于1而小于等于N的整数。
  2. 如权利要求1所述的起始信号生成电路，其中，在每一帧显示时间段内，每个时钟信号输入端输入的时钟信号的周期T相等，相邻后一个时钟信号比相邻前一个时钟信号周期延迟T/2N。
  3. 如权利要求1或2所述的起始信号生成电路，其中，所述下拉节点控制单元还分别与第一电平输入端和第二电平输入端连接，具体用于当所述上拉节点的电位为第一电平时控制所述下拉节点与第二电平输入端连接，当所述上拉节点的电位为第二电平时控制所述下拉节点与所述第一电平输入端连接；
    所述上拉控制节点控制单元还与所述第二电平输入端连接，具体用于在第一时钟信号输入端输入第一电平而第二时钟信号输入端和第2n时钟信号输入端都输入第二电平时控制所述上拉控制节点与所述第一时钟信号输入端连接，并用于当所述第二时钟信号输入端输入第一电平和/或第2n时钟信号输入端输入第一电平时控制所述上拉控制节点与所述第二电平输入端连接。
  4. 如权利要求3所述的起始信号生成电路，其中，所述下拉节点控制单元包括：
    第一下拉节点控制晶体管，栅极与所述上拉节点连接，第一极与下拉控制节点连接，第二极与所述第二电平输入端连接；
    第二下拉节点控制晶体管，栅极与所述上拉节点连接，第一极与所述下拉节点连接，第二极与所述第二电平输入端连接；
    第三下拉节点控制晶体管，栅极和第一极都与所述第一电平输入端连接，第二极与所述下拉控制节点连接；以及，
    第四下拉节点控制晶体管，栅极与所述下拉控制节点连接，第一极与所述第一电平输入端连接，第二极与所述下拉节点连接。
  5. 如权利要求3所述的起始信号生成电路，其中，所述上拉控制节点控制单元包括：
    上拉控制晶体管，栅极和第一极都与所述第一时钟信号输入端连接，第二极与所述上拉控制节点连接；
    第一上拉控制节点控制晶体管，栅极与所述第二时钟信号输入端连接，第一极与所述上拉控制节点连接，第二极与所述第二电平输入端连接；以及，
    第n上拉控制节点控制晶体管，栅极与所述第2n时钟信号输入端连接，第一极与所述上拉控制节点连接，第二极与所述第二电平输入端连接。
  6. 如权利要求1或2所述的起始信号生成电路，其中，所述上拉节点控制单元还分别与所述第一电平输入端和所述第二电平输入端连接，具体用于当所述上拉控制节点的电位为第一电平时控制所述上拉节点与所述第一电平输入端连接，并所述下拉节点的电位为第一电平和/或所述第二时钟信号输入端输入第一电平时控制所述上拉节点与所述第二电平输入端连接；
    所述起始信号输出单元具体用于当所述上拉节点的电位为第一电平时控 制所述起始信号输出端与所述第一电平输入端连接，并当所述下拉节点的电位为第一电平和/或所述第二时钟信号输入端输入第一电平时控制所述起始信号输出端与所述第二电平输入端连接。
  7. 如权利要求6所述的起始信号生成电路，其中，所述上拉节点控制单元包括：
    第一上拉节点控制晶体管，栅极与所述上拉控制节点连接，第一极与所述第一电平输入端连接，第二极与所述上拉节点连接；
    第二上拉节点控制晶体管，栅极与所述下拉节点连接，第一极与所述上拉节点连接，第二极与所述第二电平输入端连接；以及，
    第三上拉节点控制晶体管，栅极与所述第二时钟信号输入端连接，第一极与所述上拉节点连接，第二极与所述第二电平输入端连接。
  8. 如权利要求6所述的起始信号生成电路，其中，所述起始信号输出单元包括：
    第一起始信号输出晶体管，栅极与所述上拉节点连接，第一极与所述第一电平输入端连接，第二极与所述起始信号输出端连接；
    第二起始信号输出晶体管，栅极与所述下拉节点连接，第一极与所述起始信号输出端连接，第二极与所述第二电平输入端连接；以及，
    第三起始信号输出晶体管，栅极与所述第二时钟信号输入端连接，第一极与所述起始信号输出端连接，第二极与所述第二电平输入端连接。
  9. 一种起始信号生成电路的驱动方法，应用于如权利要求1至8中任一权利要求所述的起始信号生成电路，所述起始信号生成电路用于为GOA电路提供起始信号，所述GOA电路分别与2N个时钟信号输入端、第一电平输入端和第二电平输入端连接，N为大于1的整数；其中，所述驱动方法包括：
    当第一时钟信号输入端输入第一电平并第二时钟信号输入端和第2n时钟信号输入端都输入第二电平时，上拉控制节点控制单元控制上拉控制节点与所述第一时钟信号输入端连接，上拉节点控制单元在所述上拉控制节点的控制下控制上拉节点的电位为第一电平；在所述上拉节点的控制下，下拉节点控制单元控制下拉节点的电位为第二电平；起始信号输出单元在所述上拉节点和所述下拉节点的控制下控制起始信号输出端输出第一电平；
    当第二时钟信号输入端输入第一电平时，所述上拉控制节点控制单元控制所述上拉控制节点与所述第二电平输入端连接，上拉节点控制单元在所述上拉控制节点和所述第二时钟信号输入端的控制下控制所述上拉节点的电位为第二电平，下拉节点控制单元在所述上拉节点的控制下控制所述下拉节点的电位为第一电平，所述起始信号输出单元在所述上拉节点和所述下拉节点的控制下控制所述起始信号输出端输出第二电平；
    当第2n时钟信号输入端输入第一电平时，所述上拉控制节点控制单元继续控制所述上拉控制节点与所述第二电平输入端连接，上拉节点控制单元在所述上拉控制节点的控制下控制所述上拉节点的电位维持为第二电平，下拉节点控制单元在所述上拉节点的控制下控制所述下拉节点的电位为第一电平，所述起始信号输出单元在所述上拉节点和所述下拉节点的控制下控制所述起始信号输出端输出第二电平；
    n为大于1而小于等于N的整数。
  10. 一种栅极驱动装置，包括GOA电路以及如权利要求1至8中任一权利要求所述的起始信号生成电路；
    所述起始信号生成电路与所述GOA电路连接，用于为所述GOA电路提供起始信号。
PCT/CN2018/076976 2017-03-02 2018-02-22 起始信号生成电路、驱动方法和显示装置 WO2018157751A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US16/077,992 US11158224B2 (en) 2017-03-02 2018-02-22 Start signal generation circuit, driving method and display device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201710119977.9A CN106875886B (zh) 2017-03-02 2017-03-02 起始信号生成电路、驱动方法和显示装置
CN201710119977.9 2017-03-02

Publications (1)

Publication Number Publication Date
WO2018157751A1 true WO2018157751A1 (zh) 2018-09-07

Family

ID=59168426

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2018/076976 WO2018157751A1 (zh) 2017-03-02 2018-02-22 起始信号生成电路、驱动方法和显示装置

Country Status (3)

Country Link
US (1) US11158224B2 (zh)
CN (1) CN106875886B (zh)
WO (1) WO2018157751A1 (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106875886B (zh) 2017-03-02 2019-11-12 京东方科技集团股份有限公司 起始信号生成电路、驱动方法和显示装置
CN112820237B (zh) * 2019-10-31 2022-08-26 京东方科技集团股份有限公司 电子基板及其驱动方法、显示装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140198023A1 (en) * 2013-01-14 2014-07-17 Novatek Microelectronics Corp. Gate driver on array and method for driving gate lines of display panel
US20140346520A1 (en) * 2013-05-27 2014-11-27 Samsung Display Co., Ltd. Gate driver and display apparatus having the same
CN104882111A (zh) * 2015-06-24 2015-09-02 京东方科技集团股份有限公司 一种显示驱动电路及其驱动方法、显示装置
CN105609135A (zh) * 2015-12-31 2016-05-25 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路和显示装置
CN106875886A (zh) * 2017-03-02 2017-06-20 京东方科技集团股份有限公司 起始信号生成电路、驱动方法和显示装置

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101783124B (zh) * 2010-02-08 2013-05-08 北京大学深圳研究生院 栅极驱动电路单元、栅极驱动电路及显示装置
CN103714780B (zh) * 2013-12-24 2015-07-15 京东方科技集团股份有限公司 栅极驱动电路、方法、阵列基板行驱动电路和显示装置
CN103730094B (zh) * 2013-12-30 2016-02-24 深圳市华星光电技术有限公司 Goa电路结构
CN104036714B (zh) * 2014-05-26 2017-02-01 京东方科技集团股份有限公司 Goa电路、显示基板及显示装置
CN104282288B (zh) * 2014-11-07 2016-08-17 京东方科技集团股份有限公司 移位寄存器单元以及使用它的栅极驱动电路和显示设备
CN104332146B (zh) * 2014-11-12 2016-09-28 合肥鑫晟光电科技有限公司 移位寄存器单元、移位寄存器、栅极驱动电路和显示装置
CN104575354B (zh) * 2014-12-31 2017-02-22 上海天马微电子有限公司 一种栅极驱动电路及其驱动方法
CN105489180B (zh) * 2016-01-04 2018-06-01 武汉华星光电技术有限公司 Goa电路
CN105427825B (zh) * 2016-01-05 2018-02-16 京东方科技集团股份有限公司 一种移位寄存器、其驱动方法及栅极驱动电路
CN105551421B (zh) * 2016-03-02 2019-08-02 京东方科技集团股份有限公司 移位寄存器单元、驱动方法、栅极驱动电路和显示装置
US10360866B2 (en) * 2017-08-14 2019-07-23 Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. GOA circuit and liquid crystal display device
CN107507591B (zh) * 2017-09-04 2019-03-15 深圳市华星光电半导体显示技术有限公司 一种扫描驱动电路以及液晶显示器

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140198023A1 (en) * 2013-01-14 2014-07-17 Novatek Microelectronics Corp. Gate driver on array and method for driving gate lines of display panel
US20140346520A1 (en) * 2013-05-27 2014-11-27 Samsung Display Co., Ltd. Gate driver and display apparatus having the same
CN104882111A (zh) * 2015-06-24 2015-09-02 京东方科技集团股份有限公司 一种显示驱动电路及其驱动方法、显示装置
CN105609135A (zh) * 2015-12-31 2016-05-25 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路和显示装置
CN106875886A (zh) * 2017-03-02 2017-06-20 京东方科技集团股份有限公司 起始信号生成电路、驱动方法和显示装置

Also Published As

Publication number Publication date
CN106875886A (zh) 2017-06-20
US11158224B2 (en) 2021-10-26
CN106875886B (zh) 2019-11-12
US20210272492A1 (en) 2021-09-02

Similar Documents

Publication Publication Date Title
US9791968B2 (en) Shift register, its driving method, gate driver circuit and display device
US10930360B2 (en) Shift register, driving method thereof, gate driving circuit, and display device
US10540923B2 (en) Shift register, method for driving same, gate driving circuit
WO2017211149A1 (zh) 移位寄存器及其驱动方法、栅极驱动装置
US10566071B2 (en) Shift register unit, method for driving shift register unit, gate driving circuit and display device
TWI514362B (zh) 移位暫存器模組及驅動其之方法
US10923207B2 (en) Shift register unit and method for driving the same, gate driving circuit and display apparatus
KR102383363B1 (ko) 게이트 구동 회로 및 이를 포함하는 표시 장치
WO2015109769A1 (zh) 移位寄存器单元、栅极驱动电路及其驱动方法、显示装置
KR102448227B1 (ko) 게이트 구동 회로 및 이를 포함하는 표시 장치
WO2016058351A1 (zh) 显示电路及其驱动方法和显示装置
WO2020168798A1 (zh) 移位寄存器单元及其驱动方法、栅极驱动电路及其驱动方法和显示装置
CN107068033B (zh) 移位寄存器单元、栅极驱动电路、测试方法及显示装置
TWI505276B (zh) 移位暫存電路及移位暫存器
WO2018126691A1 (zh) 移位寄存器单元及其驱动方法、移位寄存器以及显示装置
WO2020098309A1 (zh) 移位寄存器及其驱动方法、栅极驱动电路、阵列基板及显示装置
JP2013214088A (ja) 走査信号線駆動回路およびそれを備えた表示装置
KR20160051675A (ko) 시프트 레지스터 유닛, 시프트 레지스터, 게이트 드라이버 회로 및 디스플레이 장치
KR20140141190A (ko) 스테이지 회로 및 이를 이용한 주사 구동부
WO2020001625A1 (zh) 漂移控制模块、漂移控制方法、栅极驱动单元、栅极驱动方法和显示装置
US20150091822A1 (en) Gate driving circuit, gate line driving method and display apparatus
TW201027502A (en) Gate driver and display driver using thereof
WO2020082956A1 (zh) 移位寄存器单元及其驱动方法、栅极驱动电路和显示装置
WO2020133823A1 (zh) Goa电路
WO2018228042A1 (zh) 移位寄存器单元、驱动方法、栅极驱动电路和显示装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18761948

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 13.02.2020)

122 Ep: pct application non-entry in european phase

Ref document number: 18761948

Country of ref document: EP

Kind code of ref document: A1