WO2018126785A1 - 电荷释放电路、显示基板、显示装置及其电荷释放方法 - Google Patents

电荷释放电路、显示基板、显示装置及其电荷释放方法 Download PDF

Info

Publication number
WO2018126785A1
WO2018126785A1 PCT/CN2017/109965 CN2017109965W WO2018126785A1 WO 2018126785 A1 WO2018126785 A1 WO 2018126785A1 CN 2017109965 W CN2017109965 W CN 2017109965W WO 2018126785 A1 WO2018126785 A1 WO 2018126785A1
Authority
WO
WIPO (PCT)
Prior art keywords
conductor
line
charge release
charge
transistors
Prior art date
Application number
PCT/CN2017/109965
Other languages
English (en)
French (fr)
Inventor
程鸿飞
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to MX2018012047A priority Critical patent/MX2018012047A/es
Priority to AU2017391552A priority patent/AU2017391552C9/en
Priority to US16/065,492 priority patent/US11238820B2/en
Priority to EP17882277.1A priority patent/EP3567577A4/en
Priority to RU2018134593A priority patent/RU2732990C1/ru
Priority to JP2018548389A priority patent/JP7195928B2/ja
Priority to KR1020187028345A priority patent/KR102096993B1/ko
Priority to BR112018069452A priority patent/BR112018069452A2/pt
Publication of WO2018126785A1 publication Critical patent/WO2018126785A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0245—Clearing or presetting the whole screen independently of waveforms, e.g. on power-on
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G09G2310/063—Waveforms for resetting the whole screen at once
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0238—Improving the black level
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0257—Reduction of after-image effects
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/027—Arrangements or methods related to powering off a display

Definitions

  • An example of the present disclosure relates to a charge release circuit, a display substrate, a display device, and a charge release method thereof.
  • the liquid crystal display panel includes a color film substrate and an array substrate disposed opposite to each other, and a liquid crystal between the color filter substrate and the array substrate.
  • a common electrode is formed on the base substrate of the color filter substrate; a plurality of laterally arranged gate lines and a plurality of longitudinally arranged data lines are formed on the base substrate of the array substrate, and the gate lines and the data lines are formed to intersect.
  • the thin film transistor includes a gate connected to the gate line, a source connected to the data line, and a drain connected to the pixel electrode.
  • a voltage-conducting thin film transistor may be applied to the gate through the gate line, a pixel voltage is applied to the pixel electrode through the data line, the source and the drain, and a common voltage is applied to the common electrode, and the liquid crystal is at the pixel voltage. And deflecting under the action of the common voltage, so that the display panel displays an image.
  • An example of the present disclosure provides a charge release circuit, a display substrate, a display device, and a charge release method thereof.
  • At least one example of the present disclosure provides a charge release circuit including: a controller, a charge release sub-circuit, and a first conductor, the charge release sub-circuit and the controller, the first conductor, and the array base, respectively a second conductor in an effective display area of the board is coupled; the charge release sub-circuit is configured to conduct the first conductor and the second conductor under control of the controller to cause the second The charge on the conductor moves toward the first conductor.
  • the second conductor includes: at least one gate line
  • the controller includes: a first control line
  • the charge release sub-circuit including: a first charge release unit; a first charge release unit is respectively connected to the at least one gate line, the first control line, and the first conductor, and the first charge release unit is configured to be based on a control signal on the first control line And conducting the first conductor and the at least one gate line.
  • the second conductor includes a plurality of gate lines
  • the first charge release unit includes a plurality of first transistors
  • the first control line is perpendicular to the gate lines.
  • the plurality of first transistors are in one-to-one correspondence with the plurality of gate lines; the gates of each of the first transistors are connected to the first control line, and the first poles of each of the first transistors are One of the plurality of gate lines is connected, and a second pole of each of the first transistors is connected to the first conductor.
  • the second conductor includes at least one data line
  • the controller includes a second control line
  • the charge release sub-circuit includes a second charge release unit; a release unit is respectively connected to the at least one data line, the second control line, and the first conductor, and the second charge release unit is configured to be turned on according to a control signal on the second control line The first conductor and the at least one data line.
  • the second conductor includes a plurality of data lines
  • the second charge release unit includes a plurality of second transistors
  • the second control line is perpendicular to the data line
  • the plurality of second transistors are in one-to-one correspondence with the plurality of data lines; the gates of each of the second transistors are connected to the second control line, and the first poles of each of the second transistors are One of the plurality of data lines is connected, and a second pole of each of the second transistors is connected to the first conductor.
  • the second conductor further includes at least one pixel electrode
  • the controller further includes a third control line
  • the charge release sub-circuit further includes a third charge release unit; a third charge release unit is respectively connected to the gate line in the array substrate and the third control line, the third charge release unit being configured to write a control signal on the third control line into the a gate line electrically connecting each of the pixel electrodes and the pixel electrode Data line.
  • the third charge release unit includes a plurality of third transistors, the plurality of third transistors respectively corresponding to a plurality of gate lines in the array substrate, the
  • the second conductor includes: a plurality of pixel electrodes connected to each of the gate lines, the third control line is perpendicular to the gate lines, and a gate and a first pole of each of the third transistors are The third control line is connected, and the second pole of each of the third transistors is connected to one of the plurality of gate lines.
  • a charge release circuit according to an example of the present disclosure, wherein a volume of the first conductor is greater than a volume of the second conductor.
  • the first conductor is a common electrode line or a storage electrode line.
  • At least one example of the present disclosure provides a display substrate comprising: any of the above-described charge release circuits.
  • At least one example of the present disclosure also provides a display device including a display panel including any of the above display substrates.
  • At least one example of the present disclosure also provides a charge release method of any of the above display devices, including:
  • the first conductor is a common electrode line or a storage electrode line
  • the second conductor includes at least one of a gate line, a data line, or a pixel electrode.
  • a volume of the first conductor is greater than a volume of the second conductor.
  • FIG. 1 is a schematic structural diagram of a charge release circuit according to an example of the present disclosure
  • 2A is a schematic structural view of an array substrate
  • 2B is a schematic structural view of another array substrate
  • FIG. 3 is a schematic structural diagram of another charge release circuit according to an example of the present disclosure.
  • FIG. 4 is a schematic structural diagram of still another charge release circuit according to an example of the present disclosure.
  • FIG. 5 is a schematic structural diagram of still another charge release circuit according to an example of the present disclosure.
  • FIG. 6 is a schematic structural diagram of a charge release circuit according to another example of the present disclosure.
  • FIG. 7 is a schematic structural diagram of another charge release circuit according to another example of the present disclosure.
  • some of the conductors (such as the gate lines and the data lines) in the effective display area of the array substrate may have residual charges on the voltage applied at the previous moment, so that some liquid crystals still deflect.
  • the display panel in a black screen displays a bright spot.
  • the transistors employed in all of the examples of the present disclosure may be thin film transistors or field effect transistors or other devices having the same characteristics, and the transistors employed in the examples of the present disclosure are mainly switching transistors according to the role in the circuit. Since the source and drain of the switching transistor used here are symmetrical, the source and the drain are interchangeable. In the example of the present disclosure, in order to distinguish the two transistors except the gate In the pole, the source is referred to as the first pole and the drain is referred to as the second pole. According to the form in the drawing, the middle end of the transistor is the gate, the signal input end is the source, and the signal output end is the drain.
  • the switching transistor employed in the example of the present disclosure includes at least one of a P-type switching transistor and an N-type switching transistor, wherein the P-type switching transistor is turned on when the gate is at a low level, and is turned off when the gate is at a high level, and the N-type switch is turned off. The transistor is turned on when the gate is at a high level and turned off when the gate is at a low level.
  • the charge release circuit 0 may include: a controller 01, a charge release sub-circuit 02, and a first conductor 03, and charge release.
  • the sub-circuit 02 is connected to the controller 01, the first conductor 03, and the second conductor A in the effective display area of the array substrate, respectively.
  • the controller 01 can be a control module
  • the charge release sub-circuit 02 can be a charge release module.
  • the charge release sub-circuit 02 is configured to turn on the first conductor 03 and the second conductor A under the control of the controller 01 to move the charge on the second conductor A toward the first conductor 03.
  • the first conductor 03 can be grounded.
  • the charge release sub-circuit 02 is connected to the controller 01 and the first conductor 03, respectively, and the charge release sub-circuit 02 is configured to be turned on under the action of the controller 01.
  • the first conductor 03 and the array substrate effectively display the second conductor A of the region such that the charge on the second conductor A can be moved onto the first conductor 03, thereby reducing the second conductor A in the effective display region of the array substrate
  • the charge reduces the probability of liquid crystal deflection when the display panel is in a black screen state, and reduces the number of bright spots on the display panel in a black screen state.
  • the array substrate 1 may include a base substrate 100.
  • the effective display area Y of the base substrate 100 is formed with a plurality of gate lines A1 and a plurality of data lines.
  • the plurality of gate lines A1 and the plurality of data lines A2 are insulated from each other and intersect to form a plurality of pixel regions, and each of the pixel regions is formed with a transistor A4 and a pixel electrode A3, and the gate of the transistor A4 is enclosed
  • the gate line A1 of the pixel region is connected, the source of the transistor A4 is connected to the data line A2 surrounding the pixel region, and the drain of the transistor A4 is connected to the pixel electrode A3 in the pixel region.
  • the first common electrode line 031 and the second common electrode line 032 are formed in the ineffective display region (ie, the edge region) of the base substrate 100.
  • the first common electrode line 031 is perpendicular to the gate line A1, and the second common electrode line 032 is perpendicular to the data line A2.
  • the first common electrode line 031 is insulated from the gate line A1, and the second common electrode line 032 is insulated from the data line A2.
  • the data line is configured to input a data signal to the pixel, the data signal including, for example, a gray scale voltage.
  • the grid The line is configured to input a gate signal to the transistor, the gate signal including, for example, a gate voltage.
  • a plurality of storage electrode lines A0 may be formed, and each of the storage electrode lines A0 may pass through a row of pixel regions and be disposed in parallel with the gate line A1.
  • the transistors A4 are arranged in an array, each gate line is connected to a row of transistors A4, each data line is connected to a column of transistors A4, and each pixel electrode is connected to one transistor A4.
  • the pixel electrode corresponding to each gate line is a pixel electrode connected to the gate line through the transistor A4.
  • the data line corresponding to each pixel electrode is a data line connected to the pixel electrode through the transistor A4.
  • the volume of the first conductor 03 may be greater than the volume of the second conductor A.
  • the amount of electric charge that the first conductor 03 can carry is also large, and therefore, the first conductor 03 can share a large amount of electric charge for the second conductor A.
  • the line width of the first conductor 03 may be greater than the line width of the second conductor A such that the amount of charge that the first conductor 03 can carry is large.
  • the array substrate may include a base substrate on which a plurality of wires may be formed, wherein the common electrode lines and the storage electrode lines are wider, and other wires (such as gate lines and data lines) are narrower, first
  • the conductor 03 may be a common electrode line or a storage electrode line on the array substrate
  • the second conductor A may be any conductor in the effective display area of the array substrate.
  • the second conductor A may be a gate line, a data line or a pixel electrode.
  • the charge release circuit provided by the example of the present disclosure will be explained below by taking the first conductor as a common electrode line on the array substrate and the second conductor as a gate line, a data line and a pixel electrode on the array substrate, respectively.
  • the second conductor may include: at least one gate line
  • the controller may include: a first control line
  • the charge release sub-circuit may include: a first charge release unit; the first charge release unit and the at least one gate line, respectively The first control line and the first conductor are connected, and the first charge release unit is configured to turn on the first conductor and the at least one gate line according to a control signal on the first control line.
  • FIG. 3 is a schematic structural diagram of a charge release circuit 0 according to an example of the present disclosure.
  • the second conductor may include: a plurality of gate lines A1
  • the first charge release unit 021 may include: a plurality of first transistors. 0211, the plurality of first transistors 0211 are in one-to-one correspondence with the plurality of gate lines A1.
  • the gate G of each of the first transistors 0211 is connected to the first control line 011, and the first pole J1 of each of the first transistors 0211 is connected to the corresponding gate line A1, and the second pole J2 of each of the first transistors 0211
  • the first common electrode line 031 perpendicular to the gate line A1 is connected, wherein the first control line 011 is perpendicular to the gate line A1.
  • the first control line 011 and each gate line A1 are insulated from each other.
  • a control signal may be input to the first control line 011 such that each of the plurality of first transistors 0211 is in an on state (ie, each first transistor)
  • the first pole J1 and the second pole J2 in the 0211 are in a connected state), so that each of the first transistors 0211 turns on the connected gate line A1 and the first common electrode line 031, and at this time, if the gate line A1 is on
  • the residual charge can flow to the first common electrode line 031, thereby reducing the charge on the gate line A1.
  • the first conductor for sharing the charge on the second conductor is the first common electrode line. 031.
  • the charge on the gate line is less, thereby preventing the liquid crystal from being deflected under the action of the voltage, preventing the display panel from displaying bright spots, and solving the problem that the display panel in the black screen state displays the bright spot.
  • the second conductor may include: at least one data line
  • the controller may include: a second control line
  • the charge release sub-circuit may include: a second charge release unit
  • the second charge release unit may be respectively connected to the at least one data line
  • the second control line and the first conductor are connected, and the second charge release unit is configured to turn on the first conductor and the at least one data line according to a control signal on the second control line.
  • FIG. 4 is a schematic structural diagram of still another charge release circuit 0 according to an example of the present disclosure.
  • at least one data line in the second conductor may include: a plurality of data lines A2, and the second charge release unit 022 may The method includes a plurality of second transistors 0221, and the plurality of second transistors 0221 can be in one-to-one correspondence with the plurality of data lines A2; the gates G of each of the second transistors 0221 are connected to the second control line 012, and each of the second transistors
  • the first pole J1 of 0221 is connected to the corresponding data line A2, and the second pole J2 of each second transistor 0221 is connected to the second common electrode line 032 which is perpendicular to the data line A2.
  • the second control line 012 can be perpendicular to the data line A2.
  • a control signal may be input to the second control line 012 such that each of the second transistors 0221 is in an on state, so that each of the second transistors 0221 will be connected to the data line A2.
  • the second common electrode line 032 is turned on. At this time, if a charge remains on the data line A2, the residual charge can flow to the second common electrode line 032, thereby reducing the charge on the data line A2.
  • the first conductor for sharing the charge on the second conductor is the second common electrode line 032. After the display panel is in a black screen state, the charge on the data line is less, thereby preventing the liquid crystal from being deflected by the voltage and preventing the display panel from displaying bright spots.
  • the second conductor may further include: at least one pixel electrode
  • the controller may further include: a third control line
  • the charge release sub-circuit further comprising: a third charge release unit
  • the three charge release units may be respectively connected to the gate lines in the array substrate and the third control line, and the third charge release unit is configured to write the control signals on the third control line to the gate lines, and turn on the pixel electrodes and the pixel electrodes Corresponding data line.
  • FIG. 5 is a schematic structural diagram of still another charge release circuit 0 according to an example of the present disclosure.
  • the charge release sub-circuit may further include: a third charge release unit 023, a third charge
  • the release unit 023 may include: a plurality of third transistors 0231 respectively corresponding to the plurality of gate lines A1 in the array substrate, and at least one of the second conductors may include: each gate line A plurality of pixel electrodes A3 corresponding to A1, a gate G and a first pole J1 of each third transistor 0231 are connected to a third control line 013, and a second pole J2 of each third transistor 0231 is connected to the third transistor
  • the gate line A1 corresponding to 0231 is connected, and the third control line 013 may be perpendicular to the gate line A1.
  • a control signal may also be input to the third control line 013, so that each of the third transistors 0231 is in an on state, so that the control signal on the third control line 013 is along the third transistor.
  • the first pole and the second pole of 0231 are input to the gate line A1 corresponding to the third transistor 0231, and the transistor in the pixel region connected to the gate line A1 is turned on, so that the pixel electrode A3 corresponding to the gate line A1 is The data line A2 corresponding to the pixel electrode A3 is turned on.
  • each of the second transistors 0221 is in an on state, so that each of the second transistors 0221 will be connected to the data line A2 and the second common electrode line 032.
  • the first conductor for sharing the charge on the second conductor is the second common electrode line 032.
  • FIG. 6 is a schematic structural diagram of a charge release circuit 0 according to another example of the present disclosure.
  • the second conductor includes a plurality of gate lines A1 and a plurality of data lines A2 on the array substrate.
  • the charge release circuit 0 may include a plurality of first transistors 0211, a plurality of second transistors 0221, a first control line 011, a second control line 012, a first common electrode line 031, and a second common electrode line. 032.
  • first common electrode line 031 is perpendicular to the gate line A1 and parallel to the data line A2, and the first control line 011 is parallel to the first common electrode line 031.
  • the second common electrode line 032 is perpendicular to the data line A2 and parallel to the gate line A1, and the second control line 012 is parallel to the second common electrode line 032.
  • the plurality of first transistors 0211 are in one-to-one correspondence with the plurality of gate lines A1
  • the plurality of second transistors 0221 are in one-to-one correspondence with the plurality of data lines A2.
  • each of the first transistors 0211 is connected to the first control line 011, and the first pole of each of the first transistors 0211 is connected to the gate line A1 corresponding to the first transistor, and the first transistor of each of the first transistors 0211 The two poles are all connected to the first common electrode line 031.
  • the gate of each second transistor 0221 is connected to the second control line 012, and the first pole of each second transistor 0221 is connected to the data line A2 corresponding to the second transistor, and the second transistor 0221 The two poles are all connected to the second common electrode line 032.
  • a control signal may be input to the first control line 011 such that each of the first transistors 0211 is in an on state, so that each of the first transistors 0211 will be connected to the gate line A1.
  • the first common electrode line 031 is turned on. At this time, if a charge remains on the gate line A1, the residual charge can flow to the first common electrode line 031, thereby reducing the charge on the gate line A1.
  • the first conductor for sharing the charge on the second conductor is the first common electrode line 031 and the second common electrode line 032.
  • FIG. 7 is a schematic structural diagram of another charge release circuit 0 according to another example of the present disclosure.
  • the second conductor includes a plurality of gate lines A1 and a plurality of data lines A2 on the array substrate.
  • the charge release circuit 0 may include a plurality of first transistors 0211, a plurality of second transistors 0221, a plurality of third transistors 0231, a first control line 011, a second control line 012, and a third control Line 013, first common electrode line 031, and second common electrode line 032.
  • the first common electrode line 031 is perpendicular to the gate line A1 and parallel to the data line A2.
  • the first control line 011 and the third control line 013 are both parallel to the first common electrode line 031, and are disposed in the vicinity of the first common electrode line 031.
  • the first control line 011 is disposed near the first common electrode line 031.
  • the third control line 013 is disposed at the first common electrode line 031 away from One side of the display area.
  • the second common electrode line 032 is perpendicular to the data line A2 and is parallel to the gate line A1.
  • the second control line 012 is parallel to the second common electrode line 032 and is disposed in the vicinity of the second common electrode line 032 as disposed on the side of the second common electrode line 032 near the effective display area.
  • the plurality of first transistors 0211 are in one-to-one correspondence with the plurality of gate lines A1, the plurality of second transistors 0221 are in one-to-one correspondence with the plurality of data lines A2, and the plurality of third transistors 0231 are in one-to-one correspondence with the plurality of gate lines A1.
  • the gate of each of the first transistors 0211 is connected to the first control line 011, and the first pole of each of the first transistors 0211 is connected to the gate line A1 corresponding to the first transistor, and the first transistor of each of the first transistors 0211 The two poles are all connected to the first common electrode line 031.
  • each second transistor 0221 is connected to the second control line 012, and the first pole of each second transistor 0221 is connected to the data line A2 corresponding to the second transistor, and the second transistor 0221 The two poles are all connected to the second common electrode line 032.
  • the gate and the first pole of each of the third transistors 0231 are connected to the third control line 013, and the second pole of each of the third transistors 0231 is connected to the gate line A1 corresponding to the third transistor.
  • a control signal may be input to the first control line 011 such that each of the first transistors 0211 is in an on state, so that each of the first transistors 0211 will be connected to the gate line A1.
  • the first common electrode line 031 is turned on. At this time, if a charge remains on the gate line A1, the residual charge can flow to the first common electrode line 031, thereby reducing the charge on the gate line A1.
  • each of the second transistors 0221 is in an on state, so that each of the second transistors 0221 will be connected to the data line A2 and the second common electrode line 032.
  • the second common electrode line 032 it is also possible to input a control signal to the second control line 012 such that each of the second transistors 0221 is in an on state, so that each of the second transistors 0221 will be connected to the data line A2 and the second common electrode line 032.
  • a control signal may be input to the third control line 013, so that each of the third transistors 0231 is in an on state, so that the control signal on the third control line 013 is from the first pole and the third transistor of the third transistor 0231.
  • the two poles are input to the gate line A1 corresponding to the third transistor 0231, and the pixel electrode A3 corresponding to the gate line A1 and the data line A2 corresponding to the pixel electrode A3 are turned on.
  • the residual electric charge can flow on the data line A2 and further flow to the second common electrode line 032, thereby reducing charges on the data line A2 and the pixel electrode A3.
  • the first conductor for sharing the charge on the second conductor is the first common electrode line 031 and the second common electrode line 032.
  • the effective display area of the array substrate after the display panel is in a black screen state
  • the inner conductors (such as the gate lines, the data lines, and the pixel electrodes) have less charge, thereby preventing the liquid crystal from being deflected by the voltage and preventing the display panel from displaying bright spots.
  • members extending in the same direction may be formed in the same layer.
  • at least two of the data line A2, the first common electrode line 031, the first control line 011, and the third control line 013 may be formed in the same layer, for example, in the first layer.
  • At least two of the gate line A1, the second control line 012, and the common electrode line 032 may be formed in the same layer, for example, in the second layer.
  • an insulating layer may be disposed between the first layer and the second layer such that the intersection of the two lines is not electrically connected.
  • two components may be connected by a transistor.
  • black dots in the various figures may represent electrical connections.
  • the two lines that intersect are insulated from each other at the intersection.
  • the charge release sub-circuit is respectively connected to the controller and the first conductor, and the charge release sub-circuit is configured to be turned on by the controller.
  • the conductor and the array substrate effectively display the second conductor of the region such that the charge on the second conductor can be moved to the first conductor, thereby reducing the charge on the second conductor in the effective display area of the array substrate, reducing the display panel
  • the probability of liquid crystal deflection when in a black screen state reduces the number of bright spots on the display panel in a black screen state.
  • the present disclosure example also provides a display substrate, which may include a charge release circuit as shown in any of FIGS. 1, 3, 4, 5, 6, or 7.
  • the present disclosure further provides a display panel, which may include: a display substrate provided with a charge release circuit as shown in any of FIG. 1, FIG. 3, FIG. 4, FIG. 5, FIG. 6, or FIG. .
  • the display substrate can be an array substrate.
  • the display panel may further include a counter substrate opposite to the array substrate.
  • the counter substrate may be a color film substrate, but is not limited thereto.
  • the display substrate may also be an opposite substrate, which is not limited by the examples in the disclosure.
  • the example of the present disclosure further provides a display device, where the display device includes: a display panel, and the display substrate in the display panel may include FIG. 1, FIG. 3, FIG. 4, FIG. 5, FIG. 6, or FIG. Any of the charge release circuits shown.
  • the display device may be: a liquid crystal panel, an electronic paper, an Organic Light-Emitting Diode (OLED) panel, an active-matrix organic light emitting diode (AMOLED) panel, a mobile phone, a tablet Any product or component with display function such as computer, TV, monitor, laptop, digital photo frame, navigator, etc.
  • At least one example of the present disclosure also provides a charge release method of a display device, comprising: discharging a charge using any of the charge release circuits as described above, the method comprising: applying a control signal to a controller when the display panel is in a black screen, Under the control of the controller, the first conductor and the second conductor are turned on to move the charge on the second conductor toward the first conductor.
  • the display device when the display panel is in a black screen state, the display device is in a standby state.

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Liquid Crystal (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种电荷释放电路(0)、显示基板、显示面板及显示装置。电荷释放电路(0)包括：控制器(01)、电荷释放子电路(02)和第一导体(03)，电荷释放子电路(02)分别与控制器(01)、第一导体(03)以及阵列基板(1)的有效显示区域内的第二导体(A)相连接；电荷释放子电路(02)被配置为在控制器(01)的控制下，导通第一导体(03)和第二导体(A)，使第二导体(A)上的电荷向第一导体(03)移动。电荷释放电路(0)可解决处于黑屏状态的显示面板显示亮点的问题，减少了黑屏状态的显示面板上的亮点数量。

Description

电荷释放电路、显示基板、显示装置及其电荷释放方法
相关申请的交叉引用
本专利申请要求于2017年1月3日递交的中国专利申请第201720002380.1号的优先权，在此全文引用上述中国专利申请公开的内容以作为本公开的示例的一部分。
技术领域
本公开的示例涉及一种电荷释放电路、显示基板、显示装置及其电荷释放方法。
背景技术
液晶显示面板包括相对设置的彩膜基板和阵列基板，以及位于彩膜基板和阵列基板之间的液晶。
例如，彩膜基板的衬底基板上形成有公共电极；阵列基板的衬底基板上形成有多条横向排布的栅线和多条纵向排布的数据线，且栅线和数据线交叉形成多个像素区域，每个像素区域内形成有一个薄膜晶体管以及一个像素电极。例如，薄膜晶体管包括与栅线相连接的栅极、与数据线相连接的源极以及与像素电极相连接的漏极。在控制显示面板显示图像时，可以通过栅线向栅极施加电压导通薄膜晶体管，通过数据线、源极和漏极向像素电极施加像素电压，并向公共电极施加公共电压，液晶在像素电压以及公共电压的作用下进行偏转，使得显示面板显示图像。在无需控制显示面板显示图像时，可以停止向像素电极和公共电极施加电压，使得液晶不偏转，显示面板处于黑屏状态。
发明内容
本公开的示例提供一种电荷释放电路、显示基板、显示装置及其电荷释放方法。
本公开至少一示例提供一种电荷释放电路，包括：控制器、电荷释放子电路和第一导体，所述电荷释放子电路分别与控制器、第一导体以及阵列基 板的有效显示区域内的第二导体相连接；所述电荷释放子电路被配置为在所述控制器的控制下，导通所述第一导体和所述第二导体，使所述第二导体上的电荷向所述第一导体移动。
根据本公开一示例提供的电荷释放电路，所述第二导体包括：至少一条栅线，所述控制器包括：第一控制线，所述电荷释放子电路包括：第一电荷释放单元；所述第一电荷释放单元分别与所述至少一条栅线、所述第一控制线以及所述第一导体相连接，所述第一电荷释放单元被配置为根据所述第一控制线上的控制信号，导通所述第一导体和所述至少一条栅线。
根据本公开一示例提供的电荷释放电路，所述第二导体包括多条栅线，所述第一电荷释放单元包括多个第一晶体管，所述第一控制线垂直于所述栅线，所述多个第一晶体管与所述多条栅线一一对应；每个所述第一晶体管的栅极均与所述第一控制线连接，每个所述第一晶体管的第一极均与所述多条栅线中的一条栅线连接，每个所述第一晶体管的第二极均与所述第一导体连接。
根据本公开一示例提供的电荷释放电路，所述第二导体包括至少一条数据线，所述控制器包括第二控制线，所述电荷释放子电路包括第二电荷释放单元；所述第二电荷释放单元分别与所述至少一条数据线、所述第二控制线以及所述第一导体相连接，所述第二电荷释放单元被配置为根据所述第二控制线上的控制信号，导通所述第一导体和所述至少一条数据线。
根据本公开一示例提供的电荷释放电路，所述第二导体包括多条数据线，所述第二电荷释放单元包括多个第二晶体管，所述第二控制线垂直于所述数据线，所述多个第二晶体管与所述多条数据线一一对应；每个所述第二晶体管的栅极均与所述第二控制线连接，每个所述第二晶体管的第一极均与所述多条数据线中的一条数据线连接，每个所述第二晶体管的第二极均与所述第一导体连接。
根据本公开一示例提供的电荷释放电路，所述第二导体还包括至少一个像素电极，所述控制器还包括第三控制线，所述电荷释放子电路还包括第三电荷释放单元；所述第三电荷释放单元分别与所述阵列基板中的栅线以及所述第三控制线相连接，所述第三电荷释放单元被配置为将所述第三控制线上的控制信号写入所述栅线，导通每个所述像素电极和与所述像素电极相连的 数据线。
根据本公开一示例提供的电荷释放电路，所述第三电荷释放单元包括多个第三晶体管，所述多个第三晶体管分别与所述阵列基板中的多条栅线一一对应，所述第二导体包括：与每条所述栅线相连的多个像素电极，所述第三控制线垂直于所述栅线，每个所述第三晶体管的栅极和第一极均与所述第三控制线连接，每个所述第三晶体管的第二极均与所述多条栅线中的一条栅线连接。
根据本公开一示例提供的电荷释放电路，其中，所述第一导体的体积大于所述第二导体的体积。
根据本公开一示例提供的电荷释放电路，所述第一导体为公共电极线或存储电极线。
本公开至少一示例提供一种显示基板，包括：上述任一电荷释放电路。
本公开至少一示例还提供一种显示装置，包括显示面板，所述显示面板包括上述任一显示基板。
本公开至少一示例还提供上述任一显示装置的电荷释放方法，包括：
在显示面板处于黑屏时，向所述控制器施加控制信号，在所述控制器的控制下，导通所述第一导体和所述第二导体，使所述第二导体上的电荷向所述第一导体移动。
根据本公开一示例提供的方法，所述第一导体为公共电极线或存储电极线，所述第二导体包括栅线、数据线或像素电极至少之一。
根据本公开一示例提供的方法，所述第一导体的体积大于所述第二导体的体积。
附图说明
为了更清楚地说明本公开示例中的技术方案，下面将对示例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的示例的一些示例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开一示例提供的一种电荷释放电路的结构示意图；
图2A为一种阵列基板的结构示意图；
图2B为另一种阵列基板的结构示意图；
图3为本公开一示例提供的另一种电荷释放电路的结构示意图；
图4为本公开一示例提供的又一种电荷释放电路的结构示意图；
图5为本公开一示例提供的再一种电荷释放电路的结构示意图；
图6为本公开另一示例提供的一种电荷释放电路的结构示意图；
图7为本公开另一示例提供的另一种电荷释放电路的结构示意图。
具体实施方式
为使本公开示例的目的、技术方案和优点更加清楚，下面将结合本公开示例的附图，对本公开示例的技术方案进行清楚、完整地描述。显然，所描述的示例是本公开的一部分示例，而不是全部的示例。基于所描述的本公开的示例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他示例，都属于本发明保护的范围。
除非另作定义，此处使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
在无需控制显示面板显示图像时，由于阵列基板的有效显示区域内的部分导体(如栅线和数据线)上会存在上一时刻施加电压时残留的电荷，从而使得部分液晶仍然发生偏转，导致处于黑屏状态的显示面板显示亮点。
本公开所有示例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件，根据在电路中的作用，本公开的示例所采用的晶体管主要为开关晶体管。由于这里采用的开关晶体管的源极、漏极是对称的，所以其源极、漏极是可以互换的。在本公开示例中，为区分晶体管除栅极之外的两 极，将其中源极称为第一极，漏极称为第二极。按附图中的形态规定晶体管的中间端为栅极、信号输入端为源极、信号输出端为漏极。此外本公开示例所采用的开关晶体管包括P型开关晶体管和N型开关晶体管中的至少一个，其中，P型开关晶体管在栅极为低电平时导通，在栅极为高电平时截止，N型开关晶体管为在栅极为高电平时导通，在栅极为低电平时截止。
图1为本公开一示例提供的一种电荷释放电路0的结构示意图，如图1所示，该电荷释放电路0可以包括：控制器01、电荷释放子电路02和第一导体03，电荷释放子电路02分别与控制器01、第一导体03以及阵列基板的有效显示区域内的第二导体A相连接。控制器01可以为控制模块，电荷释放子电路02可以为电荷释放模块。
电荷释放子电路02被配置为在控制器01的控制下，导通第一导体03和第二导体A，使第二导体A上的电荷向第一导体03移动。例如，第一导体03可接地。
例如，由于本公开示例提供的电荷释放电路中，电荷释放子电路02分别与控制器01和第一导体03相连接，且电荷释放子电路02被配置为在控制器01的作用下，导通第一导体03和阵列基板有效显示区域的第二导体A，使得第二导体A上的电荷能够移动至第一导体03上，从而减少了阵列基板的有效显示区域内的第二导体A上的电荷，减小了显示面板处于黑屏状态时液晶偏转的概率，减少了黑屏状态的显示面板上的亮点数量。
图2A为一种阵列基板1的结构示意图，如图2A所示，阵列基板1可以包括衬底基板100，衬底基板100的有效显示区域Y内形成有多条栅线A1和多条数据线A2，该多条栅线A1和多条数据线A2彼此绝缘并交叉形成多个像素区域，每个像素区域内形成有一个晶体管A4和一个像素电极A3，该晶体管A4的栅极与围成该像素区域的栅线A1连接，晶体管A4的源极与围成该像素区域的数据线A2连接，晶体管A4的漏极与该像素区域内的像素电极A3连接。例如，衬底基板100的非有效显示区域(也即边缘区域)内形成有第一公共电极线031和第二公共电极线032。例如，第一公共电极线031垂直于栅线A1，第二公共电极线032垂直于数据线A2。例如，第一公共电极线031与栅线A1绝缘，第二公共电极线032与数据线A2绝缘。例如，数据线被配置为向像素输入数据信号，数据信号例如包括灰阶电压。例如，栅 线被配置为向晶体管输入栅极信号，栅极信号例如包括栅极电压。
如图2B所示，衬底基板100的有效显示区域Y内，还可形成有多条存储电极线A0，每条存储电极线A0可穿过一行像素区域，且与栅线A1平行设置。
例如，如图2A和2B所示，晶体管A4阵列排布，每条栅线连接一行晶体管A4，每条数据线连接一列晶体管A4，每个像素电极连接一个晶体管A4。每条栅线对应的像素电极为：通过晶体管A4与该栅线相连接的像素电极。每个像素电极对应的数据线为：通过晶体管A4与该像素电极相连接的数据线。
例如，第一导体03的体积可以大于第二导体A的体积。此时，由于第一导体03的体积较大，所以第一导体03能够承载的电荷量也较大，因此，第一导体03能够为第二导体A分担较多的电荷。例如，第一导体03的线宽可以大于第二导体A的线宽，以使得第一导体03能够承载的电荷量较大。示例的，阵列基板可以包括衬底基板，衬底基板上可以形成有多种导线，其中，公共电极线和存储电极线较宽，而其他导线(如栅线和数据线)较窄，第一导体03可以为阵列基板上的公共电极线或者存储电极线，第二导体A可以为阵列基板的有效显示区域内的任一导体，如第二导体A可以为栅线、数据线或像素电极。
下面以第一导体为阵列基板上的公共电极线，以第二导体分别为阵列基板上的栅线、数据线以及像素电极为例，对本公开示例提供的电荷释放电路进行解释说明。
第一方面，第二导体可以包括：至少一条栅线，控制器可以包括：第一控制线，电荷释放子电路可以包括：第一电荷释放单元；第一电荷释放单元分别与至少一条栅线、第一控制线以及第一导体相连接，第一电荷释放单元被配置为根据第一控制线上的控制信号，导通第一导体和至少一条栅线。
图3为本公开示例提供的一种电荷释放电路0的结构示意图，如图3所示，第二导体可以包括：多条栅线A1，第一电荷释放单元021可以包括：多个第一晶体管0211，多个第一晶体管0211与多条栅线A1一一对应。每个第一晶体管0211的栅极G均与第一控制线011连接，每个第一晶体管0211的第一极J1均与对应的栅线A1连接，每个第一晶体管0211的第二极J2均与 垂直于栅线A1的第一公共电极线031连接，其中，第一控制线011垂直于栅线A1。例如，第一控制线011与各栅线A1彼此绝缘。
在需要控制显示面板处于黑屏状态时，可以向第一控制线011输入控制信号，使得多个第一晶体管0211中的每个第一晶体管0211均处于导通的状态(也即每个第一晶体管0211中的第一极J1与第二极J2处于连通状态)，从而，每个第一晶体管0211将相连接的栅线A1和第一公共电极线031导通，此时，若栅线A1上残留有电荷，则该残留的电荷可以向第一公共电极线031流动，从而减少了栅线A1上的电荷，此时，用于分担第二导体上电荷的第一导体为第一公共电极线031。在显示面板处于黑屏状态后，栅线上的电荷较少，从而防止了液晶在电压的作用下进行偏转，防止了显示面板上显示亮点，可解决处于黑屏状态的显示面板显示亮点的问题。
第二方面，第二导体可以包括：至少一条数据线，控制器可以包括：第二控制线，电荷释放子电路可以包括：第二电荷释放单元；第二电荷释放单元可以分别与至少一条数据线、第二控制线以及第一导体相连接，第二电荷释放单元被配置为根据第二控制线上的控制信号，导通第一导体和至少一条数据线。
图4为本公开示例提供的又一种电荷释放电路0的结构示意图，如图4所示，第二导体中的至少一条数据线可以包括：多条数据线A2，第二电荷释放单元022可以包括：多个第二晶体管0221，多个第二晶体管0221可以与多条数据线A2一一对应；每个第二晶体管0221的栅极G均与第二控制线012连接，每个第二晶体管0221的第一极J1均与对应的数据线A2连接，每个第二晶体管0221的第二极J2均与垂直于数据线A2的第二公共电极线032连接。例如，第二控制线012可以垂直于数据线A2。
在需要控制显示面板处于黑屏状态时，可以向第二控制线012输入控制信号，使得每个第二晶体管0221均处于导通的状态，从而，每个第二晶体管0221将相连接的数据线A2和第二公共电极线032导通，此时，若数据线A2上残留有电荷，则该残留的电荷可以向第二公共电极线032流动，从而减少了数据线A2上的电荷，此时，用于分担第二导体上电荷的第一导体为第二公共电极线032。在显示面板处于黑屏状态后，数据线上的电荷较少，从而防止了液晶在电压的作用下进行偏转，防止了显示面板上显示亮点。
第三方面，在第二方面的基础上，第二导体还可以包括：至少一个像素电极，控制器还可以包括：第三控制线，电荷释放子电路还可以包括：第三电荷释放单元；第三电荷释放单元可以分别与阵列基板中的栅线以及第三控制线相连接，第三电荷释放单元被配置为将第三控制线上的控制信号写入栅线，导通像素电极和像素电极对应的数据线。
图5为本公开示例提供的再一种电荷释放电路0的结构示意图，如图5所示，在图4的基础上，电荷释放子电路还可以包括：第三电荷释放单元023，第三电荷释放单元023可以包括：多个第三晶体管0231，多个第三晶体管0231分别与阵列基板中的多条栅线A1一一对应，第二导体中的至少一个像素电极可以包括：每条栅线A1对应的多个像素电极A3，每个第三晶体管0231的栅极G和第一极J1均与第三控制线013连接，每个第三晶体管0231的第二极J2均与该第三晶体管0231对应的栅线A1连接，第三控制线013可以垂直于栅线A1。
在需要控制显示面板处于黑屏状态时，还可以向第三控制线013输入控制信号，使得每个第三晶体管0231均处于导通状态，从而将第三控制线013上的控制信号沿第三晶体管0231的第一极和第二极输入至该第三晶体管0231对应的栅线A1，将该栅线A1相连接的像素区域中的晶体管导通，从而将该栅线A1对应的像素电极A3与像素电极A3对应的数据线A2导通。例如，还可以向第二控制线012输入控制信号，使得每个第二晶体管0221均处于导通的状态，从而，每个第二晶体管0221将相连接的数据线A2和第二公共电极线032导通。此时，若像素电极A3上残留有电荷，则该残留的电荷可以向数据线A2上流动，进而流向第二公共电极线032，从而减少了数据线A2和像素电极A3上的电荷，此时，用于分担第二导体上电荷的第一导体为第二公共电极线032。在显示面板处于黑屏状态后，数据线和像素电极上的电荷较少，从而防止了液晶在电压的作用下进行偏转，防止了显示面板上显示亮点。
第四方面，图6为本公开另一示例提供的一种电荷释放电路0的结构示意图，如图6所示，第二导体包括阵列基板上的多条栅线A1和多条数据线A2，该电荷释放电路0可以包括多个第一晶体管0211、多个第二晶体管0221、第一控制线011、第二控制线012、第一公共电极线031和第二公共电极线 032。
例如，第一公共电极线031垂直于栅线A1，且平行于数据线A2，第一控制线011平行于第一公共电极线031。第二公共电极线032垂直于数据线A2，且平行于栅线A1，第二控制线012平行于第二公共电极线032。多个第一晶体管0211与多条栅线A1一一对应，多个第二晶体管0221与多条数据线A2一一对应。每个第一晶体管0211的栅极均与第一控制线011连接，每个第一晶体管0211的第一极均与该第一晶体管对应的栅线A1相连接，每个第一晶体管0211的第二极均与第一公共电极线031相连接。每个第二晶体管0221的栅极均与第二控制线012连接，每个第二晶体管0221的第一极均与该第二晶体管对应的数据线A2相连接，每个第二晶体管0221的第二极均与第二公共电极线032相连接。
在需要控制显示面板处于黑屏状态时，可以向第一控制线011输入控制信号，使得每个第一晶体管0211均处于导通的状态，从而，每个第一晶体管0211将相连接的栅线A1和第一公共电极线031导通，此时，若栅线A1上残留有电荷，则该残留的电荷可以向第一公共电极线031流动，从而减少了栅线A1上的电荷。还可以向第二控制线012输入控制信号，使得每个第二晶体管0221均处于导通的状态，从而，每个第二晶体管0221将相连接的数据线A2和第二公共电极线032导通，此时，若数据线A2上残留有电荷，则该残留的电荷可以向第二公共电极线032流动，从而减少了数据线A2上的电荷。此时，用于分担第二导体上电荷的第一导体为第一公共电极线031和第二公共电极线032。在显示面板处于黑屏状态后，数据线上的电荷较少。
第五方面，图7为本公开另一示例提供的另一种电荷释放电路0的结构示意图，如图7所示，第二导体包括阵列基板上的多条栅线A1、多条数据线A2和多个像素电极A3，该电荷释放电路0可以包括多个第一晶体管0211、多个第二晶体管0221、多个第三晶体管0231、第一控制线011、第二控制线012、第三控制线013、第一公共电极线031和第二公共电极线032。
例如，第一公共电极线031垂直于栅线A1，且平行于数据线A2。第一控制线011和第三控制线013均平行于第一公共电极线031，且均设置在第一公共电极线031的附近，如第一控制线011设置在第一公共电极线031靠近有效显示区域的一侧，第三控制线013设置在第一公共电极线031远离有 效显示区域的一侧。第二公共电极线032垂直于数据线A2，且平行于栅线A1。第二控制线012平行于第二公共电极线032，且设置在第二公共电极线032的附近，如设置在第二公共电极线032靠近有效显示区域的一侧。
多个第一晶体管0211与多条栅线A1一一对应，多个第二晶体管0221与多条数据线A2一一对应，多个第三晶体管0231与多条栅线A1一一对应。每个第一晶体管0211的栅极均与第一控制线011连接，每个第一晶体管0211的第一极均与该第一晶体管对应的栅线A1相连接，每个第一晶体管0211的第二极均与第一公共电极线031相连接。每个第二晶体管0221的栅极均与第二控制线012连接，每个第二晶体管0221的第一极均与该第二晶体管对应的数据线A2相连接，每个第二晶体管0221的第二极均与第二公共电极线032相连接。每个第三晶体管0231的栅极和第一极均与第三控制线013连接，每个第三晶体管0231的第二极均与该第三晶体管对应的栅线A1相连接。
在需要控制显示面板处于黑屏状态时，可以向第一控制线011输入控制信号，使得每个第一晶体管0211均处于导通的状态，从而，每个第一晶体管0211将相连接的栅线A1和第一公共电极线031导通，此时，若栅线A1上残留有电荷，则该残留的电荷可以向第一公共电极线031流动，从而减少了栅线A1上的电荷。
例如，还可以向第二控制线012输入控制信号，使得每个第二晶体管0221均处于导通的状态，从而，每个第二晶体管0221将相连接的数据线A2和第二公共电极线032导通，此时，若数据线A2上残留有电荷，则该残留的电荷可以向第二公共电极线032流动，从而减少了数据线A2上的电荷。在显示面板处于黑屏状态后，数据线上的电荷较少。
进一步的，还可以向第三控制线013输入控制信号，使得每个第三晶体管0231均处于导通状态，从而将第三控制线013上的控制信号从第三晶体管0231的第一极和第二极输入至该第三晶体管0231对应的栅线A1，将该栅线A1对应的像素电极A3与该像素电极A3对应的数据线A2导通。此时，若像素电极A3上残留有电荷，则该残留的电荷可以向数据线A2上流动，进而向第二公共电极线032流动，从而减少了数据线A2和像素电极A3上的电荷。
此时，用于分担第二导体上电荷的第一导体为第一公共电极线031和第二公共电极线032。在显示面板处于黑屏状态后，阵列基板的有效显示区域 内的导体(如栅线、数据线和像素电极)上的电荷较少，从而防止了液晶在电压的作用下进行偏转，防止了显示面板上显示亮点。
例如，本公开的示例中，延伸方向相同的部件可以同层形成。例如，数据线A2、第一公共电极线031、第一控制线011和第三控制线013中的至少两个可同层形成，例如，位于第一层。栅线A1、第二控制线012和公共电极线032中的至少两个可同层形成，例如，位于第二层。例如，第一层和第二层之间可设置绝缘层以使得两条线的交叉处非电连接。
例如，本公开的示例中，两个部件可以通过晶体管相连。例如，各图中的黑色圆点可表示电连接。例如，各图中，有交叉的两条线在交叉处彼此绝缘。
综上所述，由于本公开示例提供的电荷释放电路中，电荷释放子电路分别与控制器和第一导体相连接，且电荷释放子电路被配置为在控制器的作用下，导通第一导体和阵列基板有效显示区域的第二导体，使得第二导体上的电荷能够移动至第一导体上，从而减少了阵列基板的有效显示区域内的第二导体上的电荷，减小了显示面板处于黑屏状态时液晶偏转的概率，减少了黑屏状态的显示面板上的亮点数量。
本公开示例还提供了一种显示基板，该显示基板可以包括：如图1、图3、图4、图5、图6或图7任一所示的电荷释放电路。
进一步的，本公开示例还提供了一种显示面板，该显示面板可以包括：设置有如图1、图3、图4、图5、图6或图7任一所示的电荷释放电路的显示基板。例如，该显示基板可以为阵列基板。例如，显示面板还可以包括与阵列基板对置的对置基板。例如，对置基板可为彩膜基板，但不限于此。实际应用中，该显示基板还可以为对置基板，本公开示例对此不作限定。
进一步的，本公开示例还提供了一种显示装置，该显示装置中包括：显示面板，该显示面板中的显示基板可以包括如图1、图3、图4、图5、图6或图7任一所示的电荷释放电路。该显示装置可以为：液晶面板、电子纸、有机发光二极管(Organic Light-Emitting Diode，OLED)面板、有源矩阵有机发光二极体(Active-matrix organic light emitting diode，AMOLED)面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本公开至少一示例还提供一种显示装置的电荷释放方法，包括：利用如上所述的任一电荷释放电路释放电荷，该方法包括：在显示面板处于黑屏时，向控制器施加控制信号，在控制器的控制下，导通第一导体和第二导体，使第二导体上的电荷向第一导体移动。
例如，显示面板处于黑屏状态时，显示装置为待机状态。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。

Claims (14)

  1. 一种电荷释放电路，包括：控制器、电荷释放子电路和第一导体，所述电荷释放子电路分别与所述控制器、所述第一导体以及阵列基板的有效显示区域内的第二导体相连接；
    所述电荷释放子电路被配置为在所述控制器的控制下，导通所述第一导体和所述第二导体，使所述第二导体上的电荷向所述第一导体移动。
  2. 根据权利要求1所述的电荷释放电路，其中，
    所述第二导体包括：至少一条栅线，所述控制器包括：第一控制线，所述电荷释放子电路包括：第一电荷释放单元；
    所述第一电荷释放单元分别与所述至少一条栅线、所述第一控制线以及所述第一导体相连接，所述第一电荷释放单元被配置为根据所述第一控制线上的控制信号，导通所述第一导体和所述至少一条栅线。
  3. 根据权利要求2所述的电荷释放电路，其中，
    所述第二导体包括多条栅线，所述第一电荷释放单元包括多个第一晶体管，所述第一控制线垂直于所述栅线，所述多个第一晶体管与所述多条栅线一一对应；
    每个所述第一晶体管的栅极均与所述第一控制线连接，每个所述第一晶体管的第一极均与所述多条栅线中的一条栅线连接，每个所述第一晶体管的第二极均与所述第一导体连接。
  4. 根据权利要求1所述的电荷释放电路，其中，
    所述第二导体包括至少一条数据线，所述控制器包括第二控制线，所述电荷释放子电路包括第二电荷释放单元；
    所述第二电荷释放单元分别与所述至少一条数据线、所述第二控制线以及所述第一导体相连接，所述第二电荷释放单元被配置为根据所述第二控制线上的控制信号，导通所述第一导体和所述至少一条数据线。
  5. 根据权利要求4所述的电荷释放电路，其中，
    所述第二导体包括多条数据线，所述第二电荷释放单元包括多个第二晶体管，所述第二控制线垂直于所述数据线，所述多个第二晶体管与所述多条数据线一一对应；
    每个所述第二晶体管的栅极均与所述第二控制线连接，每个所述第二晶体管的第一极均与所述多条数据线中的一条数据线连接，每个所述第二晶体管的第二极均与所述第一导体连接。
  6. 根据权利要求5所述的电荷释放电路，其中，
    所述第二导体还包括至少一个像素电极，所述控制器还包括第三控制线，所述电荷释放子电路还包括第三电荷释放单元；
    所述第三电荷释放单元分别与所述阵列基板中的栅线以及所述第三控制线相连接，所述第三电荷释放单元被配置为将所述第三控制线上的控制信号写入所述栅线，导通每个所述像素电极和与所述像素电极相连的数据线。
  7. 根据权利要求6所述的电荷释放电路，其中，
    所述第三电荷释放单元包括多个第三晶体管，所述多个第三晶体管分别与所述阵列基板中的多条栅线一一对应，所述第二导体包括：与每条所述栅线相连的多个像素电极，所述第三控制线垂直于所述栅线，
    每个所述第三晶体管的栅极和第一极均与所述第三控制线连接，每个所述第三晶体管的第二极均与所述多条栅线中的一条栅线连接。
  8. 根据权利要求1至7任一项所述的电荷释放电路，其中，所述第一导体的体积大于所述第二导体的体积。
  9. 根据权利要求1至8任一项所述的电荷释放电路，其中，所述第一导体为公共电极线或存储电极线。
  10. 一种显示基板，包括如权利要求1至9项任一所述的电荷释放电路。
  11. 一种显示装置，包括显示面板，所述显示面板包括如权利要求10所述的显示基板。
  12. 权利要求11所述的显示装置的电荷释放方法，包括：
    在显示面板处于黑屏时，向所述控制器施加控制信号，在所述控制器的控制下，导通所述第一导体和所述第二导体，使所述第二导体上的电荷向所述第一导体移动。
  13. 根据权利要求12所述的方法，其中，所述第一导体为公共电极线或存储电极线，所述第二导体包括栅线、数据线或像素电极至少之一。
  14. 根据权利要求12或13所述的方法，其中，所述第一导体的体积大于所述第二导体的体积。
PCT/CN2017/109965 2017-01-03 2017-11-08 电荷释放电路、显示基板、显示装置及其电荷释放方法 WO2018126785A1 (zh)

Priority Applications (8)

Application Number Priority Date Filing Date Title
MX2018012047A MX2018012047A (es) 2017-01-03 2017-11-08 Circuito de liberacion de carga, sustrato de visualizacion, dispositivo de pantalla, y metodo de liberacion de carga del mismo.
AU2017391552A AU2017391552C9 (en) 2017-01-03 2017-11-08 Charge release circuit, display substrate, display device, and charge release method thereof
US16/065,492 US11238820B2 (en) 2017-01-03 2017-11-08 Charge release circuit, display substrate, display device and charge release method thereof
EP17882277.1A EP3567577A4 (en) 2017-01-03 2017-11-08 CHARGE RELEASE CIRCUIT, DISPLAY SUBSTRATE, DISPLAY DEVICE AND CHARGE RELEASE PROCEDURE FOR IT
RU2018134593A RU2732990C1 (ru) 2017-01-03 2017-11-08 Схема освобождения заряда, подложка дисплея, устройство отображения и соотвествующий способ освобождения заряда
JP2018548389A JP7195928B2 (ja) 2017-01-03 2017-11-08 電荷放出回路、表示基板、表示装置及びその電荷放出方法
KR1020187028345A KR102096993B1 (ko) 2017-01-03 2017-11-08 전하 방출 회로, 디스플레이 기판, 디스플레이 디바이스, 및 그것의 전하 방출 방법
BR112018069452A BR112018069452A2 (pt) 2017-01-03 2017-11-08 circuito de liberação de carga, substrato de exibição, dispositivo de exibição, e método de liberação de carga dos mesmos

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201720002380.1U CN206370279U (zh) 2017-01-03 2017-01-03 电荷释放电路、显示基板、显示面板及显示装置
CN201720002380.1 2017-01-03

Publications (1)

Publication Number Publication Date
WO2018126785A1 true WO2018126785A1 (zh) 2018-07-12

Family

ID=59391456

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2017/109965 WO2018126785A1 (zh) 2017-01-03 2017-11-08 电荷释放电路、显示基板、显示装置及其电荷释放方法

Country Status (10)

Country Link
US (1) US11238820B2 (zh)
EP (1) EP3567577A4 (zh)
JP (1) JP7195928B2 (zh)
KR (1) KR102096993B1 (zh)
CN (1) CN206370279U (zh)
AU (1) AU2017391552C9 (zh)
BR (1) BR112018069452A2 (zh)
MX (1) MX2018012047A (zh)
RU (1) RU2732990C1 (zh)
WO (1) WO2018126785A1 (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN206370279U (zh) * 2017-01-03 2017-08-01 京东方科技集团股份有限公司 电荷释放电路、显示基板、显示面板及显示装置
CN114114767B (zh) * 2021-11-30 2022-07-12 绵阳惠科光电科技有限公司 阵列基板和显示面板
CN115240583A (zh) * 2022-09-23 2022-10-25 广州华星光电半导体显示技术有限公司 残留电荷释放电路和显示面板

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110292005A1 (en) * 2010-06-01 2011-12-01 Au Optronics Corp. Display apparatus and method for eliminating ghost thereof
CN202473180U (zh) * 2012-01-12 2012-10-03 京东方科技集团股份有限公司 一种驱动电路和显示装置
CN102867491A (zh) * 2012-09-03 2013-01-09 京东方科技集团股份有限公司 一种液晶面板驱动电路及方法、显示装置
CN103412427A (zh) * 2013-08-13 2013-11-27 南京中电熊猫液晶显示科技有限公司 一种液晶显示面板
CN104297969A (zh) * 2014-10-28 2015-01-21 京东方科技集团股份有限公司 液晶显示面板及其放电方法和显示装置
CN204667021U (zh) * 2015-06-15 2015-09-23 京东方科技集团股份有限公司 阵列基板和显示装置
CN206370279U (zh) * 2017-01-03 2017-08-01 京东方科技集团股份有限公司 电荷释放电路、显示基板、显示面板及显示装置

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10282471A (ja) * 1997-04-04 1998-10-23 Hitachi Ltd アクティブマトリックス型液晶パネルとその駆動方法
JP4103425B2 (ja) 2002-03-28 2008-06-18 セイコーエプソン株式会社 電気光学装置、電子機器及び投射型表示装置
US7698573B2 (en) * 2002-04-02 2010-04-13 Sharp Corporation Power source apparatus for display and image display apparatus
JP2004109824A (ja) 2002-09-20 2004-04-08 Seiko Epson Corp 電気光学装置、電気光学装置の駆動方法、電気光学装置の駆動回路および電子機器
KR101331211B1 (ko) * 2006-12-19 2013-11-20 삼성디스플레이 주식회사 액정 표시 장치
JP2008170995A (ja) * 2007-01-06 2008-07-24 Samsung Electronics Co Ltd 液晶表示装置及び液晶表示装置の残像除去方法
TWI402594B (zh) * 2007-04-27 2013-07-21 Chunghwa Picture Tubes Ltd 主動元件陣列基板
TWI393110B (zh) * 2008-09-26 2013-04-11 Au Optronics Corp 用於消除殘影之裝置、移位暫存器單元、液晶顯示設備及方法
KR101579842B1 (ko) 2008-10-30 2015-12-24 삼성디스플레이 주식회사 게이트 라인 구동 방법, 이를 수행하기 위한 게이트 구동회로 및 이를 구비한 표시 장치
WO2010052954A1 (ja) * 2008-11-05 2010-05-14 シャープ株式会社 アクティブマトリクス基板、アクティブマトリクス基板の製造方法、液晶パネル、液晶パネルの製造方法、液晶表示装置、液晶表示ユニット、テレビジョン受像機
RU2488895C1 (ru) * 2009-06-17 2013-07-27 Шарп Кабусики Кайся Сдвиговый регистр, схема управления дисплеем, панель отображения и устройство отображения
JP2011059380A (ja) 2009-09-10 2011-03-24 Renesas Electronics Corp 表示装置及びそれに使用される駆動回路
KR101747758B1 (ko) * 2010-12-06 2017-06-16 삼성디스플레이 주식회사 표시 패널의 구동 방법 및 이를 수행하기 위한 표시 장치
JP2012173469A (ja) 2011-02-21 2012-09-10 Japan Display Central Co Ltd 液晶表示装置及び液晶表示装置の駆動方法
KR101925993B1 (ko) * 2011-12-13 2018-12-07 엘지디스플레이 주식회사 방전회로를 포함하는 액정표시장치 및 액정표시장치 구동방법
JP5397491B2 (ja) 2012-02-20 2014-01-22 セイコーエプソン株式会社 駆動回路、電気光学装置及び電子機器
US20140232964A1 (en) 2013-02-20 2014-08-21 Hannstar Display Corp. Integrated gate driver circuit and liquid crystal panel
CN103400546B (zh) 2013-07-25 2015-08-12 合肥京东方光电科技有限公司 一种阵列基板及其驱动方法、显示装置
CN103995407B (zh) * 2014-05-08 2016-08-24 京东方科技集团股份有限公司 阵列基板和显示面板
KR101679923B1 (ko) 2014-12-02 2016-11-28 엘지디스플레이 주식회사 스캔 구동부를 포함하는 표시패널 및 그의 구동방법
CN105185332B (zh) * 2015-09-08 2018-01-09 深圳市华星光电技术有限公司 液晶显示面板及其驱动电路、制造方法
CN206301112U (zh) * 2016-10-18 2017-07-04 京东方科技集团股份有限公司 一种阵列基板及显示装置
CN106950775A (zh) * 2017-05-16 2017-07-14 京东方科技集团股份有限公司 一种阵列基板和显示装置

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110292005A1 (en) * 2010-06-01 2011-12-01 Au Optronics Corp. Display apparatus and method for eliminating ghost thereof
CN202473180U (zh) * 2012-01-12 2012-10-03 京东方科技集团股份有限公司 一种驱动电路和显示装置
CN102867491A (zh) * 2012-09-03 2013-01-09 京东方科技集团股份有限公司 一种液晶面板驱动电路及方法、显示装置
CN103412427A (zh) * 2013-08-13 2013-11-27 南京中电熊猫液晶显示科技有限公司 一种液晶显示面板
CN104297969A (zh) * 2014-10-28 2015-01-21 京东方科技集团股份有限公司 液晶显示面板及其放电方法和显示装置
CN204667021U (zh) * 2015-06-15 2015-09-23 京东方科技集团股份有限公司 阵列基板和显示装置
CN206370279U (zh) * 2017-01-03 2017-08-01 京东方科技集团股份有限公司 电荷释放电路、显示基板、显示面板及显示装置

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP3567577A4 *

Also Published As

Publication number Publication date
JP2020503536A (ja) 2020-01-30
AU2017391552B2 (en) 2019-10-10
EP3567577A4 (en) 2020-08-26
AU2017391552C1 (en) 2020-05-28
US20210210038A1 (en) 2021-07-08
AU2017391552C9 (en) 2020-07-09
KR102096993B1 (ko) 2020-04-03
JP7195928B2 (ja) 2022-12-26
KR20180113627A (ko) 2018-10-16
EP3567577A1 (en) 2019-11-13
CN206370279U (zh) 2017-08-01
AU2017391552A1 (en) 2018-10-04
BR112018069452A2 (pt) 2019-02-05
US11238820B2 (en) 2022-02-01
MX2018012047A (es) 2019-01-10
RU2732990C1 (ru) 2020-09-28

Similar Documents

Publication Publication Date Title
US9478567B1 (en) Thin-film transistor, array substrate and display apparatus
US9778791B2 (en) Touch display panel and touch display device
US20190109184A1 (en) Display panel and display device
KR102034112B1 (ko) 액정 디스플레이 장치와 이의 구동방법
US9965063B2 (en) Display circuitry with reduced pixel parasitic capacitor coupling
WO2021218437A1 (zh) 显示基板及显示装置
US10720450B2 (en) Array substrate and manufacturing method thereof, display panel and display device
US9331101B2 (en) Organic light emitting display panel
US20130148049A1 (en) Display device
KR102601818B1 (ko) 터치 센서를 구비하는 표시장치
US10732754B2 (en) Display device having a compact peripheral region
US20160335975A1 (en) Array Substrate and Driving Method Thereof, Display Panel, and Display Apparatus
US10330992B2 (en) Display device
JP7247392B2 (ja) 表示装置
WO2018126785A1 (zh) 电荷释放电路、显示基板、显示装置及其电荷释放方法
US11569334B2 (en) Display substrate including first reference voltage line being electrically coupled to first reference voltage auxiliary line through via holes penetrating through insulation layer therebetween, and display device having the same
KR20190122920A (ko) 표시 장치
US10747349B2 (en) Display substrate, display panel, display apparatus and method for driving the same
CN111948859A (zh) 显示基板以及显示装置
US9618810B2 (en) Array substrate and liquid crystal display panel
KR20150078563A (ko) 액정 화소
US20220130945A1 (en) Display Panel and Display Apparatus Using the Same
KR20060020173A (ko) 신호선을 가지고 있는 표시판 및 표시 장치

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 2017882277

Country of ref document: EP

ENP Entry into the national phase

Ref document number: 2017882277

Country of ref document: EP

Effective date: 20180614

ENP Entry into the national phase

Ref document number: 2018548389

Country of ref document: JP

Kind code of ref document: A

WWE Wipo information: entry into national phase

Ref document number: MX/A/2018/012047

Country of ref document: MX

ENP Entry into the national phase

Ref document number: 2017391552

Country of ref document: AU

Date of ref document: 20171108

Kind code of ref document: A

REG Reference to national code

Ref country code: BR

Ref legal event code: B01A

Ref document number: 112018069452

Country of ref document: BR

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17882277

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 112018069452

Country of ref document: BR

Kind code of ref document: A2

Effective date: 20180924

NENP Non-entry into the national phase

Ref country code: DE