WO2018120328A1 - Goa电路的驱动方法和驱动装置 - Google Patents

Goa电路的驱动方法和驱动装置 Download PDF

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Publication number
WO2018120328A1
WO2018120328A1 PCT/CN2017/071330 CN2017071330W WO2018120328A1 WO 2018120328 A1 WO2018120328 A1 WO 2018120328A1 CN 2017071330 W CN2017071330 W CN 2017071330W WO 2018120328 A1 WO2018120328 A1 WO 2018120328A1
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Prior art keywords
pull
transistor
circuit
signal
clock signal
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PCT/CN2017/071330
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English (en)
French (fr)
Inventor
石龙强
陈书志
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深圳市华星光电技术有限公司
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Priority to US15/328,629 priority Critical patent/US10121442B2/en
Publication of WO2018120328A1 publication Critical patent/WO2018120328A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/18—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages
    • G11C19/182—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes

Definitions

  • the present invention relates to the field of display driving technologies, and in particular, to a driving method and a driving device for a GOA circuit.
  • the flat panel display device has many advantages such as thin body, power saving, no radiation, and has been widely used.
  • the conventional flat panel display device mainly includes a liquid crystal display (LCD) and an organic light emitting display (OLED).
  • each pixel has a thin film transistor (TFT) whose gate is connected to a horizontal scanning line, a drain is connected to a vertical data line, and a source is connected.
  • TFT thin film transistor
  • Applying a sufficient voltage on the horizontal scan line causes all the TFTs on the line to be turned on.
  • the pixel electrode on the horizontal scan line is connected to the vertical data line, thereby writing the display signal voltage on the data line.
  • the driving of the horizontal scanning line of the active liquid crystal display panel is mainly completed by the external IC of the panel, and the external IC can control the stepwise charging and discharging of the horizontal scanning lines of each level.
  • the GOA technology that is, the Gate Driver on Array technology, can use the original process of the liquid crystal display panel to make the horizontal scanning line driving circuit on the substrate around the display area, so that it can replace the external IC to complete The drive of the horizontal scan line.
  • GOA technology can reduce the bonding process of external ICs, increase the productivity and reduce the cost of products, and make the LCD panel more suitable for making narrow-frame or borderless display products.
  • the existing GOA driving circuit generally includes a plurality of cascaded GOA units, and each level of the GOA unit corresponds to driving a level one horizontal scanning line.
  • the main structure of the GOA unit includes a pull-up part, a pull-up control part, a transfer part and a pull-down holding part, and is responsible for the potential rise.
  • Bootstrap (Boast) capacitor is responsible for the potential rise.
  • the pull-up circuit is mainly responsible for outputting the clock signal (Clock) as a gate signal;
  • the pull-up control circuit is responsible for controlling the opening time of the pull-up circuit, and is generally connected to the transmitted signal transmitted by the GOA circuit of the previous stage or The Gate signal;
  • the pull-down sustain circuit is responsible for maintaining the Gate output signal and the Gate signal of the pull-up circuit (commonly referred to as the Q point) in the off state (ie, the low level potential), and the bootstrap capacitor (C boast) is responsible for The second rise of the Q point is beneficial to the output of the Gate signal of the pull-up circuit.
  • the data buffer time (Line Buffer) is defined as the interval between the rising edge of the scan start signal (STV) and the first rising edge of the data voltage signal (Date) of the data driver output of the display device.
  • STV scan start signal
  • Date data voltage signal
  • a driving method of a GOA circuit comprising a cascaded multi-level GOA driving unit, the driving method comprising: inputting a first clock signal, a second clock signal, and a constant piezoelectric position to each stage of the GOA driving unit Controlling the multi-level GOA driving unit to output a scan driving signal step by step, wherein the first to fourth stage GOA driving units further input a scan start signal; wherein the first clock signal and the second clock signal are selected From two different clock signals in a clock signal group, the clock signal group includes eight high frequency clock signals CK 1 CK CK 8 , wherein CK m and CK m+4 are mutually inverted signals; The clock signal cyclically outputs high frequency clock signals CK 1 CK CK 8 from CK 5 , and the second clock signal cyclically outputs high frequency clock signals CK 1 CK CK 8 from CK 1 ; wherein the period of each high frequency clock signal For T, the high-level pulse width is T 1 in one period T; wherein
  • each stage of the GOA driving unit comprises a pull-up control circuit, a pull-up circuit, a level transfer circuit, a bootstrap capacitor and a pull-down sustain circuit, and the pull-up control circuit is based on the second clock signal and the first four stages
  • the scan driving signal outputs a gate control signal of the current stage
  • the pull-up circuit outputs a scan drive signal of the current stage according to the first clock signal and the gate control signal of the current stage
  • the level transfer circuit is configured according to the first clock signal and
  • the gate control signal of the current stage outputs a signal of the current level
  • the pull-down maintaining circuit is configured to pull the gate control signal of the current stage and the scan driving signal of the current level when the GOA driving unit of the current stage is in a non-driving time Low to low level.
  • Another aspect of the present invention provides a driving apparatus for a GOA circuit including a timing control chip and a GOA circuit, the GOA circuit including a cascaded multi-level GOA driving unit, the timing control chip to each level of GOA
  • the driving unit inputs the first clock signal, the second clock signal, and the constant voltage bit, and drives the multi-stage GOA driving unit to output the scan driving signal step by step, wherein the timing control chip further drives the first to fourth stage GOA driving units Inputting a scan start signal; wherein the first clock signal and the second clock signal are selected from two different clock signals in a clock signal group, and the clock signal group includes eight high frequency clock signals CK 1 ⁇ CK 8 ; wherein CK m and CK m+4 are mutually inverted signals; the first clock signal cyclically outputs high frequency clock signals CK 1 CK CK 8 starting from CK 5 , the second clock signal starting from CK 1 The high frequency clock signals CK 1 to CK 8 are cyclically outputted; wherein the period of each
  • Each stage of the GOA driving unit includes a pull-up control circuit, a pull-up circuit, a level transfer circuit, a bootstrap capacitor, and a pull-down sustain circuit, and the pull-up control circuit is configured according to the second clock signal and the first four-level scan driving signal.
  • the pull-up circuit Outputting a gate control signal of the current stage, the pull-up circuit outputs a scan driving signal of the current stage according to the first clock signal and the gate control signal of the current stage, and the level circuit is configured according to the first clock signal and the current level gate
  • the pole control signal outputs a signal of the level of the stage; the pull-down maintaining circuit is configured to pull the gate control signal of the current stage and the scan driving signal of the current level to a low level when the GOA driving unit of the stage is in a non-driving time Level.
  • the driving method and driving device of the GOA circuit provided in the embodiment of the present invention correspond to a GOA circuit driven by eight high frequency clock signals, and the first to fourth high frequency clock signals are used in the scanning driving of each frame image.
  • the high-level pulse width of the first cycle of CK 1 to CK 4 is small, and the output of the scan driving signal of the first-stage GOA driving unit is accelerated, without affecting the overall output timing and level of the GOA circuit.
  • the interval between the rising edge of the scan start signal (STV) and the first rising edge of the data voltage signal (Date), that is, shortening the data buffer time (Line Buffer), is advantageous for reducing the cost of the driving circuit.
  • FIG. 1 is a schematic structural diagram of a driving apparatus of a GOA circuit according to an embodiment of the present invention
  • FIG. 2 is a circuit diagram of a GOA driving unit in an embodiment of the present invention.
  • FIG. 3 is a signal waveform diagram of a driving method of a GOA circuit according to an embodiment of the present invention.
  • the embodiment provides a driving device for a GOA circuit.
  • the driving device includes a timing control chip (Tcon) 1 and a GOA circuit 2
  • the GOA circuit 2 includes a cascaded multi-level GOA driver.
  • the units GOA 1 to GOA N the timing control chip 1 inputs a first clock signal CK, a second clock signal XCK, and a constant voltage bit VSS to each of the GOA driving units GOA 1 to GOA N to drive the multi-level GOA driving GOA 1 ⁇ GOA N unit step by step scan driver output signal G 1 ⁇ G N, supplied to the display panel.
  • the timing control chip 1 also inputs a scan start signal STV to the first to fourth stage GOA drive units GOA 1 to GOA 4 .
  • each stage of the GOA driving unit includes a pull-up control circuit 10, a pull-up circuit 20, a level transfer circuit 30, a bootstrap capacitor Cb, and a pull-down sustain circuit 40.
  • the pull-up control circuit 10 outputs a gate control signal Q n of the current stage according to the second clock signal XCK and the first four-stage scan driving signal ST n-4 , and the pull-up circuit 20 is configured according to the first clock signal CK.
  • the pull-down maintaining circuit 40 is configured to pull the local gate control signal Q n and the local-level scan driving signal G n to a low level when the GOA driving unit of the current stage is in a non-driving time (ie, constant Piezoelectric position VSS). It should be noted that when n-4 is less than zero, ST n-4 does not exist, and the STV signal provided by the timing control chip 1 should be used instead.
  • the pull-up control circuit 10 includes a first pull-up transistor T11 and a second pull-up transistor T12, and the gates of the first pull-up transistor T11 and the second pull-up transistor T12 are mutually Connecting and receiving the second clock signal XCK, the source of the first pull-up transistor T11 receives a corresponding first four-stage transfer signal ST n-4 , the drain of the first pull-up transistor T11 and the second upper The sources of the pull-up transistor T12 are connected to each other, and the drain of the second pull-up transistor T12 serves as an output terminal of the pull-up control circuit 10, and outputs the gate control signal Q n of the present stage. Further, in this embodiment, as shown in FIG.
  • the pull-up control circuit 10 further includes a third pull-up transistor T13, and the gate of the third pull-up transistor T13 is connected to The drain of the second pull-up transistor T12 is connected to the drain of the first pull-up transistor T11, and the gate is connected to the output terminal of the pull-up circuit 20. It should be noted that when the third pull-up transistor T13 is turned on, the resistance between the source and the drain is large, and the current is small so as not to affect the output of the pull-up circuit 20 connected to the drain thereof. The potential of the terminal is correct.
  • the pull-up circuit 20 includes a fourth pull-up transistor T21, and the gate of the fourth pull-up transistor T21 is connected to the output of the pull-up control circuit 10, and the receiving gate is controlled.
  • the signal Q n the source is connected to the first clock signal CK, and the drain serves as an output terminal of the pull-up circuit 20 to output the current-level scan driving signal G n .
  • the bootstrap capacitor Cb is connected between the output terminal of the pull-up control circuit 10 and the output terminal of the pull-up circuit 20. That is, the two ends of the bootstrap capacitor Cb are respectively connected with the gate control signal Q n and the scan driving signal G n , and the function of the bootstrap capacitor Cb is to store the gate voltage of the transistor T21 when Q n is high level, when G The n output is high, and the bootstrap capacitor Cb can second raise the potential of the gate of the transistor T21 to ensure that the transistor T21 reliably turns on and outputs the scan driving signal.
  • the stage transmission circuit 30 includes a transfer transistor T22 whose gate is connected to an output terminal of the pull-up control circuit 10, and receives a gate control signal Q n , a source Connected to the first clock signal CK, the drain serves as the output of the stage transmission circuit 30, and outputs the stage-level transmission signal ST n .
  • the output stage-level signal ST n is a pull-up control unit for controlling the last four stages, and the pull-up control unit is controlled by the transfer signal to avoid using the scan drive signal to control this action, so that the scan drive signal is more stable.
  • the pull-down maintaining circuit 40 is mainly used for some main nodes in the circuit (for example, the gate control signal Q n , the scan driving signal G n , and the level transmission signal ST n ) when the GOA driving unit of the current stage is in the non-output timing. The potential of the pull is pulled low.
  • the pull-down maintaining unit 40 includes a first pull-down maintaining circuit 41 and a second pull-down maintaining circuit 42. The first pull-down maintaining circuit 41 and the second pull-down maintaining circuit 42 alternately turn the gate control signal.
  • Q n , the scan driving signal G n and the level transfer signal ST n are connected to the reference low level signal VSS and maintained in the off state.
  • the first pull-down maintaining circuit 41 and the second pull-down maintaining circuit 42 have the same circuit structure, and the first pull-down maintaining circuit 41 and the second pull-down maintaining circuit 42 respectively include the first A transistor T31, T32, second transistors T23, T24, third transistors T41, T42, fourth transistors T51, T61, fifth transistors T52, T62, sixth transistors T53, T63 and seventh transistors T54, T64.
  • the drains of the first transistors T31, T32, the second transistors T23, T24, and the third transistors T41, T42 are all connected to the reference low level signal VSS, the first transistors T31, T32, the second transistors T23, T24, The gates of the three transistors T41 and T42 are connected to each other and receive the control signals P n , K n at the same time.
  • the sources of the first transistors T31 and T32 are connected to the scan driving signal G n , and the sources of the second transistors T23 and T24 are connected to the stage.
  • the signal ST n is transmitted, and the sources of the third transistors T41, T42 are connected to the gate control signal Q n .
  • the gates and sources of the fourth transistors T51 and T61 are connected to and receive the pull-down clock signals LC1 and LC2, and the drains are connected to the sources of the fifth transistors T52 and T62.
  • the gates of the fifth transistors T52 and T62 are connected.
  • the pole is connected to the gate control signal Q n , the drain is connected to the reference low level signal VSS; the sources of the sixth transistors T53 , T63 are connected to the sources of the fourth transistors T51 , T61 , and receive the pull-down
  • the clock signals LC1, LC2 the gates are connected to the drains of the fourth transistors T51, T61, the drains are connected to the sources of the seventh transistors T54, T64; the gates of the seventh transistors T54, T64 are connected To the gate control signal Q n , the drain is connected to the reference low level signal VSS.
  • the drain outputs control signal control signals P n , K n of the sixth transistors T53 and T63 are connected to the gates of the first transistors T31 and T32, the second transistors T23 and T24, and the third transistors T41 and T42.
  • the reference low level signal VSS includes a first reference low level signal Vss1 and a second reference low level signal Vss2,
  • the drains of the first transistors T31, T32, the second transistors T23, T24, and the third transistors T41, T42 are respectively connected to the first reference low level signal Vss1, and the drains of the fifth transistors T52, T62
  • the pole is connected to the first reference low level signal Vss1; the drains of the seventh transistors T54, T64 are connected to the second reference low level signal Vss2.
  • the potential of the first reference low level signal Vss1 is lower than the potential of the second reference low level signal Vss2.
  • the embodiment Before the transfer to the nth stage GOA driving unit, the embodiment takes the first pull-down clock signal LC1 as the high level and the second pull-down clock signal LC2 as the low level, and the control signal P n is The high level and K n are low, and the first pull-down maintaining circuit 41 maintains the voltage of each node.
  • the gate control signal Q n , the scan drive signal G n , and the level transfer signal ST n of the nth stage GOA driving unit are all pulled down to the reference low level signal.
  • the first clock signal CK and the second clock signal XCK enter the next timing.
  • the second clock signal XCK and the corresponding first four stages of the transmission signal ST n-4 are at a low level, due to the bootstrap capacitor Cb.
  • the function of the node Q n is kept high, the control signal P n is kept at a low level, and the fourth pull-up transistor T21 is kept turned on; at this time, the first clock signal CK is opposite to the second clock signal XCK, and is high.
  • the scan driving signal G n is outputted to a high level, and the corresponding line is scanned.
  • the level signal ST n is also high.
  • the first clock signal CK and the second clock signal XCK enter the next timing.
  • the second clock signal XCK is at a high level, and the corresponding first four stages of the transmitted signal ST n-4 are at a low level.
  • the node Q n becomes a low level, and the first clock signal CK is at a low level.
  • the scan driving signal G n is at a low level, and the scanning of the corresponding line is completed.
  • the control signal P n becomes a high level, and the gate control signal Q n , the scan driving signal G n , and the level transmission signal ST n of the nth stage GOA driving unit are all pulled down again. To the reference low level signal, keep low and maintain the off state.
  • the first clock signal CK and the second clock signal XCK are selected from two different clock signals in a clock signal group, and the clock signal group includes eight high frequency signals.
  • Clock signals CK 1 CK CK 8 ; wherein CK m and CK m+4 are mutually inverted signals (m 1, 2, 3, 4), specifically: CK 1 and CK 5 are mutually inverted signals, CK 2 And CK 6 are mutually inverted signals, CK 3 and CK 7 are mutually inverted signals, and CK 4 and CK 8 are mutually inverted signals.
  • the first clock signal CK cyclically outputs high frequency clock signals CK 1 to CK 8 from CK 5
  • the second clock signal XCK cyclically outputs high frequency clock signals CK 1 to CK 8 from CK 1 .
  • a second pull-up control circuit 10 receives the clock signal XCK is CK. 1, the first pull-up circuit 20 clock signal CK is selected to be received CK 5.
  • there is no corresponding first four stages of the transfer signal STn -4 so the scan start signal STV needs to be input, and similar cases also occur in the second to fourth stage GOA drive units.
  • the period of each high frequency clock signal is T
  • the high level pulse width is T 1 in one period T.
  • the output of the scan drive signal G 1 reduces the interval between the rising edge of the scan start signal (STV) and the first rising edge of the data voltage signal (Date).
  • the high-level pulse width of the first period is T 1m, preferably not less than half of the pulse width of the normal period (the second period is backward), that is,
  • this value becomes 7.5H. Therefore, according to the driving method and driving device of the GOA circuit provided by the present invention, the data buffer time of the initial driving stage is shortened, which is advantageous for reducing the cost of the driving circuit.
  • the driving method and the driving device of the GOA circuit provided in the embodiment of the present invention correspond to a GOA circuit driven by eight high-frequency clock signals, and the first to fourth in the scanning drive of each frame image.
  • the high-frequency pulse width of the first period of the high-frequency clock signals CK 1 to CK 4 is small, and the scan driving signal of the first-stage GOA driving unit is accelerated without affecting the overall output timing and level of the GOA circuit.
  • the output reduces the interval between the rising edge of the scan start signal (STV) and the first rising edge of the data voltage signal (Date), which shortens the data buffer time (Line Buffer), which helps to reduce the cost of the drive circuit. .

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Abstract

一种GOA电路的驱动方法和驱动装置，包括时序控制芯片和GOA电路，该GOA电路包括级联设置的多级GOA驱动单元，该时序控制芯片向每一级GOA驱动单元输入第一时钟信号、第二时钟信号以及恒压电位，驱动该多级GOA驱动单元逐级输出扫描驱动信号；该第一时钟信号和该第二时钟信号选自一时钟信号组中的两个不同时钟信号，该时钟信号组包括八个高频时钟信号CK1～CK8；其中，CKm和CKm+4互为反相信号；每一个高频时钟信号的周期为T，在一个周期T中高电平脉宽为T1；其中，在每一帧图像的扫描驱动中：高频时钟信号CKm的第一个周期的高电平脉宽为T1m，且T1m<T1；m＝1、2、3、4。

Description

GOA电路的驱动方法和驱动装置 技术领域
本发明涉及显示器驱动技术领域,尤其涉及一种GOA电路的驱动方法和驱动装置。
背景技术
平板显示装置具有机身薄、省电、无辐射等众多优点，得到了广泛的应用。现有的平板显示装置主要包括液晶显示装置(Liquid Crystal Display，LCD)及有机电致发光显示装置(Organic Light Emitting Display，OLED)。
主动式液晶显示装置中，每个像素具有一个薄膜晶体管(TFT)，其栅极(Gate)连接至水平扫描线，漏极(Drain)连接至垂直方向的数据线，源极(Source)则连接至像素电极。在水平扫描线上施加足够的电压，会使得该条线上的所有TFT打开，此时该水平扫描线上的像素电极会与垂直方向的数据线连接，从而将数据线上的显示信号电压写入像素，控制不同液晶的透光度进而达到控制色彩的效果。目前主动式液晶显示面板水平扫描线的驱动主要由面板外接的IC来完成，外接的IC可以控制各级水平扫描线的逐级充电和放电。而GOA技术，即Gate Driver on Array(阵列基板行驱动)技术，可以运用液晶显示面板的原有制程将水平扫描线的驱动电路制作在显示区周围的基板上，使之能替代外接IC来完成水平扫描线的驱动。GOA技术能减少外接IC的绑定(bonding)工序，有机会提升产能并降低产品成本，而且可以使液晶显示面板更适合制作窄边框或无边框的显示产品。
现有的GOA驱动电路，通常包括级联的多个GOA单元，每一级GOA单元对应驱动一级水平扫描线。GOA单元的主要结构包括上拉电路(Pull-up part)，上拉控制电路(Pull-up control part)，传递电路(Transfer Part)和下拉维持电路(Pull-down Holding Part)，以及负责电位抬升的自举(Boast)电容。上拉电路主要负责将时钟信号(Clock)输出为栅极(Gate)信号；上拉控制电路负责控制上拉电路的打开时间，一般连接前面级GOA电路传递过来的传递信号或者 Gate信号；下拉维持电路则负责将Gate输出信号和上拉电路的Gate信号(通常称为Q点)维持(Holding)在关闭状态(即低电平电位)，自举电容(C boast)则负责Q点的二次抬升，这样有利于上拉电路的Gate信号输出。
在GOA电路的中，数据缓冲时间(Line Buffer)的定义是扫描起始信号(STV)的上升沿到显示装置的数据驱动器输出的数据电压信号(Date)的第一上升沿的间隔时间。数据缓冲时间越长，则数据驱动电路的成本越高，这样就不利于显示装置成本的降低。
发明内容
为了解决上述现有技术存在的问题，本发明的目的在于提供一种减小数据缓冲时间(Line Buffer)的GOA电路的驱动方法和驱动装置。
为了实现上述目的，本发明采用了如下的技术方案：
一种GOA电路的驱动方法，所述GOA电路包括级联设置的多级GOA驱动单元，所述驱动方法包括：向每一级GOA驱动单元输入第一时钟信号、第二时钟信号以及恒压电位，控制所述多级GOA驱动单元逐级输出扫描驱动信号，其中，第一至第四级GOA驱动单元还输入扫描起始信号；其中，所述第一时钟信号和所述第二时钟信号选自一时钟信号组中的两个不同时钟信号，所述时钟信号组包括八个高频时钟信号CK1～CK8，其中，CKm和CKm+4互为反相信号；所述第一时钟信号自CK5开始循环输出高频时钟信号CK1～CK8，所述第二时钟信号自CK1开始循环输出高频时钟信号CK1～CK8；其中，每一个高频时钟信号的周期为T，在一个周期T中高电平脉宽为T1；其中，在每一帧图像的扫描驱动中：高频时钟信号CKm的第一个周期的高电平脉宽为T1m，且T1m<T1；m＝1、2、3、4。
其中，
Figure PCTCN2017071330-appb-000001
其中，
Figure PCTCN2017071330-appb-000002
其中，高频时钟信号CK1的第一个周期相比于所述扫描驱动起始信号滞后的时间为H；其中，T＝8H，T1＝3.2H。
其中，每一级GOA驱动单元包括上拉控制电路、上拉电路、级传电路、自举电容以及下拉维持电路，所述上拉控制电路根据所述第二时钟信号和前四级 扫描驱动信号输出本级栅极控制信号，所述上拉电路根据所述第一时钟信号和本级栅极控制信号输出本级扫描驱动信号，所述级传电路根据所述第一时钟信号和本级栅极控制信号输出本级级传信号；所述下拉维持电路用于在本级GOA驱动单元处于非驱动时间时，将所述本级栅极控制信号和所述本级扫描驱动信号拉低至低电平。
本发明的另一方面是提供一种GOA电路的驱动装置，其包括时序控制芯片和GOA电路，所述GOA电路包括级联设置的多级GOA驱动单元，所述时序控制芯片向每一级GOA驱动单元输入第一时钟信号、第二时钟信号以及恒压电位，驱动所述多级GOA驱动单元逐级输出扫描驱动信号，其中，所述时序控制芯片还向第一至第四级GOA驱动单元输入扫描起始信号；其中，所述第一时钟信号和所述第二时钟信号选自一时钟信号组中的两个不同时钟信号，所述时钟信号组包括八个高频时钟信号CK1～CK8；其中，CKm和CKm+4互为反相信号；所述第一时钟信号自CK5开始循环输出高频时钟信号CK1～CK8，所述第二时钟信号自CK1开始循环输出高频时钟信号CK1～CK8；其中，每一个高频时钟信号的周期为T，在一个周期T中高电平脉宽为T1；其中，在每一帧图像的扫描驱动中：高频时钟信号CKm的第一个周期的高电平脉宽为T1m，且T1m<T1；m＝1、2、3、4。
其中，
Figure PCTCN2017071330-appb-000003
其中，
Figure PCTCN2017071330-appb-000004
其中，高频时钟信号CK1的第一个周期相比于所述扫描驱动起始信号滞后的时间为H；其中，T＝8H，T1＝3.2H。
其中，每一级GOA驱动单元包括上拉控制电路、上拉电路、级传电路、自举电容以及下拉维持电路，所述上拉控制电路根据所述第二时钟信号和前四级扫描驱动信号输出本级栅极控制信号，所述上拉电路根据所述第一时钟信号和本级栅极控制信号输出本级扫描驱动信号，所述级传电路根据所述第一时钟信号和本级栅极控制信号输出本级级传信号；所述下拉维持电路用于在本级GOA驱动单元处于非驱动时间时，将所述本级栅极控制信号和所述本级扫描驱动信号拉低至低电平。
本发明实施例中提供的GOA电路的驱动方法和驱动装置，对应采用八个高 频时钟信号驱动的GOA电路，在每一帧图像的扫描驱动中，将第一至第四个高频时钟信号CK1～CK4的第一个周期的高电平脉宽较小，在不影响GOA电路整体输出时序和电平的情况下，加快第一级GOA驱动单元的扫描驱动信号的输出，减小了扫描起始信号(STV)的上升沿到数据电压信号(Date)的第一上升沿的间隔时间，即缩短了数据缓冲时间(Line Buffer)，有利于降低驱动电路的成本。
附图说明
图1是本发明实施例提供的GOA电路的驱动装置的结构示意图；
图2是本发明实施例中的GOA驱动单元的电路图；
图3是本发明实施例提供的GOA电路的驱动方法的信号波形图。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚，下面结合附图对本发明的具体实施方式进行详细说明。这些优选实施方式的示例在附图中进行了例示。附图中所示和根据附图描述的本发明的实施方式仅仅是示例性的，并且本发明并不限于这些实施方式。
在此，还需要说明的是，为了避免因不必要的细节而模糊了本发明，在附图中仅仅示出了与根据本发明的方案密切相关的结构和/或处理步骤，而省略了与本发明关系不大的其他细节。
本实施例提供了一种GOA电路的驱动装置，如图1所示，所述驱动装置包括时序控制芯片(Tcon)1和GOA电路2，所述GOA电路2包括级联设置的多级GOA驱动单元GOA1～GOAN，所述时序控制芯片1向每一级GOA驱动单元GOA1～GOAN输入第一时钟信号CK、第二时钟信号XCK以及恒压电位VSS，驱动所述多级GOA驱动单元GOA1～GOAN逐级输出扫描驱动信号G1～GN，提供到显示面板中。其中，所述时序控制芯片1还向第一至第四级GOA驱动单元GOA1～GOA4输入扫描起始信号STV。
其中，如图2所示，本实施例中，每一级GOA驱动单元包括上拉控制电路10、上拉电路20、级传电路30、自举电容Cb以及下拉维持电路40。所述上拉控制电路10根据所述第二时钟信号XCK和前四级扫描驱动信号STn-4输出本级栅极控制信号Qn，所述上拉电路20根据所述第一时钟信号CK和本级栅极控制信号Qn输出本级扫描驱动信号Gn，所述级传电路30根据所述第一时钟信号CK 和本级栅极控制信号Qn输出本级级传信号STn；所述下拉维持电路40用于在本级GOA驱动单元处于非驱动时间时，将所述本级栅极控制信号Qn和所述本级扫描驱动信号Gn拉低至低电平(即恒压电位VSS)。需要说明的是，当n-4小于零时，STn-4不存在，此时应当采用时序控制芯片1提供的STV信号代替。
具体地，如图2所示，所述上拉控制电路10包括第一上拉晶体管T11和第二上拉晶体管T12，所述第一上拉晶体管T11和第二上拉晶体管T12的栅极相互连接并接收第二时钟信号XCK，所述第一上拉晶体管T11的源极接收对应的前四级传递信号STn-4，所述第一上拉晶体管T11的漏极与所述第二上拉晶体管T12的源极相互连接，所述第二上拉晶体管T12的漏极作为上拉控制电路10输出端，输出本级栅极控制信号Qn。进一步地，在本实施例中，如图2所示，为了使得电路更加稳定，所述上拉控制电路10还包括第三上拉晶体管T13，所述第三上拉晶体管T13的栅极连接到所述第二上拉晶体管T12的漏极，源极连接至所述所述第一上拉晶体管T11的漏极，栅极连接至所述上拉电路20的输出端。需要说明的是，所述第三上拉晶体管T13在导通时，其源极和漏极之间的电阻很大，电流很小，以不影响连接在其漏极的上拉电路20的输出端的电位为准。
具体地，如图2所示，所述上拉电路20包括第四上拉晶体管T21，所述第四上拉晶体管T21的栅极连接至所述上拉控制电路10输出端，接收栅极控制信号Qn，源极连接至第一时钟信号CK，漏极作为所述上拉电路20的输出端，输出本级扫描驱动信号Gn。
具体地，如图2所示，所述自举电容Cb连接在所述上拉控制电路10的输出端和所述上拉电路20的输出端之间。即，自举电容Cb的两端分别连接栅极控制信号Qn和扫描驱动信号Gn，所述自举电容Cb的作用是在Qn为高电平时，存储晶体管T21栅端电压，当Gn输出高电平，自举电容Cb可以二次抬升晶体管T21的栅极的电位，以保证晶体管T21可靠地开启与输出扫描驱动信号。
具体地，如图2所示，所述级传电路30包括传递晶体管T22，所述传递晶体管T22的栅极连接至所述上拉控制电路10输出端，接收栅极控制信号Qn，源极连接至第一时钟信号CK，漏极作为所述级传电路30的输出端，输出本级级传信号STn。输出本级级传信号STn是用于控制后四级的上拉控制单元，通过由传递信号控制上拉控制单元，避免使用扫描驱动信号来控制这一动作，使得扫描驱动信号更加稳定。
所述下拉维持电路40主要是用于在本级的GOA驱动单元处于非输出时序 时，将电路中的一些主要节点(例如栅极控制信号Qn、扫描驱动信号Gn和级传信号STn)的电位拉低至低电平。本实施例中，所述下拉维持单元40包括第一下拉维持电路41和第二下拉维持电路42，第一下拉维持电路41和第二下拉维持电路42交替地将所述栅极控制信号Qn、扫描驱动信号Gn和级传信号STn连通至基准低电平信号VSS，维持在关闭状态。
具体地，如图2所示，所述第一下拉维持电路41和第二下拉维持电路42具有相同的电路结构，所述第一下拉维持电路41和第二下拉维持电路42分别包括第一晶体管T31、T32、第二晶体管T23、T24、第三晶体管T41、T42、第四晶体管T51、T61、第五晶体管T52、T62、第六晶体管T53、T63和第七晶体管T54、T64。其中，第一晶体管T31、T32、第二晶体管T23、T24、第三晶体管T41、T42的漏极均连接至基准低电平信号VSS，第一晶体管T31、T32、第二晶体管T23、T24、第三晶体管T41、T42的栅极相互连接并同时接收控制信号Pn、Kn，第一晶体管T31、T32的源极连接至扫描驱动信号Gn，第二晶体管T23、T24的源极连接至级传信号STn，第三晶体管T41、T42的源极连接至栅极控制信号Qn。所述第四晶体管T51、T61的栅极和源极连接并接收下拉时钟信号LC1、LC2，漏极与所述第五晶体管T52、T62的源极连接；所述第五晶体管T52、T62的栅极连接至所述栅极控制信号Qn，漏极连接至基准低电平信号VSS；所述第六晶体管T53、T63的源极与所述第四晶体管T51、T61的源极连接，接收下拉时钟信号LC1、LC2，栅极与所述第四晶体管T51、T61的漏极连接，漏极与所述第七晶体管T54、T64的源极连接；所述第七晶体管T54、T64的栅极连接至所述栅极控制信号Qn，漏极连接至基准低电平信号VSS。其中，所述第六晶体管T53、T63的漏极输出控制信号控制信号Pn、Kn，连接至第一晶体管T31、T32、第二晶体管T23、T24、第三晶体管T41、T42的栅极。
其中，所述第一下拉维持电路41接收的第一下拉时钟信号LC1与所述第二下拉维持电路42接收的第二下拉时钟信号LC2的高低电平逻辑相反的低频信号，即，当LC1为高电平，则LC2为低电平；反之，当LC1为低电平，则LC2为高电平。
进一步地，在本实施例中，如图2所示，为了使得电路更加稳定，所述基准低电平信号VSS包括第一基准低电平信号Vss1和第二基准低电平信号Vss2，所述第一晶体管T31、T32、第二晶体管T23、T24、第三晶体管T41、T42的漏极分别连接至所述第一基准低电平信号Vss1，所述第五晶体管T52、T62的漏 极连接至所述第一基准低电平信号Vss1；所述第七晶体管T54、T64的漏极连接至所述第二基准低电平信号Vss2。其中，所述第一基准低电平信号Vss1的电位低于所述第二基准低电平信号Vss2的电位。
如上实施例所提供的GOA电路的驱动装置的驱动过程如下：
(1)、在传递到第n级GOA驱动单元之前，本实施例以第一下拉时钟信号LC1为高电平和第二下拉时钟信号LC2为低电平为例，此时控制信号Pn为高电平、Kn为低电平，由第一下拉维持电路41维持各节点电压。第n级GOA驱动单元的栅极控制信号Qn、扫描驱动信号Gn和级传信号STn都被拉低至基准低电平信号。
(2)、在传递到第n级GOA驱动单元时，第二时钟信号XCK和对应的前四级传递信号STn-4为高电平，节点Qn为高电平，第四上拉晶体管T21导通；由于第一时钟信号CK和第二时钟信号XCK反相，为低电平，此时扫描驱动信号Gn为低电平；而由于节点Qn为高电平，控制信号Pn被拉低为低电平，第n级GOA驱动单元的栅极控制信号Qn、扫描驱动信号Gn和级传信号STn与基准低电平信号之间的连接被切断。
(3)、第一时钟信号CK和第二时钟信号XCK进入下一个时序，此时，第二时钟信号XCK和对应的前四级传递信号STn-4为低电平，由于自举电容Cb的作用，节点Qn保持高电平，控制信号Pn保持为低电平，第四上拉晶体管T21保持导通；此时，第一时钟信号CK与第二时钟信号XCK相反，为高电平，扫描驱动信号Gn为输出为高电平，进行相应行的扫描。级传信号STn也为高电平。
(4)、第一时钟信号CK和第二时钟信号XCK进入下一个时序，此时，第二时钟信号XCK为高电平，而对应的前四级传递信号STn-4为低电平，节点Qn变为低电平，第一时钟信号CK为低电平，此时扫描驱动信号Gn为低电平，完成相应行的扫描。而由于节点Qn为低电平，控制信号Pn变为高电平，第n级GOA驱动单元的栅极控制信号Qn、扫描驱动信号Gn和级传信号STn都重新被拉低至基准低电平信号，保持低电位，维持关闭状态。
具体地，参阅图3的信号波形图，所述第一时钟信号CK和所述第二时钟信号XCK选自一时钟信号组中的两个不同时钟信号，所述时钟信号组包括八个高频时钟信号CK1～CK8；其中，CKm和CKm+4互为反相信号(m＝1、2、3、4)，具体为：CK1和CK5互为反相信号，CK2和CK6互为反相信号，CK3和CK7互 为反相信号，CK4和CK8互为反相信号。所述第一时钟信号CK自CK5开始循环输出高频时钟信号CK1～CK8，所述第二时钟信号XCK自CK1开始循环输出高频时钟信号CK1～CK8。例如，对于第一级GOA驱动单元，上拉控制电路10接收的第二时钟信号XCK为CK1，上拉电路20接收的第一时钟信号CK则选择为CK5。进一步地，对于第一级GOA驱动单元，没有对应的前四级传递信号STn-4，因此需要输入扫描起始信号STV，类似的情况还发生在第二至第四级GOA驱动单元。
其中，对于八个高频时钟信号CK1～CK8，每一个高频时钟信号的周期为T，在一个周期T中高电平脉宽为T1。
如图3所示，在本实施例中，为了缩短了数据缓冲时间(Line Buffer)，在每一帧图像的扫描驱动中：高频时钟信号CKm的第一个周期的高电平脉宽为T1m，且T1m<T1；m＝1、2、3、4。即减小CK1～CK4的第一个周期的高电平脉宽，由此可以使得第一级GOA驱动单元的Q点电压更快地完成第一次爬升，加快第一级GOA驱动单元的扫描驱动信号G1的输出，减小了扫描起始信号(STV)的上升沿到数据电压信号(Date)的第一上升沿的间隔时间。
其中，第一个周期的高电平脉宽为T1m最好是不小于正常周期(第二周期往后)的脉宽的一半，即
Figure PCTCN2017071330-appb-000005
在本实施例中，T1m(m＝1、2、3、4)的设定具体为
Figure PCTCN2017071330-appb-000006
具体地，参阅图3，高频时钟信号CK1的第一个周期相比于所述扫描驱动起始信号滞后的时间为H；其中，高频时钟信号的周期T＝8H，脉宽T1＝3.2H。
以上实施例中，通过将T1m(m＝1、2、3、4)的设定具体为
Figure PCTCN2017071330-appb-000007
Figure PCTCN2017071330-appb-000008
扫描起始信号(STV)的上升沿到数据电压信号(Date)的第一上升沿的间隔时间减小为5.9H。相对于传统的GOA电路的驱动方式，即T11＝T12＝T13＝T14＝T1，这一数值变为7.5H。因此，按照本发明提供的GOA电路的驱动方法和驱动装置，缩短了初始驱动阶段的数据缓冲时间(Line Buffer)，有利于降低驱动电路的成本。
综上所述，本发明实施例中提供的GOA电路的驱动方法和驱动装置，对应采用八个高频时钟信号驱动的GOA电路，在每一帧图像的扫描驱动中，将第一至第四个高频时钟信号CK1～CK4的第一个周期的高电平脉宽较小，在不影响 GOA电路整体输出时序和电平的情况下，加快第一级GOA驱动单元的扫描驱动信号的输出，减小了扫描起始信号(STV)的上升沿到数据电压信号(Date)的第一上升沿的间隔时间，即缩短了数据缓冲时间(Line Buffer)，有利于降低驱动电路的成本。
需要说明的是，在本文中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括所述要素的过程、方法、物品或者设备中还存在另外的相同要素。
以上所述仅是本申请的具体实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本申请原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本申请的保护范围。

Claims (20)

  1. 一种GOA电路的驱动方法，所述GOA电路包括级联设置的多级GOA驱动单元，所述驱动方法包括：向每一级GOA驱动单元输入第一时钟信号、第二时钟信号以及恒压电位，控制所述多级GOA驱动单元逐级输出扫描驱动信号，其中，第一至第四级GOA驱动单元还输入扫描起始信号；其中，
    所述第一时钟信号和所述第二时钟信号选自一时钟信号组中的两个不同时钟信号，所述时钟信号组包括八个高频时钟信号CK1～CK8；其中，CKm和CKm+4互为反相信号；
    所述第一时钟信号自CK5开始循环输出高频时钟信号CK1～CK8，所述第二时钟信号自CK1开始循环输出高频时钟信号CK1～CK8；其中，每一个高频时钟信号的周期为T，在一个周期T中高电平脉宽为T1；
    其中，在每一帧图像的扫描驱动中：高频时钟信号CKm的第一个周期的高电平脉宽为T1m，且T1m<T1；m＝1、2、3、4。
  2. 根据权利要求1所述的GOA电路的驱动方法，其中，
    Figure PCTCN2017071330-appb-100001
  3. 根据权利要求1所述的GOA电路的驱动方法，其中，
    Figure PCTCN2017071330-appb-100002
    Figure PCTCN2017071330-appb-100003
  4. 根据权利要求3所述的GOA电路的驱动方法，其中，高频时钟信号CK1的第一个周期相比于所述扫描驱动起始信号滞后的时间为H；其中，T＝8H，T1＝3.2H。
  5. 根据权利要求4所述的GOA电路的驱动方法，其中，每一级GOA驱动单元包括上拉控制电路、上拉电路、级传电路、自举电容以及下拉维持电路，所述上拉控制电路根据所述第二时钟信号和前四级传递信号输出本级栅极控制信号，所述上拉电路根据所述第一时钟信号和本级栅极控制信号输出本级扫描驱动信号，所述级传电路根据所述第一时钟信号和本级栅极控制信号输出本级级传信号；所述下拉维持电路用于在本级GOA驱动单元处于非驱动时间时，将所述本级栅极控制信号和所述本级扫描驱动信号拉低至低电平。
  6. 根据权利要求5所述的GOA电路的驱动方法，其中，所述上拉控制电 路包括第一上拉晶体管和第二上拉晶体管，所述第一上拉晶体管和第二上拉晶体管的栅极相互连接并接收所述第二时钟信号，所述第一上拉晶体管的源极接收对应的前四级传递信号，所述第一上拉晶体管的漏极与所述第二上拉晶体管的源极相互连接，所述第二上拉晶体管的漏极作为所述上拉控制电路输出端，输出本级栅极控制信号。
  7. 根据权利要求5所述的GOA电路的驱动方法，其中，所述上拉电路包括第四上拉晶体管，所述第四上拉晶体管的栅极连接至所述上拉控制电路输出端，接收栅极控制信号，源极连接至所述第一时钟信号，漏极作为所述上拉电路的输出端，输出本级扫描驱动信号。
  8. 根据权利要求5所述的GOA电路的驱动方法，其中，所述级传电路包括传递晶体管，所述传递晶体管的栅极连接至所述上拉控制电路输出端，接收栅极控制信号，源极连接至所述第一时钟信号，漏极作为所述级传电路的输出端，输出本级级传信号。
  9. 根据权利要求5所述的GOA电路的驱动方法，其中，所述下拉维持电路包括第一下拉维持电路和第二下拉维持电路，第一下拉维持电路和第二下拉维持电路交替地将所述栅极控制信号和扫描驱动信号拉低至低电平；
    所述第一下拉维持电路和第二下拉维持电路具有相同的电路结构，所述第一下拉维持电路和第二下拉维持电路分别包括第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管和第七晶体管；其中，第一晶体管、第二晶体管、第三晶体管的漏极均连接至基准低电平信号，第一晶体管、第二晶体管、第三晶体管的栅极相互连接并同时接收控制信号，第一晶体管的源极连接至扫描驱动信号，第二晶体管的源极连接至级传信号，第三晶体管的源极连接至栅极控制信号；所述第四晶体管的栅极和源极连接并接收下拉时钟信号，漏极与所述第五晶体管的源极连接；所述第五晶体管的栅极连接至所述栅极控制信号，漏极连接至基准低电平信号；所述第六晶体管的源极与所述第四晶体管的源极连接，接收下拉时钟信号，栅极与所述第四晶体管的漏极连接，漏极与所述第七晶体管的源极连接，所述第七晶体管的栅极连接至所述栅极控制信号，漏极连接至基准低电平信号；其中，所述第六晶体管的漏极输出控制信号控制信号，连接至第一晶体管、第二晶体管、第三晶体管的栅极；
    其中，所述第一下拉维持电路接收的第一下拉时钟信号与所述第二下拉维持电路接收的第二下拉时钟信号的高低电平逻辑相反。
  10. 根据权利要求5所述的GOA电路的驱动方法，其中，所述自举电容的一端连接至所述上拉控制电路的输出端，另一端连接至所述所述上拉电路的输出端。
  11. 一种GOA电路的驱动装置，包括时序控制芯片和GOA电路，所述GOA电路包括级联设置的多级GOA驱动单元，所述时序控制芯片向每一级GOA驱动单元输入第一时钟信号、第二时钟信号以及恒压电位，驱动所述多级GOA驱动单元逐级输出扫描驱动信号，其中，所述时序控制芯片还向第一至第四级GOA驱动单元输入扫描起始信号；其中，
    所述第一时钟信号和所述第二时钟信号选自一时钟信号组中的两个不同时钟信号，所述时钟信号组包括八个高频时钟信号CK1～CK8；其中，CKm和CKm+4互为反相信号；
    所述第一时钟信号自CK5开始循环输出高频时钟信号CK1～CK8，所述第二时钟信号自CK1开始循环输出高频时钟信号CK1～CK8；其中，每一个高频时钟信号的周期为T，在一个周期T中高电平脉宽为T1；
    其中，在每一帧图像的扫描驱动中：高频时钟信号CKm的第一个周期的高电平脉宽为T1m，且T1m<T1；m＝1、2、3、4。
  12. 根据权利要求11所述的GOA电路的驱动装置，其中，
    Figure PCTCN2017071330-appb-100004
  13. 根据权利要求11所述的GOA电路的驱动装置，其中，
    Figure PCTCN2017071330-appb-100005
    Figure PCTCN2017071330-appb-100006
  14. 根据权利要求13所述的GOA电路的驱动装置，其中，高频时钟信号CK1的第一个周期相比于所述扫描驱动起始信号滞后的时间为H；其中，T＝8H，T1＝3.2H。
  15. 根据权利要求14所述的GOA电路的驱动装置，其中，每一级GOA驱动单元包括上拉控制电路、上拉电路、级传电路、自举电容以及下拉维持电路，所述上拉控制电路根据所述第二时钟信号和前四级传递信号输出本级栅极控制信号，所述上拉电路根据所述第一时钟信号和本级栅极控制信号输出本级扫描驱动信号，所述级传电路根据所述第一时钟信号和本级栅极控制信号输出本级级传信号；所述下拉维持电路用于在本级GOA驱动单元处于非驱动时间时，将 所述本级栅极控制信号和所述本级扫描驱动信号拉低至低电平。
  16. 根据权利要求15所述的GOA电路的驱动装置，其中，所述上拉控制电路包括第一上拉晶体管和第二上拉晶体管，所述第一上拉晶体管和第二上拉晶体管的栅极相互连接并接收所述第二时钟信号，所述第一上拉晶体管的源极接收对应的前四级传递信号，所述第一上拉晶体管的漏极与所述第二上拉晶体管的源极相互连接，所述第二上拉晶体管的漏极作为所述上拉控制电路输出端，输出本级栅极控制信号。
  17. 根据权利要求15所述的GOA电路的驱动装置，其中，所述上拉电路包括第四上拉晶体管，所述第四上拉晶体管的栅极连接至所述上拉控制电路输出端，接收栅极控制信号，源极连接至所述第一时钟信号，漏极作为所述上拉电路的输出端，输出本级扫描驱动信号。
  18. 根据权利要求15所述的GOA电路的驱动装置，其中，所述级传电路包括传递晶体管，所述传递晶体管的栅极连接至所述上拉控制电路输出端，接收栅极控制信号，源极连接至所述第一时钟信号，漏极作为所述级传电路的输出端，输出本级级传信号。
  19. 根据权利要求15所述的GOA电路的驱动装置，其中，所述下拉维持电路包括第一下拉维持电路和第二下拉维持电路，第一下拉维持电路和第二下拉维持电路交替地将所述栅极控制信号和扫描驱动信号拉低至低电平；
    所述第一下拉维持电路和第二下拉维持电路具有相同的电路结构，所述第一下拉维持电路和第二下拉维持电路分别包括第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管和第七晶体管；其中，第一晶体管、第二晶体管、第三晶体管的漏极均连接至基准低电平信号，第一晶体管、第二晶体管、第三晶体管的栅极相互连接并同时接收控制信号，第一晶体管的源极连接至扫描驱动信号，第二晶体管的源极连接至级传信号，第三晶体管的源极连接至栅极控制信号；所述第四晶体管的栅极和源极连接并接收下拉时钟信号，漏极与所述第五晶体管的源极连接；所述第五晶体管的栅极连接至所述栅极控制信号，漏极连接至基准低电平信号；所述第六晶体管的源极与所述第四晶体管的源极连接，接收下拉时钟信号，栅极与所述第四晶体管的漏极连接，漏极与所述第七晶体管的源极连接，所述第七晶体管的栅极连接至所述栅极控制信号，漏极连接至基准低电平信号；其中，所述第六晶体管的漏极输出控制信号控制信号，连接至第一晶体管、第二晶体管、第三晶体管的栅极；
    其中，所述第一下拉维持电路接收的第一下拉时钟信号与所述第二下拉维持电路接收的第二下拉时钟信号的高低电平逻辑相反。
  20. 根据权利要求15所述的GOA电路的驱动装置，其中，所述自举电容的一端连接至所述上拉控制电路的输出端，另一端连接至所述所述上拉电路的输出端。
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