WO2018107533A1 - 一种栅极驱动电路及驱动方法、显示装置 - Google Patents

一种栅极驱动电路及驱动方法、显示装置 Download PDF

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WO2018107533A1
WO2018107533A1 PCT/CN2016/113027 CN2016113027W WO2018107533A1 WO 2018107533 A1 WO2018107533 A1 WO 2018107533A1 CN 2016113027 W CN2016113027 W CN 2016113027W WO 2018107533 A1 WO2018107533 A1 WO 2018107533A1
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Prior art keywords
node
transistor
signal
gate
pull
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English (en)
French (fr)
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李亚锋
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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Priority to US15/327,305 priority Critical patent/US10657919B2/en
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a gate driving circuit and a driving method thereof, and a display device manufactured according to the gate driving circuit and the driving method.
  • TFT-LCD Thin Film Transistor Liquid Crystal Display
  • OLED Active Matrix Driving OLED
  • the display device is generally provided with a Gate Driver on Array circuit, which uses a thin film transistor array process in a conventional thin film transistor liquid crystal display to fabricate a gate row scan driving signal circuit on a thin film transistor array substrate.
  • the output terminal of each stage of the integrated driving circuit is connected to a row of gate lines for outputting a gate scan signal to the gate line to realize progressive scanning of the gate lines.
  • the existing connection mode of the gate integrated driving circuit when the number of stages of the gate integrated driving circuit increases, the signal attenuation of the upper and lower stages occurs, and once the level transmission signal is attenuated, the gate integration is caused.
  • the pre-charging ability of a certain stage of the driving circuit to the Q point is weakened, thereby causing the output of the gate driving signal of the current stage to be attenuated, and finally affecting the charging of the pixel electrode in the plane.
  • One of the present invention to solve the technical problem is to provide a gate drive circuit which can be integrated in a multistage driver circuit stage transfer gate, each gate driving signal G n are capable of a stable output.
  • another technical problem to be solved by the present invention is to reduce the probability of leakage of the precharge node in the gate drive circuit.
  • a first aspect of the present invention provides a gate driving circuit having a multi-stage structure, wherein the nth-level circuit includes:
  • the nth stage circuit includes:
  • a Q n node pre-charging unit that controls signal transmission between the high voltage signal VGH and the Q n node under the action of the first input signal Q n-1 and the second output signal Q n+1 , thereby the Q n node Precharged;
  • a Q n node pull-up unit electrically connected between the Q n node and the output terminal G n of the current stage for maintaining a high state of the Q n node;
  • a Q n node pull-down unit electrically connected between the low voltage signal VGL and the Q n node for controlling signal transmission between the low voltage signal VGL and the Q n node under the action of the P n node voltage signal, thereby maintaining The low state of the Q n node;
  • a P n node pull-up unit electrically connected between the high voltage signals VGH and P n nodes for controlling signal transmission between the high voltage signals VGH and P n nodes under the action of the first clock signal, thereby maintaining The high state of the P n node;
  • a P n node pull-down unit electrically connected between the low voltage signals VGL and P n nodes for controlling signal transmission between the low voltage signals VGL and P n nodes under the action of the Q n node voltage signal, thereby maintaining The low state of the P n node;
  • a G n output unit electrically connected between the second clock signal and the output terminal G n of the current stage for controlling the second clock signal and the output terminal G n of the current stage under the action of the voltage signal of the Q n node Signal transmission, thereby outputting a G n high level signal;
  • a G n output pull-down unit electrically connected between the low voltage signal VGL and the output terminal G n of the current stage for controlling the low voltage signal VGL and the output terminal G n of the current stage under the action of the voltage signal of the P n node signal transmission between, thereby maintaining the state of the low level of the output of circuit G n.
  • the first input signal Q n-1 is a Q n-1 node output signal in the pre-drive circuit
  • the second input signal Q n+1 is a Q n+1 node output signal in the subsequent stage drive circuit.
  • the Q n node pre-charging unit includes a first transistor, a second transistor, a third transistor, and a fourth transistor; a source of the first transistor is coupled to the high voltage signal VGH, and a gate of the first transistor Connected to the second output signal Q n+1 , the drain of the first transistor is connected to the source of the second transistor; the gate of the second transistor is connected to the first input signal Q n-1 , and the drain of the second transistor is connected The source of the three transistors is connected to the Q n node at the same time; the gate of the third transistor is connected to the first input signal Q n-1 , the drain of the third transistor is connected to the source of the fourth transistor; the fourth transistor The gate is coupled to the second output signal Qn +1 , and the drain of the fourth transistor is coupled to the high voltage signal VGH.
  • the Q n node pull-up unit includes a first capacitor, and the first capacitor is respectively connected to the Q n node and the output terminal G n .
  • the Q n node pull-down unit includes a fifth transistor, a source of the fifth transistor is connected to the Q n node, a gate of the fifth transistor is connected to the P n node, and a drain of the fifth transistor is connected to the low voltage signal. VGL.
  • the P n node pull-up unit includes a sixth transistor and a second capacitor, a source of the sixth transistor is connected to the high voltage signal VGH, and a gate of the sixth transistor is connected to the first clock signal, The drain of the six transistors is connected to the P n node; the two ends of the second capacitor are respectively connected to the P n node and the low voltage signal VGL.
  • the P n node pull-down unit includes a seventh transistor, a source of the seventh transistor is connected to the P n node, a gate of the seventh transistor is connected to the Q n node, and a drain of the seventh transistor is low. Voltage signal VGL.
  • the G n output unit includes an eighth transistor, a source of the eight transistor is connected to the second clock signal, a gate of the eighth transistor is connected to the Q n node, and a drain of the eighth transistor is connected to the output end. G n .
  • the output terminal G n pull-down unit includes a ninth transistor, a source of said ninth transistor is connected to an output terminal G n, the gate of the ninth transistor is connected to the node P n, the drain of the ninth transistor Connect the low voltage signal VGL.
  • a gate driving method comprising the following stages in performing forward and reverse bidirectional scanning:
  • the forward scan phase includes:
  • stage a when the first input signal Q n-1 and the second input signal Q n+1 overlap to a high level, the first and second transistors are turned on in series, and the third and fourth transistors are also turned on in series, and at the same time, Q n The node is precharged;
  • Phase b in phase a, the Q n node is precharged, the first capacitor C1 in the Q n node pullup unit maintains the Q n node in a high state, and the eighth transistor in the G n output cell is in a conducting state high level second clock signal to the output terminal G n;
  • phase c the first capacitor in the Q n node pull-up unit continues to maintain the Q n node in a high state, while the low level of the second clock signal pulls the G n output terminal low when the first input
  • the signal Q n-1 and the second input signal Q n+1 are simultaneously at a high level
  • the first, second, third, and fourth transistors are all in a series conduction state, and the Q n node is supplementally charged
  • stage d when the first clock signal is high, the sixth transistor in the P n node pull-up unit is in an on state, the P n node level is pulled high, and the fifth transistor in the Q n node pull-down unit is turned on. Pass, at this time the Q n node level is pulled down to the low voltage signal VGL;
  • stage e when the Q n node becomes a low level, the seventh transistor of the P n node pull-down unit is in an off state, and when the first clock jumps to a high level, the sixth transistor is turned on, and the P n node is charged, then
  • the ninth transistor of the five-transistor and the G n output pull-down unit are both in an on state, which can ensure the stability of the low level of the Q n node and the output terminal G n , and the second capacitor has a certain high level to the P n node. Keep it alive.
  • the reverse scan phase includes:
  • phase 1 when the first input signal Q n-1 and the second input signal Q n+1 overlap to a high level, the first and second transistors are turned on in series, and the third and fourth transistors are also turned on in series, and at the same time, Q n The node is precharged;
  • phase 2 in phase 1, the Q n node is precharged, the first capacitor C1 in the Q n node pullup unit maintains the Q n node in a high state, and the eighth transistor T8 in the G n output unit is turned on. state, the high-level second clock signal to the output terminal G n;
  • phase 3 the first capacitor C1 in the Q n- node pull-up unit continues to maintain the Q n node in a high state, and at this time, the low level of the second clock signal pulls the G n output terminal low, when the first When the input signal Q n-1 and the second input signal Q n+1 are simultaneously at a high level, the first, second, third, and fourth transistors are all in series conduction state, and the Q n node is supplementally charged;
  • phase 4 when the first clock signal is high, the sixth transistor T6 in the P n node pull-up unit is in an on state, the P n node level is pulled high, and the fifth transistor in the Q n node pull-down unit T5 is turned on, at which time the Q n node level is pulled down to the low voltage signal VGL;
  • phase 5 when the Q n node becomes a low level, the seventh transistor T7 of the P n node pull-down unit is in an off state, and when the first clock jumps to a high level, the sixth transistor T6 is turned on, and the P n node is charged. Then, the ninth transistor T9 of the five-transistor T5 and the G n output pull-down unit are both in an on state, which can ensure the stability of the low level of the Q n node and the output terminal G n , and the second capacitor C2 to the P n node The high level has a certain holding effect.
  • a third aspect of the invention provides a display device comprising the gate drive circuit of any of the above embodiments.
  • the gate driving circuit of the present invention for the nth stage circuit, the high voltage when the Q n-1 node output signal in the pre-drive circuit and the Q n+1 node output signal in the post-drive circuit overlap are used. Normally, the n nth circuit Q n node is precharged, which can greatly improve the stability of the G n output of the nth stage circuit. At the same time, the first and second transistors are connected in series, and the third and fourth transistors are connected in series to greatly reduce the probability of leakage of the Q n node.
  • FIG. 2 is a timing diagram of forward scanning of a gate driving circuit in the prior art
  • FIG. 3 is a timing diagram of reverse scanning of a gate driving circuit in the prior art
  • FIG. 4 is a gate drive circuit in accordance with the present invention.
  • Figure 5 is a timing diagram of forward scanning of a gate driving circuit in accordance with the present invention.
  • Figure 6 is a timing diagram of a reverse scan of a gate drive circuit in accordance with the present invention.
  • First input signal Q n-1 12. Second output signal Q n+1 ;
  • FIG. 1 is a circuit structure of a certain stage circuit unit in a conventional gate integrated driving circuit.
  • two nodes Q and P are introduced.
  • the circuit is in forward scanning, its signal timing diagram is shown in Figure 2.
  • the signal timing diagram is shown in Figure 3.
  • connection mode of the gate integrated driving circuit described above when the number of stages of the gate integrated driving circuit increases, signal attenuation of the upper and lower stages occurs, and once the level transmission signal is attenuated, the gate integrated driving circuit is caused.
  • the pre-charging ability of a certain stage to the Q point is weakened, which in turn causes the output power of the gate driving signal G n of the current stage to be attenuated, and finally affects the charging of the pixel electrode in the plane.
  • the present invention proposes a new gate driver integrated circuit structure, when the intended multi-stage gate driver integrated circuit stage transmission, a gate drive signal G n each are an output can be stably
  • FIG. 4 is a gate drive circuit shown in accordance with an embodiment of the present invention.
  • the gate drive circuit will be described below with reference to FIG.
  • the gate driving circuit has a multi-stage structure
  • the nth stage circuit includes a Q n node pre-charging unit 1, a Q n node pull-up unit 2, and a Q n node pull-down.
  • Unit 3 P n node pull up unit 4, P n node pull down unit 5, G n output unit 6, G n output pull down unit 7.
  • the Q n node pre-charging unit 1 is connected to the first input signal Q n-1 11 , the second output signal Q n+1 12 and the high voltage signal VGH8, and the first input signal Q n-1 11 is a pre-drive circuit.
  • the middle Q n-1 node outputs a signal
  • the second output signal Q n+1 12 is a Q n+1 node output signal in the subsequent stage driving circuit.
  • the first input signal Q n-1 11 and the second output signal Q n+1 12 control signal transmission between the high voltage signal VGH8 and the Q n node 10 through the Q n node precharge unit 1 , thereby realizing the Q n node 10 pre-charge.
  • the Q n node pre-charging unit 1 includes a first transistor T1, a second transistor T2, a third transistor T3, and a fourth transistor T4.
  • the source of the first transistor T1 is connected to the high voltage signal VGH8, the gate of the first transistor T1 is connected to the second output signal Q n+1 12 , and the drain of the first transistor T1 is connected to the source of the second transistor T2.
  • the gate of the second transistor T2 is connected to the first input signal Q n-1 11, and the drain of the second transistor T2 is connected to the source of the third transistor T3 and simultaneously connected to the Q n node 10.
  • the gate of the third transistor T3 is connected to the first input signal Q n-1 11 , and the drain of the third transistor T3 is connected to the source of the fourth transistor T4.
  • the gate of the fourth transistor T4 is connected to the second output signal Q n+1 12 , and the drain of the fourth transistor T4 is connected to the high voltage signal VGH8.
  • the Q n- node pull-up unit 2 is used to maintain the high-level state of the Q n- node 10.
  • the Q n node pull-up unit 2 includes a first capacitor C1 , and the first capacitor C1 is connected to the Q n node 10 and the output terminal G n 14 respectively.
  • the Q n- node pull-down unit 3 is connected to the low voltage signal VGL9 for maintaining the low state of the Q n node 10.
  • the Q n node pull-down unit 3 includes a fifth transistor T5, the source of the fifth transistor T5 is connected to the Q n node 10, the gate of the fifth transistor T5 is connected to the P n node 13, and the drain of the fifth transistor T5 is connected to the low voltage. Signal VGL9.
  • the P n node pull-up unit 4 is connected to the high voltage signal VGH8 and the clock signal CKV4 for controlling signal transmission between the high voltage signal VGH8 and the P n node 13.
  • the P n node pull-up unit 4 includes a sixth transistor T6 and a second capacitor C2, a source of the sixth transistor T6 is connected to the high voltage signal VGH8, a gate of the sixth transistor T6 is connected to the clock signal CKV4, and a sixth transistor The drain of T6 is connected to the P n node 13. Both ends of the second capacitor C2 are connected to the P n node 13 and the low voltage signal VGL9, respectively.
  • the P n node pull-down unit 5 is connected to the low voltage signal VGL9 for maintaining the P n node 13 in a low state.
  • the P n node pull-down unit 5 includes a seventh transistor T7, the source of the seventh transistor T7 is connected to the P n node, the gate of the seventh transistor T7 is connected to the Q n node 10, and the drain of the seventh transistor T7 is low. Voltage signal VGL9.
  • the G n output unit 6 is connected to the clock signal CKV1 and the output terminal G n 14 for controlling signal transmission between the clock signal CKV1 and the output terminal G n 14.
  • the G n output unit 6 includes an eighth transistor T8 whose source is connected to the clock signal CKV1, the gate of the eighth transistor T8 is connected to the Q n node 10, and the eighth transistor T8 The drain is connected to the output terminal G n 14.
  • the G n output pull-down unit 7 is connected to the low voltage signal VGL9 and the output terminal G n 14 for maintaining the output terminal G n 14 in a low state.
  • the G n output pull-down unit 7 includes a ninth transistor T9 whose source is connected to the output terminal G n 14.
  • the gate of the ninth transistor T9 is connected to the P n node 13 and the drain of the ninth transistor T9 Connect the low voltage signal VGL9.
  • the technical effect of the embodiment is that, when the gate driving circuit of the embodiment uses the Q n-1 node output signal in the pre-stage driving circuit and the Q n+1 node output signal in the subsequent-stage driving circuit overlap, When the high level is used, the n nth circuit Q n node is precharged, which can greatly improve the stability of the G n output terminal of the nth stage circuit.
  • the first and second transistors are connected in series, and the third and fourth transistors are connected in series to greatly reduce the probability of leakage of the Q n node.
  • the present embodiment provides a driving method for driving the above-described gate driving circuit.
  • the signal timing diagram of the driving method during forward scanning is as shown in FIG. 5, and the scanning process includes phase a to phase e.
  • stage a when the first input signal Q n-1 11 and the second input signal Q n+1 12 overlap to a high level, the first and second transistors are turned on in series, and the third and fourth transistors are also turned on in series, and simultaneously The Q n node 10 performs precharging.
  • Stage b in stage a, the Q n node 10 is precharged, the first capacitor C1 in the Q n node 10 pullup unit maintains the Q n node 10 in a high state, and the eighth transistor in the G n output unit 6 T8 in the oN state, high-level second clock signal to the output terminal G n 14.
  • phase c the first capacitor C1 in the Q n node pull-up unit 2 continues to maintain the Q n node 10 in a high state, and at this time, the low level of the second clock signal pulls the output terminal G n 14 low.
  • the first, second, third, and fourth transistors are all in series conduction state, and the Q n node 10 is supplementally charged.
  • stage d when the first clock signal is high, the sixth transistor T6 in the P n node pull-up unit 4 is in an on state, the P n node 13 level is pulled high, and the Q n node pull-down unit 3 The fifth transistor T5 is turned on, at which point the Q n node 10 level is pulled low to the low voltage signal VGL9.
  • stage e when the Q n node 10 becomes a low level, the seventh transistor T7 of the P n node pull-down unit 5 is in an off state, and the sixth transistor T6 is turned on when the first clock jumps to a high level, P n node 13 is charged, then the fifth transistor T5 and the ninth transistor T9 of the G n output pull-down unit 7 are both in an on state, which can ensure the stability of the low level of the Q n node 10 and the output terminal G n 14 while the second The capacitor C2 has a certain holding effect on the high level of the P n node 13.
  • stage 1 when the first input signal Q n-1 11 and the second input signal Q n+1 12 overlap to a high level, the first and second transistors are turned on in series, and the third and fourth transistors are also turned on in series, and simultaneously The Q n node 10 performs precharging.
  • phase 3 the first capacitor C1 in the Q n node pull-up unit 2 continues to maintain the Q n node 10 in a high state, and at this time, the low level of the second clock signal pulls the output terminal G n 14 low.
  • the first, second, third, and fourth transistors are all in series conduction state, and the Q n node 10 is supplementally charged.
  • phase 4 when the first clock signal is at a high level, the sixth transistor T6 in the P n node pull-up unit 4 is in an on state, the P n node 13 level is pulled high, and the Q n node pull-down unit 3
  • the fifth transistor T5 is turned on, at which point the Q n node 10 level is pulled low to the low voltage signal VGL9.
  • phase 5 when the Q n node 10 becomes a low level, the seventh transistor T7 of the P n node pull-down unit 5 is in an off state, and the sixth transistor T6 is turned on when the first clock jumps to a high level, P n node 13 is charged, then the fifth transistor T5 and the ninth transistor T9 of the G n output pull-down unit 7 are both in an on state, which can ensure the stability of the low level of the Q n node 10 and the output terminal G n 14 while the second The capacitor C2 has a certain holding effect on the high level of the P n node 13.
  • the technical effect of the present embodiment is that, by the driving method of the embodiment, the high level when the Q n-1 node output signal in the pre-stage driving circuit and the Q n+1 node output signal in the subsequent stage driving circuit overlap are used. Pre-charging the n-th circuit Q n node can greatly improve the stability of the G n output of the n-th stage circuit.
  • the first and second transistors are connected in series, and the third and fourth transistors are connected in series to greatly reduce the probability of leakage of the Q n node.
  • the embodiment provides a display device.
  • the display device includes a display panel and a peripheral driving circuit.
  • the display panel may be a liquid crystal display panel, a plasma display panel, or a light emitting diode Display panel or OLED display panel, etc.
  • the peripheral driving circuit includes a gate driving circuit and an image signal driving circuit.
  • the gate driving circuit employs a gate driving circuit as described in Embodiment 1. When the display device described in this embodiment operates, the operation process of the gate driving circuit operates as the gate driving method described in Embodiment 2.
  • the technical effect of the present embodiment is that the display device of the embodiment has a stable output of the gate driving circuit, so that the display effect is more stable than that of the display device in the prior art, which is more effective in reducing image smear and jitter. And so on.

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  • Chemical & Material Sciences (AREA)
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Abstract

一种栅极驱动电路及其驱动方法、以及使用该驱动电路的显示装置，栅极驱动电路采用前级驱动电路中Q n-1节点输出信号（11）和后级驱动电路中Q n+1节点输出信号（12）二者交叠时的高电平时为第n级电路Q n节点（10）预充电，可以大幅提高第n级电路的G n输出端（14）的稳定性。同时第一、二晶体管（T1、T2）串联，第三、四晶体管（T3、T4）串联。

Description

一种栅极驱动电路及驱动方法、显示装置
相关技术的交叉引用
本申请要求享有2016年12月15日提交的名称为“一种栅极驱动电路及驱动方法、显示装置”的中国专利申请为CN201611160173.5的优先权，其全部内容通过引用并入本文中。
技术领域
本发明涉及显示技术领域，尤其涉及一种栅极驱动电路及其驱动方法，以及依据该栅极驱动电路及驱动方法制造的显示装置。
背景技术
TFT-LCD(Thin Film Transistor Liquid Crystal Display，薄膜晶体管-液晶显示器)以及OLED(Active Matrix Driving OLED，有源矩阵驱动有机发光二极管)显示装置因其具有体积小、功耗低、无辐射以及制作成本相对较低等特点，而越来越多地被应用于高性能显示领域当中。
上述显示装置通常设置有栅极集成(Gate Driver on Array)电路，其利用现有薄膜晶体管液晶显示器中的薄膜晶体管阵列制程将栅极行扫描驱动信号电路制作在薄膜晶体管阵列基板上，该栅极集成驱动电路每一级输出端与一行栅线相连接，用于向该栅线输出栅极扫描信号，以实现对栅线的逐行扫描。
随着低温多晶硅(LTPS)半导体薄膜晶体管的发展，而且由于低温多晶硅半导体本身超高载流子迁移率的特性，相应的面板周边集成电路也成为大家关注的焦点，并且很多人投入到集成系统面板(SOP)的相关技术研究，并逐步成为现实。
根据现有的这种栅极集成驱动电路的连接方式，当栅极集成驱动电路级数增加的时，会出现上下级传时信号衰减，级传信号一旦出现衰减，那么就会造成栅极集成驱动电路的某一级对Q点的预充电能力减弱，进而导致本级栅极驱动信号输出能力衰减，最终影响到面内像素电极的充电。
发明内容
本发明所要解决的技术问题之一是提供一种能够在多级栅极集成驱动电路级传时，每一级栅极驱动信号Gn均能够稳定输出的栅极驱动电路。同时本发明所要解决的另一技术问题在降低栅极驱动电路中预充电节点的漏电几率。
为了解决上述技术问题，本发明的第一个方面提供了一种栅极驱动电路，该栅极驱动电路具有多级结构，其中，第n级电路中包括：
第n级电路中包括：
Qn节点预充电单元，其在第一输入信号Qn-1、第二输出信号Qn+1的作用下控制高电压信号VGH与Qn节点之间的信号传输，由此对Qn节点进行预充电；
Qn节点上拉单元，其电连接在Qn节点与本级电路输出端Gn之间，用于维持Qn节点的高电平状态；
Qn节点下拉单元，其电连接在低电压信号VGL与Qn节点之间，用于在Pn节点电压信号的作用下控制低电压信号VGL与Qn节点之间的信号传输，由此维持Qn节点的低电平状态；
Pn节点上拉单元，其电连接在高电压信号VGH与Pn节点之间，用于在第一时钟信号的作用下控制高电压信号VGH与Pn节点之间的信号传输，由此维持Pn节点的高电平状态；
Pn节点下拉单元，其电连接在低电压信号VGL与Pn节点之间，用于在Qn节点电压信号的作用下控制低电压信号VGL与Pn节点之间的信号传输，由此维持Pn节点的低电平状态；
Gn输出单元，其电连接在第二时钟信号与本级电路输出端Gn之间，用于在Qn节点电压信号的作用下控制第二时钟信号与本级电路输出端Gn之间的信号传输，由此输出Gn高电平信号；
Gn输出端下拉单元，其电连接在低电压信号VGL与本级电路输出端Gn之间，用于在Pn节点电压信号的作用下控制低电压信号VGL与本级电路输出端Gn之间的信号传输，由此维持本级电路输出端Gn的低电平状态。
其中，所述第一输入信号Qn-1为前级驱动电路中Qn-1节点输出信号，第二输入信号Qn+1为后级驱动电路中Qn+1节点输出信号。
在一个实施例中，所述Qn节点预充电单元包括第一晶体管、第二晶体管、第三晶体管及第四晶体管；第一晶体管的源极与高电压信号VGH连接，第一晶体管的栅极与第二输出信号Qn+1连接，第一晶体管的漏极与第二晶体管的源极连接；第二晶体管的栅极连接第一输入信号Qn-1，第二晶体管的漏极连接第三晶体管的源极，并同时与Qn节点连 接；第三晶体管的栅极与第一输入信号Qn-1连接，第三晶体管的漏极与第四晶体管的源极连接；第四晶体管的栅极与第二输出信号Qn+1连接，第四晶体管的漏极与高电压信号VGH连接。
在一个实施例中，所述Qn节点上拉单元包括第一电容，所述第一电容两端分别连接Qn节点与输出端Gn。
在一个实施例中，所述Qn节点下拉单元包括第五晶体管，第五晶体管的源极连接Qn节点，第五晶体管的栅极连接Pn节点，第五晶体管的漏极连接低电压信号VGL。
在一个实施例中，所述Pn节点上拉单元包括第六晶体管和第二电容，所述第六晶体管的源极连接高电压信号VGH，第六晶体管的栅极连接第一时钟信号，第六晶体管的漏极连接Pn节点；第二电容两端分别连接Pn节点与低电压信号VGL。
在一个实施例中，所述Pn节点下拉单元包括第七晶体管，所述第七晶体管的源极连接Pn节点，第七晶体管的栅极连接Qn节点，第七晶体管的漏极连接低电压信号VGL。
在一个实施例中，所述Gn输出单元包括第八晶体管，所述八晶体管的源极连接第二时钟信号，第八晶体管的栅极连接Qn节点，第八晶体管的漏极连接输出端Gn。
在一个实施例中，所述Gn输出端下拉单元包括第九晶体管，所述第九晶体管的源极连接输出端Gn，第九晶体管的栅极连接Pn节点，第九晶体管的漏极连接低电压信号VGL。
根据本发明的第二个方面，还提供了一种栅极驱动方法，在进行正反双向扫描时，包括如下阶段：
正向扫描阶段时包括：
阶段a，第一输入信号Qn-1与第二输入信号Qn+1交叠为高电平时，第一、二晶体管串联导通，第三、四晶体管也串联导通，同时对Qn节点进行预充电；
阶段b，在阶段a中，Qn节点被预充电，Qn节点上拉单元中的第一电容C1维持Qn节点处于高电平状态，Gn输出单元中的第八晶体管处于导通状态，第二时钟信号的高电平输出到输出端Gn；
阶段c，Qn节点上拉单元中的第一电容继续维持Qn节点处于高电平状态，而此时第二时钟信号的低电平将Gn输出端电平拉低，当第一输入信号Qn-1与第二输入信号Qn+1同时为高电平时，第一、二、三、四晶体管均处于串联导通状态，Qn节点被补充充电；
阶段d，当第一时钟信号为高电平时，Pn节点上拉单元中的第六晶体管处于导通的状态，Pn节点电平被拉高，Qn节点下拉单元中的第五晶体管导通，此时Qn节点电平被拉低到低电压信号VGL；
阶段e，当Qn节点变为低电平后，Pn节点下拉单元的第七晶体管处于截止状态，当第一时钟跳变为高电平时第六晶体管导通，Pn节点被充电，那么五晶体管和Gn输出端下拉单元的第九晶体管均处于导通的状态，可以保证Qn节点及输出端Gn低电平的稳定，同时第二电容对Pn节点的高电平具有一定的保持作用。
反向扫描阶段包括：
阶段1，第一输入信号Qn-1与第二输入信号Qn+1交叠为高电平时，第一、二晶体管串联导通，第三、四晶体管也串联导通，同时对Qn节点进行预充电；
阶段2，在阶段1中，Qn节点被预充电，Qn节点上拉单元中的第一电容C1维持Qn节点处于高电平状态，Gn输出单元中的第八晶体管T8处于导通状态，第二时钟信号的高电平输出到输出端Gn；
阶段3，Qn节点上拉单元中的第一电容C1继续维持Qn节点处于高电平状态，而此时第二时钟信号的低电平将Gn输出端电平拉低，当第一输入信号Qn-1与第二输入信号Qn+1同时为高电平时，第一、二、三、四晶体管均处于串联导通状态，Qn节点被补充充电；
阶段4，当第一时钟信号为高电平时，Pn节点上拉单元中的第六晶体管T6处于导通的状态，Pn节点电平被拉高，Qn节点下拉单元中的第五晶体管T5导通，此时Qn节点电平被拉低到低电压信号VGL；
阶段5，当Qn节点变为低电平后，Pn节点下拉单元的第七晶体管T7处于截止状态，当第一时钟跳变为高电平时第六晶体管T6导通，Pn节点被充电，那么五晶体管T5和Gn输出端下拉单元的第九晶体管T9均处于导通的状态，可以保证Qn节点及输出端Gn低电平的稳定，同时第二电容C2对Pn节点的高电平具有一定的保持作用。
本发明的第三个方面提供一种显示装置，该显示装置包括上述任意实施例所述的栅极驱动电路。
与现有技术相比，本发明的一个或多个实施例可以具有如下优点：
本发明中的栅极驱动电路中，针对第n级电路，采用前级驱动电路中Qn-1节点输出信号和后级驱动电路中Qn+1节点输出信号二者交叠时的高电平时为第n级电路Qn节点预充电，可以大幅提高第n级电路的Gn输出端的稳定性。同时第一、二晶体管串联，第三、四晶体管串联可以大幅降低Qn节点漏电的几率。
本发明的其它特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得显而易见，或者通过实施本发明而了解。本发明的目的和其他优点可通过在说明书、权利要求书以及附图中所特别指出的结构来实现和获得。
附图说明
附图用来提供对本发明的进一步理解，并且构成说明书的一部分，与本发明的实施例共同用于解释本发明，并不构成对本发明的限制。在附图中：
图1是现有技术中的栅极驱动电路；
图2是现有技术中的栅极驱动电路正向扫描的时序图；
图3是现有技术中的栅极驱动电路反向扫描的时序图；
图4是根据本发明的栅极驱动电路；
图5是根据本发明的栅极驱动电路正向扫描的时序图；
图6是根据本发明的栅极驱动电路反向扫描的时序图。
附图标记说明：
1.Qn节点预充电单元；          2.Qn节点上拉单元；
3.Qn节点下拉单元；            4.Pn节点上拉单元；
5.Pn节点下拉单元；            6.Gn输出单元；
7.Gn输出端下拉单元；          8.高电压信号VGH；
9.低电压信号VGL；             10.Qn节点；
11.第一输入信号Qn-1           12.第二输出信号Qn+1；
13.Pn节点；                   14.输出端Gn；
具体实施方式
为使本发明的目的、技术方案和优点更加清楚，以下结合附图对本发明作进一步地详细说明。
图1是传统栅极集成驱动电路中某级电路单元的电路结构，为了保证输出点Gn的稳定性，都会引入Q、P两节点。该电路在正向扫描时，其信号时序图如图2所示，在反向扫描时，其信号时序图如图3所示。
根据上述这种栅极集成驱动电路的连接方式，当栅极集成驱动电路级数增加的时，会出现上下级传时信号衰减，级传信号一旦出现衰减，那么就会造成栅极集成驱动电路的某一级对Q点的预充电能力减弱，进而导致本级栅极驱动信号Gn输出能力衰减，最终影响到面内像素电极的充电。
为此，本发明提出一种新的栅极集成驱动电路结构，旨在当多级栅极集成驱动电路级传时，每一级栅极驱动信号Gn均能够稳定输出的栅极驱动电路
实施例1
图4是根据本发明实施例所示的栅极驱动电路。下面结合图4对该栅极驱动电路进行说明。
如图4所示的一种栅极驱动电路，该栅极驱动电路具有多级结构，其第n级电路中包括Qn节点预充电单元1、Qn节点上拉单元2、Qn节点下拉单元3、Pn节点上拉单元4、Pn节点下拉单元5、Gn输出单元6、Gn输出端下拉单元7。
其中，Qn节点预充电单元1连接第一输入信号Qn-111、第二输出信号Qn+112及高电压信号VGH8，该第一输入信号Qn-111为前级驱动电路中Qn-1节点输出信号，第二输出信号Qn+112为后级驱动电路中Qn+1节点输出信号。第一输入信号Qn-111和第二输出信号Qn+112通过Qn节点预充电单元1控制高电压信号VGH8与Qn节点10之间的信号传输，由此实现对Qn节点10的预充电。
所述Qn节点预充电单元1包括第一晶体管T1、第二晶体管T2、第三晶体管T3及第四晶体管T4。第一晶体管T1的源极与高电压信号VGH8连接，第一晶体管T1的栅极与第二输出信号Qn+112连接，第一晶体管T1的漏极与第二晶体管T2的源极连接。第二晶体管T2的栅极连接第一输入信号Qn-111，第二晶体管T2的漏极连接第三晶体管T3的源极，并同时与Qn节点10连接。第三晶体管T3的栅极与第一输入信号Qn-111连接，第三晶体管T3的漏极与第四晶体管T4的源极连接。第四晶体管T4的栅极与第二输出信号Qn+112连接，第四晶体管T4的漏极与高电压信号VGH8连接。
Qn节点上拉单元2用于维持Qn节点10的高电平状态。所述Qn节点上拉单元2包括第一电容C1，所述第一电容C1两端分别连接Qn节点10与输出端Gn14。
Qn节点下拉单元3连接低电压信号VGL9用于维持Qn节点10的低电平状态。所述Qn节点下拉单元3包括第五晶体管T5，第五晶体管T5的源极连接Qn节点10，第五晶体管T5的栅极连接Pn节点13，第五晶体管T5的漏极连接低电压信号VGL9。
Pn节点上拉单元4连接高电压信号VGH8和时钟信号CKV4，用于控制高电压信号VGH8与Pn节点13之间的信号传输。所述Pn节点上拉单元4包括第六晶体管T6和第二电容C2，所述第六晶体管T6的源极连接高电压信号VGH8，第六晶体管T6的栅极连接时钟信号CKV4，第六晶体管T6的漏极连接Pn节点13。第二电容C2两端分别连接Pn节点13与低电压信号VGL9。
Pn节点下拉单元5连接低电压信号VGL9，用于维持Pn节点13处于低电平状态。所述Pn节点下拉单元5包括第七晶体管T7，所述第七晶体管T7的源极连接Pn节点，第七晶体管T7的栅极连接Qn节点10，第七晶体管T7的漏极连接低电压信号VGL9。
Gn输出单元6连接时钟信号CKV1和输出端Gn14，用于控制时钟信号CKV1与输出 端Gn14之间的信号传输。在一个实施例中，所述Gn输出单元6包括第八晶体管T8，所述八晶体管T8的源极连接时钟信号CKV1，第八晶体管T8的栅极连接Qn节点10，第八晶体管T8的漏极连接输出端Gn14。
Gn输出端下拉单元7连接低电压信号VGL9和输出端Gn14，用于维持输出端Gn14处于低电平状态。所述Gn输出端下拉单元7包括第九晶体管T9，所述九晶体管T9的源极连接输出端Gn14，第九晶体管T9的栅极连接Pn节点13，第九晶体管T9的漏极连接低电压信号VGL9。
本实施例的技术效果在于，通过本实施例的栅极驱动电路，采用前级驱动电路中Qn-1节点输出信号和后级驱动电路中Qn+1节点输出信号二者交叠时的高电平时为第n级电路Qn节点预充电，可以大幅提高第n级电路的Gn输出端的稳定性。同时第一、二晶体管串联，第三、四晶体管串联可以大幅降低Qn节点漏电的几率。
实施例2
根据实施例1所述的栅极驱动电路，本实施例提供一种用于驱动上述栅极驱动电路的驱动方法。
正向扫描时该驱动方法的信号时序图如图5所示，扫描过程包括阶段a至阶段e。
阶段a，第一输入信号Qn-111与第二输入信号Qn+112交叠为高电平时，第一、二晶体管串联导通，第三、四晶体管也串联导通，同时对Qn节点10进行预充电。
阶段b，在阶段a中，Qn节点10被预充电，Qn节点10上拉单元中的第一电容C1维持Qn节点10处于高电平状态，Gn输出单元6中的第八晶体管T8处于导通状态，第二时钟信号的高电平输出到输出端Gn14。
阶段c，Qn节点上拉单元2中的第一电容C1继续维持Qn节点10处于高电平状态，而此时第二时钟信号的低电平将输出端Gn14电平拉低，当第一输入信号Qn-111与第二输入信号Qn+112同时为高电平时，第一、二、三、四晶体管均处于串联导通状态，Qn节点10被补充充电。
阶段d，当第一时钟信号为高电平时，Pn节点上拉单元4中的第六晶体管T6处于导通的状态，Pn节点13电平被拉高，Qn节点下拉单元3中的第五晶体管T5导通，此时Qn节点10电平被拉低到低电压信号VGL9。
阶段e，当Qn节点10变为低电平后，Pn节点下拉单元5的第七晶体管T7处于截止状态，当第一时钟跳变为高电平时第六晶体管T6导通，Pn节点13被充电，则第五晶体管T5和Gn输出端下拉单元7的第九晶体管T9均处于导通的状态，可以保证Qn节点10 及输出端Gn14低电平的稳定，同时第二电容C2对Pn节点13的高电平具有一定的保持作用。
反向扫描时该驱动方法的信号时序图如图6所示，由于Qn节点预充电单元中，第一、二晶体管与第三、四晶体管相对Qn节点实质上为对称结构，因此反向扫描过程与正向扫描过程大致相同，区别仅在于第一输入信号Qn-1与第二输入信号Qn+1相对于正向扫描时相反，其扫描过程包括阶段1至阶段5。
阶段1，第一输入信号Qn-111与第二输入信号Qn+112交叠为高电平时，第一、二晶体管串联导通，第三、四晶体管也串联导通，同时对Qn节点10进行预充电。
阶段2，在阶段1中，Qn节点10被预充电，Qn节点10上拉单元中的第一电容C1维持Qn节点10处于高电平状态，Gn输出单元6中的第八晶体管T8处于导通状态，第二时钟信号的高电平输出到输出端Gn14。
阶段3，Qn节点上拉单元2中的第一电容C1继续维持Qn节点10处于高电平状态，而此时第二时钟信号的低电平将输出端Gn14电平拉低，当第一输入信号Qn-111与第二输入信号Qn+112同时为高电平时，第一、二、三、四晶体管均处于串联导通状态，Qn节点10被补充充电。
阶段4，当第一时钟信号为高电平时，Pn节点上拉单元4中的第六晶体管T6处于导通的状态，Pn节点13电平被拉高，Qn节点下拉单元3中的第五晶体管T5导通，此时Qn节点10电平被拉低到低电压信号VGL9。
阶段5，当Qn节点10变为低电平后，Pn节点下拉单元5的第七晶体管T7处于截止状态，当第一时钟跳变为高电平时第六晶体管T6导通，Pn节点13被充电，则第五晶体管T5和Gn输出端下拉单元7的第九晶体管T9均处于导通的状态，可以保证Qn节点10及输出端Gn14低电平的稳定，同时第二电容C2对Pn节点13的高电平具有一定的保持作用。
本实施的技术效果在于，通过本实施例的驱动方法，采用前级驱动电路中Qn-1节点输出信号和后级驱动电路中Qn+1节点输出信号二者交叠时的高电平时为第n级电路Qn节点预充电，可以大幅提高第n级电路的Gn输出端的稳定性。同时第一、二晶体管串联，第三、四晶体管串联可以大幅降低Qn节点漏电的几率。
实施例3
根据前述实施例1和实施例2，本实施例提供一种显示装置。该显示装置包括显示面板和外围驱动电路。所述显示面板可以是液晶显示面板、等离子显示面板、发光二极管 显示面板或有机发光二极管显示面板等。所述外围驱动电路包括栅极驱动电路和图像信号驱动电路。所述栅极驱动电路采用如实施例1中所述的栅极驱动电路。本实施例所述的显示装置在运行时，其栅极驱动电路的工作过程如实施例2所述的栅极驱动方法进行工作。
本实施的技术效果在于，本实施例的显示装置，由于其栅极驱动电路信号输出稳定，因此其显示效果相对现有技术中的显示装置更为稳定，其更够大大降低画面拖影、抖动等现象。
以上所述，仅为本发明的具体实施案例，本发明的保护范围并不局限于此，任何熟悉本技术的技术人员在本发明所述的技术规范内，对本发明的修改或替换，都应在本发明的保护范围之内。

Claims (17)

  1. 一种栅极驱动电路，该栅极驱动电路具有多级结构，第n级电路中包括：
    Qn节点预充电单元，其在第一输入信号Qn-1、第二输出信号Qn+1的作用下控制高电压信号VGH与Qn节点之间的信号传输，由此对Qn节点进行预充电；
    Qn节点上拉单元，其电连接在Qn节点与本级电路输出端Gn之间，用于维持Qn节点的高电平状态；
    Qn节点下拉单元，其电连接在低电压信号VGL与Qn节点之间，用于在Pn节点电压信号的作用下控制低电压信号VGL与Qn节点之间的信号传输，由此维持Qn节点的低电平状态；
    Pn节点上拉单元，其电连接在高电压信号VGH与Pn节点之间，用于在第一时钟信号的作用下控制高电压信号VGH与Pn节点之间的信号传输，由此维持Pn节点的高电平状态；
    Pn节点下拉单元，其电连接在低电压信号VGL与Pn节点之间，用于在Qn节点电压信号的作用下控制低电压信号VGL与Pn节点之间的信号传输，由此维持Pn节点的低电平状态；
    Gn输出单元，其电连接在第二时钟信号与本级电路输出端Gn之间，用于在Qn节点电压信号的作用下控制第二时钟信号与本级电路输出端Gn之间的信号传输，由此输出Gn高电平信号；
    Gn输出端下拉单元，其电连接在低电压信号VGL与本级电路输出端Gn之间，用于在Pn节点电压信号的作用下控制低电压信号VGL与本级电路输出端Gn之间的信号传输，由此维持本级电路输出端Gn的低电平状态；
    其中，所述第一输入信号Qn-1为前级驱动电路中Qn-1节点输出信号，第二输入信号Qn+1为后级驱动电路中Qn+1节点输出信号。
  2. 如权利要求1所述的栅极驱动电路，其中，所述Qn节点预充电单元包括第一晶体管、第二晶体管、第三晶体管及第四晶体管；第一晶体管的源极与高电压信号VGH连接，第一晶体管的栅极与第二输出信号Qn+1连接，第一晶体管的漏极与第二晶体管的源极连接；第二晶体管的栅极连接第一输入信号Qn-1，第二晶体管的漏极连接第三晶体管的源极，并同时与Qn节点连接；第三晶体管的栅极与第一输入信号Qn-1连接，第三晶体管的漏极与第四晶体管的源极连接；第四晶体管的栅极与第二输出信号Qn+1连接，第四晶体管的漏极与高电压信号VGH连接。
  3. 如权利要求2所述的栅极驱动电路，其中，所述Qn节点上拉单元包括第一电容， 所述第一电容两端分别连接Qn节点与输出端Gn。
  4. 如权利要求3所述的栅极驱动电路，其中，所述Qn节点下拉单元包括第五晶体管，第五晶体管的源极连接Qn节点，第五晶体管的栅极连接Pn节点，第五晶体管的漏极连接低电压信号VGL。
  5. 如权利要求4所述的栅极驱动电路，其中，所述Pn节点上拉单元包括第六晶体管和第二电容，所述第六晶体管的源极连接高电压信号VGH，第六晶体管的栅极连接第一时钟信号，第六晶体管的漏极连接Pn节点；第二电容两端分别连接Pn节点与低电压信号VGL。
  6. 如权利要求5所述的栅极驱动电路，其中，所述Pn节点下拉单元包括第七晶体管，所述第七晶体管的源极连接Pn节点，第七晶体管的栅极连接Qn节点，第七晶体管的漏极连接低电压信号VGL。
  7. 如权利要求6所述的栅极驱动电路，其中，所述Gn输出单元包括第八晶体管，所述八晶体管的源极连接第二时钟信号，第八晶体管的栅极连接Qn节点，第八晶体管的漏极连接输出端Gn。
  8. 如权利要求7所述的栅极驱动电路，其中，所述Gn输出端下拉单元包括第九晶体管，所述第九晶体管的源极连接输出端Gn，第九晶体管的栅极连接Pn节点，第九晶体管的漏极连接低电压信号VGL。
  9. 一种栅极驱动电路的驱动方法，
    所述栅极驱动电路具有多级结构，第n级电路中包括：
    Qn节点预充电单元，其在第一输入信号Qn-1、第二输出信号Qn+1的作用下控制高电压信号VGH与Qn节点之间的信号传输，由此对Qn节点进行预充电；
    Qn节点上拉单元，其电连接在Qn节点与本级电路输出端Gn之间，用于维持Qn节点的高电平状态；
    Qn节点下拉单元，其电连接在低电压信号VGL与Qn节点之间，用于在Pn节点电压信号的作用下控制低电压信号VGL与Qn节点之间的信号传输，由此维持Qn节点的低电平状态；
    Pn节点上拉单元，其电连接在高电压信号VGH与Pn节点之间，用于在第一时钟信号的作用下控制高电压信号VGH与Pn节点之间的信号传输，由此维持Pn节点的高电平状态；
    Pn节点下拉单元，其电连接在低电压信号VGL与Pn节点之间，用于在Qn节点电压信号的作用下控制低电压信号VGL与Pn节点之间的信号传输，由此维持Pn节点的低电 平状态；
    Gn输出单元，其电连接在第二时钟信号与本级电路输出端Gn之间，用于在Qn节点电压信号的作用下控制第二时钟信号与本级电路输出端Gn之间的信号传输，由此输出Gn高电平信号；
    Gn输出端下拉单元，其电连接在低电压信号VGL与本级电路输出端Gn之间，用于在Pn节点电压信号的作用下控制低电压信号VGL与本级电路输出端Gn之间的信号传输，由此维持本级电路输出端Gn的低电平状态；
    其中，所述第一输入信号Qn-1为前级驱动电路中Qn-1节点输出信号，第二输入信号Qn+1为后级驱动电路中Qn+1节点输出信号；
    在所述栅极驱动电路的驱动方法中，正向扫描阶段时包括：
    阶段a，第一输入信号Qn-1与第二输入信号Qn+1交叠为高电平时，第一、二晶体管串联导通，第三、四晶体管也串联导通，同时对Qn节点进行预充电；
    阶段b，在阶段a中，Qn节点被预充电，Qn节点上拉单元中的第一电容维持Qn节点处于高电平状态，Gn输出单元中的第八晶体管处于导通状态，第二时钟信号的高电平输出到输出端Gn；
    阶段c，Qn节点上拉单元中的第一电容继续维持Qn节点处于高电平状态，而此时第二时钟信号的低电平将Gn输出端电平拉低，当第一输入信号Qn-1与第二输入信号Qn+1同时为高电平时，第一、二、三、四晶体管均处于串联导通状态，Qn节点被补充充电；
    阶段d，当第一时钟信号为高电平时，Pn节点上拉单元中的第六晶体管处于导通的状态，Pn节点电平被拉高，Qn节点下拉单元中的第五晶体管导通，此时Qn节点电平被拉低到低电压信号VGL；
    阶段e，当Qn节点变为低电平后，Pn节点下拉单元的第七晶体管处于截止状态，当第一时钟跳变为高电平时第六晶体管导通，Pn节点被充电，那么第五晶体管和Gn输出端下拉单元的第九晶体管均处于导通的状态，可以保证Qn节点及输出端Gn低电平的稳定，同时第二电容对Pn节点的高电平具有一定的保持作用。
  10. 如权利要求9所述的栅极驱动电路的驱动方法，其中，该驱动方法还包括反向扫描阶段，所述反向扫描阶段包括：
    阶段1，第一输入信号Qn-1与第二输入信号Qn+1交叠为高电平时，第一、二晶体管串联导通，第三、四晶体管也串联导通，同时对Qn节点进行预充电；
    阶段2，在阶段1中，Qn节点被预充电，Qn节点上拉单元中的第一电容维持Qn节点处于高电平状态，Gn输出单元中的第八晶体管处于导通状态，第二时钟信号的高电平输 出到输出端Gn；
    阶段3，Qn节点上拉单元中的第一电容继续维持Qn节点处于高电平状态，而此时第二时钟信号的低电平将Gn输出端电平拉低，当第一输入信号Qn-1与第二输入信号Qn+1同时为高电平时，第一、二、三、四晶体管均处于串联导通状态，Qn节点被补充充电；
    阶段4，当第一时钟信号为高电平时，Pn节点上拉单元中的第六晶体管处于导通的状态，Pn节点电平被拉高，Qn节点下拉单元中的第五晶体管导通，此时Qn节点电平被拉低到低电压信号VGL；
    阶段5，当Qn节点变为低电平后，Pn节点下拉单元的第七晶体管处于截止状态，当第一时钟跳变为高电平时第六晶体管导通，Pn节点被充电，那么五晶体管和Gn输出端下拉单元的第九晶体管均处于导通的状态，可以保证Qn节点及输出端Gn低电平的稳定，同时第二电容对Pn节点的高电平具有一定的保持作用。
  11. 如权利要求9所述的栅极驱动电路的驱动方法，其中，所述Qn节点预充电单元包括第一晶体管、第二晶体管、第三晶体管及第四晶体管；第一晶体管的源极与高电压信号VGH连接，第一晶体管的栅极与第二输出信号Qn+1连接，第一晶体管的漏极与第二晶体管的源极连接；第二晶体管的栅极连接第一输入信号Qn-1，第二晶体管的漏极连接第三晶体管的源极，并同时与Qn节点连接；第三晶体管的栅极与第一输入信号Qn-1连接，第三晶体管的漏极与第四晶体管的源极连接；第四晶体管的栅极与第二输出信号Qn+1连接，第四晶体管的漏极与高电压信号VGH连接。
  12. 如权利要求11所述的栅极驱动电路的驱动方法，其中，所述Qn节点上拉单元包括第一电容，所述第一电容两端分别连接Qn节点与输出端Gn。
  13. 如权利要求12所述的栅极驱动电路的驱动方法，其中，所述Qn节点下拉单元包括第五晶体管，第五晶体管的源极连接Qn节点，第五晶体管的栅极连接Pn节点，第五晶体管的漏极连接低电压信号VGL。
  14. 如权利要求13所述的栅极驱动电路的驱动方法，其中，所述Pn节点上拉单元包括第六晶体管和第二电容，所述第六晶体管的源极连接高电压信号VGH，第六晶体管的栅极连接第一时钟信号，第六晶体管的漏极连接Pn节点；第二电容两端分别连接Pn节点与低电压信号VGL。
  15. 如权利要求14所述的栅极驱动电路的驱动方法，其中，所述Pn节点下拉单元包括第七晶体管，所述第七晶体管的源极连接Pn节点，第七晶体管的栅极连接Qn节点，第七晶体管的漏极连接低电压信号VGL。
  16. 如权利要求15所述的栅极驱动电路的驱动方法，其中，所述Gn输出单元包括第 八晶体管，所述八晶体管的源极连接第二时钟信号，第八晶体管的栅极连接Qn节点，第八晶体管的漏极连接输出端Gn。
  17. 如权利要求16所述的栅极驱动电路的驱动方法，其中，所述Gn输出端下拉单元包括第九晶体管，所述第九晶体管的源极连接输出端Gn，第九晶体管的栅极连接Pn节点，第九晶体管的漏极连接低电压信号VGL。
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