Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
  • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
  • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
  • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
  • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
  • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
  • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
  • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
  • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
  • H10D62/107—Buried supplementary regions, e.g. buried guard rings 
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
  • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
  • H10D62/112—Constructional design considerations for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layers, e.g. by using channel stoppers
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
  • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
  • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
  • H10D62/8325—Silicon carbide
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P30/00—Ion implantation into wafers, substrates or parts of devices
  • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
  • H10P30/22—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping using masks
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
  • H10W10/01—Manufacture or treatment
  • H10W10/031—Manufacture or treatment of isolation regions comprising PN junctions
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
  • H10W10/30—Isolation regions comprising PN junctions
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
  • H10D12/411—Insulated-gate bipolar transistors [IGBT]
  • H10D12/441—Vertical IGBTs
  • H10D12/461—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions
  • H10D12/481—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
  • H10D30/66—Vertical DMOS [VDMOS] FETs
  • H10D30/665—Vertical DMOS [VDMOS] FETs having edge termination structures
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
  • H10D30/66—Vertical DMOS [VDMOS] FETs
  • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D8/00—Diodes
  • H10D8/60—Schottky-barrier diodes 
  • H10D8/605—Schottky-barrier diodes  of the trench conductor-insulator-semiconductor barrier type, e.g. trench MOS barrier Schottky rectifiers [TMBS]

Definitions

• the technique disclosed herein relates to a semiconductor device and a production method thereof.
• JP 2000-114549 A discloses a semiconductor device including an element region and an outer-periphery voltage withstanding region around the element region.
• the element region is provided with a vertical semiconductor element.
• the outer-periphery voltage withstanding region is provided with a plurality of p-type guard rings and an n-type outer-periphery drift region.
• the guard rings surround the element region in a multiple manner and are placed in a range facing a front surface of a semiconductor substrate.
• the outer-periphery drift region separates the guard rings from each other.
• the depletion layer extends toward an outer peripheral side inside the outer-periphery drift region through the plurality of guard rings.
• the extension of the depletion layer toward the outer peripheral side is promoted by the plurality of guard rings.
• FIG. 14 An upper diagram of FIG. 14 is a sectional view of an outer-periphery voltage withstanding region of a semiconductor device in a related art, and a lower diagram of FIG. 14 illustrates an electric field distribution in the outer-periphery voltage withstanding region.
• the lower diagram of FIG. 14 illustrates an electric field in the vicinity of a front surface of a semiconductor substrate.
• a p-type impurity concentration is distributed such that the p-type impurity concentration is high at a central part and decreases toward a peripheral part (a part near an outer-periphery drift region 110).
• a high concentration region in which the p-type impurity concentration is high is indicated as a p + region
• a low concentration region in which the p-type impurity concentration is low is indicated as a p ' region.
• a width Wal of a distribution range of the electric field in an outermost guard ring lOOx which is a guard ring placed on an outermost peripheral side, is wider than widths Wbl of respective distribution ranges of the electric field in the other guard rings 100.
• the reason why the width Wal becomes wider than the widths Wbl as such is as follows. That is, the outermost guard ring lOOx does not have a guard ring 100 on its outer peripheral side, whereas the other guard rings 100 each have an adjacent guard ring 100 on their outer peripheral sides.
• a width Wa2 of a part where an electric field is generated inside the outermost guard ring lOOx is wider than widths Wb2 of respective parts where an electric field is generated inside the other guard rings 100.
• the electric field is applied to the high concentration region (the p + region). Crystal defects exist at a high density in the high concentration region, and therefore, when the electric field is applied to the high concentration region, a leak current occurs. As such, the semiconductor device of the related art has a possibility that a leak current easily occurs in the outermost guard ring.
• a semiconductor device in this disclosure includes: a semiconductor substrate; a front-surface electrode making contact with a front surface of the semiconductor substrate; and a back-surface electrode making contact with a back surface of the semiconductor substrate, wherein: the semiconductor substrate includes an element region overlapping with a contact face between the front-surface electrode and the semiconductor substrate in a plan view of the semiconductor substrate along a thickness direction of the semiconductor substrate, and an outer-periphery voltage withstanding region provided around the element region; the element region includes a semiconductor element capable of applying an electric current between the front-surface electrode and the back-surface electrode; the outer-periphery voltage withstanding region includes a plurality of p-type guard rings facing the front surface and surrounding the element region in a multiple manner, and an n-type outer-periphery drift region separating the guard rings from each other; each of the guard rings includes a high concentration region having a p-type impurity concentration higher than 10% of a peak value of a p-type impurity concentration of the each of the guard rings,
• the widths of the first part and the second parts indicate dimensions in a direction from an inner peripheral side (an element region side) toward an outer peripheral side (an outer peripheral end surface side of the semiconductor substrate).
• FIG. 15 illustrates one exemplary semiconductor device disclosed in the present specification.
• An upper diagram of FIG. 15 is a sectional view of an outer-periphery voltage withstanding region and a lower diagram of FIG. 15 illustrates an electric field distribution in the outer-periphery voltage withstanding region.
• a plurality of guard rings 200 and an outer-periphery drift region 210 are illustrated.
• Each of the guard rings 200 includes a high concentration region (a p + -region) in which a p-type impurity concentration is high, and a low concentration region (a p " -region) in which the p-type impurity concentration is low. Note that a crystal defect density in the high concentration region is higher than a crystal defect density in the low concentration region.
• the low concentration region is placed between the high concentration region and the outer-periphery drift region 210.
• a low concentration region of an outermost guard ring 200x includes a first part 201 positioned on an outer peripheral side of a high concentration region of the outermost guard ring 200x. Further, the low concentration regions include respective second parts 202 each placed within a range sandwiched between a corresponding pair of high concentration regions adjacent to each other.
• a width Wcl of the first part 201 on a front surface is wider than widths Wdl of the second parts 202 on the front surface.
• an electric field is generated in a pn junction 200a positioned at an outer peripheral end of each of the guard rings 200.
• a width Wei of a distribution range of the electric field is wide in the pn junction 200a of the outermost guard ring 200x. Because of this, a width We2 of a distribution range of the electric field in the first part 201 is also wide.
• the width Wcl of the first part 201 which is a low concentration region, is wide, the electric field is hardly applied to the high concentration region of the outermost guard ring 200x. Since the electric field can be hardly applied to the high concentration region where a crystal defect density is high, a leak current is restrained.
• a width Wf 1 of a distribution range of the electric field is narrow in the pn junction 200a of each of the other guard rings 200. Because of this, a width Wf2 of a distribution range of the electric field in the second part 202 adjacent to the pn junction 200a is also narrow. Because of this, in each of the other guard rings 200, even if the width Wdl of the second part 202 adjacent to the pn junction 200a is narrow, the electric field can be hardly applied to the high concentration region. Further, when a distance between the high concentration regions becomes wider, the electric field to be applied to the pn junction 200a increases, so that a withstand voltage of the semiconductor device decreases.
• FIG. 15 is used in the above description, but the semiconductor device proposed in the present specification is not limited to the configuration of FIG. 15. A position and a shape of each of the semiconductor regions, the number of semiconductor regions, and the like can be modified appropriately.
• the semiconductor substrate may be an SiC substrate.
• a production method of a semiconductor device includes: forming a plurality of p-type guard rings facing a front surface of a semiconductor substrate and surrounding a specific region in a multiple manner by injecting p-type impurities into the semiconductor substrate; and completing the semiconductor device by use of the semiconductor substrate, wherein: the semiconductor device includes a front-surface electrode making contact with the.
• each of the guard rings includes a high concentration region having a p-type impurity concentration higher than 10% of a peak value of a p-type impurity concentration of the each of the guard rings, and a low concentration region having a p-type impurity concentration equal to or lower than 10% of the peak value and placed between the high concentration region and the outer-periphery drift region;
• the low concentration region of an outermost guard ring positioned on an outermost peripheral side, among the plurality of guard rings includes a first part positioned on an outer peripheral side of the high concentration region of the outermost guard ring;
• respective low concentration regions of the guard rings include respective second parts each positioned in a range sandwiched between corresponding two adjacent high
• a mask having openings, a blocking portion, and a low permeability portion is formed on the front surface of the semiconductor substrate, and the p-type impurities are injected into the semiconductor substrate through the mask; in the injecting of the p-type impurities, a permeability of the p-type impurities in the low permeability portion is lower than a permeability of the p-type impurities in the openings, but is higher than a permeability of the p-type impurities in the blocking portion; the high concentration regions are formed in respective regions within the semiconductor substrate, the respective regions being placed below respective openings; and the first part is formed in a region within the semiconductor substrate, the region being placed below the low permeability portion.
• FIG. 1 is a sectional view of a semiconductor device of an embodiment (a sectional view along a line I-I in FIG. 2);
• FIG. 2 is a plan view of the semiconductor device of the embodiment (a view illustrating an arrangement of guard rings and an end n-type region by dot hatching);
• FIG. 3 is an enlarged sectional view and an electric field distribution map of an outer-periphery voltage withstanding region
• FIG. 4 is an explanatory view of a production method of a semiconductor device (a sectional view of a guard-ring formation part);
• FIG. 5 is an explanatory view of the production method of the semiconductor device (a sectional view of the guard-ring formation part);
• FIG. 6 is an explanatory view of the production method of the semiconductor device (a sectional view of the guard-ring formation part);
• FIG. 7 is an explanatory view of a production method of a semiconductor device (a sectional view of a guard-ring formation part);
• FIG. 8 is an explanatory view of the production method of the semiconductor device (a sectional view of the guard-ring formation part);
• FIG. 9 is an explanatory view of the production method of the semiconductor device (a sectional view of the guard-ring formation part);
• FIG. 10 is an explanatory view of a production method of a semiconductor device (a sectional view of a guard-ring formation part);
• FIG. 11 is an explanatory view of the production method of the semiconductor device (a plan view of the guard-ring formation part);
• FIG. 12 is an explanatory view of the production method of the semiconductor device (a plan view of the guard-ring formation part);
• FIG. 13 is an explanatory view of a production method of a semiconductor device (a sectional view of a guard-ring formation part);
• FIG. 14 is a sectional view and an electric field distribution map of a semiconductor device in a related art.
• FIG. 15 is a sectional view and an electric field distribution map of an exemplary semiconductor device disclosed in the present specification. DETAILED DESCRIPTION OF EMBODIMENTS
• a semiconductor device 10 of an embodiment illustrated in FIGS. 1 and 2 includes a semiconductor substrate 12.
• the semiconductor substrate 12 is an SiC substrate.
• a front-surface electrode 14 and an insulating film 18 are provided on a front surface 12a of the semiconductor substrate 12.
• an electrode and an insulating film (including the front-surface electrode 14 and the insulating film 18) on the front surface 12a are not illustrated.
• a dotted line in FIG. 2 indicates a contour of a contact face 15 where the front-surface electrode 14 makes contact with the semiconductor substrate 12.
• the front-surface electrode 14 makes contact with the semiconductor substrate 12 in a central part of the front surface 12a of the semiconductor substrate 12.
• the insulating film 18 covers a region of the front surface 12a, the region being not covered with the front-surface electrode 14. That is, the insulating film 18 covers an outer periphery of the front surface 12a of the semiconductor substrate 12. As illustrated in FIG. 1, a back-surface electrode 16 is formed on a back surface 12b of the semiconductor substrate 12. The back-surface electrode 16 covers a whole area of the back surface 12b of the semiconductor substrate 12. In the following description, a region overlapping with the contact face 15 when viewed along a thickness direction of the semiconductor substrate 12 is referred to as an element region 20.
• an outer-periphery voltage withstanding region 22 a region outside the element region 20 (a region between the element region 20 and an outer peripheral end surface 12c of the semiconductor substrate 12) is referred to as an outer-periphery voltage withstanding region 22.
• the outer-periphery voltage withstanding region 22 surrounds the element region 20.
• a side closer to the element region 20 is referred to as an inner peripheral side
• a side closer to the outer peripheral end surface 12c is referred to as an outer peripheral side.
• the semiconductor substrate 12 includes a drain region 38 and a drift region 36.
• the drain region 38 is an n-type region having a high n-type impurity concentration.
• the drain region 38 is distributed throughout the semiconductor substrate 12 in its lateral direction from the element region 20 to the outer-periphery voltage withstanding region 22.
• the drain region 38 is placed in a range facing the back surface 12b of the semiconductor substrate 12.
• the drain region 38 makes ohmic contact with the back-surface electrode 16 in the whole back surface 12b.
• the drift region 36 is an n-type region having a lower n-type impurity concentration than the drain region 38.
• the drift region 36 is distributed throughout the semiconductor substrate 12 in the lateral direction from the element region 20 to the outer-periphery voltage withstanding region 22.
• the drift region 36 is placed on the drain region 38 and makes contact with the drain region 38.
• a plurality of gate electrodes 30, a plurality of source regions 32, and a body region 34 are provided in the element region 20.
• a plurality of trenches is provided on the front surface 12a of the semiconductor substrate 12 within the element region 20.
• the gate electrodes 30 are provided in respective trenches.
• the gate electrode 30 is insulated from the semiconductor substrate 12 by a gate insulating film covering an inner surface of a corresponding trench.
• a top surface of the gate electrode 30 is covered with an interlayer insulator, and a top surface of the interlayer insulator is covered with the front-surface electrode 14.
• the gate electrode 30 is insulated from the front-surface electrode 14 by the interlayer insulator.
• the source region 32 is an n-type region having a high n-type impurity concentration.
• the source region 32 is placed in a range facing the front surface 12a of the semiconductor substrate 12.
• the source region 32 makes ohmic contact with the front-surface electrode 14.
• the source region 32 makes contact with the gate insulating film in an upper end of a corresponding trench.
• the body region 34 is a p-type region.
• the body region 34 extends from a position (a position facing the front surface 12a) adjacent to the source regions 32 to a position below the source regions 32.
• a p-type impurity concentration in the body region 34 is high at the position facing the front surface 12a, but is low at the position below the source regions 32.
• the body region 34 makes ohmic contact with the front-surface electrode 14 at the position facing the front surface 12a.
• the body region 34 makes contact with the gate insulating film at the position below the source regions 32.
• the drift region 36 is placed below the body region 34.
• the body region 34 makes contact with the drift region 36.
• the drift region 36 makes contact with the gate insulating film below the body region 34.
• a MOSFET is formed by the gate electrodes 30, the source regions 32, the body region 34, the drift region 36, and the drain region 38 within the element region 20.
• a current flows from the back-surface electrode 16 to the front-surface electrode 14.
• a plurality of guard rings 40 is provided in the outer-periphery voltage withstanding region 22.
• the guard rings 40 are p-type regions. As illustrated in FIGS. 1 to 3, the guard rings 40 face the front surface 12a of the semiconductor substrate 12 within the outer-periphery voltage withstanding region 22 (that is, the guard rings 40 are exposed to the front surface 12a). As illustrated in FIG. 2, the guard rings 40 extend in an annular shape in a plan view of the semiconductor substrate 12 in a thickness direction. The plurality of guard rings 40 surround the element region 20 in a multiple manner. As illustrated in FIG. 3, a part of the drift region 36 is placed at a position between the guard rings 40. The guard rings 40 are separated from each other by the drift region 36. Further, the guard ring 40 on an innermost peripheral side is separated from the body region 34 by the drift region 36. Top surfaces of the guard rings 40 are covered with the insulating film.18..
• a p-type impurity concentration changes depending on a position inside the guard ring 40.
• the guard ring 40 has a peak point M where the p-type impurity concentration is highest in itself, at a position near the front surface 12a of the semiconductor substrate 12.
• the p-type impurity concentration decreases from the peak point M toward the drift region 36.
• a region having a p-type impurity concentration higher than 10% of the p-type impurity concentration at the peak point M is referred to as a high concentration region 42
• a region having a p-type impurity concentration equal to or lower than 10% of the p-type impurity concentration at the peak point M is referred to as a low concentration region 44.
• the high concentration region 42 is illustrated as a p + -type region
• the low concentration region 44 is illustrated as a p " -type region.
• the high concentration region 42 is distributed around the peak point M, and faces the front surface 12a of the semiconductor substrate 12.
• the low concentration region 44 is distributed between the high concentration region 42 and the drift region 36. That is, in the guard ring 40, the low concentration region 44 is placed on a lateral side of the high concentration region 42 and on the lower side of the high concentration region 42. Since the high concentration region 42 is formed by injecting p-type impurities into the semiconductor substrate 12 at a high concentration, crystal defects exist at a high density in the high concentration region 42. The low concentration region 44 is formed by p-type impurities diffused from the high concentration region 42 or by p-type impurities injected into the semiconductor substrate 12 at a low concentration, and therefore, a density of crystal defects is low in the low concentration region 44.
• the low concentration region 44 faces the front surface 12a on both the inner peripheral side and the outer peripheral side of the high concentration region 42.
• a part of the low concentration region 44, the part being adjacent to the high concentration region 42 on the outer peripheral side is referred to as an outer peripheral part 51
• a part of the low concentration region 44, the part being adjacent to the high concentration region 42 on the inner peripheral side is referred to as an inner peripheral part 52.
• the outer peripheral parts 51 and the inner peripheral parts 52 are each placed in a range sandwiched between corresponding two of the high concentration regions 42 (a pair of high concentration regions 42 adjacent to each other).
• a low concentration region 44 of the outermost guard ring 40x placed on the outermost peripheral side among the plurality of guard rings 40 has the outer peripheral part 51x with a wide width.
• a width W51x of the outer peripheral part 1x of the outermost guard ring 40x is wider than widths W51 of the other outer peripheral parts 51 and widths W52 of the inner peripheral parts 52.
• the widths W51x, W51, and W52 are dimensions in a direction from the inner peripheral side toward the outer peripheral side.
• the widths W51 and the widths W52 are generally equal to each other.
• the high concentration regions 42 have generally the same widths. On this account, a width of the outermost guard ring 40x is wider than widths of the other guard rings 40.
• an end n-type region 48 is provided in the outer-periphery voltage withstanding region 22.
• the end n-type region 48 is an n-type region having a higher n-type impurity concentration than the drift region 36.
• the end n-type region 48 is placed in a range facing the front surface 12a and the outer peripheral end surface 12c.
• the end n-type region 48 extends in an annular manner along the outer peripheral end surface 12c.
• the end n-type region 48 is separated from the outermost guard ring 40x by the drift region 36. A distance between the end n-type region 48 and the outermost guard ring 40x is wider than a distance between the guard rings 40.
• a potential higher than the front-surface electrode 14 is applied to the back-surface electrode 16.
• a potential higher than a threshold is applied to the gate electrodes 30
• a channel is formed in the body region 34 within a range where the body region 34 makes contact with the gate insulating film.
• electrons flow from the front-surface electrode 14 to the back-surface electrode 16 through the source regions 32, the channel, the drift region 36, and the drain region 38. That is, the MOSFET is turned on.
• the potential of the gate electrodes 30 is decreased to the threshold or less, the channel disappears and the flow of electrons stops. That is, the MOSFET is turned off.
• a depletion layer expands from the body region 34 into the drift region 36.
• the depletion layer expands from a front side to a back side.
• a depletion layer expands from the inner peripheral side toward the outer peripheral side.
• the depletion layer extends toward the outer peripheral side through the plurality of guard rings 40. That is, each of the guard rings 40 promotes the depletion layer to extend toward the outer peripheral side.
• the depletion layer extends to the vicinity of the end n-type region 48.
• the depletion layer extends to the drift region 36 in the outer-periphery voltage withstanding region 22
• a voltage is applied to a pn junction 40a positioned at an outer peripheral end of each of the guard rings 40. Because of this, the low concentration regions 44 are depleted near respective pn junctions 40a. That is, the depletion layer expands into the outer peripheral part 51 from the pn junction 40a.
• An electric field is generated inside depletion layers on both sides of the pn junction 40a (that is, a depletion layer formed by depletion of the n-type drift region 36 and a depletion layer formed by depletion of the outer peripheral part 51 of the p-type low concentration region 44.
• a width Wxl of a part where an electric field is generated in the pn junction 40a of the outermost guard ring 40x is wider than a width Wyl of a part where an electric field is generated i the pn junction 40a of each of the other guard rings 40.
• a width Wx2 of a part (a part to be depleted) where an electric field is generated within the outer peripheral part 51x of the outermost guard ring 40x is wider than a width Wy2 of a part where an electric field is generated within the outer peripheral part 51 of each of the other guard rings 40.
• the width W51x of the outer peripheral part 51x of the outermost guard ring 40x is wider than the widths W51 of the other outer peripheral parts 51 of the other guard rings 40.
• the width Wx2 of the part where the electric field is generated is large in the outermost guard ring 40x, the part where the electric field is generated does not reach the high concentration region 42 (that is, a relationship of W51x > Wx2 is established).
• the outermost guard ring 40x is provided with the outer peripheral part 51x having a wide width on the outer peripheral side of the high concentration region 42, it is possible to restrain the electric field from being applied to the high concentration region 42.
• the width W51 of the outer peripheral part 51 is narrow.
• the width Wy2 of the part where the electric field is generated is narrow. Accordingly, even if the width W51 of the outer peripheral part 51 is narrow, the electric field can be hardly applied to the high concentration region 42. Accordingly, a leak current is restrained also in the guard rings 40 other than the outermost guard ring 40x.
• the width W51x of the outer peripheral part 51x of the outermost guard ring 40x is wide, whereas the widths W51 of the other outer peripheral parts 51 and the widths W52 of the inner peripheral parts 52 are narrow. Because of this, the distance between the high concentration regions 42 is narrow. This accordingly secures a withstand voltage of the semiconductor device 10. Further, by narrowing the distance between the high concentration regions 42, the semiconductor device 10 is downsized.
• FIGS. 4 to 13 used in the following description illustrate a range where the outermost guard ring 40x and its adjacent guard ring 40 are to be formed.
• FIGS. 4 to 6 illustrate a first production method.
• a semiconductor substrate 12 (a semiconductor substrate before machining) in which an n-type drift region 36 is exposed to a front surface 12a is prepared.
• a mask 60a an oxide film, a resist, and the like
• the mask 60a is patterned so that openings 62 are formed at positions corresponding to respective guard rings 40.
• p-type impurities are injected into the semiconductor substrate 12 several times through the mask 60a while an impurity implantation energy (that is, an impurity injection depth) is changed.
• the p-type impurities are injected into lower semiconductor layers of the openings 62.
• the p-type impurities are injected at a high concentration in a shallow range, and the p-type impurities are injected at a low concentration in a deep range.
• crystal defects are generated at a high density.
• a width of the opening 62 on the outermost peripheral side that is, the opening 62 corresponding to an outermost guard ring 40x
• an outer peripheral wall surface of the opening 62 on the outermost peripheral side is shifted further to the outer peripheral side, so as to enlarge a width of this opening 62.
• the mask 60a is an oxide film
• additional etching is performed on the mask 60a selectively, so that the width of the opening 62 can be widened as illustrated in FIG. 5.
• the mask 60a is a resist
• the mask 60a illustrated in FIG. 4 is removed and a mask 60a of a new pattern illustrated in FIG. 5 is formed, so that the width of the opening 62 can be widened.
• p-type impurities are injected into the semiconductor substrate 12 through the mask 60a with the opening 62 thus enlarged.
• the p-type impurities are injected at a low concentration both in the shallow range and the deep range.
• the p-type impurities are distributed at a low concentration in the shallow range and the deep range of the semiconductor substrate 12.
• the mask 60a is removed and annealing to activate the p-type impurities thus injected is performed, so that guard rings 40 are formed as illustrated in FIG. 6.
• the crystal defects existing in the guard rings 40 partially disappear, but the crystal defects remain in a predetermined ratio after the annealing.
• a crystal defect density is higher than a low concentration region 44 where the p-type impurities are injected at a low concentration.
• an outer peripheral part 51x with a wide width is formed in a range where the opening 62 is enlarged. With the use of the production method, it is possible to form the outermost guard ring 40x having the outer peripheral part 51x with a wide width.
• FIGS. 7, 8 illustrate a second production method.
• a mask 60b having openings 62 is formed on a front surface 12a of a semiconductor substrate 12.
• the mask 60b is formed so that an outer peripheral wall surface of an opening 62 on the outermost peripheral side (that is, an opening 62 corresponding to an outermost guard ring 40x) is inclined.
• p-type impurities are injected into the semiconductor substrate 12 several times through the mask 60b while an impurity implantation energy is changed.
• the p-type impurities are injected into lower semiconductor layers of the openings 62.
• the p-type impurities are injected at a high concentration in a shallow range, and the p-type impurities are injected at a low concentration in a deep range.
• a thickness of the mask 60b is thin. Accordingly, at the time of the ion implantation into the deep range, the p-type impurities penetrate through the part 61a so as to be injected into the semiconductor substrate 12. Accordingly, the p-type impurities are injected into the lower semiconductor layer of the part 61a at a low concentration.
• the p-type impurities are injected at a low concentration in the shallow range.
• guard rings 40 are formed as illustrated in FIG. 8.
• the production method it is possible to form the outermost guard ring 40x having an outer peripheral part 5 lx with a wide width.
• a mask 60c illustrated in FIG. 9 may be used instead of the mask 60b.
• the mask 60c illustrated in FIG. 9 has a part 61b with a thin thickness, instead of the part 61a having an inclined wall surface in FIG. 7.
• the p-type impurities are injected into a lower semiconductor layer of the part 61b at a low concentration at the time of ion implantation.
• FIGS. 10, 11 illustrate a third production method.
• a mask 60d having openings 62 is formed on a front surface 12a of a semiconductor substrate 12.
• the mask 60d includes a region 64 having a lot of very small openings 63 further on the outer peripheral side relative to an opening 62 on the outermost peripheral side (that is, an opening 62 corresponding to an outermost guard ring 40x).
• a density of the very small openings 63 is high at a position near the opening 62, but is low at a position distant from the opening 62. That is, an aperture ratio in the region 64 becomes lower toward the position distant from the opening 62.
• p-type impurities are injected into the semiconductor substrate 12 several times through the mask 60d while an impurity implantation energy is changed.
• the p-type impurities are injected at a high concentration in a shallow range, and the p-type impurities are injected at a low concentration in a deep range.
• the p-type impurities are injected into the semiconductor substrate 12 through the very small openings 63. Since the aperture ratio of the region 64 is low, the p-type impurities are injected into a lower semiconductor layer of the region 64 at a low concentration.
• the aperture ratio in the region 64 becomes lower toward the position distant from the opening 62, so the p-type impurities are injected into the lower semiconductor layer in the region 64 such that its concentration becomes lower toward the position distant from the opening 62.
• the mask 60d is removed and annealing to activate the p-type impurities thus injected is performed, so that guard rings 40 are formed similarly to FIG. 8.
• a mask 60e illustrated in FIG. 12 may be used instead of the mask 60d.
• a region 64 is configured such that very small openings 63 have a larger size at a position near an opening 62, and those at a position distant from the opening 62 have a smaller size. That is, an aperture ratio in the region 64 becomes lower toward the position distant from the opening 62. Accordingly with the use of the mask 60e illustrated in FIG. 12, it is also possible to form an outermost guard- ring 40x having an outer peripheral part 51x with a wide width.
• FIGS. 4, 13 illustrate a fourth production method.
• a mask 60a having openings 62 is formed, and p-type impurities are injected into a semiconductor substrate 12 through the mask 60a, as illustrated in FIG. 4.
• a formation step of the mask 60a and an injection step of the p-type impurities through the mask 60a are similar to the first production method.
• a resist 65 is formed on the mask 60a so that a part around an outer peripheral wall surface in an opening 62 on an outermost peripheral side is exposed and the other parts are covered therewith.
• an ion implantation angle is inclined to a front surface 12a of the semiconductor substrate 12 in a direction from the inner peripheral side toward the outer peripheral side, and the p-type impurities are injected into the semiconductor substrate 12.
• the p-type impurities partially penetrate .through the mask 60a in a range where the mask 60a is not covered with the resist 65 and are injected into a semiconductor layer below the mask 60a. That is, the p-type impurities are injected, at a low concentration, into the semiconductor layer below the mask 60a in the range where the mask 60a is not covered with the resist 65. Note that, as illustrated in FIG.
• an outermost guard ring 40x is formed in an annular manner so as to surround the element region 20, and in view of this, the p-type impurities are injected several times while an orientation to incline an injection direction is changed, so that the p-type impurities can be injected at an angle inclined from the inner peripheral side toward the outer peripheral side relative to each part of the outermost guard ring 40x.
• the mask 60a and the resist 65 are removed and annealing to activate the p-type impurities thus injected is performed, so that guard rings 40 are formed similarly to FIG. 8. With the use of the production method, it is possible to form an outermost guard ring 40x having an outer peripheral part 5 lx with a wide width.
• the MOSFET is formed in the element region 20, but other semiconductor elements may be provided in the element region 20.
• an IGBT may be provided in the element region 20.
• a diode a pn diode, a schottky barrier diode, and the like in which the front-surface electrode 14 functions as an anode electrode and the back-surface electrode 16 functions as a cathode electrode may be provided in the element region.
• a depletion layer extends in the outer-periphery voltage withstanding region, thereby making it possible to obtain an effect similar to the above embodiment.
• the p-type impurity concentration in the high concentration region 42 is higher than 10% of the p-type impurity concentration at the peak point M.
• the high concentration region 42 it is preferable that the high concentration region 42 have a p-type impurity concentration higher than 1 x 10 ! 8 atoms/cm 3 .
• the semiconductor substrate 12 is constituted by SiC, but the semiconductor substrate 12 may be constituted by other semiconductor materials (e.g., a compound semiconductor material other than SiC, or silicon and the like).
• the SiC substrate is more suitable for the technique disclosed in the present specification.
• the MOSFET of the embodiment is an example of a semiconductor element of the present invention.
• the drift region 36 in the outer-periphery voltage withstanding region 22 of the above embodiment is an example of an outer-periphery drift region of the present invention.
• the outer peripheral part 51x of the embodiment is an example of a first part of the present invention.
• the outer peripheral parts 51 other than the outer peripheral part 51x and the inner peripheral parts 52 other than the inner peripheral part 52z in the embodiment are examples of a second part of the present invention.
• a mask (a mask through which the p-type impurities at a low concentration pass) above the outer peripheral part 51x of the outermost guard ring 40x is an example of a low permeability portion of the present invention.
• the openings 62 are an example of openings of the present invention.
• a mask (a mask of a part above a region where the guard rings 40 are not formed) of a part blocking the p-type impurities is an example of a blocking portion of the present invention.
• the production method of the semiconductor device includes: a step of forming a plurality of p-type guard rings facing a front surface of a semiconductor substrate and surrounding a specific region in a multiple manner by injecting p-type impurities into the semiconductor substrate; and a step of completing the- semiconductor device by use of the semiconductor substrate.
• a part of the step of completing the semiconductor device may be performed before the step of forming the guard rings.
• the step of forming the guard rings includes: a step of forming a mask having openings, a blocking portion, and a low permeability portion on the front surface of the semiconductor substrate; and a step of injecting the p-type impurities into the semiconductor substrate through the mask.
• a permeability of the p-type impurities in the low permeability portion is lower than a permeability of the p-type impurities in the openings, but is higher than a permeability of the p-type impurities in the blocking portion.
• High concentration region are formed in respective regions within the semiconductor substrate, the respective regions being placed below the openings.
• a first part is formed in a region within the semiconductor substrate, the region being placed below the low permeability portion.

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• 2016
  • 2016-10-21 JP JP2016207266A patent/JP2018067690A/ja active Pending
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