WO2018064984A1 - 去除晶片上的二氧化硅的方法及集成电路制造工艺 - Google Patents

去除晶片上的二氧化硅的方法及集成电路制造工艺 Download PDF

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WO2018064984A1
WO2018064984A1 PCT/CN2017/105369 CN2017105369W WO2018064984A1 WO 2018064984 A1 WO2018064984 A1 WO 2018064984A1 CN 2017105369 W CN2017105369 W CN 2017105369W WO 2018064984 A1 WO2018064984 A1 WO 2018064984A1
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sti
silicon dioxide
oxide layer
sio
harp
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French (fr)
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马振国
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Beijing Naura Microelectronics Equipment Co Ltd
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Beijing Naura Microelectronics Equipment Co Ltd
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Priority to KR1020197008822A priority Critical patent/KR102287682B1/ko
Priority to JP2019518991A priority patent/JP6896849B2/ja
Priority to SG11201902965XA priority patent/SG11201902965XA/en
Publication of WO2018064984A1 publication Critical patent/WO2018064984A1/zh
Priority to US16/372,849 priority patent/US10937661B2/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P70/00—Cleaning of wafers, substrates or parts of devices
    • H10P70/20—Cleaning during device manufacture
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0411—Manufacture or treatment of FETs having insulated gates [IGFET] of FETs having floating gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6326—Deposition processes
    • H10P14/6328—Deposition from the gas or vapour phase
    • H10P14/6334—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
    • H10P14/69215—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/04—Apparatus for manufacture or treatment
    • H10P72/0402—Apparatus for fluid treatment
    • H10P72/0418—Apparatus for fluid treatment for etching
    • H10P72/0421—Apparatus for fluid treatment for etching for drying etching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H10P76/408—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes
    • H10P76/4085—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes characterised by the processes involved to create the masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H10W10/0143—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations comprising concurrently refilling multiple trenches having different shapes or dimensions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells

Definitions

  • the present invention relates to the field of integrated circuit fabrication processes, and more particularly to a method of removing silicon dioxide on a wafer for use in an integrated circuit fabrication process and an integrated circuit fabrication process using the same.
  • silicon-based materials are currently commonly used to fabricate integrated circuits.
  • silicon or polysilicon
  • the surface will naturally oxidize to form a dense layer of silicon dioxide (SiO 2 ), as shown in Figure 1a.
  • SiO 2 silicon dioxide
  • a metal silicide process a metal nickel platinum (NiPt) film is in direct contact with a substrate of a silicon-based material, and if there is a layer of SiO 2 on the surface of the substrate, the resistivity is increased. It affects device performance, so it is necessary to remove this layer of SiO 2 before manufacturing the subsequent process.
  • the line width of the spacer (made of silicon nitride (Si 3 N 4 ) material). Dimensions can affect device electrical properties, such as increased leakage. Therefore, it is necessary to keep the separation layer (Spacer, Si 3 N 4 ) as far as possible while removing SiO 2 .
  • the existing processes mostly use wet etching, plasma dry etching, etc. to remove SiO 2 , which has a low etching selectivity to Si 3 N 4 and excessive removal of the isolation layer, resulting in isolation.
  • the layer size is reduced, thereby increasing leakage and affecting device performance.
  • the present invention provides a method for removing silicon dioxide on a wafer in an integrated circuit manufacturing process by directly reacting a gaseous etchant with silicon dioxide under high pressure and extracting the reaction product after the reaction. To achieve high selectivity and high efficiency to remove silicon dioxide.
  • a method of removing silicon dioxide on a wafer comprising: introducing dehydrated hydrogen fluoride gas and a dehydrated alcohol gas into a process chamber; dehydrating the hydrogen fluoride gas and dehydrating Mixing an alcohol gas to form a gaseous etchant; reacting the etchant with a wafer within the process chamber, and maintaining the process chamber at a high pressure to increase an etch selectivity; and The reaction product is withdrawn from the process chamber.
  • the pressure in the process chamber is 30 Torr to 300 Torr.
  • the pressure in the process chamber is 200 Torr.
  • the temperature in the process chamber is 20 ° C - 80 ° C.
  • the temperature in the process chamber is 40 °C.
  • the flow rate of the hydrogen fluoride gas is 100 sccm-500 sccm
  • the flow rate of the alcohol gas is 100 sccm-1000 sccm.
  • the flow rate of the hydrogen fluoride gas is 150 sccm to 225 sccm, and the flow rate of the alcohol gas is 200 sccm to 450 sccm.
  • the flow ratio of the hydrogen fluoride gas to the alcohol gas is 0.8-1.2:1.
  • the flow ratio of the hydrogen fluoride gas to the alcohol gas is 1:1.
  • the alcohol gas is at least one of C 1 -C 8 monohydric alcohol gases.
  • the alcohol gas is at least one of methanol, ethanol and isopropyl alcohol.
  • the invention also provides an integrated circuit fabrication process comprising the method of removing silicon dioxide on a wafer as described in any of the above aspects of the invention.
  • the manufacturing process includes a sub-process of filling the contour adjustment of the shallow trench insulating layer with HARP.
  • a certain thickness of HARP is first deposited by a CVD process, and then The STI is etched by the method of removing silicon dioxide on the wafer to make the opening large, and the above deposition and etching operations are repeatedly performed until the end of the process.
  • the manufacturing process includes a sub-process of removing the SiO 2 natural oxide layer on the hard mask layer of the STI, and the hard mask layer of the STI is Si 3 N 4 .
  • etching the SiO 2 natural oxide layer on the surface of the STI hard mask layer by using the method of removing silicon dioxide on the wafer, and controlling the SiO 2 natural oxide layer relative to The etching selectivity ratio of the STI HARP is to quickly remove the SiO 2 natural oxide layer and avoid over-etching the STI HARP.
  • the manufacturing process includes a sub-process of removing the pad oxide layer, wherein the pad oxide layer is oxidized to form a SiO 2 layer on the surface of the substrate by heating, which is a buffer of the STI hard mask layer Si 3 N 4 Floor.
  • the pad oxide layer is etched by the method of removing silicon dioxide on the wafer, and the etching selectivity of the pad oxide layer relative to the STI HARP is controlled so that The pad oxide layer is quickly removed and excessive etching of the STI HARP is avoided.
  • the manufacturing process includes a sub-process of removing the SiO 2 natural oxide layer on the silicon substrate before depositing silicon germanium.
  • etching the SiO 2 natural oxide layer on the silicon substrate by using the method of removing silicon dioxide on the wafer, and controlling the SiO 2 natural oxide layer relative to the polysilicon The selection ratio is etched to quickly remove the SiO 2 native oxide layer and to avoid excessive damage to the Si substrate.
  • the manufacturing process includes a sub-process of removing the SiO 2 natural oxide layer on the surface of the substrate and the surface of the polysilicon gate before depositing the silicide.
  • the sub-process using the method of the silicon dioxide on the wafer for removing a native oxide layer SiO 2 surface and a polysilicon gate etching the substrate surface, and to control the natural oxide layer SiO 2 An etching selectivity ratio with respect to polysilicon in order to quickly remove the SiO 2 natural oxide layer and avoid excessive damage to the Si substrate.
  • the manufacturing process includes an STI recess sub-process in a 2D NAND memory manufacturing process, the NAND memory including a floating gate and a pattern dense region STI HARP located in a pattern dense region and a control switch gate located in the graphics sparse region a pole and a pattern sparse region STI HARP, the floating gate and the control switch gate being polysilicon, the pattern dense region STI HARP And the graphic sparse region STI HARP is silicon dioxide.
  • etching the pattern dense region STI HARP and the graphics sparse region STI HARP by using the method of removing silicon dioxide on a wafer, and controlling the STI HARP relative to the A floating gate or an etch selectivity ratio relative to the control switch gate to quickly remove the STI HARP and avoid excessive damage to the floating gate and the control switch gate.
  • the method provided by the present invention uses a vapor phase etching process to remove silicon dioxide on a wafer. Compared with the wet etching process or the plasma dry etching process in the prior art, the present invention removes SiO 2 by a chemical reaction. There is no solid reaction product in the removal process, and therefore, the reaction product can be easily pumped out, thereby keeping the chamber clean, reducing or even eliminating particle contamination caused by the reaction product. Moreover, since the method provided by the present invention does not have a solid reaction product, it is not necessary to vaporize or liquefy the solid reaction product by high-temperature heating as in the prior art, and then discharge it. Therefore, the method provided by the present invention does not require high-temperature heating. This eliminates the need for a cooling step corresponding to the heating step, so that the reaction process is simple, which not only improves the process efficiency, increases the process throughput, but also eliminates the process cost corresponding to the high temperature step and the cooling step.
  • the method provided by the present invention adopts a high voltage process (for example, 50 Torr to 300 Torr), and can improve the etching selectivity ratio of SiO 2 to Si 3 N 4 (or polysilicon, HARP, etc.), thereby improving the silicon dioxide on the wafer.
  • the removal efficiency can reduce the damage to the substrate.
  • the integrated circuit manufacturing process provided by the present invention uses the method provided by the present invention to remove silicon dioxide on a wafer, thereby removing silicon dioxide by wet etching or plasma dry etching compared to the prior art.
  • the integrated circuit manufacturing process, the integrated circuit manufacturing process provided by the invention can also improve the removal efficiency of silicon dioxide on the wafer, reduce the damage to the substrate, and can keep the chamber clean, reduce or even eliminate the reaction product.
  • the particle pollution while also having the characteristics of simple reaction process, high process efficiency, high process capacity and low cost.
  • Figure 1a shows a schematic of an integrated circuit device having a native oxide layer.
  • Figure 1b shows a schematic diagram of the effect of removing silica according to the method of the prior art.
  • FIG. 2 shows a flow chart of the steps of a method of removing silicon dioxide on a wafer in accordance with the present invention.
  • Fig. 3 is a schematic view showing the effect of a method of removing silicon dioxide on a wafer according to the present invention.
  • 4a, 4b and 4c respectively show schematic views of the contour adjustment of a HARP filled shallow channel insulating layer according to the prior art.
  • 5a, 5b, 5c, and 5d respectively show schematic views of the effect of the method of removing silicon dioxide on a wafer in the process of HARP-filled shallow-channel insulating layer profile adjustment according to the present invention.
  • Figures 6a and 6b show schematic views of a device having a native oxide layer and a device after removal of the native oxide layer in accordance with the method of the present invention, respectively.
  • Figures 7a and 7b show schematic views of a device having a pad oxide layer and a device after removing the pad oxide layer in accordance with the method of the present invention, respectively.
  • Figures 8a and 8b show schematic views of a device having a native oxide layer and a device after removal of the native oxide layer in accordance with the method of the present invention, respectively.
  • Figures 9a and 9b respectively show an integrated circuit device having an oxide recess and in accordance with the present invention A schematic diagram of the effect of a device after removal of silicon dioxide.
  • FIG. 2 shows a flow chart of the steps of a method of removing silicon dioxide on a wafer in accordance with the present invention.
  • a method of removing silicon dioxide on a wafer includes: step 201, introducing dehydrated hydrogen fluoride gas and a dehydrated alcohol gas into a process chamber; and step 202, dehydrating the hydrogen fluoride
  • the gas is mixed with the dehydrated alcohol gas to form a gaseous etchant; in step 203, the etchant is reacted with a substance to be removed such as silica on the surface of the wafer in the process chamber, and
  • the process chamber maintains a high pressure state to increase the etch selectivity; and in step 204, the reaction product is withdrawn from the process chamber.
  • This embodiment achieves high selectivity and high efficiency removal of silica by directly reacting a gaseous etchant with silica under high pressure and extracting the reaction product after the reaction.
  • the object to be removed on the surface of the wafer is silicon dioxide
  • the method of removing silicon dioxide on the wafer according to the present invention may include: step 201, introducing dehydrated hydrogen fluoride gas and dehydrated alcohol into the process chamber. a gas-like gas; step 202, mixing the dehydrated hydrogen fluoride gas and the dehydrated alcohol gas to form a gaseous etchant; and step 203, the etchant and the surface of the wafer in the process chamber
  • the silicon oxide reacts and maintains the process chamber at a high pressure to increase the etch selectivity; and step 204 extracts the reaction product from the process chamber.
  • the conditions of the reaction may include a pressure in the process chamber of 30 Torr to 300 Torr and a temperature in the process chamber of 20 ° C to 80 ° C. Further preferably, the conditions of the reaction include a pressure in the process chamber of 200 Torr and a temperature in the process chamber of 40 °C. It has been found that the higher the pressure in the process chamber is in the range of 30 Torr to 300 Torr, the easier the gaseous etchant (reaction gas) condenses on the surface of the wafer and reacts with SiO 2 .
  • reaction gas gas
  • the SiO 2 removal rate The increase is greatly increased while the removal rate of Si 3 N 4 hardly increases, which greatly increases the removal selectivity ratio (i.e., etching selectivity ratio) of SiO 2 to Si 3 N 4 (or polysilicon, HARP, etc.).
  • the flow rate of the hydrogen fluoride gas may be 100 sccm to 500 sccm, and the flow rate of the alcohol gas is 100 sccm to 1000 sccm. Further preferably, the flow rate of the hydrogen fluoride gas is from 150 sccm to 225 sccm, and the flow rate of the alcohol gas is from 200 sccm to 450 sccm.
  • the flow ratio of the hydrogen fluoride gas to the alcohol gas may be from 0.8 to 1.2:1.
  • the flow ratio of the hydrogen fluoride gas to the alcohol gas may be 0.8:1, 1:1, or 1.2:1.
  • the flow ratio of the hydrogen fluoride gas to the alcohol gas is 1:1.
  • the alcohol gas may be at least one of a C 1 to C 8 monohydric alcohol gas. Further preferably, the alcohol gas is at least one of methanol (CH 3 OH), ethanol (C 2 H 5 OH), and isopropyl alcohol (IPA).
  • methanol CH 3 OH
  • ethanol C 2 H 5 OH
  • IPA isopropyl alcohol
  • the reaction formula of the method for removing silicon dioxide on a wafer according to the present invention can be expressed as:
  • the dehydrated HF gas and the dehydrated CH 3 OH gas can be mixed inside the chamber to form gaseous etchants HF 2 - and CH 3 OH 2 + , and the pressure in the chamber can be set to 200 Torr during the process.
  • the temperature is 40 ° C, and HF 2 - and CH 3 OH 2 + are mixed and reacted with SiO 2 to form SiF 4 , CH 3 OH and H 2 O.
  • CH 3 OH has strong water absorption, which can reduce the residual of H 2 O on the surface of the wafer, and the reaction products such as SiF 4 , CH 3 OH and H 2 O can be pumped out after the reaction.
  • the process chamber used in the method for removing silicon dioxide on a wafer of the present invention can be integrated with a vacuum process on the next process, so that the SiO 2 surface can be removed without damaging the vacuum environment.
  • the next process is performed to prevent the wafer from being re-oxidized again in a non-vacuum environment before proceeding to the next process and affecting the next process.
  • platinum-nickel (NiPt) in a silicide process before the deposition of silicon germanium (SiGe).
  • the invention improves the selection ratio by a high pressure process. It is found that when a high pressure process (for example, a process pressure of 200 Torr) is used, the gaseous etchant is more likely to condense on the surface of the wafer and react with SiO 2 , and the removal rate of SiO 2 is greatly increased. At the same time, the removal rate of Si 3 N 4 hardly increases, thereby reducing the damage to the substrate while increasing the removal rate of SiO 2 . That is, the method provided by the present invention greatly increases the removal selectivity of SiO 2 relative to Si 3 N 4 (or polysilicon, HARP, etc.).
  • a high pressure process for example, a process pressure of 200 Torr
  • FIGS 5a through 5b show schematic views of another effect of a method of removing silicon dioxide on a wafer in accordance with the present invention. As shown, since the diffusion of the reaction product is good, so the same density for the holes 5 of the hole area and sparse regions SiO 2 SiO 2 removal, the reaction product such as gaseous SiF 4, pumped out easily, without causing The small hole is clogged, the cleaning effect is good, the cleaning effect on the small hole is high, and the removal uniformity is high.
  • the method provided in this embodiment can also improve the loading effect of pad oxide removal and STI (Shallow Trench Isolation) recess etching, so that large and small The holes are deeply etched in the same groove and the STI height is consistent. Also CH 3 OH and H 2 O can easily be pulled out, it will not condense on the chamber walls, small particles.
  • STI Shallow Trench Isolation
  • the method for removing silicon dioxide on a wafer provided by the embodiment of the present invention has a low process temperature, for example, 20 ° C - 80 ° C, so that high temperature heating is not required, and accordingly, no high temperature heating step is required.
  • the corresponding cooling step, and thus the reaction process is simple, the reaction can be completed in one step, so that not only the process efficiency can be improved, the productivity can be improved, but also the cost generated by at least the heating step and the cooling step can be saved.
  • an integrated circuit fabrication process can also be provided that includes a method of removing silicon dioxide on a wafer as described above.
  • the integrated circuit manufacturing process provided by the present invention removes the silicon dioxide on the wafer by the method provided by the above embodiments of the present invention, and thus removes the second method by wet etching or plasma dry etching compared to the prior art.
  • the integrated circuit manufacturing process of silicon oxide, the integrated circuit manufacturing process provided by the invention can also improve the removal efficiency of silicon dioxide on the wafer, reduce the damage to the substrate, and can keep the chamber clean, reduce or even eliminate the reaction product.
  • the particle pollution caused by the method has the characteristics of simple reaction process, high process efficiency, high process capacity and low cost.
  • Example 1 STI HAPR deposition gap fill profile modified using HARP :
  • FIG. 4a, 4b, and 4c respectively show schematic views of contour adjustment of a shallow trench insulating layer filled with a HARP (High Aspect Ratio Process) according to the prior art, wherein FIG. 4a is after STI etching
  • Figure 4b is the device during STI HARP deposition
  • Figure 4c is the device that creates voids after STI HARP deposition.
  • STI HAPR deposition is deposited by CVD. Due to the large aspect ratio of 28 nm STI and the poor contour of STI etching, voids are easily generated during STI HARP deposition.
  • the prior art used in Figures 4a, 4b and 4c produces a solid reaction product with low void cleaning efficiency and low throughput.
  • the integrated circuit manufacturing process in this example 1 includes a wheel that fills a shallow trench insulating layer with HARP
  • the sub-process of the profile adjustment In the sub-process, a certain thickness of HARP is first deposited by a CVD process, and then the STI is etched to remove the opening by using the method of removing silicon dioxide on the wafer, and the deposition and etching operations are repeatedly performed. Until the end of the process.
  • FIGS. 5a, 5b, 5c, and 5d respectively show schematic views of the effect of the method of removing silicon dioxide on a wafer in the contour adjustment process of a HARP-filled shallow-channel insulating layer according to the present invention, wherein FIG. 5a For the device after STI etching, FIG. 5b is a device during STI HARP deposition, FIG. 5c is a device for performing STI opening adjustment by using the method for removing silicon dioxide on the wafer of the present invention, and FIG. 5d is after STI HARP deposition. Device.
  • the method of removing silicon dioxide on a wafer comprises the steps of: mixing dehydrated hydrogen fluoride gas with dehydrated methanol to form gaseous etchants HF 2 - and CH 3 OH 2 + ; Passing an etchant into the process chamber and reacting with SiO 2 on the surface of the wafer in the process chamber to generate SiF 4 , CH 3 OH and H 2 O, wherein the process conditions in the process chamber are The pressure in the chamber was set to 200 Torr, and the temperature in the chamber was maintained at 40 ° C; after the reaction was completed, SiF 4 , CH 3 OH and H 2 O were pumped out.
  • the STI is etched to make the opening change. Big, so that no holes can be created.
  • the method of the invention to remove SiO 2 , the non-solid reaction product is easily pumped out, so that the chamber can be cleaned, and the particle contamination caused by the reaction product can be reduced or even eliminated.
  • the method provided in the embodiment does not need high temperature heating.
  • the reaction process is simple, and has the characteristics of high process efficiency, high process productivity and low cost.
  • the method provided by the invention has a process pressure of 200 Torr and a process temperature of 40 ° C, thereby improving the etching selection of SiO 2 for HARP, etc.
  • the removal efficiency of the silicon dioxide on the wafer can be improved, and the damage to the substrate can be reduced, thereby controlling the contour of the opening and increasing the filling ability of the CVD HARP pore.
  • the integrated circuit fabrication process of this example 2 includes a sub-process of removing the SiO 2 native oxide layer on the hard mask layer of the STI, the hard mask layer of the STI being Si3N4.
  • the SiO 2 natural oxide layer on the surface of the STI hard mask layer is etched by the method for removing silicon dioxide on the wafer provided by the present invention, and the SiO 2 natural oxide layer is controlled relative to the STI HARP. Etching selection ratio to quickly remove the SiO 2 native oxide layer and avoid over-etching the STI HARP.
  • Figures 6a and 6b show schematic views of a device having a native oxide layer and a device after removal of the native oxide layer in accordance with the method of the present invention, respectively.
  • the integrated circuit fabrication process uses Si 3 N 4 as the hard mask layer of the STI, which is removed by H 3 PO 4 wet removal when removing the hard mask layer.
  • the wafer with the hard mask layer is naturally oxidized on the surface of the Si 3 N 4 layer to form a dense SiO 2 layer after being left in the air for a period of time, and the layer is removed before the Si 3 N 4 is removed. SiO 2 natural oxide layer. If the H 3 PO 4 wet process used to remove the hard mask layer is used to remove SiO 2 , the removal rate of SiO 2 is very slow.
  • the SiO 2 layer 6a is a SiO 2 layer deposited by CVD, and the SiO 2 layer has a low density and is easily removed, in this case, natural oxidation on the surface of the Si 3 N 4 layer is removed.
  • the removal amount of the STI HARP that is, to control the etching selectivity ratio of the SiO 2 natural oxide layer on the surface of the Si 3 N 4 with respect to the STI HARP to ensure the step height of the STI (ie, STI). Above the height of the substrate surface), because the step height of the STI affects the electrical properties of the device, it cannot be too high or too low.
  • FIG. 6b is a device morphology after removing the SiO 2 oxide layer on the surface of Si 3 N 4 by the method.
  • the processing steps of the silica removal method provided by the present invention are similar to those of the example 1, and are not described herein again.
  • the method according to the present invention can increase the etching selectivity ratio of the SiO 2 natural oxide layer on the surface of Si 3 N 4 to STI HARP by using a high voltage process, thereby rapidly removing the SiO 2 natural oxide layer on the surface of Si 3 N 4 .
  • the integrated circuit fabrication process in the example 3 includes a sub-process of removing the pad oxide layer, wherein the pad oxide layer is oxidized to form a SiO2 layer on the surface of the substrate by heating, which is a buffer layer of the STI hard mask layer Si3N4. .
  • the pad oxide layer is etched by the method for removing silicon dioxide on the wafer provided by the present invention, and the etching selectivity of the pad oxide layer relative to the STI HARP is controlled to quickly remove the liner. Pad the oxide layer and avoid over-etching the STI HARP.
  • Figures 7a and 7b show schematic views of a device having a pad oxide layer and a device after removing the pad oxide layer in accordance with the method of the present invention, respectively.
  • a pad oxide layer is used as a buffer layer of the hard mask layer Si 3 N 4 of the STI, and is a layer of SiO 2 formed by thermal oxidation of the surface of the substrate by a furnace tube method.
  • the thickness can be determined according to different processes (for example, a 28 nm process, the SiO 2 layer has a thickness of about 50 A).
  • the SiO 2 pad oxide layer needs to be removed prior to a subsequent process.
  • the STI HARP in FIG. 7a is a SiO 2 layer deposited by CVD, and the SiO 2 layer has a low density. In this case, it is necessary to control the removal of STI HARP when the pad oxide layer is removed.
  • the etching selectivity ratio of the pad oxide layer to the STIHARP is controlled so that the pad oxide layer can be quickly removed, and at the same time, the STI HARP can be prevented from being over-etched, thereby ensuring the step height of the STI.
  • FIG. 7b is a schematic view of the morphology of the device after the pad oxide layer is removed by the method.
  • the processing steps of the silica removal method provided by the present invention are similar to those of the example 1, and are not described herein again.
  • the method according to the present invention uses a high voltage process to increase the etching selectivity of the pad oxide layer relative to the STI HARP, thereby enabling rapid removal of the pad oxide layer while avoiding over-etching the STI HARP to control the STI steps.
  • the pad oxide layer is removed, no solid reaction product is generated, so that process efficiency and process productivity can be improved. Avoid problems such as divots caused by wet etching and affecting electrical properties.
  • Example 4 Removing the native oxide layer before depositing silicon germanium (SiGe):
  • the integrated circuit fabrication process in this example 4 includes a sub-process of removing the native oxide layer of SiO 2 on the silicon substrate prior to depositing germanium silicon.
  • the SiO 2 natural oxide layer on the silicon substrate is etched by the method for removing silicon dioxide on the wafer provided by the present invention, and the etching selectivity ratio of the SiO 2 natural oxide layer to the polysilicon is controlled. In order to quickly remove the SiO 2 natural oxide layer and avoid excessive damage to the Si substrate.
  • Figures 8a and 8b show schematic views of a device having a native oxide layer and a device after removal of the native oxide layer in accordance with the method of the present invention, respectively.
  • the Si substrate inside the etched region is exposed to the air and naturally oxidizes, and this layer of natural oxide layer causes the device to be electrically Performance failure and other issues, so this layer of natural oxide must be removed before the deposition of SiGe, and the removal of this layer of SiO 2 can not damage the Si substrate, that is, to control this layer of SiO 2 natural oxide layer relative to Etching selectivity ratio of polysilicon (ie, Si substrate).
  • FIG. 8b is a schematic diagram of the morphology of the device after the SiO 2 natural oxide layer is removed by the method.
  • the processing steps of the silica removal method provided by the present invention are similar to those of the example 1, and are not described herein again.
  • the method according to the present invention adopts a high voltage process, which can improve the etching selectivity ratio of the SiO 2 natural oxide layer to the polysilicon, thereby rapidly removing the SiO 2 natural oxide layer while reducing the damage to the gate and the Si substrate. .
  • the integrated circuit manufacturing process uses the method of removing silicon dioxide provided by the present invention, which can improve process efficiency and process productivity, and can improve device performance.
  • Example 5 Removing the natural oxide layer before depositing silicide:
  • the integrated circuit fabrication process in this example 5 includes a sub-process of removing the SiO 2 native oxide layer of the substrate surface and the polysilicon gate surface prior to depositing the silicide.
  • the SiO 2 natural oxide layer on the surface of the substrate and the surface of the polysilicon gate is etched by the method for removing silicon dioxide on the wafer provided by the present invention, and the natural oxide layer of the SiO 2 is controlled relative to the polysilicon.
  • the selection ratio is etched to quickly remove the native oxide layer of SiO 2 and to avoid excessive damage to the Si substrate.
  • Figures 1a and 3 respectively show schematic views of the morphology of a device having a native oxide layer and a device after removal of silicon dioxide in accordance with the method of the present invention.
  • FIG. 3 is a schematic diagram of the morphology of the device after removing the SiO 2 natural oxide layer by the method.
  • the processing steps of the silica removal method provided by the present invention are similar to those of the example 1, and are not described herein again.
  • the method according to the present invention uses a high voltage process to increase the etching selectivity of the SiO 2 natural oxide layer relative to the Si 3 N 4 and Si substrate, thereby enabling rapid removal of the SiO 2 surface of the Si substrate surface and the polysilicon gate surface.
  • the oxide layer can reduce damage to the polysilicon gate and the Si substrate at the same time, and avoid problems such as size reduction of the insulating spacer and increase of the leakage rate.
  • the integrated circuit manufacturing process utilizes the method of removing silicon dioxide provided by the present invention, which can improve process efficiency and process productivity, and can improve device performance.
  • the integrated circuit fabrication process shown in this example 6 includes an STI recess sub-process in a 2D NAND memory fabrication process, the NAND memory including a floating gate and a pattern dense region STI HARP located in a pattern dense region and located in a pattern sparse region
  • the control switch gate and the pattern sparse region STI HARP, the floating gate and the control switch gate are polysilicon, and the pattern dense region STI HARP and the pattern sparse region STI HARP are silicon dioxide.
  • the pattern dense region STI HARP and the pattern sparse region STI HARP are etched by the method for removing silicon dioxide on the wafer provided by the present invention, and the STI HARP is controlled relative to the floating gate Or an etch selection ratio relative to the control switch gate to quickly remove STIHARP and avoid excessive damage to the floating gate and control switch gate.
  • Figures 9a and 9b show schematic diagrams of the effect of an integrated circuit device having oxide recesses and a device after removing silicon dioxide in accordance with the method of the present invention, respectively.
  • the STI recess process in this example is a process in a 2D NAND fabrication process
  • NAND is a memory device.
  • the pattern-dense area on the left side is the memory area of the device, including the floating gate (ie, the dark bars in the densely patterned region, which is polysilicon) and the pattern dense region STI HARP (ie, the graphics are dense a light colored bar in the area, which is silicon dioxide);
  • the pattern sparse area on the right side is the control area, including the source/drain selective control switch gate (ie, the dark bar in the pattern sparse area)
  • control switch gate polysilicon
  • the pattern sparse area STI HARP light bar in the thinned area of the figure, which is silicon dioxide.
  • FIG. 9b is a schematic diagram of the morphology of the device after removing silicon dioxide (STI HARP) by the method.
  • the processing steps of the silica removal method provided by the present invention are similar to those of the example 1, and are not described herein again.
  • the method according to the present invention employs a high voltage process to increase the etch selectivity of the STI HARP relative to the floating gate or to the source/drain selective control switch gate, ie, etch of SiO 2 relative to polysilicon
  • the ratio is selected so that SiO 2 can be removed quickly while reducing damage to polysilicon.
  • the SiO 2 layer is removed, no solid reaction product is produced, so that there is no problem that is common in the prior art: that small pores are easily clogged and difficult to clean due to the generation of solid reaction products.
  • the integrated circuit manufacturing process applies the method for removing silicon dioxide provided by the present invention, which can improve process efficiency and process productivity, and can improve device performance.

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Abstract

一种去除晶片上的二氧化硅的方法及制造工艺。该方法可包括：向工艺腔室内通入脱水的氟化氢气体和脱水的醇类气体（201）；使所述脱水的氟化氢气体和脱水的醇类气体混合，生成气态的刻蚀剂（202）；使所述刻蚀剂与所述工艺腔室内的晶片反应，并使所述工艺腔室内保持高压状态以提高刻蚀选择比（203）；以及将所述反应生成物从所述工艺腔室内抽出（204）。所述去除晶片上的二氧化硅的方法通过使气态的刻蚀剂在高压力下与二氧化硅直接反应，并在反应后将反应产物抽出，实现高选择比、高效率地去除二氧化硅。

Description

去除晶片上的二氧化硅的方法及集成电路制造工艺 技术领域
本发明涉及集成电路制造工艺领域，更具体地，涉及一种应用于集成电路制造工艺中去除晶片上的二氧化硅的方法以及应用该方法的集成电路制造工艺。
背景技术
在集成电路制造工艺领域，目前通常使用硅基材料制造集成电路，硅(或者多晶硅)放置在空气中时表面会自然氧化形成一层致密的二氧化硅(SiO2)层，如图1a所示。在有些工艺中，例如，在金属硅化物(Silicide)工艺中，金属镍铂(NiPt)薄膜要与硅基材料的衬底直接接触，如果衬底表面有一层SiO2，则会增加电阻率，影响器件性能，因此，制造后续工艺前需要去除这层SiO2。而在去除这层SiO2的同时，必须保护其他薄膜/结构不能被去除或者损伤，如图1a所示，隔离层(Spacer，由氮化硅(Si3N4)材料制成)的线宽尺寸会影响器件电性，如漏电(leakage)增加等。因此，需要在去除SiO2的同时尽量保持隔离层(Spacer，Si3N4)不被去除。
如图1b所示，现有工艺多采用湿法刻蚀、等离子体干法刻蚀等方法去除SiO2，其对Si3N4的刻蚀选择比低，对隔离层去除过多，造成隔离层尺寸缩小，从而增大漏电，影响器件性能。
因此，有必要开发一种应用于集成电路制造工艺中的高选择比、高效率的去除晶片上的二氧化硅的方法。
公开于本发明背景技术部分的信息仅仅旨在加深对本发明的一般背景技术的理解，而不应当被视为承认或以任何形式暗示该信息构成已为本领域技术人员所公知的现有技术。
发明内容
本发明提出了一种应用于集成电路制造工艺中去除晶片上的二氧化硅的方法，其通过使气态的刻蚀剂在高压力下与二氧化硅直接反应，并在反应后将反应产物抽出，实现高选择比、高效率地去除二氧化硅。
根据本发明的一个方面，提出了一种去除晶片上的二氧化硅的方法，包括：向工艺腔室内通入脱水的氟化氢气体和脱水的醇类气体；使所述脱水的氟化氢气体和脱水的醇类气体混合，生成气态的刻蚀剂；使所述刻蚀剂与所述工艺腔室内的晶片反应，并使所述工艺腔室内保持高压状态，以提高刻蚀选择比；以及将所述反应生成物从所述工艺腔室内抽出。
其中，所述工艺腔室内的压力为30Torr-300Torr。
其中，所述工艺腔室内的压力为200Torr。
其中，所述工艺腔室内的温度为20℃-80℃。
其中，所述工艺腔室内的温度为40℃。
其中，所述氟化氢气体的流量为100sccm-500sccm，所述醇类气体的流量为100sccm-1000sccm。
其中，所述氟化氢气体的流量为150sccm-225sccm，所述醇类气体的流量为200sccm-450sccm。
其中，所述氟化氢气体与所述醇类气体的流量比为0.8-1.2:1。
其中，所述氟化氢气体与所述醇类气体的流量比为1:1。
其中，所述醇类气体为C1-C8一元醇气体中的至少一种。
其中，所述醇类气体为甲醇、乙醇和异丙醇中的至少一种。
作为另一个方面，本发明还提供一种集成电路制造工艺，其包括本发明上述任一方案所述的去除晶片上的二氧化硅的方法。
其中，所述制造工艺包括利用HARP填充浅沟道绝缘层的轮廓调整的子工艺。在所述子工艺中，首先利用CVD工艺沉积一定厚度的HARP，而后采 用所述的去除晶片上的二氧化硅的方法对STI进行刻蚀而使开口变大，重复执行上述沉积和刻蚀操作，直至工艺结束。
其中，所述制造工艺包括去除STI的硬掩膜层上的SiO2自然氧化层的子工艺，所述STI的硬掩膜层为Si3N4。在所述子工艺中，利用所述的去除晶片上的二氧化硅的方法对STI的硬掩膜层表面上的SiO2自然氧化层进行刻蚀，并控制所述SiO2自然氧化层相对于STI HARP的刻蚀选择比，以便快速去除所述SiO2自然氧化层，且避免过度刻蚀STI HARP。
其中，所述制造工艺包括去除衬垫氧化层的子工艺，所述衬垫氧化层为采用加热方式在衬底表面氧化形成SiO2层，其为STI的硬掩膜层Si3N4的缓冲层。在所述子工艺中，利用所述的去除晶片上的二氧化硅的方法对所述衬垫氧化层进行刻蚀，并控制所述衬垫氧化层相对于STI HARP的刻蚀选择比，以便快速去除所述衬垫氧化层，且避免过度刻蚀STI HARP。
其中，所述制造工艺包括沉积锗硅之前去除硅衬底上的SiO2自然氧化层的子工艺。在所述子工艺中，利用所述的去除晶片上的二氧化硅的方法对所述硅衬底上的SiO2自然氧化层进行刻蚀，并控制所述SiO2自然氧化层相对于多晶硅的刻蚀选择比，以便快速去除所述SiO2自然氧化层，且避免过度损伤Si衬底。
其中，所述制造工艺包括沉积硅化物之前去除衬底表面和多晶硅栅极表面的SiO2自然氧化层的子工艺。在所述子工艺中，利用所述的去除晶片上的二氧化硅的方法对所述衬底表面和多晶硅栅极表面的SiO2自然氧化层进行刻蚀，并控制所述SiO2自然氧化层相对于多晶硅的刻蚀选择比，以便快速去除所述SiO2自然氧化层，且避免过度损伤Si衬底。
其中，所述制造工艺包括2D NAND存储器制造过程中的STI凹槽子工艺，所述NAND存储器包括位于图形密集区域内的浮置栅极和图形密集区域STI HARP以及位于图形稀疏区域内的控制开关栅极和图形稀疏区域STI HARP，所述浮置栅极和所述控制开关栅极为多晶硅，所述图形密集区域STI HARP 和所述图形稀疏区域STI HARP为二氧化硅。在所述子工艺中，利用所述的去除晶片上的二氧化硅的方法对所述图形密集区域STI HARP和所述图形稀疏区域STI HARP进行刻蚀，并控制所述STI HARP相对于所述浮置栅极或者相对于所述控制开关栅极的刻蚀选择比，以便快速去除所述STI HARP，且避免过度损伤所述浮置栅极和所述控制开关栅极。
根据本发明的去除晶片上的二氧化硅的方法及集成电路制造工艺的优点在于：
本发明提供的方法采用气相刻蚀工艺去除晶片上的二氧化硅，相比于现有技术中的湿法刻蚀工艺或等离子体干法刻蚀工艺，本发明是通过化学反应去除SiO2，在该去除工艺中无固态反应生成物，因此，反应生成物可以容易地被泵抽出，从而可以保持腔室内的洁净，减少甚至消除反应生成物所造成的颗粒污染。而且，由于本发明提供的方法无固态反应生成物，因此无需像现有技术那样必须通过高温加热将固态反应生成物汽化或液化后再将其排出，因此本发明提供的方法无需高温加热，为此也就无需对应于加热步骤而设置冷却步骤，因而反应过程简单，这样既能够提高工艺效率、提高工艺产能，又能够省却高温步骤和冷却步骤所对应的工艺成本。
进一步地，本发明提供的方法采用高压工艺(例如50Torr-300Torr)，能够提高SiO2对Si3N4(或多晶硅、HARP等)的刻蚀选择比，这样既能够提高晶片上的二氧化硅的去除效率，又能够降低对衬底的损伤。
类似地，本发明提供的集成电路制造工艺中采用本发明所提供方法去除晶片上的二氧化硅，因而相比于现有技术中采用湿法刻蚀或等离子体干法刻蚀去除二氧化硅的集成电路制造工艺，本发明提供的集成电路制造工艺同样能够提高晶片上的二氧化硅的去除效率，降低对衬底的损伤，并且能够保持腔室内的洁净，减少甚至消除反应生成物所造成的颗粒污染，同时还具有反应过程简单、工艺效率和工艺产能高、成本低等特点。
本发明的方法具有其它的特性和优点，这些特性和优点从并入本文中的附图和随后的具体实施方式中将是显而易见的，或者将在并入本文中的附图和随后的具体实施方式中进行详细陈述，这些附图和具体实施方式共同用于解释本发明的特定原理。
附图说明
通过结合附图对本发明示例性实施方式进行更详细的描述，本发明的上述以及其它目的、特征和优势将变得更加明显，其中，在本发明示例性实施方式中，相同的参考标号通常代表相同部件。
图1a示出了具有自然氧化层的集成电路器件的示意图。
图1b示出了根据现有技术的方法去除二氧化硅的效果的示意图。
图2示出了根据本发明的去除晶片上的二氧化硅的方法的步骤的流程图。
图3示出了根据本发明的去除晶片上的二氧化硅的方法的效果的示意图。
图4a、4b和4c分别示出了根据现有技术的HARP填充浅沟道绝缘层轮廓调整的示意图。
图5a、5b、5c和5d分别示出了根据本发明的去除晶片上的二氧化硅的方法在HARP填充浅沟道绝缘层轮廓调整过程中的作用的示意图。
图6a和6b分别示出了具有自然氧化层的器件和根据本发明的方法去除自然氧化层后的器件的示意图。
图7a和7b分别示出了具有衬垫氧化层的器件和根据本发明的方法去除衬垫氧化层后的器件的示意图。
图8a和8b分别示出了具有自然氧化层的器件和根据本发明的方法去除自然氧化层后的器件的示意图。
图9a和9b分别示出了具有氧化物凹槽的集成电路器件和根据本发明的 方法去除二氧化硅后的器件的效果的示意图。
具体实施方式
下面将参照附图更详细地描述本发明。虽然附图中显示了本发明的优选实施方式，然而应该理解，可以以各种形式实现本发明而不应被这里阐述的实施方式所限制。相反，提供这些实施方式是为了使本发明更加透彻和完整，并且能够将本发明的范围完整地传达给本领域的技术人员。
图2示出了根据本发明的去除晶片上的二氧化硅的方法的步骤的流程图。
在该实施方式中，根据本发明的去除晶片上的二氧化硅的方法包括：步骤201，向工艺腔室内通入脱水的氟化氢气体和脱水的醇类气体；步骤202，使所述脱水的氟化氢气体和脱水的醇类气体混合，生成气态的刻蚀剂；步骤203，使所述刻蚀剂与所述工艺腔室内的晶片的表面上的诸如二氧化硅的待去除物反应，并使所述工艺腔室内保持高压状态以提高刻蚀选择比；以及步骤204，将所述反应生成物从所述工艺腔室内抽出。
该实施方式通过使气态的刻蚀剂在高压力下与二氧化硅直接反应，并在反应后将反应产物抽出，实现高选择比、高效率地去除二氧化硅。
下面详细说明根据本发明的去除晶片上的二氧化硅的方法的具体步骤。
在一个示例中，晶片表面上的待去除物为二氧化硅，根据本发明的去除晶片上的二氧化硅的方法可以包括：步骤201，向工艺腔室内通入脱水的氟化氢气体和脱水的醇类气体；步骤202，使所述脱水的氟化氢气体和脱水的醇类气体混合，生成气态的刻蚀剂；步骤203，使所述刻蚀剂与所述工艺腔室内的晶片的表面上的二氧化硅发生反应，并使所述工艺腔室内保持高压状态以提高刻蚀选择比；以及步骤204，将所述反应生成物从所述工艺腔室内抽出。
优选地，所述反应的条件可以包括：工艺腔室内的压力为 30Torr-300Torr，工艺腔室内的温度为20℃-80℃。进一步优选地，所述反应的条件包括：工艺腔室内的压力为200Torr，工艺腔室内的温度为40℃。实验发现，工艺腔室内的压力在30Torr-300Torr的范围内取值越高，气态刻蚀剂(反应气体)越容易凝结在晶片表面并与SiO2发生反应，这种情况下，SiO2去除速率大大增加，而同时Si3N4的去除速率几乎不增加，这样就大大增加SiO2对Si3N4(或多晶硅、HARP等)的去除选择比(即，刻蚀选择比)。
优选地，所述氟化氢气体的流量可以为100sccm-500sccm，所述醇类气体的流量为100sccm-1000sccm。进一步优选地，所述氟化氢气体的流量为150sccm-225sccm，所述醇类气体的流量为200sccm-450sccm。
优选地，所述氟化氢气体与所述醇类气体的流量比可以为0.8-1.2:1。例如，所述氟化氢气体与所述醇类气体的流量比可以为0.8:1、1:1或1.2:1。进一步优选地，所述氟化氢气体与所述醇类气体的流量比为1:1。使氟化氢气体与醇类气体的流量接近，可以提高去除二氧化硅的均匀性。
优选地，所述醇类气体可以为C1至C8一元醇气体中的至少一种。进一步优选地，所述醇类气体为甲醇(CH3OH)、乙醇(C2H5OH)和异丙醇(IPA)中的至少一种。
在所述醇类气体为气化的甲醇的情况下；所述刻蚀剂为HF2 -和CH3OH2 +；所述反应产物为四氟化硅、甲醇以及水。具体地，在采用甲醇(CH3OH)时，根据本发明的去除晶片上的二氧化硅的方法的反应式可以表示为：
HF+CH3OH→HF2 -+CH3OH2 +    (1)
HF2 -+CH3OH2 ++SiO2→SiF4+CH3OH+H2O    (2)
可以使用经过脱水的HF气体和脱水的CH3OH气体在腔室内部混合，生成气态的刻蚀剂HF2 -和CH3OH2 +，工艺时腔室内的压力可以设定为200Torr，腔室内的温度为40℃，HF2 -和CH3OH2 +混合与SiO2反应生成SiF4、CH3OH和H2O。CH3OH有很强的吸水性，能够减少H2O在晶片表面的残留，同时SiF4、CH3OH和H2O等反应生成物都可以在反应后用泵抽出。
在实际应用中，本发明的去除晶片上的二氧化硅的方法所采用的工艺腔室可以与下一道工艺集成在一个真空平台，这样，在去除晶片表面SiO2后可在不破坏真空环境的情况下进行下一道工艺，防止晶片在进行一下道工艺前因再次处于非真空环境中而被再次氧化，并影响下一道工艺。例如，硅化(Silicide)工艺中铂镍(NiPt)沉积前；锗硅(SiGe)沉积前。
根据本发明的去除晶片上的二氧化硅的方法的优点在于：
1、选择比高。本发明通过高压工艺来提高选择比，实验发现采用高压工艺(例如，工艺压力为200Torr)时气态刻蚀剂更容易凝结在晶片表面并与SiO2发生反应，这时SiO2去除速率大大增加，而同时Si3N4的去除速率几乎不增加，从而在增大SiO2去除速率的同时，减小对衬底的损伤。也就是说，本发明提供的方法大大增加SiO2相对于Si3N4(或多晶硅、HARP等)的去除选择比。
2、不使用等离子体，不容易形成其他副产物，这样既不会损伤衬底、减少颗粒污染、保持腔室内干净；同时又能够降低设备成本。
3、通过化学反应去除SiO2，因而无固态反应生成物，由此反应生成物可以被泵抽出。图5a至图5b示出了根据本发明的去除晶片上的二氧化硅的方法的另一效果的示意图。如图5所示，由于反应生成物扩散好，所以对于密集区域的小孔洞中的SiO2和稀疏区域的SiO2去除量一致，反应生成物如气态SiF4，易被泵抽出，不会造成小孔洞堵塞，清洗效果好，对小孔洞清洗效果高，去除均匀性高。而且，本实施例提供的方法还可以改善衬垫氧化层移除(pad oxide removal)和STI(Shallow Trench Isolation，浅沟槽隔离)凹槽(recess)刻蚀的负载作用，使大、小的孔洞凹槽深刻蚀一致、STI高度一致。另外CH3OH和H2O也很容易被抽走，不会凝结在腔室壁，颗粒少。
4、本发明实施例提供的去除晶片上的二氧化硅的方法，工艺温度较低，例如20℃-80℃，因此无需高温加热，相应地也就无需再设置与高温加热步 骤相对应的冷却步骤，因而反应过程简单，一步即可完成反应，这样，不仅能够提高工艺效率、提高产能，又能够节约至少是由加热步骤和冷却步骤所产生的成本。
应用示例
根据本发明的另一方面，还可以提供一种集成电路制造工艺，所述制造工艺包括如上所述的去除晶片上的二氧化硅的方法。
本发明提供的集成电路制造工艺，由于其采用本发明上述实施例提供的方法去除晶片上的二氧化硅，因而相比于现有技术中采用湿法刻蚀或等离子体干法刻蚀去除二氧化硅的集成电路制造工艺，本发明提供的集成电路制造工艺同样能够提高晶片上的二氧化硅的去除效率，降低对衬底的损伤，并且能够保持腔室内的洁净，减少甚至消除反应生成物所造成的颗粒污染，同时还具有反应过程简单、工艺效率和工艺产能高、成本低等特点。
为便于理解本发明实施方式的方案及其效果，以下给出几个具体应用示例。本领域技术人员应理解，该示例仅为了便于理解本发明，其任何具体细节并非意在以任何方式限制本发明。
示例1：利用HARP填充浅沟道绝缘层的轮廓调整(STI HAPR deposition gap fill profile modified)：
图4a、4b和4c分别示出了根据现有技术的利用HARP(High Aspect Ratio Process,高深宽比工艺)填充浅沟道绝缘层的轮廓调整的示意图，其中，图4a为STI刻蚀之后的器件，图4b为STI HARP沉积过程中的器件，图4c为STI HARP沉积后产生空洞(void)的器件。如图4a、4b和4c所示，STI HAPR沉积是使用CVD方式沉积，由于28nm STI深宽比大，同时STI刻蚀的轮廓不好，造成STI HARP沉积时很容易产生空洞(void)，而且图4a、4b和4c所用现有技术产生固态反应生成物，并且小孔洞清洗效率低，产能低。
本示例1中的集成电路制造工艺包括利用HARP填充浅沟道绝缘层的轮 廓调整的子工艺。在该子工艺中，首先利用CVD工艺沉积一定厚度的HARP，而后采用所述的去除晶片上的二氧化硅的方法对STI进行刻蚀而使开口变大，重复执行上述沉积和刻蚀操作，直至工艺结束。
具体地，图5a、5b、5c和5d分别示出了根据本发明的去除晶片上的二氧化硅的方法在HARP填充浅沟道绝缘层的轮廓调整过程中的作用的示意图，其中，图5a为STI刻蚀之后的器件，图5b为STI HARP沉积过程中的器件，图5c为采用本发明的去除晶片上的二氧化硅的方法进行STI开口调整的器件，图5d为STI HARP沉积后的器件。
在该示例中，根据本发明的去除晶片上的二氧化硅的方法的步骤为：将脱水的氟化氢气体和脱水的甲醇混合，生成气态的刻蚀剂HF2 -和CH3OH2 +；然后，将刻蚀剂通入工艺腔室中，与所述工艺腔室内的晶片表面上的SiO2接触进行反应，生成SiF4、CH3OH和H2O，其中，工艺腔室中工艺条件为：腔室内的压力设定为200Torr，腔室内的温度保持在40℃；反应完成后，用泵抽出SiF4、CH3OH和H2O。
如图5a、5b、5c和5d所示，本发明实施例提供的集成电路制造工艺中，采用CVD工艺沉积一定厚度的HARP(沉积一层SiO2)后就要刻蚀一下STI，让开口变大，这样才能不产生空洞。采用本发明的方法去除SiO2，非固态的反应生成物易于被泵抽出，从而可以保持腔室内的洁净，减少甚至消除反应生成物所造成的颗粒污染，本实施例提供的方法无需高温加热，反应过程简单，从而具有工艺效率和工艺产能高，成本低的特点；进一步地，本发明提供的方法工艺压力为200Torr、工艺温度为40℃，由此能够提高SiO2对HARP等的刻蚀选择比，这样既能提高晶片上的二氧化硅的去除效率，又能降低对衬底的损伤，从而能够控制开口的轮廓，增加CVD HARP孔隙的填充能力。
示例2：STI Si3N4自然氧化层去除：
本示例2中的集成电路制造工艺包括去除STI的硬掩膜层上的SiO2自然氧化层的子工艺，所述STI的硬掩膜层为Si3N4。在该子工艺中，利用本发明提供的去除晶片上的二氧化硅的方法对STI的硬掩膜层表面上的SiO2自然氧化层进行刻蚀，并控制SiO2自然氧化层相对于STI HARP的刻蚀选择比，以便快速去除SiO2自然氧化层，且避免过度刻蚀STI HARP。
具体地，图6a和6b分别示出了具有自然氧化层的器件和根据本发明的方法去除自然氧化层后的器件的示意图。
如图6a所示，集成电路制造工艺使用Si3N4作为STI的硬掩膜(Hard Mask)层，在去除该硬掩膜层时需使用H3PO4湿法去除。然而，带有该硬掩膜层的晶片在空气中放置一段时间后会在Si3N4层的表面自然氧化生成一层致密的SiO2层，在去除Si3N4之前要先去除这层SiO2自然氧化层。若使用去除该硬掩膜层时所采用的H3PO4湿法来去除SiO2，则SiO2的去除速率非常慢。另外，图6a中的STI HARP是使用CVD方式沉积的SiO2层，该SiO2层的致密性很低，非常容易被去除，这种情况下，在去除Si3N4层表面上的自然氧化层SiO2层时，需要控制好STI HARP的去除量，即控制好Si3N4表面上的SiO2自然氧化层相对于STI HARP的刻蚀选择比，以保证STI的台阶高度(即，STI高出衬底表面的高度)，因为STI的台阶高度会影响器件的电性性能，因此其既不能过高，也不能过低。
为此，就需要采用本发明的方法去除Si3N4表面上的这层SiO2自然氧化层，图6b即为采用该方法去除Si3N4表面上的SiO2氧化层后的器件形貌。在该示例中，所采用的本发明提供的二氧化硅去除方法的处理步骤类似于示例1，在此不再赘述。
根据本发明的方法采用高压工艺，可以提高Si3N4表面上的SiO2自然氧化层相对于STI HARP的刻蚀选择比，从而能够快速地去除Si3N4表面上的SiO2自然氧化层，同时又能够避免过度刻蚀STI HARP，由此能够很好地控制STI的台阶高度；而且，根据本发明的方法，去除Si3N4表面上的SiO2自然氧化 层时，不产生固态反应生成物，因此可以避免出现反应生成物堵塞小孔洞的问题，从而能够提高小孔洞的清洗效率低，提高产能。
示例3：集成电路衬垫氧化层去除(IC Pad oxide remove)：
本示例3中的集成电路制造工艺包括去除衬垫氧化层的子工艺，其中，衬垫氧化层为采用加热方式在衬底表面氧化形成SiO2层，其为STI的硬掩膜层Si3N4的缓冲层。在该子工艺中，利用本发明提供的去除晶片上的二氧化硅的方法对上述衬垫氧化层进行刻蚀，并控制衬垫氧化层相对于STI HARP的刻蚀选择比，以便快速去除衬垫氧化层，且避免过度刻蚀STI HARP。
具体地，图7a和7b分别示出了具有衬垫氧化层的器件和根据本发明的方法去除衬垫氧化层后的器件的示意图。
如图7a所示，衬垫氧化层(Pad oxide)作为STI的硬掩膜层Si3N4的缓冲层，是使用炉管方式在衬底表面热氧化而成的一层SiO2层，其厚度可根据不同的工艺确定(例如，28nm工艺，该SiO2层的厚度约为50A)。该SiO2衬垫氧化层在后续工艺前需要去除。另外，图7a中的STI HARP是使用CVD方式沉积的SiO2层，该SiO2层的致密性很低，这种情况下，就需要在去除衬垫氧化层时，控制好STI HARP的去除量，即控制好衬垫氧化层相对于STIHARP的刻蚀选择比，以便能够快速去除衬垫氧化层，同时又能够避免过度刻蚀STI HARP，从而保证STI的台阶高度。
为此，就需要采用本发明的方法去除衬垫氧化层，图7b即为采用该方法去除衬垫氧化层后的器件的形貌示意图。在该示例中，所采用的本发明提供的二氧化硅去除方法的处理步骤类似于示例1，在此不再赘述。
根据本发明的方法采用高压工艺，可以提高衬垫氧化层相对于STI HARP的刻蚀选择比，从而能够快速地去除衬垫氧化层，同时又能够避免过度刻蚀STI HARP，以便控制STI的台阶高度；而且，根据本发明的方法，去除衬垫氧化层时，不产生固态反应生成物，因此能够提高工艺效率及工艺产能，同 时避免因采用湿法刻蚀而产生凹陷(divot)并影响电性能等问题。
示例4：沉积锗硅(SiGe)之前去除自然氧化层：
本示例4中的集成电路制造工艺包括沉积锗硅之前去除硅衬底上的SiO2自然氧化层的子工艺。在该子工艺中，利用本发明提供的去除晶片上的二氧化硅的方法对硅衬底上的SiO2自然氧化层进行刻蚀，并控制SiO2自然氧化层相对于多晶硅的刻蚀选择比，以便快速去除SiO2自然氧化层，且避免过度损伤Si衬底。
具体地，图8a和8b分别示出了具有自然氧化层的器件和根据本发明的方法去除自然氧化层后的器件的示意图。
如图8a所示，在Si衬底上为后续的SiGe沉积进行预刻蚀后，刻蚀区域内部的Si衬底会暴露在空气中而发生自然氧化，这层自然氧化层会造成器件的电性能失效等问题，所以必须在沉积SiGe之前将这层自然氧化层去除干净，且在去除这层SiO2时不能损伤Si衬底，也就是说，要控制好这层SiO2自然氧化层相对于多晶硅(即，Si衬底)的刻蚀选择比。
为此，就需要采用本发明的方法去除这层SiO2自然氧化层，图8b即为采用该方法去除SiO2自然氧化层后的器件的形貌示意图。在该示例中，所采用的本发明提供的二氧化硅去除方法的处理步骤类似于示例1，在此不再赘述。
根据本发明的方法采用高压工艺，可以提高SiO2自然氧化层相对于多晶硅的刻蚀选择比，从而能够快速地去除SiO2自然氧化层，同时又能够减小对栅极和Si衬底的损伤。而且，根据本发明的方法，去除SiO2自然氧化层时，不产生固态反应生成物，从而可以避免现有技术中产生固态反应生成物且在该固态反应生成物高温升华过程中Si衬底又会再次遭受氧化的问题，因此，集成电路制造工艺应用本发明提供的去除二氧化硅的方法，既可以提高工艺效率和工艺产能，又能够提高器件性能。
示例5：沉积硅化物(Silicide)之前去除自然氧化层：
本示例5中的集成电路制造工艺包括沉积硅化物之前去除衬底表面和多晶硅栅极表面的SiO2自然氧化层的子工艺。在该子工艺中，利用本发明提供的去除晶片上的二氧化硅的方法对衬底表面和多晶硅栅极表面的SiO2自然氧化层进行刻蚀，并控制SiO2自然氧化层相对于多晶硅的刻蚀选择比，以便快速去除SiO2自然氧化层，且避免过度损伤Si衬底。
具体地，图1a和图3分别示出了具有自然氧化层的器件和根据本发明的方法去除二氧化硅后的器件的形貌示意图。
如图1a所示，晶片放置在空气中时，Si衬底表面和多晶硅栅极表面会自然氧化生成一层致密的SiO2层，为了避免接触电极(contact)与衬底之间的接触电阻过大，需要在沉积Ni或NiPt(5-10％)(在后续工艺中会形成NiPt硅化物)之前将SiO2自然氧化层去除掉，然而在该去除过程中不能损伤Si衬底。此外，多晶硅栅极两侧有用作绝缘隔离片的Si3N4，在去除SiO2自然氧化层的过程中也不能损伤Si3N4。
为此，就需要采用本发明的方法去除这层SiO2自然氧化层，图3即为采用该方法去除SiO2自然氧化层后的器件的形貌示意图。在该示例中，所采用的本发明提供的二氧化硅去除方法的处理步骤类似于示例1，在此不再赘述。
根据本发明的方法采用高压工艺，可以提高SiO2自然氧化层相对于Si3N4和Si衬底的刻蚀选择比，从而能够快速地去除Si衬底表面和多晶硅栅极表面的SiO2自然氧化层，同时又能够减小对多晶硅栅极和Si衬底的损伤，避免产生绝缘隔离片尺寸缩小、电漏率增大等问题。而且，根据本发明的方法，去除SiO2自然氧化层时，不产生固态反应生成物，从而可以避免现有技术中因存在固态反应生成物而导致的孔洞底部的SiO2去除效率低，且在该固态反应生成物高温升华过程中Si衬底又会再次遭受氧化的问题。因此，集成电路制造工艺应用本发明提供的去除二氧化硅的方法，既可以提高工艺效率和 工艺产能，又能够提高器件性能。
示例6：STI HARP氧化凹槽刻蚀(STI HARP oxide recess etch)：
本示例6所示的集成电路制造工艺包括2D NAND存储器制造过程中的STI凹槽子工艺，所述NAND存储器包括位于图形密集区域内的浮置栅极和图形密集区域STI HARP以及位于图形稀疏区域内的控制开关栅极和图形稀疏区域STI HARP，所述浮置栅极和所述控制开关栅极为多晶硅，所述图形密集区域STI HARP和所述图形稀疏区域STI HARP为二氧化硅。在该子工艺中，利用本发明提供的去除晶片上的二氧化硅的方法对所述图形密集区域STI HARP和所述图形稀疏区域STI HARP进行刻蚀，并控制STI HARP相对于浮置栅极或者相对于控制开关栅极的刻蚀选择比，以便快速去除STIHARP，且避免过度损伤浮置栅极和控制开关栅极。
具体地，图9a和9b分别示出了具有氧化物凹槽的集成电路器件和根据本发明的方法去除二氧化硅后的器件的效果的示意图。
如图9a所示，本示例中的STI凹槽工艺是2D NAND制造过程中的工艺，NAND是存储器件。在图9a中，左侧的图形密集区域为器件的存储区域，包括浮置栅极(即，图形密集区域内的深色条柱，其为多晶硅)和图形密集区域STI HARP(即，图形密集区域内的浅色条柱，其为二氧化硅)；右侧的图形稀疏区域为控制区域，包括源极/漏极的选择性控制开关栅极(即，图形稀疏区域内的深色条柱，其为多晶硅，以下简称“控制开关栅极”)和图形稀疏区域STI HARP(图形稀疏区域内的浅色条柱，为二氧化硅)。在STI凹槽工艺过程中，图形密集区域和图形稀疏区域的STI HARP的去除量需要一致。
为此，就需要采用本发明的方法去除STI HARP，图9b即为采用该方法去除二氧化硅(STI HARP)后的器件的形貌示意图。在该示例中，所采用的本发明提供的二氧化硅去除方法的处理步骤类似于示例1，在此不再赘述。
根据本发明的方法采用高压工艺，可以提高STI HARP相对于浮置栅极或者相对于源极/漏极的选择性控制开关栅极的刻蚀选择比，即，SiO2相对于多晶硅的刻蚀选择比，从而能够快速地去除SiO2，同时又能够减小对多晶硅的损伤。而且，根据本发明的方法，去除SiO2层时，不产生固态反应生成物，从而不会出现现有技术中常见的问题：即，因产生固态反应生成物而导致小孔洞易于堵塞且不易清洗，而且在固态反应生成物高温升华过程中多晶硅又会再次遭受氧化的问题。因此，集成电路制造工艺应用本发明提供的去除二氧化硅的方法，既可以提高工艺效率和工艺产能，又能够提高器件性能。
本领域技术人员应理解，上面对本发明的实施方式的描述的目的仅为了示例性地说明本发明的实施方式的有益效果，并不意在将本发明的实施方式限制于所给出的任何示例。
以上已经描述了本发明的各实施方式，上述说明是示例性的，并非穷尽性的，并且也不限于所披露的各实施方式。在不偏离所说明的各实施方式的范围和精神的情况下，对于本技术领域的普通技术人员来说许多修改和变更都是显而易见的。本文中所用术语的选择，旨在最好地解释各实施方式的原理、实际应用或对市场中的技术的改进，或者使本技术领域的其它普通技术人员能理解本文披露的各实施方式。

Claims (18)

  1. 一种去除晶片上的二氧化硅的方法，其特征在于，包括：
    向工艺腔室内通入脱水的氟化氢气体和脱水的醇类气体；
    使所述脱水的氟化氢气体和脱水的醇类气体混合，生成气态的刻蚀剂；
    使所述刻蚀剂与所述工艺腔室内的晶片反应，并使所述工艺腔室内保持高压状态，以提高刻蚀选择比；以及
    将所述反应生成物从所述工艺腔室内抽出。
  2. 根据权利要求1所述的去除晶片上的二氧化硅的方法，其中，所述工艺腔室内的压力为30Torr-300Torr。
  3. 根据权利要求2所述的去除晶片上的二氧化硅的方法，其中，所述工艺腔室内的压力为200Torr。
  4. 根据权利要求1所述的去除晶片上的二氧化硅的方法，其中，所述工艺腔室内的温度为20℃-80℃。
  5. 根据权利要求4所述的去除晶片上的二氧化硅的方法，其中，所述工艺腔室内的温度为40℃。
  6. 根据权利要求1所述的去除晶片上的二氧化硅的方法，其中，所述氟化氢气体的流量为100sccm-500sccm，所述醇类气体的流量为100sccm-1000sccm。
  7. 根据权利要求6所述的去除晶片上的二氧化硅的方法，其中，所述氟化氢气体的流量为150sccm-225sccm，所述醇类气体的流量为 200sccm-450sccm。
  8. 根据权利要求1所述的去除晶片上的二氧化硅的方法，其中，所述氟化氢气体与所述醇类气体的流量比为0.8-1.2:1。
  9. 根据权利要求6所述的去除晶片上的二氧化硅的方法，其中，所述氟化氢气体与所述醇类气体的流量比为1:1。
  10. 根据权利要求1所述的去除晶片上的二氧化硅的方法，其中，所述醇类气体为C1-C8一元醇气体中的至少一种。
  11. 根据权利要求10所述的去除晶片上的二氧化硅的方法，其中，所述醇类气体为甲醇、乙醇和异丙醇中的至少一种。
  12. 一种集成电路制造工艺，其中，包括根据权利要求1-11中任意一项所述的去除晶片上的二氧化硅的方法。
  13. 根据权利要求12所述的集成电路制造工艺，其中，所述制造工艺包括利用HARP填充浅沟道绝缘层的轮廓调整的子工艺，
    在所述子工艺中，首先利用CVD工艺沉积一定厚度的HARP，而后采用所述的去除晶片上的二氧化硅的方法对STI进行刻蚀而使开口变大，重复执行上述沉积和刻蚀操作，直至工艺结束。
  14. 根据权利要求12所述的集成电路制造工艺，其中，所述制造工艺包括去除STI的硬掩膜层上的SiO2自然氧化层的子工艺，所述STI的硬掩膜层为Si3N4，
    在所述子工艺中，利用所述的去除晶片上的二氧化硅的方法对STI的硬掩膜层表面上的SiO2自然氧化层进行刻蚀，并控制所述SiO2自然氧化层相对于STI HARP的刻蚀选择比，以便快速去除所述SiO2自然氧化层，且避免过度刻蚀STI HARP。
  15. 根据权利要求12所述的集成电路制造工艺，其中，所述制造工艺包括去除衬垫氧化层的子工艺，所述衬垫氧化层为采用加热方式在衬底表面氧化形成SiO2层，其为STI的硬掩膜层Si3N4的缓冲层，
    在所述子工艺中，利用所述的去除晶片上的二氧化硅的方法对所述衬垫氧化层进行刻蚀，并控制所述衬垫氧化层相对于STI HARP的刻蚀选择比，以便快速去除所述衬垫氧化层，且避免过度刻蚀STI HARP。
  16. 根据权利要求12所述的集成电路制造工艺，其中，所述制造工艺包括沉积锗硅之前去除硅衬底上的SiO2自然氧化层的子工艺，
    在所述子工艺中，利用所述的去除晶片上的二氧化硅的方法对所述硅衬底上的SiO2自然氧化层进行刻蚀，并控制所述SiO2自然氧化层相对于多晶硅的刻蚀选择比，以便快速去除所述SiO2自然氧化层，且避免过度损伤Si衬底。
  17. 根据权利要求12所述的集成电路制造工艺，其中，所述制造工艺包括沉积硅化物之前去除衬底表面和多晶硅栅极表面的SiO2自然氧化层的子工艺，
    在所述子工艺中，利用所述的去除晶片上的二氧化硅的方法对所述衬底表面和多晶硅栅极表面的SiO2自然氧化层进行刻蚀，并控制所述SiO2自然氧化层相对于多晶硅的刻蚀选择比，以便快速去除所述SiO2自然氧化层，且避免过度损伤Si衬底。
  18. 根据权利要求12所述的集成电路制造工艺，其中，所述制造工艺包括2D NAND存储器制造过程中的STI凹槽子工艺，所述NAND存储器包括位于图形密集区域内的浮置栅极和图形密集区域STI HARP以及位于图形稀疏区域内的控制开关栅极和图形稀疏区域STI HARP，所述浮置栅极和所述控制开关栅极为多晶硅，所述图形密集区域STI HARP和所述图形稀疏区域STI HARP为二氧化硅，
    在所述子工艺中，利用所述的去除晶片上的二氧化硅的方法对所述图形密集区域STI HARP和所述图形稀疏区域STI HARP进行刻蚀，并控制所述STI HARP相对于所述浮置栅极或者相对于所述控制开关栅极的刻蚀选择比，以便快速去除所述STI HARP，且避免过度损伤所述浮置栅极和所述控制开关栅极。
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JP7204348B2 (ja) 2018-06-08 2023-01-16 東京エレクトロン株式会社 エッチング方法およびエッチング装置
KR20220011212A (ko) * 2018-09-13 2022-01-27 샌트랄 글래스 컴퍼니 리미티드 실리콘 산화물의 에칭 방법 및 에칭 장치
KR102902002B1 (ko) 2018-09-13 2025-12-18 샌트랄 글래스 컴퍼니 리미티드 실리콘 산화물의 에칭 방법 및 에칭 장치

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US10937661B2 (en) 2021-03-02
US20190244828A1 (en) 2019-08-08
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