WO2018014538A1 - 张弛振荡器及单片集成芯片 - Google Patents

张弛振荡器及单片集成芯片 Download PDF

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Publication number
WO2018014538A1
WO2018014538A1 PCT/CN2017/072886 CN2017072886W WO2018014538A1 WO 2018014538 A1 WO2018014538 A1 WO 2018014538A1 CN 2017072886 W CN2017072886 W CN 2017072886W WO 2018014538 A1 WO2018014538 A1 WO 2018014538A1
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current source
circuit
switching element
current
capacitor
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PCT/CN2017/072886
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English (en)
French (fr)
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樊骕研
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珠海全志科技股份有限公司
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Publication of WO2018014538A1 publication Critical patent/WO2018014538A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/012—Modifications of generator to improve response time or to decrease power consumption

Definitions

  • the present invention relates to the field of oscillators, and in particular to a relaxation oscillator based on a bootstrap technique, and to a monolithic integrated chip using the relaxation oscillator.
  • the present invention is based on a Chinese invention patent application whose application date is July 20, 2016, the application publication number is CN106209027A, and the application publication date is December 07, 2016. The content of the application is incorporated herein by reference. .
  • the mainstream clock sources include an off-chip crystal oscillator, an on-chip harmonic oscillator, an on-chip ring oscillator, and an on-chip relaxation oscillator. Good frequency accuracy and stability are widely used.
  • the relaxation oscillator is widely used and studied because of its low power consumption, easy frequency control, and simple structure.
  • Cia Patent Application Publication No. CN104124921A discloses an invention entitled "Low-Voltage Low-Power CMOS Relaxation Oscillator and Method Based on Current Mode Comparator", which uses two capacitors to avoid delay time of capacitor discharge The effect on frequency stability, but the area of the capacitive circuit layout has doubled, resulting in increased costs.
  • the threshold voltage at the input of the SR latch is out of regulation and is also affected by temperature. Once the offset voltage or temperature changes cause the threshold voltage to change, the frequency accuracy and stability will be deteriorated.
  • a capacitor is charged by a capacitor every half cycle during oscillation and then alternated. When the device discharges a capacitor, the charging current source still supplies current. Therefore, at any time, the current consumed by the main circuit oscillating the capacitor is twice the reference current, resulting in low current utilization and large power consumption.
  • the Chinese Patent Application Publication No. CN103338026A discloses an invention entitled "Zhang Relaxation Oscillator" which uses P-type polysilicon resistors and N-type polysilicon with complementary temperature coefficients in order to improve the frequency stability to temperature.
  • the resistance in which the unit resistance of the N-type polysilicon resistor is low, increases the area occupied by the resistor in the circuit layout, resulting in an increase in cost.
  • the oscillator is designed with a relatively complicated comparator structure and switch switching unit.
  • a more complicated clock generator is designed, which increases the circuit. Complexity extends the development cycle.
  • the loop delay is long, resulting in a long non-ideal delay in the period.
  • the non-ideal delay time is susceptible to temperature and voltage, resulting in frequency stability. limit.
  • the comparator needs to supply voltage to the comparator stage by means of an operational amplifier, and in order to obtain good performance, the comparator stage needs to consume quiescent current, thus resulting in higher power consumption of the oscillator circuit.
  • the capacitor is charged once every half cycle, and then immediately discharged, and then charged for the second half of the cycle. Therefore, at any time, the current consumed by the oscillator main circuit on the capacitor is twice the reference current, and the current utilization rate is low.
  • a primary object of the present invention is to provide a relaxation oscillator that reduces production costs, shortens development cycles, improves frequency stability, and achieves ultra-low power consumption.
  • Another object of the present invention is to provide a monolithic integrated chip with high frequency stability and low power consumption.
  • the relaxation oscillator provided by the present invention includes a relaxation oscillator circuit including a threshold voltage generation circuit, a capacitor charge and discharge circuit, and a comparator circuit, and an inverse input of the threshold voltage generation circuit to the comparator circuit.
  • the terminal input threshold voltage signal, the capacitor charging and discharging circuit inputs a capacitor voltage signal to the non-inverting input end of the comparator circuit;
  • the threshold voltage generating circuit includes a first current source, a second current source and a threshold resistor, and the first current source passes the first inversion
  • the switching element applies a current to the threshold resistor, and the second current source draws current to the threshold resistor through the first in-phase switching element;
  • the capacitor charging and discharging circuit includes a third current source, a fourth current source, and a capacitor, and the third current source passes the second reverse
  • the phase switching element applies a current to the capacitor, and the fourth current source draws a current to the capacitor through the second non-inverting switching element.
  • the first inverting switching element, the first in-phase switching element, the second inverting switching element, and the second in-phase switching element are electrically coupled to the output of the comparator circuit, respectively.
  • the circuit can automatically control the process of charging and discharging the capacitor.
  • the output of the comparator circuit is electrically coupled to a branch between the threshold resistor and the capacitor.
  • the relaxation oscillator of the present invention increases the voltage range of the charge and discharge of the capacitor by feeding back the output voltage of the comparator to the branch between the threshold resistor and the capacitor, and the capacitor is charged and then uses the existing charge. Discharge, improve current utilization.
  • the comparator circuit includes a current mode comparison circuit and an inverter circuit, and the current mode comparison circuit transmits a voltage signal to the inverter circuit.
  • the comparator circuit compares the threshold resistance and the voltage of the capacitor through the current mode comparator, and then digitally quantizes the voltage value through the inverter circuit. This makes the conversion of the output level faster.
  • the first current source and the third current source are respectively electrically connected to the power line, and the second current source and the fourth current source are respectively grounded.
  • the first current source and the third current source of the present invention respectively supply a current source to the threshold resistor and the capacitor when the capacitor is charged, and the second current source and the fourth current source respectively provide the threshold resistor and the capacitor when the capacitor is discharged. Battery.
  • the first current source, the second current source, the third current source, and the fourth current source respectively comprise a MOS transistor, and the MOS transistor of the first current source is connected to the MOS transistor of the third current source.
  • the MOS transistor of the second current source is connected to the MOS transistor of the fourth current source in a common gate.
  • the relaxation oscillator circuit further includes a bias circuit, and the bias circuit is electrically connected to the first current source, the second current source, the third current source, and the fourth current source, respectively.
  • a bias circuit is electrically connected to the first current source, the second current source, the third current source, and the fourth current source, respectively, to provide a reference current source for the oscillating circuit.
  • the monolithic integrated chip provided by the present invention includes the relaxation oscillator provided by the present invention, and the relaxation oscillator provides a clock signal to the clock use circuit in the monolithic integrated chip.
  • the relaxation oscillator of the present invention uses a threshold voltage generating circuit to generate two threshold voltages, and uses a charge and discharge circuit to charge and discharge the same capacitor node.
  • the oscillator formed by such a structure has a simple structure, a small number of modules, and a high current utilization rate, thereby achieving a problem of shortening the development cycle, reducing the layout area of the board, and achieving ultra-low power consumption.
  • the monolithic integrated chip of the present invention uses a relaxation oscillator, which has a simple structure, few modules, low power consumption, and high current utilization, so that the monolithic integrated chip can achieve high frequency stability and low power consumption.
  • Figure 1 is an electrical schematic diagram of a first embodiment of a relaxation oscillator of the present invention.
  • Figure 2 is an electrical schematic diagram of a second embodiment of the relaxation oscillator of the present invention.
  • FIG 3 is a schematic diagram showing the voltage output waveform of the capacitor C2 reference terminal voltage VC2 in the second embodiment of the relaxation oscillator of the present invention.
  • Figure 4 is an electrical schematic diagram of a third embodiment of the relaxation oscillator of the present invention.
  • the relaxation oscillator of the present invention is a relaxation oscillator based on a bootstrap technique, and the present invention can be applied to the design of an oscillator, and can also be applied to the design of a monolithic integrated chip.
  • FIG. 1 is an electrical schematic diagram of a relaxation oscillator circuit of an embodiment of a relaxation oscillator of the present invention.
  • the relaxation oscillator circuit of the oscillator includes a threshold voltage generating circuit 1, a capacitor charging and discharging circuit 2, and a comparator circuit 3, and the threshold voltage generating circuit 1 inputs a threshold to the inverting input terminal of the comparator circuit 3.
  • the voltage signal, the capacitor charging and discharging circuit 2 inputs a capacitance voltage signal to the non-inverting input terminal of the comparator circuit 3.
  • the threshold voltage generating circuit 1 includes a first current source I1, a second current source I2, and a threshold resistor R1.
  • the first current source I1 applies a current to the threshold resistor R1 through the first inverting switching element SW1 (ie, current flows from the first current source).
  • I1 flows through the first inverting switching element SW1 to the threshold resistor R1)
  • the second current source I2 draws current to the threshold resistor R1 through the first in-phase switching element SW2 (ie, current flows from the threshold resistor R1 through the first in-phase switching element SW2)
  • the capacitor charging and discharging circuit 2 includes a third current source I3, a fourth current source I4, and a capacitor C1.
  • the third current source I3 applies a current to the capacitor C1 through the second inverting switching element SW3 (ie, the current passes from the third current source I3).
  • the second inverting switching element SW3 flows to the capacitor C1), and the fourth current source I4 draws current to the capacitor C1 through the second in-phase switching element SW4 (ie, current flows from the capacitor C1 through the second in-phase switching element SW4 to the fourth current source I4) .
  • the first current source I1 and the third current source I3 are electrically connected to the power line VDD, respectively, and the second current source I2 and the fourth current source I4 are electrically connected to the ground line GND, respectively.
  • the first inverting switching element SW1, the first in-phase switching element SW2, the second inverting switching element SW3, and the second in-phase switching element SW4 are electrically connected to the output of the comparator circuit 3, respectively, and receive an output voltage feedback signal. Further, the output of the comparator circuit 3 is electrically connected to a branch between the threshold resistor R1 and the capacitor C1.
  • the threshold voltage generating circuit 1 is provided with a first current source I1 and a second current source I2, a first inverting switching element SW1 having an opposite enable level, a first in-phase switching element SW2, and a threshold resistor R1.
  • first inverting switching element SW1 When the first inverting switching element SW1 is turned on, the first in-phase switching element SW2 is turned off, and the first current source I1 and the threshold resistor R1 can establish a voltage difference of I1 ⁇ R1; otherwise, the second current source I2 can be connected with the threshold resistor.
  • R1 establishes a differential pressure of I2 ⁇ R1.
  • the capacitor charging and discharging circuit 2 is provided with a third current source I3 and a fourth current source I4, second inversion switching elements SW3 and second in-phase switching elements SW4 and capacitors C1 having opposite levels of enable.
  • a third current source I3 and a fourth current source I4 second inversion switching elements SW3 and second in-phase switching elements SW4 and capacitors C1 having opposite levels of enable.
  • the comparator circuit 3 compares the threshold voltage VR1 generated by the threshold resistor R1 with the voltage VC1 of the capacitor C1 charge and discharge node, and outputs a voltage of the power line VDD terminal or a control voltage Vout1 of the ground line GND terminal voltage according to the comparison result, and the control voltage Vout1 It is used to control the reference terminal voltage of the threshold resistor R1 and the capacitor C1 and the conduction state of the switch.
  • the working principle of the relaxation oscillator circuit is as follows:
  • Vout1 is the ground GND voltage VGND.
  • the first inverting switching element SW1 and the second inverting switching element SW3 are turned on, the threshold voltage VR1 is established by the first current source I1, the capacitor C1 is charged by the third current source I3, and the capacitor voltage VC1 rises.
  • the control voltage Vout1 becomes the power supply voltage VDD, and the reference terminal of the resistor R1 and the capacitor C1 becomes the power supply voltage VDD to perform bootstrap.
  • the control voltage Vout1 is in a high state
  • the inverting switching element SW1 and the second inverting switching element SW3 are turned off when the control voltage Vout1 is at a high level
  • the first in-phase switching element SW2 and the second in-phase switching element SW4 are turned on when the control voltage Vout1 is at a high level.
  • the threshold voltage VR1 is established by the second current source I2, and the capacitor voltage VC1 is changed to VR1+VDD by bootstrap and discharged by the fourth current source I4, and the capacitor voltage VC1 falls.
  • the comparator output control voltage Vout1 becomes the ground line voltage VGND, and the reference terminal of the resistor R1 and the capacitor C1 becomes the ground line voltage VGND to perform bootstrap.
  • the control voltage Vout1 is at In the low state, the first inverting switching element SW1 and the second inverting switching element SW3 are turned on when the control voltage Vout1 is low level, and the first in-phase switching element SW2 and the second in-phase switching element SW4 are low in the control voltage Vout1.
  • the first inverting switching element SW1 and the second inverting switching element SW3 are turned on when the control voltage Vout1 is low level, and the first in-phase switching element SW2 and the second in-phase switching element SW4 are low in the control voltage Vout1.
  • the threshold voltage VR1 is established by the first current source I1, and the capacitor voltage VC1 is bootstrapped to be changed to VR1-VDD and charged by the third current source I3. And rise.
  • the voltage range of charge and discharge is increased due to the application of the bootstrap technique, so that the same oscillation period can be realized with a smaller capacitance resistance. And after the capacitor is charged, it also uses the existing charge to discharge, which improves the current utilization. At the same time, if the comparator offset voltage makes the charging time prolonged, the discharge time will be shortened accordingly, so that the influence of the comparator offset voltage on the frequency stability is reduced.
  • FIG. 2 is a circuit schematic diagram of another embodiment of the relaxation oscillator of the present invention.
  • the relaxation oscillator circuit includes a bias circuit including a reference current source IR, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, and a fifth PMOS transistor MP5, wherein the reference current source IR and the power supply line VDD is electrically connected, while the reference current source IR is electrically connected to the drain and the gate of the fifth NMOS transistor MN5, the gate of the fifth NMOS transistor MN5 is electrically connected to the gate of the sixth NMOS transistor MN6, and the fifth PMOS transistor MP5 is The drain and the gate are electrically connected to the drain of the sixth NMOS transistor MN6.
  • the bias circuit forms a mirror current source from the test current source IR, the fifth NMOS transistor MN5, the sixth NMOS transistor MN6, and the fifth PMOS transistor MP5, and provides a bias current for the oscillation circuit.
  • the gates of the fifth PMOS transistor MP5 are electrically connected to the gates of the first PMOS transistor MP1 and the second PMOS transistor MP2, respectively, and the sources of the first PMOS transistor MP1 and the source of the second PMOS transistor MP2 are respectively electrically connected to the power supply line VDD.
  • the connection is such that the bias circuit and the first PMOS transistor MP1 form a current source for supplying current to the resistor R2 during charging, and the bias circuit and the second PMOS transistor MP2 constitute a current source for supplying current to the capacitor C2 during charging.
  • the gates of the fifth NMOS transistor MN5 are electrically connected to the gates of the first NMOS transistor MN1 and the second NMOS transistor MN2, respectively.
  • the source of the first NMOS transistor MN1 is electrically connected to the ground GND, so that the bias circuit and the first NMOS transistor MN1 form a current source for supplying current to the resistor R2 during the discharging process, and the source and the ground GND of the second NMOS transistor MN2. Electrically connected, and the bias circuit and the second NMOS transistor MN2 constitute a current source for supplying current to the capacitor C2 during discharge.
  • the comparator circuit of the oscillating circuit in this embodiment comprises a current mode comparator circuit and a inverter circuit, the current mode comparator circuit transmitting a voltage signal to the inverter circuit, wherein the current mode comparator circuit comprises a first current mode comparison circuit And a second current mode comparison circuit.
  • the first current mode comparison circuit and the second current mode comparison circuit are electrically connected to the first input end and the second input end of the comparator circuit.
  • the first input end of the comparator circuit inputs the voltage of the reference end of the resistor R2.
  • the first current mode comparison circuit includes a current mode comparator composed of a third NMOS transistor MN3 and a fourth NMOS transistor MN4. The gate and the drain of the third NMOS transistor MN3 are electrically connected to the gate of the fourth NMOS transistor MN4.
  • the drain of the three NMOS transistor MN3 is electrically connected to the drain of the first PMOS transistor MP1, the drain of the fourth NMOS transistor MN4 is electrically connected to the drain of the second PMOS transistor MP2, and the source of the third NMOS transistor MN3 passes through the switching component.
  • SW5 is electrically connected to the resistor R2, and the source of the fourth NMOS transistor MN4 is electrically connected to the capacitor C2 through the switching element SW7.
  • the second current mode comparison circuit includes a current mode comparator composed of a third PMOS transistor MP3 and a fourth PMOS transistor MP4. The gate and the drain of the third PMOS transistor MP3 are electrically connected to the gate of the fourth PMOS transistor MP4.
  • the drain of the third PMOS transistor MP3 is electrically connected to the drain of the first NMOS transistor MN1, the drain of the fourth PMOS transistor MP4 is electrically connected to the drain of the second NMOS transistor MN2, and the source of the third PMOS transistor MP3 passes through the switching component.
  • SW6 is electrically connected to the resistor R2, and the source of the fourth PMOS transistor MP4 is electrically connected to the capacitor C2 through the switching element SW8.
  • the inverter circuit includes an inverter Inv1 and an inverter Inv2.
  • the inverter Inv1 and the inverter Inv2 are connected in series, and the input end of the inverter Inv1 is electrically connected to the drain of the fourth NMOS transistor MN4 through the switching element SW9.
  • the input end of the inverter Inv1 is electrically connected to the drain of the fourth PMOS transistor MP4 through the switching element SW10, and the voltage VR2 of the resistor R2 and the voltage VC2 of the capacitor C2 are obtained by the first current mode comparator or the second current mode comparator.
  • the voltage VP is input to the inverter Inv1 and quantized by the inverter Inv1, and then shaped by the waveform of the inverter Inv2 to obtain the voltage Vout2.
  • the inverter circuit is used in the comparator circuit because the bootstrap technique is used, even if the inverter flip threshold voltage is unstable, it will only have a certain influence on the duty cycle, and will not cause too much oscillation period. The effect of avoiding the use of a more powerful comparator to eliminate the offset voltage.
  • the simplest digital logic inverters are used to implement comparator and digital control logic generation, reducing design complexity while reducing power consumption. At the same time, inverter-implemented comparators are automatically eliminated during operation. The effect of offset voltage and temperature changes on its threshold voltage reduces the limitations on frequency stability.
  • the switching element SW5, the switching element SW6, the switching element SW7, the switching element SW8, the switching element SW9, and the switching element SW10 are respectively supplied with a control signal from the output terminal of the inverter Inv2, the switching element SW5, the switching element SW6, and the switching element SW7
  • the switching element SW8, the switching element SW9, and the switching element SW10 can control the conduction state of the switch according to the output terminal voltage Vout2 of the inverter Inv2.
  • the switching element SW5, the switching element SW7, and the switching element SW9 are inverting switching elements, and the switching element SW5, the switching element SW7, and the switching element SW9 are turned off when the voltage Vout2 is at a high level, and turned on at a low level; the switching element SW6, the switch The element SW8 and the switching element SW10 are in-phase switching elements, and the switching element SW6, the switching element SW8, and the switching element SW10 are turned on when the voltage Vout2 is at a high level, and are turned off at a low level.
  • the oscillator is switched between charging and discharging states at a fixed cycle.
  • the branch between the resistor R2 and the capacitor C2 is electrically connected to the output terminal voltage Vout2 of the inverter Inv2, and the output voltage Vout2 is fed back to the branch between the threshold resistor and the capacitor, thereby improving the current utilization.
  • FIG. 3 is a voltage waveform diagram of the capacitor C2 reference terminal voltage VC2.
  • the current supplied by the current source is equal to I.
  • the capacitor C2 is discharged.
  • the relaxation oscillator of the present invention has a simple structure, a small number of modules, low power consumption, and high current utilization, thereby achieving a problem of shortening the development cycle, reducing the layout area of the board, and achieving ultra-low power consumption.
  • the first-stage comparison circuit of the comparator circuit is composed of a common-gate MOS transistor having a voltage amplification effect, at the same time, the output voltage Vout2 is fed back to a branch between the threshold resistance R2 and the capacitor C2, thereby improving current utilization. rate.
  • FIG. 4 there is shown an electrical schematic diagram of a relaxation oscillator circuit of a third embodiment of the relaxation oscillator of the present invention.
  • the relaxation oscillator circuit includes a bias circuit including a reference current source IR1, an NMOS transistor MN51, an NMOS transistor MN61, and a PMOS transistor MP51, wherein the reference current source IR1 is electrically connected to the power supply line VDD, and is also referred to
  • the current source IR1 is electrically connected to the drain and the gate of the NMOS transistor MN51
  • the gate of the NMOS transistor MN51 is electrically connected to the gate of the NMOS transistor MN61
  • the drain and the gate of the PMOS transistor MP51 are electrically connected to the drain of the NMOS transistor MN61.
  • the bias circuit forms a mirror current source from the test current source IR1, the NMOS transistor MN51, the NMOS transistor MN61, and the PMOS transistor MP51, and provides a bias current for the oscillation circuit.
  • the gates of the PMOS transistors MP51 are electrically connected to the gates of the PMOS transistor MP11 and the PMOS transistor MP21, respectively.
  • the source of the PMOS transistor MP11 and the source of the PMOS transistor MP21 are electrically connected to the power supply line VDD, respectively, so that the bias circuit and the PMOS transistor MP11 are provided.
  • the current source for supplying current to the resistor R3 during the charging process is formed, and the bias circuit and the PMOS transistor MP21 constitute a current source for supplying current to the capacitor C3 during charging.
  • the gates of the NMOS transistors MN51 are electrically connected to the gates of the NMOS transistor MN11 and the NMOS transistor MN21, respectively.
  • the source of the NMOS transistor MN11 is electrically connected to the ground GND, so that the bias circuit and the NMOS transistor MN11 form a current source for supplying current to the resistor R3 during discharge.
  • the source of the NMOS transistor MN21 is electrically connected to the ground GND, and the bias circuit and the NMOS transistor MN21 constitute a current source for supplying current to the capacitor C3 during discharge.
  • the comparator circuit of the oscillating circuit in this embodiment includes a current mode comparator circuit and a voltage comparison circuit, wherein the current mode comparator circuit includes a first current mode comparison circuit and a second current mode comparison circuit.
  • the first current mode comparison circuit is used for comparing the voltage VR3 of the reference end of the resistor R3 with the voltage VC3 of the reference end of the capacitor C3 during the charging process
  • the second current mode comparison circuit is used for comparing the voltage VR3 of the reference end of the resistor R3 with the voltage of the reference end of the capacitor C3 during the discharging process VC3.
  • the first current mode comparison circuit includes a current mode comparator composed of an NMOS transistor MN31 and an NMOS transistor MN41.
  • the gate and the drain of the NMOS transistor MN31 are electrically connected to the gate of the NMOS transistor MN41.
  • the drain of the NMOS transistor MN31 is electrically connected to the drain of the PMOS transistor MP11
  • the drain of the NMOS transistor MN41 is electrically connected to the drain of the PMOS transistor MP21
  • the source of the NMOS transistor MN31 is electrically connected to the resistor R3 through the switching element SW13.
  • the source of the MN 41 is electrically connected to the capacitor C3 through the switching element SW15.
  • the second current mode comparison circuit includes a current mode comparator composed of a PMOS transistor MP31 and a PMOS transistor MP41.
  • the gate and the drain of the PMOS transistor MP31 are electrically connected to the gate of the PMOS transistor MP41, and the drain and NMOS transistor of the PMOS transistor MP31
  • the drain of the MN11 is electrically connected
  • the drain of the PMOS transistor MP41 is electrically connected to the drain of the NMOS transistor MN21
  • the source of the PMOS transistor MP31 is electrically connected to the resistor R3 through the switching element SW14
  • the source of the PMOS transistor MP41 is passed through the switching element SW16 and Capacitor C3 is electrically connected.
  • the inverting input terminal of the voltage comparison circuit U2 is electrically connected to the drain of the NMOS transistor MN31 via the switching element SW11, and the inverting input terminal of the voltage comparison circuit U2 is electrically connected to the drain of the PMOS transistor MP31 via the switching element SW12.
  • the non-inverting input terminal of the voltage comparison circuit U2 is electrically connected to the drain of the NMOS transistor MN41 via the switching element SW17, and the non-inverting input terminal of the voltage comparison circuit U2 is electrically connected to the drain of the PMOS transistor MP41 via the switching element SW18.
  • the output end of the voltage comparison circuit U2 provides a control signal to the switching element SW11, the switching element SW12, the switching element SW13, the switching element SW14, the switching element SW15, the switching element SW16, the switching element SW17, and the switching element SW18, respectively, wherein the switching element SW11, The switching element SW13, the switching element SW15, and the switching element SW17 are inverting switching elements, and the switching element SW12, the switching element SW14, the switching element SW16, and the switching element SW18 are in-phase switching elements.
  • the first current mode comparison circuit or the second current mode comparison circuit inputs a first voltage signal to the inverting input end of the voltage comparison circuit U2, and the first current mode comparison circuit or the second current mode comparison circuit is in the same direction as the voltage comparison circuit U2.
  • the input terminal inputs a second voltage signal.
  • the voltage VR3 of the resistor R3 and the voltage VC3 of the capacitor C3 pass through the first current mode comparator or the second current mode comparator, and the voltage VN is outputted at the drain of the NMOS transistor MN31 or the drain of the PMOS transistor MP31, in the NMOS transistor MN41.
  • the drain of the drain or PMOS transistor MP41 outputs a voltage VP1.
  • the voltage VN is input to the inverting input terminal of the voltage comparison circuit U2, the voltage VP1 is input to the non-inverting input terminal of the voltage comparison circuit U2, and the output voltage Vout3 is obtained at the output terminal of the voltage comparison circuit U2.
  • the switching element SW17, the switching element SW18, the switching element SW11, and the switching element SW12 can control the conduction state of the switch according to the output voltage Vout3 at the output end of the voltage comparison circuit U2.
  • the switching element SW17 and the switching element SW11 are turned off when the voltage Vout3 is at a high level, and are turned on at a low level; the switching element SW18 and the switching element SW12 are turned off when the voltage Vout3 is at a low level, and turned on at a high level.
  • a clock signal of a stable frequency can be provided for a clock use circuit in the monolithic integrated chip, and the clock use circuit is a circuit that requires a clock signal to be triggered, such as a digital circuit for timing control, etc.
  • the oscillator has a simple structure, few modules, low power consumption, and high current utilization, so that the monolithic integrated chip can achieve high frequency stability and low power consumption.

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  • Manipulation Of Pulses (AREA)
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Abstract

一种张弛振荡器及单片集成芯片，该振荡器包括张弛振荡器电路，张弛振荡器电路包括阈值电压产生电路（1）、电容充放电电路（2）以及比较器电路（3），阈值电压产生电路（1）向比较器电路（3）的反相输入端输入阈值电压信号，电容充放电电路（2）向比较器电路（3）的同相输入端输入电容电压信号。阈值电压产生电路（1）包括第一电流源（I1）、第二电流源（I2）以及阈值电阻（R1），第一电流源（I1）通过第一反相开关元件（SW1）向阈值电阻（R1）施加电流，第二电流源（I2）通过第一同相开关元件（SW2）向阈值电阻（R1）抽取电流；电容充放电电路（2）包括第三电流源（I3）、第四电流源（I4）以及电容（C1），第三电流源（I3）通过第二反相开关元件（SW3）向电容（C1）施加电流，第四电流源（I4）通过第二同相开关元件（SW4）向电容（C1）抽取电流。该单片集成芯片应用该张弛振荡器。

Description

张弛振荡器及单片集成芯片
本发明涉及振荡器领域，具体的地，涉及一种基于自举技术的张弛振荡器，还涉及一种应用该张弛振荡器的单片集成芯片。本发明基于申请日为2016年07月20日、申请公布号为CN106209027A、申请公布日为2016年12月07日的中国发明专利申请，该申请的内容作为与本发明密切相关的参考文献引入本文。
所有需要时钟信号的单片集成电路设备都需要时钟源提供时钟信号，主流的时钟源有片外晶体振荡器、片上谐波振荡器、片上环形振荡器和片上张弛振荡器，晶体振荡器因为其良好的频率精确度和稳定性而被广泛应用。随着物联网设备、可穿戴设备和医疗植入式设备的发展，市场对电子设备的可集成性的需求越来越高、功耗控制的要求越来越苛刻、成本降低的渴望越来越强，因此片上可集成振荡器的性能需要被大幅提升以替代晶体振荡器同时满足不断提高的市场需求。张弛振荡器因为功耗较低、频率易控、结构简单而被广泛的应用和研究。
公开号为CN104124921A的中国发明专利申请公开了名为“基于电流模比较器的低压低功耗CMOS张弛振荡器及方法”的发明创造，该张弛振荡器使用两个电容避免了电容放电的延迟时间对频率稳定性的影响，但是电容电路版图的面积增加了一倍，使得成本增加。同时，SR锁存器输入端的阈值电压存在失调且还会受到温度的影响，一旦失调电压或者温度变化导致阈值电压变化，使频率精度和稳定性都会变差。此外，在振荡时每半个周期都会对一个电容充电一个电容放电，然后交替进行。在器对某一电容放电时，充电电流源仍然提供电流。所以在任何时刻振荡主电路在电容上消耗的电流都是两倍参考电流，使得电流利用率低、功耗较大。
此外，公开号为CN103338026A的中国发明专利申请公开了名为“张弛振荡器”的发明创造，该振荡器为了提升对温度的频率稳定性，采用了温度系数互补的P型多晶硅电阻和N型多晶硅电阻，其中N型多晶硅电阻的单位阻值较低，增大了电路版图中电阻所占用的面积，导致成本增加。为了消除比较器和电流模比较器的失调电压，该振荡器设计了较为复杂的比较器结构和开关切换单元，同时为了配合控制切换单元，又设计了较为复杂的时钟产生器，增加了电路的复杂度，延长了开发周期。同时，由于电压信号经过比较器和时钟产生器时，回路延迟较长，导致在周期内加入了较长的非理想延迟，非理想延迟时间易受到温度和电压的影响，从而导致频率稳定性受到限制。此外，比较器需要借助运算放大器为比较级提供电压，且为了得到良好的性能，比较级需要消耗静态电流，因而导致振荡电路的功耗较高。另外，振荡器在振荡时，每半个周期会对电容充电一次，紧接着立刻放电，再进行下半个周期的充电。所以在任何时刻振荡器主电路在电容上消耗的电流都是一倍参考电流，电流利用率较低。
本发明的主要目的是提供一种降低生产成本、缩短开发周期、提升频率稳定性以及实现超低功耗的张弛振荡器。
本发明的另一目的是提供一种频率稳定性高且功耗低的单片集成芯片。
为了实现上述主要目的，本发明提供的张弛振荡器包括张弛振荡器电路，张弛振荡器电路包括阈值电压产生电路、电容充放电电路以及比较器电路，阈值电压产生电路向比较器电路的反相输入端输入阈值电压信号，电容充放电电路向比较器电路的同相输入端输入电容电压信号；阈值电压产生电路包括第一电流源、第二电流源以及阈值电阻，第一电流源通过第一反相开关元件向阈值电阻施加电流，第二电流源通过第一同相开关元件向阈值电阻抽取电流；电容充放电电路包括第三电流源、第四电流源以及电容，第三电流源通过第二反相开关元件向电容施加电流，第四电流源通过第二同相开关元件向电容抽取电流。
一个方案中，第一反相开关元件、第一同相开关元件、第二反相开关元件与第二同相开关元件分别与比较器电路的输出端电连接。
由上述方案可见，利用比较器电路的输出电压对开关元件进行控制，可实现电路自动控制电容充放电的进程。
一个方案中，比较器电路的输出端与阈值电阻和电容之间的支路电连接。
由此可见，本发明的张弛振荡器通过将比较器的输出电压反馈到阈值电阻和电容之间的支路，使得电容充放电的电压范围增加，并且电容经过充电后，还利用已有电荷进行放电，提高了电流利用率。
进一步的方案中，比较器电路包括电流模比较电路和反相器电路，电流模比较电路向反相器电路发送电压信号。
由上述方案可见，比较器电路通过电流模比较器比较阈值电阻与电容的电压后，再通过反相器电路进行电压值的数字量化。使得输出电平的转换更加迅速。
进一步的方案中，第一电流源和第三电流源分别与电源线电连接，第二电流源和第四电流源分别接地。
由此可见，本发明的第一电流源和第三电流源在电容充电时分别给阈值电阻和电容提供电流源，第二电流源和第四电流源在电容放电时分别给阈值电阻和电容提供电流源。
优选的方案中，第一电流源、第二电流源、第三电流源和第四电流源分别包括一个MOS管，第一电流源的MOS管与第三电流源的MOS管共栅极连接，第二电流源的MOS管与第四电流源的MOS管共栅极连接。
由上述方案可见，由于MOS管在现今工艺中容易实施，在振荡电路中使用MOS管可降低制造成本。
具体的方案中，张弛振荡器电路还包括偏置电路，偏置电路分别与第一电流源、第二电流源、第三电流源及第四电流源电连接。
由上述方案可见，利用一个偏置电路分别与第一电流源、第二电流源、第三电流源及第四电流源电连接，可为振荡电路提供参考电流源。
为了实现上述的另一目的，本发明提供的单片集成芯片包括本发明提供的张弛振荡器，张弛振荡器向单片集成芯片中的时钟使用电路提供时钟信号。
本发明的张弛振荡器使用一个阈值电压产生电路产生了两个阈值电压，使用一个充放电电路对同一电容节点进行充放电。由这种结构形成的振荡器结构简单、模块少、电流利用率高，从而实现了缩短开发周期、减小电路板版图面积、实现超低功耗的问题。 本发明的单片集成芯片通过使用张弛振荡器，该振荡器结构简单、模块少、功耗低、电流利用率高，可使单片集成芯片实现高频率稳定性及低功耗。
图1是本发明张弛振荡器第一实施例的电原理图。
图2是本发明张弛振荡器第二实施例的电原理图。
图3是本发明张弛振荡器第二实施例中电容C2参考端电压VC2的电压输出波形示意图。
图4是本发明张弛振荡器第三实施例的电原理图。
以下结合附图及实施例对本发明作进一步说明。
 本发明的实施方式
本发明的张弛振荡器是基于自举技术的张弛振荡器，本发明可应用于振荡器的设计中，还可应用于单片集成芯片的设计中。
张弛振荡器第一实施例：
如图1所示，图1为本发明张弛振荡器的一个实施例的张弛振荡器电路电原理图。从图中可以看出，该振荡器的张弛振荡器电路包括阈值电压产生电路1、电容充放电电路2以及比较器电路3，阈值电压产生电路1向比较器电路3的反相输入端输入阈值电压信号，电容充放电电路2向比较器电路3的同相输入端输入电容电压信号。阈值电压产生电路1包括第一电流源I1、第二电流源I2以及阈值电阻R1，第一电流源I1通过第一反相开关元件SW1向阈值电阻R1施加电流（即，电流从第一电流源I1经过第一反相开关元件SW1流向阈值电阻R1），第二电流源I2通过第一同相开关元件SW2向阈值电阻R1抽取电流（即，电流从阈值电阻R1经过第一同相开关元件SW2流向第二电流源I2）。电容充放电电路2包括第三电流源I3、第四电流源I4以及电容C1，第三电流源I3通过第二反相开关元件SW3向电容C1施加电流（即，电流从第三电流源I3经过第二反相开关元件SW3流向电容C1），第四电流源I4通过第二同相开关元件SW4向电容C1抽取电流（即，电流从电容C1经过第二同相开关元件SW4流向第四电流源I4）。其中，第一电流源I1和第三电流源I3分别与电源线VDD电连接，第二电流源I2和第四电流源I4分别与地线GND电连接。第一反相开关元件SW1、第一同相开关元件SW2、第二反相开关元件SW3和第二同相开关元件SW4分别与比较器电路3的输出端电连接，并接收输出端电压反馈信号。此外，比较器电路3的输出端与阈值电阻R1和电容C1之间的支路电连接。
阈值电压产生电路1设置有第一电流源I1和第二电流源I2、使能电平相反的第一反相开关元件SW1和第一同相开关元件SW2以及阈值电阻R1。第一反相开关元件SW1导通时第一同相开关元件SW2截止，第一电流源I1可以和阈值电阻R1建立一个为I1×R1的压差；反之，第二电流源I2可以和阈值电阻R1建立一个为I2×R1的压差。
电容充放电电路2设置有第三电流源I3和第四电流源I4、使能电平相反的第二反相开关元件SW3和第二同相开关元件SW4以及电容C1。第二反相开关元件SW3导通时第二同相开关元件SW4截止，第三电流源I3可以为电容C1充电；反之，第四电流源I4可以为电容C1放电。
比较器电路3对阈值电阻R1产生的阈值电压VR1和电容C1充放电节点的电压VC1进行比较，根据比较结果输出为电源线VDD端电压或为地线GND端电压的控制电压Vout1，控制电压Vout1用来控制阈值电阻R1和电容C1的参考端电压和开关的导通状态。
为了进一步的描述本发明张弛振荡器电路的工作情况，张弛振荡器电路的工作原理如下：
假设初始电容C1未充电，且Vout1为地线GND电压VGND。首先，使第一反相开关元件SW1、第二反相开关元件SW3导通，阈值电压VR1由第一电流源I1建立，电容C1由第三电流源I3充电，电容电压VC1上升。当电容电压VC1超过阈值电压VR1时，控制电压Vout1变为电源电压VDD，将电阻R1和电容C1的参考端变为电源电压VDD实现自举，此时，控制电压Vout1处于高电平状态，第一反相开关元件SW1、第二反相开关元件SW3在控制电压Vout1高电平时截止，第一同相开关元件SW2、第二同相开关元件SW4在控制电压Vout1高电平时导通。此时阈值电压VR1由第二电流源I2建立，电容电压VC1经自举后变为VR1+VDD并由第四电流源I4放电，电容电压VC1下降。当电容电压VC1低于阈值电压VR1时，比较器输出控制电压Vout1变为地线电压VGND，将电阻R1和电容C1的参考端变为地线电压VGND实现自举，此时，控制电压Vout1处于低电平状态，第一反相开关元件SW1、第二反相开关元件SW3在控制电压Vout1低电平时导通，第一同相开关元件SW2、第二同相开关元件SW4在控制电压Vout1低电平时截止。第一反相开关元件SW1、第二反相开关元件SW3导通后，阈值电压VR1由第一电流源I1建立，电容电压VC1经自举后变化至VR1-VDD并由第三电流源I3充电而上升。
由上述的描述可知，由于自举技术的应用，使得充放电的电压范围增加，从而相同振荡周期可以用更小的电容电阻实现。并且电容经过充电后，还利用已有电荷进行放电，提高了电流利用率。同时如果比较器失调电压使得充电时间延长，则会相应导致放电时间缩短，从而使比较器失调电压对频率稳定性的影响降低。
张弛振荡器第二实施例：
如图2所示，图2为本发明张弛振荡器另一实施例的电路原理图。该实施例中，张弛振荡器电路包括偏置电路，偏置电路包括参考电流源IR、第五NMOS管MN5、第六NMOS管MN6和第五PMOS管MP5，其中，参考电流源IR与电源线VDD电连接，同时参考电流源IR与第五NMOS管MN5的漏极和栅极电连接，第五NMOS管MN5的栅极与第六NMOS管MN6的栅极电连接，第五PMOS管MP5的漏极和栅极与第六NMOS管MN6的漏极电连接。偏置电路由考电流源IR、第五NMOS管MN5、第六NMOS管MN6和第五PMOS管MP5构成镜像电流源，为振荡电路提供偏置电流。
第五PMOS管MP5的栅极分别与第一PMOS管MP1和第二PMOS管MP2的栅极电连接，第一PMOS管MP1的源极、第二PMOS管MP2的源极分别与电源线VDD电连接，使偏置电路与第一PMOS管MP1组成充电过程中为电阻R2提供电流的电流源，并使偏置电路与第二PMOS管MP2组成充电过程中为电容C2提供电流的电流源。此外，第五NMOS管MN5的栅极分别与第一NMOS管MN1和第二NMOS管MN2的栅极电连接。第一NMOS管MN1的源极与地线GND电连接，使偏置电路与第一NMOS管MN1组成放电过程中为电阻R2提供电流的电流源，第二NMOS管MN2的源极与地线GND电连接，并使偏置电路与第二NMOS管MN2组成放电过程中为电容C2提供电流的电流源。
该实施例中振荡电路的比较器电路包括电流模比较器电路和反相器电路，电流模比较器电路向反相器电路发送电压信号，其中，电流模比较器电路包括第一电流模比较电路、第二电流模比较电路。第一电流模比较电路与第二电流模比较电路均与比较器电路的第一输入端及第二输入端电连接，本实施例中，比较器电路的第一输入端输入电阻R2参考端的电压VR2，第二输入端输入电容C2参考端的电压VC2，第一电流模比较电路用于充电过程中比较电阻R2参考端的电压VR2与电容C2参考端的电压VC2，第二电流模比较电路用于放电过程中比较电阻R2参考端的电压VR2与电容C2参考端的电压VC2。第一电流模比较电路包括由第三NMOS管MN3和第四NMOS管MN4组成的电流模比较器，第三NMOS管MN3的栅极和漏极与第四NMOS管MN4的栅极电连接，第三NMOS管MN3的漏极与第一PMOS管MP1的漏极电连接，第四NMOS管MN4的漏极与第二PMOS管MP2的漏极电连接，第三NMOS管MN3的源极通过开关元件SW5与电阻R2电连接，第四NMOS管MN4的源极通过开关元件SW7与电容C2电连接。第二电流模比较电路包括由第三PMOS管MP3和第四PMOS管MP4组成的电流模比较器，第三PMOS管MP3的栅极和漏极与第四PMOS管MP4的栅极电连接，第三PMOS管MP3的漏极与第一NMOS管MN1的漏极电连接，第四PMOS管MP4的漏极与第二NMOS管MN2的漏极电连接，第三PMOS管MP3的源极通过开关元件SW6与电阻R2电连接，第四PMOS管MP4的源极通过开关元件SW8与电容C2电连接。
反相器电路包括反相器Inv1和反相器Inv2，反相器Inv1和反相器Inv2串联连接，反相器Inv1的输入端通过开关元件SW9与第四NMOS管MN4的漏极电连接，反相器Inv1的输入端通过开关元件SW10与第四PMOS管MP4的漏极电连接，电阻R2的电压VR2和电容C2的电压VC2经过第一电流模比较器或第二电流模比较器后得到电压VP，电压VP输入到反相器Inv1中并被反相器Inv1量化，再经过反相器Inv2的波形整形，得到电压Vout2。在比较器电路中使用反相器电路，是因为采用了自举技术后，即使反相器翻转阈值电压不稳定，也只会对占空比有一定影响，而不会对振荡周期造成太大的影响，从而避免了使用功耗较大的比较器来消除失调电压。此外，使用最简单的数字逻辑反相器来实现比较器和数字控制逻辑产生，降低了设计复杂度的同时也降低了功耗，同时，反相器实现的比较器在工作过程中自动消除了失调电压和温度变化对其阈值电压的影响，降低频率稳定性受到的限制。
此外，开关元件SW5、开关元件SW6、开关元件SW7、开关元件SW8、开关元件SW9和开关元件SW10分别由反相器Inv2的输出端给入控制信号，开关元件SW5、开关元件SW6、开关元件SW7、开关元件SW8、开关元件SW9和开关元件SW10可根据反相器Inv2的输出端电压Vout2进行控制开关的导通状态。其中，开关元件SW5、开关元件SW7和开关元件SW9为反相开关元件，开关元件SW5、开关元件SW7、开关元件SW9在电压Vout2为高电平时截止，低电平时导通；开关元件SW6、开关元件SW8和开关元件SW10为同相开关元件，开关元件SW6、开关元件SW8、开关元件SW10在电压Vout2为高电平时导通，低平时截止。使得振荡器以固定周期在充电和放电状态间转换。同时，电阻R2与电容C2之间的支路与反相器Inv2的输出端电压Vout2电连接，将输出电压Vout2反馈到阈值电阻和电容之间的支路，提高了电流利用率。
为了体现本发明张弛振荡器的优点，参见图3，图3为电容C2参考端电压VC2的电压波形图。假设电流源提供的电流都等于I。在电容C2充电时，电阻R2参考端的电压为VR2=I×R2，电容C2充电使VC2达到VR2之后，由于自举的作用，电容C2参考端的电压立刻抬升VDD，使得VC2=VDD+I×R2，紧接着开始对电容C2放电。在电容C2放电时，电阻R2参考端的电压为VR2=VDD-I×R2，电容C2放电到VC2=VDD-I×R2之后，由于自举的作用，电容C2参考端的电压立刻降低VDD，使得VC2=-I×R2，紧接着又开始对电容C2充电，循环上述过程。由此可知，电容C2充电时VC2变化了2×I×R2，放电时VC2也变化了2×I×R2，因此，VC2的变化合计为ΔV=4×I×R2。根据公式ΔV×C2=I×T，可得出4×I×R2×C2=I×T，其中，T为振荡周期，所以振荡周期T等于4×R2×C2。当然，该计算方法也适用于第一实施例中。
由上述可知，本发明张弛振荡器的结构简单、模块少、功耗低、电流利用率高，从而实现了缩短开发周期、减小电路板版图面积、实现超低功耗的问题。此外，由于比较器电路的第一级比较电路由共栅极的MOS管组成具有电压放大的效果，同时，将输出电压Vout2反馈到阈值电阻R2和电容C2之间的支路，提高了电流利用率。
张驰振荡器实施例三：
参见图4，图4是本发明张弛振荡器第三实施例的张弛振荡器电路电原理图。
该实施例中，张弛振荡器电路包括偏置电路，偏置电路包括参考电流源IR1、NMOS管MN51、NMOS管MN61和PMOS管MP51，其中，参考电流源IR1与电源线VDD电连接，同时参考电流源IR1与NMOS管MN51的漏极和栅极电连接，NMOS管MN51的栅极与NMOS管MN61的栅极电连接，PMOS管MP51的漏极和栅极与NMOS管MN61的漏极电连接。偏置电路由考电流源IR1、NMOS管MN51、NMOS管MN61和PMOS管MP51构成镜像电流源，为振荡电路提供偏置电流。
PMOS管MP51的栅极分别与PMOS管MP11和PMOS管MP21的栅极电连接，PMOS管MP11的源极、PMOS管MP21的源极分别与电源线VDD电连接，使偏置电路与PMOS管MP11组成充电过程中为电阻R3提供电流的电流源，并使偏置电路与PMOS管MP21组成充电过程中为电容C3提供电流的电流源。此外，NMOS管MN51的栅极分别与NMOS管MN11和NMOS管MN21的栅极电连接。NMOS管MN11的源极与地线GND电连接，使偏置电路与NMOS管MN11组成放电过程中为电阻R3提供电流的电流源， NMOS管MN21的源极与地线GND电连接，并使偏置电路与NMOS管MN21组成放电过程中为电容C3提供电流的电流源。
该实施例中振荡电路的比较器电路包括电流模比较器电路和电压比较电路，其中，电流模比较器电路包括第一电流模比较电路、第二电流模比较电路。第一电流模比较电路用于充电过程中比较电阻R3参考端的电压VR3与电容C3参考端的电压VC3，第二电流模比较电路用于放电过程中比较电阻R3参考端的电压VR3与电容C3参考端的电压VC3。第一电流模比较电路包括由NMOS管MN31和NMOS管MN41组成的电流模比较器， NMOS管MN31的栅极和漏极与NMOS管MN41的栅极电连接， NMOS管MN31的漏极与PMOS管MP11的漏极电连接，NMOS管MN41的漏极与PMOS管MP21的漏极电连接，NMOS管MN31的源极通过开关元件SW13与电阻R3电连接，NMOS管MN41的源极通过开关元件SW15与电容C3电连接。第二电流模比较电路包括由PMOS管MP31和PMOS管MP41组成的电流模比较器，PMOS管MP31的栅极和漏极与PMOS管MP41的栅极电连接，PMOS管MP31的漏极与NMOS管MN11的漏极电连接，PMOS管MP41的漏极与NMOS管MN21的漏极电连接，PMOS管MP31的源极通过开关元件SW14与电阻R3电连接，PMOS管MP41的源极通过开关元件SW16与电容C3电连接。
电压比较电路U2的反相输入端通过开关元件SW11与NMOS管MN31的漏极电连接，电压比较电路U2的反相输入端通过开关元件SW12与PMOS管MP31的漏极电连接。电压比较电路U2的同向输入端通过开关元件SW17与NMOS管MN41的漏极电连接，电压比较电路U2的同向输入端通过开关元件SW18与PMOS管MP41的漏极电连接。电压比较电路U2的输出端分别给开关元件SW11、开关元件SW12、开关元件SW13、开关元件SW14、开关元件SW15、开关元件SW16、开关元件SW17和开关元件SW18提供控制信号，其中，开关元件SW11、开关元件SW13、开关元件SW15和开关元件SW17为反相开关元件，开关元件SW12、开关元件SW14、开关元件SW16和开关元件SW18为同相开关元件。
第一电流模比较电路或第二电流模比较电路向电压比较电路U2的反相输入端输入第一电压信号，第一电流模比较电路或第二电流模比较电路向电压比较电路U2的同向输入端输入第二电压信号。电阻R3的电压VR3和电容C3的电压VC3经过第一电流模比较器或第二电流模比较器后，在NMOS管MN31的漏极或PMOS管MP31的漏极输出电压VN，在NMOS管MN41的漏极或PMOS管MP41的漏极输出电压VP1。电压VN输入电压比较电路U2的反相输入端，电压VP1输入电压比较电路U2的同向输入端，在电压比较电路U2的输出端得到输出电压Vout3。开关元件SW17、开关元件SW18、开关元件SW11和开关元件SW12可根据电压比较电路U2输出端的输出电压Vout3进行控制开关的导通状态。其中，开关元件SW17和开关元件SW11在电压Vout3为高电平时截止，低电平时导通；开关元件SW18和开关元件SW12在电压Vout3为低电平时截止，高电平时导通。
需要说明的是，以上仅为本发明的优选实施例，但发明的设计构思并不局限于此，凡利用此构思对本发明做出的非实质性修改，也均落入本发明的保护范围之内。
本发明的张弛振荡器应用于单片集成芯片时，可为单片集成芯片中的时钟使用电路提供稳定频率的时钟信号，时钟使用电路为需要时钟信号触发的电路，如时序控制的数字电路等，且该振荡器结构简单、模块少、功耗低、电流利用率高，可使单片集成芯片实现高频率稳定性及低功耗。

Claims (8)

  1. 张弛振荡器，包括张弛振荡器电路，其特征在于：
    所述张弛振荡器电路包括阈值电压产生电路、电容充放电电路以及比较器电路，所述阈值电压产生电路向所述比较器电路的反相输入端输入阈值电压信号，所述电容充放电电路向所述比较器电路的同相输入端输入电容电压信号；
    所述阈值电压产生电路包括第一电流源、第二电流源以及阈值电阻，所述第一电流源通过第一反相开关元件向所述阈值电阻施加电流，所述第二电流源通过第一同相开关元件向所述阈值电阻抽取电流；
    所述电容充放电电路包括第三电流源、第四电流源以及电容，所述第三电流源通过第二反相开关元件向所述电容施加电流，所述第四电流源通过第二同相开关元件向所述电容抽取电流。
  2. 根据权利要求1所述的张弛振荡器，其特征在于：
    所述第一同相开关元件、所述第一反相开关元件、所述第二同相开关元件与所述第二反相开关元件分别与所述比较器电路的输出端电连接。
  3. 根据权利要求2所述的张弛振荡器，其特征在于：
    所述比较器电路的输出端与所述阈值电阻和所述电容之间的支路电连接。
  4. 根据权利要求1或3所述的张弛振荡器，其特征在于：
    所述比较器电路包括电流模比较器电路和反相器电路，所述电流模比较器电路向所述反相器电路发送电压信号。
  5. 根据权利要求1或3所述的张弛振荡器，其特征在于：
    所述第一电流源和所述第三电流源分别与电源线电连接，所述第二电流源和所述第四电流源分别接地。
  6. 根据权利要求1或3所述的张弛振荡器，其特征在于：
    所述第一电流源、所述第二电流源、所述第三电流源和所述第四电流源分别设有一个MOS管，所述第一电流源的所述MOS管与所述第三电流源的所述MOS管共栅极连接，所述第二电流源的所述MOS管与所述第四电流源的所述MOS管共栅极连接。
  7. 根据权利要求1或3所述的张弛振荡器，其特征在于：
    所述张弛振荡器电路还包括偏置电路，所述偏置电路分别与所述第一电流源、所述第二电流源、所述第三电流源及所述第四电流源电连接。
  8. 一种单片集成芯片，包括权利要求1至7中任一项张弛振荡器，所述张弛振荡器，向所述单片集成芯片中的时钟使用电路提供时钟信号。
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CN111092609A (zh) * 2019-12-30 2020-05-01 西北工业大学 一种无参考电压的rc张弛振荡器
CN111092609B (zh) * 2019-12-30 2023-03-21 西北工业大学 一种无参考电压的rc张弛振荡器
CN110995160A (zh) * 2019-12-31 2020-04-10 广州裕芯电子科技有限公司 一种高性能的振荡器
CN110995160B (zh) * 2019-12-31 2023-04-07 广州裕芯电子科技有限公司 一种高性能的振荡器
CN111478669A (zh) * 2020-04-13 2020-07-31 上海芯跳科技有限公司 一种高精度rc振荡器用电路
CN114124040A (zh) * 2021-11-15 2022-03-01 华中科技大学 一种自适应阈值的低功耗张弛振荡电路
CN114124040B (zh) * 2021-11-15 2024-05-31 华中科技大学 一种自适应阈值的低功耗张弛振荡电路

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