WO2018006739A1 - 一种图形化栅结构的微波晶体管及其制备方法 - Google Patents

一种图形化栅结构的微波晶体管及其制备方法 Download PDF

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Publication number
WO2018006739A1
WO2018006739A1 PCT/CN2017/090511 CN2017090511W WO2018006739A1 WO 2018006739 A1 WO2018006739 A1 WO 2018006739A1 CN 2017090511 W CN2017090511 W CN 2017090511W WO 2018006739 A1 WO2018006739 A1 WO 2018006739A1
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Prior art keywords
gate
barrier layer
patterned
grooves
drain
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PCT/CN2017/090511
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English (en)
French (fr)
Inventor
刘胜厚
叶念慈
黄侯魁
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厦门市三安集成电路有限公司
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Publication of WO2018006739A1 publication Critical patent/WO2018006739A1/zh
Priority to US16/236,591 priority Critical patent/US11088270B2/en

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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
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    • H01L29/2003—Nitride compounds

Definitions

  • the present invention relates to semiconductor devices, and more particularly to a microwave transistor having a patterned gate structure and a method of fabricating the same.
  • a high electron mobility transistor includes a substrate, a buffer layer, a channel layer, a barrier layer, and a source, a drain, and a gate disposed on the barrier layer, and is configured by using a channel layer and A two-dimensional electron gas layer (2-2DEG) exists at the heterojunction interface between the barrier layers, and the electron concentration of the 2-DEG is controlled between the source and the drain by changing the gate pressure to control the working state.
  • HEMT is a new generation of transistors that are preferred for high frequency, high voltage, high temperature and high power applications due to their superior performance.
  • the improvement of the frequency performance of the microwave device mainly depends on reducing the gate length, and the current technology has realized a device having a gate length of 30-50 nm.
  • the thickness of the barrier layer is about 20 nm. Therefore, at this scale, there is a huge challenge due to the short channel effect of the device, which limits the output power of the device.
  • the first is to use the recess gate process, that is, to thin the barrier layer of the gate region as a whole, and shorten the distance from the gate to the two-dimensional electron gas channel, thereby making the gate The ability to control the two-dimensional electronic gas channel is enhanced.
  • the thickness of the barrier layer decreases, the density of the two-dimensional electron gas in the conductive channel also decreases, limiting the maximum output power of the device.
  • Another method is based on the structural design of the channel array, that is, the barrier layer of the portion under the gate is completely removed, and the gate pair is formed by covering the gate metal on the top and the sidewalls of the two sides to form a ring gate structure.
  • the three-dimensional control of the conductive channel enhances the modulation capability of the channel.
  • part of the conductive area under the gate is removed, the removed part of the area cannot participate in conduction, which reduces the conductivity of the device and affects the output power of the device.
  • Another method is the design of the epitaxial structure, that is, a layer of a back barrier layer different from the barrier layer component is grown under the channel, and the binding effect of the two-dimensional electron gas in the channel is enhanced from below the channel to suppress the device. Short channel effect.
  • this imposes very high requirements on the epitaxial process because different semiconductor crystal materials have different growth temperatures, and frequent switching of temperature affects The final quality of the epitaxial material. None of the above methods can solve the existing problems well.
  • the object of the present invention is to overcome the deficiencies of the prior art, and to provide a microwave transistor with a patterned gate structure and a method of fabricating the same.
  • a microwave transistor with a patterned gate structure including a substrate, a buffer layer, a channel layer and a barrier layer from bottom to top, and a barrier layer is disposed on the barrier layer a source, a drain and a gate, and a gate between the source and the drain;
  • the barrier layer has a patterned region between the source and the drain, and the plurality of patterned regions are disposed a groove partially recessed in a thickness direction of the surface of the barrier layer;
  • the gate is overlaid on the patterned region, and a gate length is greater than a length of the recess in a length direction of the gate Cover the grooves completely.
  • the grooves occupy 25% to 75% of the area of the patterned area covered by the gate.
  • the grooves are strip-shaped structures and are arranged in parallel at equal intervals.
  • the thickness of the gate at the bottom of the plurality of grooves is the same as the thickness of the surface of the barrier layer.
  • the sidewalls of the plurality of grooves are inclined inward by 0 to 60 degrees toward the bottom direction by the groove mouth, and the gate covers the sidewalls of the plurality of grooves.
  • the channel layer and the barrier layer are made of a semiconductor material capable of forming a heterojunction; the source, the drain and the gate are made of metal and the source and the drain and the barrier are The layer forms an ohmic contact and the gate forms a Schottky contact with the barrier layer.
  • a method for fabricating a microwave transistor of the above patterned gate structure comprises the following steps:
  • step (2) specifically includes the following sub-steps: [0017] a Ti/Al/Ni/Au multi-metal layer is separately deposited on the two regions of the surface of the barrier layer by electron beam evaporation, wherein the thickness of the Ti/Al/Ni/Au is 20/150/50/100nm;
  • Annealing at 800-950 ° C for 20-45 seconds forms an ohmic contact, forming the source and drain.
  • the grooves are formed by dry etching and/or wet etching.
  • the gate is a metal, and is deposited on the patterned region by magnetron sputtering, ion evaporation or arc ion evaporation and forms a barrier with the barrier layer. Special contact.
  • the present invention provides a patterned region between the source and the drain, and a plurality of recesses formed by recessing the surface of the barrier layer along the thickness direction are disposed in the patterned region, and the gate is patterned.
  • the length of the gate is greater than the length of the recess in the length direction of the gate to completely cover the recesses.
  • the arrangement of the recess enhances the gate control capability of the device, and the short channel effect is suppressed;
  • the original heterogeneous structure under the pole is preserved to avoid the decrease of the conductivity and the decrease of the two-dimensional electron gas density, so that the suppression of the short channel effect ensures the current output capability of the device and the frequency of the microwave device. Performance
  • the gate covers the bottom and the sidewall of the groove to form a ring-shaped gate structure, and the two-dimensional electronic gas channel is three-dimensionally controlled by the bottom and the sidewall, thereby further enhancing the modulation capability.
  • FIG. 1 is a schematic top plan view of an embodiment of the present invention.
  • FIG. 2 is a schematic top plan view of a barrier layer according to an embodiment of the invention.
  • FIG. 3 is a schematic cross-sectional view taken along line A-A of FIG. 1;
  • FIG. 4 is a schematic cross-sectional view taken along line A'-A' of FIG. 1.
  • FIG. 5 is a schematic structural view of a cross-sectional portion in the BB direction of FIG. 1.
  • the microwave transistor of the patterned gate structure of an embodiment includes a substrate 1, a buffer layer 2, a channel layer 3 and a barrier layer 4 from bottom to top, and the barrier layer 4 is provided with
  • the source 5, the drain 6 and the gate 7, the gate 7 is located between the source 5 and the drain 6.
  • the span of the gate in the source-to-drain direction is the gate length, and the span of the gate along the direction in which the source and the drain extend are the gate width, and the gate length direction and the gate width direction are generally considered to be perpendicular.
  • the barrier layer 4 has a patterned region L between the source 5 and the drain 6, and a plurality of recesses 41 formed by recessing the surface of the barrier layer 4 in the thickness direction are disposed in the patterned region L.
  • the gate electrode 7 is disposed on the patterned region L, and the gate length is greater than the length of the recesses 41 in the length direction of the gate to completely cover the recesses 41.
  • the distance between the gate 7 and the two-dimensional electron gas channel is shortened, which improves the control ability of the gate to the two-dimensional electron gas channel; outside the groove, the barrier layer under the gate does not change. The density of the two-dimensional electron gas and the conductivity of the barrier layer are maintained, thereby maintaining the output power of the device.
  • the grooves 41 are strip-shaped structures, the openings are rectangular, and are arranged in parallel along the width direction of the gate, and the total area of the grooves is covered by the gate 7.
  • the area of the graphical area is 25% to 50%.
  • the length of each of the grooves 41 is between 20 nm and 40 nm, and the width is the same as or similar to the pitch of the adjacent grooves, thereby forming an array arrangement, and the gate length is between 30 nm and 50 nm, and the edges on both sides are There is a certain distance between the two sides of the groove, so that complete coverage is achieved, and the groove 41 is completely within the regulation range of the gate 7.
  • the array of strip grooves may be arranged along the length of the gate, or arranged obliquely, or in a plurality of rows and other arrangements.
  • the arrangement of the strip-shaped groove arrays on the one hand, the overall distribution is relatively uniform, so that the current is relatively evenly distributed, avoiding excessive local current caused by non-uniform distribution, causing excessive local junction temperature of the device, which brings about device reliability problems; Easy to process.
  • the grooves may also be other regular or irregular shapes, and the arrangement may be arranged in an orderly manner or in an unordered manner, and is not limited thereto.
  • each groove 41 is inclined inward by 0° to 60° toward the bottom 412 by the groove mouth, and the gate covers the side wall 411 and the bottom 412 of the groove 41 in the vertical bottom direction. And the oblique sidewall direction of the same side achieves modulation of the two-dimensional electron gas channel, forming a ring-gate effect.
  • the slanted sidewalls increase the regulation capability of the device, which in turn increases the frequency performance of the device.
  • the thickness of the gate 7 at the bottom 412 of the groove is the same as the thickness of the surface of the barrier layer 4, and due to the arrangement of the inclined sidewalls, the bends are obtuse angles, the sharp angle effect is avoided, and the overall thickness tends to be uniform, and The surface topography corresponding to the patterned area is presented, and the performance is uniform and stable.
  • the thickness of the barrier layer is about 20 nm
  • the depth of the recess 41 is about 10 nm
  • the thickness of the gate is 500 nm, so that a good synergistic effect can be achieved.
  • the substrate and the buffer layer are conventional materials and structures, and for example, the substrate may be silicon, silicon carbide, sapphire or the like.
  • the buffer layer may be Al x G ai — ⁇ ⁇ , 0 ⁇ ⁇ ⁇ 1.
  • the channel layer 3 and the barrier layer 4 are formed of a semiconductor material capable of forming a heterojunction, such as GaN/AlGaN, GaAs/AlGaAs, or the like.
  • the source 5 and the drain 6 are metal and form an ohmic contact with the barrier layer 4, and the gate 7 is also a metal and forms a Schottky contact with the barrier layer 4.
  • a method of preparing the above-described patterned gate structure microwave transistor is to first form a buffer layer 2, a channel layer 3, and a barrier layer 4 on the substrate 1. After cleaning the test piece, the source 5 and the drain 6 are formed on the barrier layer 4, specifically, a Ti/Al/Ni/Au multi-metal layer is deposited by using an electron beam evaporation machine, and the thickness of each layer is 20/150. /50/100 nm, then placed in a rapid annealing machine, annealed at 850 ° C for 30 s to form an ohmic contact, thereby forming a source and a drain.
  • the source and drain electrodes may also be other metals, alloys or stacked structures.
  • the recess is etched on the barrier layer between the source and the drain, which can be achieved by dry etching, wet etching, or a combination of both.
  • the dry etching can be performed by RIE, ICP, etc., and the depth of the groove and the inclination of the side wall are controlled by controlling the power, pressure, atmosphere, and the like of the etching.
  • the wet etching can be carried out by using a solution of sodium hydroxide, potassium hydroxide or the like, and controlling the depth of the groove and the inclination of the side wall by controlling the concentration of the solution, etching the turns, and the like.
  • a gate is then deposited over the patterned region.
  • the gate can be metal and deposited on the patterned regions by magnetron sputtering, ion evaporation, or arc ion evaporation to form a Schottky contact.

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Manufacturing & Machinery (AREA)
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  • General Chemical & Material Sciences (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

一种图形化栅结构的微波晶体管，该晶体管在势垒层（4）于源极（5）和漏极（6）之间具有一图形化区域，图形化区域内设置有复数个由势垒层表面沿厚度方向部分下凹形成的凹槽（41），栅极（7）覆设于图形化区域上，且栅极长度大于该些凹槽于栅极长度方向上的长度以完全覆盖该些凹槽，一方面借由凹槽的设置增强器件的栅控能力，抑制短沟道效应；另一方面栅极下方原始的异质结构得到了保留，避免二维电子气密度下降引起导电能力降低，从而在实现抑制短沟道效应的同时保证了器件的电流输出能力。还公开了微波晶体管的制备方法。

Description

一种图形化栅结构的微波晶体管及其制备方法 技术领域
[0001] 本发明涉及半导体器件， 特别是涉及一种图形化栅结构的微波晶体管及其制备 方法。
背景技术
[0002] 高电子迁移率晶体管 (HEMT)包括衬底、 缓冲层、 沟道层、 势垒层及设置于势 垒层上的源极、 漏极和栅极等结构， 是利用沟道层和势垒层之间的异质结界面 存在的二维电子气层 (2-2DEG) , 在源极和漏极之间通过改变栅极加压控制 2-DEG 的电子浓度， 从而控制工作状态。 HEMT是新一代的晶体管， 由于其优异的性能 成为高频、 高压、 高温和大功率应用方面的首选。
技术问题
[0003] 目前， 基于普通的 HEMT结构， 微波器件的频率性能的提升主要依赖于减小栅 长， 现在的技术已经实现了栅长 30-50nm的器件。 而一般情况下势垒层的厚度在 20nm左右。 因此， 在这个尺度下， 面临着器件短沟道效应带来的巨大挑战， 这 会限制器件的输出功率。 为了增强器件的栅控能力、 抑制短沟道效应， 一是采 用凹槽栅工艺， 即将栅极区域的势垒层整体减薄， 缩短栅极到二维电子气沟道 的距离， 从而使栅极对二维电子气沟道的控制能力增强。 但是随着势垒层厚度 的减小， 导电沟道中二维电子气的密度也会随着降低， 限制器件的最大输出功 率。 另一个方法是基于沟道阵列的结构设计， 即将栅极下方部分区域的势垒层 完全去除， 并通过将栅金属覆盖在沟道的顶部和两边的侧壁形成环栅结构， 实 现栅极对导电沟道的三维控制， 从而增强了对沟道的调制能力。 但由于栅极下 方部分导电区域被去除， 去除的这部分区域不能参与导电， 降低了器件的导电 能力， 从而影响器件的输出功率。 还有一种方法是外延结构的设计， 即在沟道 下方生长一层不同于势垒层组份的背势垒层， 从沟道下方增强对沟道内二维电 子气的束缚作用， 抑制器件的短沟道效应。 但是这对外延工艺提出了非常高的 要求， 因为不同半导体晶体材料具有不同的生长温度， 温度的频繁切换会影响 外延材料最后的质量。 上述方法均无法较好的解决存在的问题。
问题的解决方案
技术解决方案
[0004] 本发明的目的在于克服现有技术之不足， 提供一种图形化栅结构的微波晶体管 及其制备方法。
[0005] 本发明解决其技术问题所采用的技术方案是： 一种图形化栅结构的微波晶体管 ， 由下至上包括衬底、 缓冲层、 沟道层及势垒层， 势垒层上设置有源极、 漏极 及栅极， 且栅极位于源极和漏极之间； 所述势垒层于源极和漏极之间具有一图 形化区域， 所述图形化区域内设置有复数个由势垒层表面沿厚度方向部分下凹 形成的凹槽； 所述栅极覆设于所述图形化区域上， 且栅极长度大于该些凹槽于 所述栅极长度方向上的长度以完全覆盖该些凹槽。
[0006] 优选的， 该些凹槽占所述栅极覆盖的图形化区域面积的 25%〜75%。
[0007] 优选的， 该些凹槽是条形结构且等距离间隔平行排列。
[0008] 优选的， 所述栅极于所述复数个凹槽底部的厚度与于所述势垒层表面的厚度相 同。
[0009] 优选的， 所述复数个凹槽的侧壁由凹槽幵口向底部方向向内倾斜 0〜60度， 所 述栅极覆盖所述复数个凹槽的侧壁。
[0010] 优选的， 所述沟道层和势垒层为可形成异质结的半导体材料制成； 所述源极、 漏极及栅极由金属制成且源极和漏极与势垒层形成欧姆接触， 栅极与势垒层形 成肖特基接触。
[0011] 一种上述图形化栅结构的微波晶体管的制备方法包括以下步骤：
[0012] (1)于一衬底上依次形成缓冲层、 沟道层及势垒层；
[0013] (2)于势垒层表面上形成源极和漏极；
[0014] (3)于源极和漏极之间定义一图形化区域， 蚀刻所述图形化区域的势垒层形成所 述复数个凹槽；
[0015] (4)于所述图形化区域上形成栅极， 且栅极长度大于该些凹槽于所述栅极长度方 向上的长度以完全覆盖所述复数个凹槽。
[0016] 优选的， 步骤 (2)具体包括以下子步骤： [0017] 通过电子束蒸镀的方法于所述势垒层表面的两个区域分别蒸镀上 Ti/Al/Ni/Au多 金属层， 其中所述 Ti/Al/Ni/Au的厚度分别是 20/150/50/100nm;
[0018] 于 800-950°C下退火 20-45秒形成欧姆接触， 形成所述源极和漏极。
[0019] 优选的， 步骤 (3)中， 是通过干法蚀刻和 /或湿式蚀刻的方式形成该些凹槽。
[0020] 优选的， 步骤 (4)中， 所述栅极是金属， 通过磁控溅镀、 离子蒸镀或电弧离子蒸 镀的方法沉积于所述图形化区域上并与势垒层形成肖特基接触。
发明的有益效果
有益效果
[0021] 1.本发明在源极和漏极之间设置一图形化区域， 图形化区域内设置复数个由势 垒层表面沿厚度方向部分下凹形成的凹槽， 栅极设置于图形化区域上且栅极长 度大于凹槽于栅极长度方向上的长度以完全覆盖该些凹槽， 一方面借由凹槽的 设置增强器件的栅控能力， 抑制短沟道效应； 另一方面栅极下方原始的异质结 构得到了保留， 避免导电能力的降低及二维电子气密度的下降， 从而在实现抑 制短沟道效应的同吋保证了器件的电流输出能力， 提升了微波器件的频率性能
[0022] 2.栅极覆盖于凹槽的底部及侧壁上， 形成环形栅结构， 由底部及侧壁对二维电 子气沟道实现三维调控， 进一步增强了调制能力。
[0023] 3.制程简单常规， 无特殊工艺要求， 不影响外延材料的最终质量， 可控性强， 适于实际生产应用。
对附图的简要说明
附图说明
[0024] 图 1为本发明一实施例之俯视结构示意图；
[0025] 图 2为本发明一实施例之势垒层俯视结构示意图；
[0026] 图 3为图 1中 A-A方向的截面示意图；
[0027] 图 4为图 1中 A'-A'方向的截面示意图
[0028] 图 5为图 1中 B-B方向的截面部分结构示意图。 本发明的实施方式
[0029] 以下结合附图及实施例对本发明作进一步详细说明。 本发明的各附图仅为示意 以更容易了解本发明， 其具体比例可依照设计需求进行调整。 文中所描述的图 形中相对元件的上下关系， 在本领域技术人员应能理解是指构件的相对位置而 言， 因此皆可以翻转而呈现相同的构件， 此皆应同属本说明书所揭露的范围。 此外， 图中所示的元件及结构的个数， 均仅为示例， 并不以此对数目进行限制 ， 实际可依照设计需求进行调整。
[0030] 参考图 1至图 5， 一实施例的图形化栅结构的微波晶体管由下至上包括衬底 1、 缓冲层 2、 沟道层 3及势垒层 4， 势垒层 4上设置有源极 5、 漏极 6及栅极 7， 栅极 7 位于源极 5和漏极 6之间。 以源极至漏极方向栅极的跨度为栅极长度， 以栅极沿 源极和漏极延伸方向的跨度为栅极宽度， 通常认为栅极长度方向和栅极宽度方 向垂直。 势垒层 4于源极 5和漏极 6之间具有一图形化区域 L， 图形化区域 L内设置 有复数个由势垒层 4表面沿厚度方向部分下凹形成的凹槽 41。 栅极 7覆设于图形 化区域 L上， 且栅极长度大于该些凹槽 41于栅极长度方向上的长度以完全覆盖该 些凹槽 41。 于凹槽 41内， 栅极 7与二维电子气沟道的距离缩短， 提高了栅极对二 维电子气沟道的控制能力； 于凹槽外， 栅极下方的势垒层不变， 二维电子气的 密度以及势垒层的导电能力得到了保持， 从而保持了器件的输出功率。
[0031] 在本实施例中， 该些凹槽 41是条形结构， 幵口为长方形， 且沿栅极宽度方向等 距离间隔平行排列， 该些凹槽幵口的总面积占栅极 7覆盖的图形化区域面积的 25 %〜50%。 举例来说， 各凹槽 41的长度在 20nm〜40nm之间， 宽度与相邻凹槽的 间距相同或相近， 从而形成阵列式排布， 栅极长度在 30nm〜50nm之间， 两侧边 缘与凹槽两侧边缘之间具有一定距离， 从而实现了完全覆盖， 凹槽 41完全在栅 极 7的调控范围之内。 如果栅极 7不能完全将凹槽 41覆盖， 则栅极 7外的凹槽 41部 分所引起的 2-DEG降低不能被栅极 7所调控， 这会影响器件的电流密度， 从而影 响器件的输出功率。 此外， 条形凹槽阵列还可以是沿栅极长度方向排布， 或者 斜向排布， 或者多列并排等其他排布方式。 条形凹槽阵列的设置， 一方面整体 分布较为均匀， 从而使得电流相对均匀分布， 避免非均匀分布导致的局部电流 过大， 引起器件局部结温过高， 带来器件可靠性问题； 一方面便于加工。 此外 ， 根据实际需求， 凹槽亦可以是其他规则或不规则的形状， 其排布亦可以是有 序排布或者无序排布， 并不以此为限。
[0032] 各凹槽 41的侧壁 411由凹槽幵口向底部 412方向向内倾斜 0°〜60°， 栅极覆盖于 凹槽 41的侧壁 411和底部 412上， 于垂直的底部方向及斜向的侧壁方向同吋实现 对二维电子气沟道的调制， 形成了环栅效应。 倾斜的侧壁增大了器件的调控能 力， 进而提高了器件的频率性能。 栅极 7于凹槽底部 412的厚度与于势垒层 4表面 的厚度相同， 且由于倾斜侧壁的设置， 其弯折处均为钝角， 避免了尖角效应， 整体厚度趋于均匀， 并呈现与图形化区域相应的表面形貌， 性能均一而稳定。 举例来说， 势垒层的厚度为 20nm左右， 凹槽 41的深度为 10nm左右， 栅极的厚度 为 500nm， 可实现较好的协同作用。
[0033] 衬底及缓冲层为习知之材料及结构， 例如衬底可以是硅、 碳化硅及蓝宝石等。
缓冲层可以是 Al xGa i— ΧΝ， 0≤χ≤1。 沟道层 3和势垒层 4为可形成异质结的半导体 材料形成， 例如 GaN/AlGaN， GaAs/AlGaAs等。 源极 5和漏极 6为金属并与势垒层 4之间形成欧姆接触， 栅极 7亦为金属并与势垒层 4之间形成肖特基接触。
[0034] 制备上述图形化栅结构的微波晶体管的方法， 是首先于衬底 1上依次形成缓冲 层 2、 沟道层 3及势垒层 4。 清洗该试片后在势垒层 4上形成源极 5和漏极 6， 具体 是使用电子束蒸镀机蒸镀上 Ti/Al/Ni/Au多金属层， 各层厚度分别是 20/150/50/100 nm， 然后放入快速退火机， 在 850°C下 30s退火形成欧姆接触， 从而形成了源极 和漏极。 此外， 源极和漏极亦可以是其他金属、 合金或叠层结构。 接着， 在源 极和漏极之间的势垒层上蚀刻凹槽， 可以通过干法蚀刻、 湿式蚀刻或两者相结 合的技术来实现。 干法蚀刻可用机台为 RIE、 ICP等， 且通过控制蚀刻的功率、 压力、 气氛等条件来控制凹槽的深度以及侧壁的倾斜度。 湿式蚀刻可用氢氧化 钠、 氢氧化钾等溶液来进行， 并通过控制溶液的浓度、 蚀刻吋间等来控制凹槽 的深度以及侧壁的倾斜度。 再在图形化区域上沉积栅极， 栅极可以是金属， 通 过磁控溅镀、 离子蒸镀或电弧离子蒸镀的方法沉积于图形化区域上并形成肖特 基接触。
[0035] 上述实施例仅用来进一步说明本发明的一种图形化栅结构的微波晶体管及其制 备方法， 但本发明并不局限于实施例， 凡是依据本发明的技术实质对以上实施 例所作的任何简单修改、 等同变化与修饰， 均落入本发明技术方案的保护范围 内。

Claims

权利要求书
一种图形化栅结构的微波晶体管， 所述晶体管由下至上包括衬底、 缓 冲层、 沟道层及势垒层， 势垒层上设置有源极、 漏极及栅极， 且栅极 位于源极和漏极之间， 其特征在于： 所述势垒层于源极和漏极之间具 有一图形化区域， 所述图形化区域内设置有复数个由势垒层表面沿厚 度方向部分下凹形成的凹槽； 所述栅极覆设于所述图形化区域上， 且 栅极长度大于该些凹槽于所述栅极长度方向上的长度以完全覆盖该些 凹槽。
根据权利要求 1所述的图形化栅结构的微波晶体管， 其特征在于： 该 些凹槽占所述栅极覆盖的图形化区域面积的 25%〜75%。
根据权利要求 1所述的图形化栅结构的微波晶体管， 其特征在于： 该 些凹槽是条形结构且等距离间隔平行排列。
根据权利要求 1所述的图形化栅结构的微波晶体管， 其特征在于： 所 述栅极于所述复数个凹槽底部的厚度与所述势垒层表面的厚度相同。 根据权利要求 1所述的图形化栅结构的微波晶体管， 其特征在于： 所 述复数个凹槽的侧壁由凹槽幵口向底部方向向内倾斜 0〜60度， 所述 栅极覆盖所述复数个凹槽的侧壁。
根据权利要求 1所述的图形化栅结构的微波晶体管， 其特征在于： 所 述沟道层和势垒层为可形成异质结的半导体材料制成； 所述源极、 漏 极及栅极由金属制成且源极和漏极与势垒层形成欧姆接触， 栅极与势 垒层形成肖特基接触。
一种如权利要求 1〜6任一项所述的图形化栅结构的微波晶体管的制备 方法， 其特征在于包括以下步骤：
(1)于一衬底上依次形成缓冲层、 沟道层及势垒层；
(2)于势垒层表面上形成源极和漏极；
(3)于源极和漏极之间定义一图形化区域， 蚀刻所述图形化区域的势 垒层形成所述复数个凹槽；
(4)于所述图形化区域上形成栅极， 且栅极长度大于该些凹槽于所述 栅极长度方向上的长度以完全覆盖所述复数个凹槽。
[权利要求 8] 根据权利要求 7所述的制备方法， 其特征在于： 步骤 (2)具体包括以下 子步骤：
通过电子束蒸镀的方法于所述势垒层表面的两个区域分别蒸镀上 ΤΪ/Α 1/Ni/Au多金属层， 其中所述 Ti/Al/Ni/Au的厚度分别是 20/150/50/100n m;
于 800-950°C下退火 20-45秒形成欧姆接触， 形成所述源极和漏极。
[权利要求 9] 根据权利要求 7所述的制备方法， 其特征在于： 步骤 (3)中， 是通过干 法蚀刻和 /或湿式蚀刻的方式形成该些凹槽。
[权利要求 10] 根据权利要求 7所述的制备方法， 其特征在于： 步骤 (4)中， 所述栅极 是金属， 通过磁控溅镀、 离子蒸镀或电弧离子蒸镀的方法沉积于所述 图形化区域上并与势垒层形成肖特基接触。
PCT/CN2017/090511 2016-07-04 2017-06-28 一种图形化栅结构的微波晶体管及其制备方法 WO2018006739A1 (zh)

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