WO2017190643A1 - 一种新型iii-v异质结场效应晶体管 - Google Patents

一种新型iii-v异质结场效应晶体管 Download PDF

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WO2017190643A1
WO2017190643A1 PCT/CN2017/082738 CN2017082738W WO2017190643A1 WO 2017190643 A1 WO2017190643 A1 WO 2017190643A1 CN 2017082738 W CN2017082738 W CN 2017082738W WO 2017190643 A1 WO2017190643 A1 WO 2017190643A1
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layer
semiconductor layer
dielectric
field effect
effect transistor
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PCT/CN2017/082738
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English (en)
French (fr)
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董志华
程知群
刘国华
柯华杰
周涛
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杭州电子科技大学
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Priority claimed from CN201610297662.9A external-priority patent/CN105826369A/zh
Priority claimed from CN201610294235.5A external-priority patent/CN105977294A/zh
Priority claimed from CN201621179373.0U external-priority patent/CN206116406U/zh
Application filed by 杭州电子科技大学 filed Critical 杭州电子科技大学
Priority to US15/755,424 priority Critical patent/US10283598B2/en
Publication of WO2017190643A1 publication Critical patent/WO2017190643A1/zh

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Definitions

  • the present application relates to the field of semiconductor device technologies, and in particular, to a novel III-V heterojunction field effect transistor.
  • Certain binary or ternary compounds composed of Group III and Group V elements have spontaneous polarization and piezoelectric polarization effects.
  • a heterojunction such as AlGaN/GaN
  • a device that forms a high concentration of two-dimensional electron gas (2DEG) at the interface of the heterojunction and a 2DEG at the interface of the heterojunction is called a heterojunction field effect transistor (HFET), which can also be called high electron.
  • HFET heterojunction field effect transistor
  • HFET devices feature high electron mobility, high device operating frequency, and high efficiency. It has very important application prospects in the field of microwave power emitter transmission and power electronics. However, to date, HFET devices have a natural defect. Taking AlGaN/GaN HFETs as an example, due to the strong spontaneous polarization and piezoelectric polarization, the heterojunction interface is formed without any applied voltage. At 2DEG concentrations, HFET devices are naturally depleted (normally open). The defects of HFET devices limit the application of the device in logic circuits and power electronic circuits. The former requires a normally-off or enhanced and depleted (normally open) logic complement, while the latter is considered for safety and energy saving. What is more needed is a normally off or enhanced device.
  • FIG. 1 there is shown a cross-sectional view of a prior art depletion mode III-V HFET device comprising a substrate material layer 9, a second semiconductor layer 10, a first semiconductor layer 14, a two-dimensional electron gas 11, a drain electrode 12, a source electrode 13, a gate dielectric layer 15 and a gate electrode 16, wherein a heterostructure is formed between the second semiconductor layer 10 and the first semiconductor layer 14, since the thickness of the first semiconductor layer 14 in the prior art exceeds a critical thickness, Without any applied voltage, due to the piezoelectric polarization and spontaneous polarization of the material system, at the interface of the heterojunction, that is, the interface between the first semiconductor and the second semiconductor, there is a high concentration of two-dimensional electron gas. 2DEG.
  • Under-gate channel F ion implantation technology the negative ions of F are implanted into the barrier layer at the lower part of the gate, and the channel electrons under the gate are depleted by a negative potential to realize the forward threshold (enhanced type) of the device.
  • this device adds a layer of p-AlGaN under the gate, which depletes the 2DEG of the channel due to the equalization of the band.
  • the above technologies have different disadvantages.
  • the F ion implantation technology has problems in reliability and obtaining a large threshold.
  • the trench gate technology has great difficulty in process control.
  • the P-AlGaN technology has difficulty in material growth and device switching. Low frequency and other shortcomings.
  • the main purpose of the present application is to provide a novel III-V heterojunction field effect transistor to solve the above problems.
  • Embodiments of the present application provide a novel III-V heterojunction field effect transistor including a substrate material layer, a second semiconductor layer, a first semiconductor layer, a drain electrode, a source electrode, a first dielectric layer, and a second medium. Layer and gate electrode, wherein
  • the second semiconductor layer and the first semiconductor layer are combined to form a heterostructure; the thickness of the first semiconductor layer is not greater than a critical thickness of a two-dimensional electron gas 2DEG formed on the heterostructure, The natural two-dimensional electron gas 2DEG in the structure is depleted;
  • the surface of the first semiconductor layer is further provided with a first dielectric layer, the gate electrode is disposed on the first dielectric layer, the gate electrode covers the entire channel length, and the two edge extensions of the gate electrode respectively exceed
  • the drain electrode and the source electrode are adjacent to an edge of the channel side, and the second dielectric layer is disposed between the gate electrode and the drain electrode and the source electrode.
  • Embodiments of the present application provide a novel III-V heterojunction field effect transistor including a substrate material layer, a first semiconductor layer, a second semiconductor layer, a dielectric template layer, a drain electrode, a source electrode, and a first dielectric layer.
  • the second semiconductor layer is formed on the substrate material layer, and a drain electrode and a source electrode are formed on the second semiconductor layer; the second semiconductor layer and The first semiconductor layer body is combined to form a heterojunction channel, and the two ends of the heterojunction channel are respectively connected to the drain electrode and the source electrode; the thickness of the first semiconductor layer body is not greater than on the heterojunction channel Forming a critical thickness of the two-dimensional electron gas 2DEG such that the natural two-dimensional electron gas 2DEG in the heterojunction channel is depleted;
  • the first semiconductor layer includes a body and n convex portions formed along the body, n is greater than or equal to 1;
  • the dielectric template layer is disposed on the first semiconductor layer body and is formed with n windows, and the n windows are grown to form the n convex portions; the convex portions cause the first semiconductor layer to exceed a critical thickness to form a two-dimensional electron gas 2DEG in a projected region of the convex portion, and n spaced apart two-dimensional electron gas 2DEG regions are formed on the heterojunction channel;
  • the gate electrode is disposed on the first dielectric layer.
  • a novel III-V heterojunction field effect transistor is a normally-off type III-V heterojunction field effect transistor including a substrate material layer, a second semiconductor layer, and a dielectric template layer. a drain electrode, a source electrode, a first dielectric layer, a second dielectric layer, and a gate electrode, wherein
  • the first semiconductor layer includes a body and n protrusions formed along the body Starting part, n ⁇ 1;
  • the second semiconductor layer and the first semiconductor layer body are combined to form a heterojunction channel, and the two ends of the heterojunction channel are respectively connected to the drain electrode and the source electrode; the thickness of the first semiconductor layer body is not Forming a critical thickness greater than that of forming a two-dimensional electron gas 2DEG on the heterojunction channel, so that the natural two-dimensional electron gas 2DEG in the heterojunction channel is depleted;
  • the dielectric template layer is disposed on the first semiconductor layer body and equally formed with n windows, and the first semiconductor layer body is grown along the n windows to form the n convex portions; Partially causing the first semiconductor layer to exceed a critical thickness to form a two-dimensional electron gas 2DEG in a projected region of the convex portion, and forming n equally spaced two-dimensional electron gas 2DEG regions on the heterojunction channel;
  • the surface of the first semiconductor layer is further provided with a first dielectric layer, the gate electrode is disposed on the first dielectric layer, the gate electrode covers the entire channel length, and the two edge extensions of the gate electrode respectively exceed
  • the drain electrode and the source electrode are adjacent to an edge of the channel side, and the second dielectric layer is disposed between the gate electrode and the drain electrode and the source electrode.
  • a dielectric wall is distributed between at least two adjacent windows in the dielectric template layer, and the dielectric wall is only distributed in an area covered by the projection of the gate electrode, and the number of the dielectric walls n, n is greater than or equal to 1, and at least one dielectric wall has a dimension in the gate width direction greater than or equal to the gate width;
  • the first semiconductor layer body is grown along the outer side of the dielectric wall to form a convex portion; the convex portion Forming the first semiconductor layer beyond a critical thickness to form a two-dimensional electron gas 2DEG in a projected region of the convex portion, and forming at least two discontinuous two-dimensional electron gas 2DEG regions on the heterojunction channel, That is, the portion where the source electrode and the drain electrode are connected;
  • the gate electrode is disposed on the first semiconductor, and the gate electrode covers only a portion of the entire heterojunction channel in which the two-dimensional electron gas is interrupted.
  • the novel III-V heterojunction field effect transistor provided by the present application has the advantages of simple structure, simple preparation process, stable performance and high reliability.
  • FIG. 1 is a schematic cross-sectional view of a prior art conventional enhanced III-V HFET device.
  • FIG. 2 is a schematic cross-sectional view of a novel enhanced III-V heterojunction field effect transistor of the present application.
  • FIG. 3 is a top plan view of a novel enhanced III-V heterojunction field effect transistor of the present application.
  • FIG. 4 is a schematic cross-sectional view of a novel normally-off type III-V heterojunction field effect transistor of the present application.
  • FIG. 8 is a schematic cross-sectional view of a normally-off type III-V heterojunction field effect transistor having a composite barrier layer structure according to the present application.
  • the inventor of the present invention conducted a continuous and in-depth study on the structure of the prior art HFET device.
  • the inventors of the present invention found that the barrier layer of the conventional device, that is, the thickness of the first semiconductor layer exceeds the critical thickness, so no applied voltage is applied.
  • the barrier layer of the conventional device that is, the thickness of the first semiconductor layer exceeds the critical thickness, so no applied voltage is applied.
  • the heterojunction interface that is, the interface between the first semiconductor and the second semiconductor
  • special processes such as trench gate, F ion implantation doping must be used. These processes have the disadvantages of being difficult to precisely control and additionally extending the process cycle.
  • the trench gate structure is etched by the process, which damages the device channel and, therefore, damages the performance of the device.
  • the F injection process is difficult to perform with precise control and has a hidden danger in reliability.
  • a novel III-V heterojunction field effect transistor provided by an embodiment of the present application is an enhanced III-V heterojunction field effect transistor including a substrate material layer, a second semiconductor layer, a first semiconductor layer, and a drain electrode. a source electrode, a first dielectric layer, a second dielectric layer, and a gate electrode, wherein
  • the second semiconductor layer and the first semiconductor layer are combined to form a heterostructure; the thickness of the first semiconductor layer is not greater than a critical thickness of a two-dimensional electron gas 2DEG formed on the heterostructure, The natural two-dimensional electron gas 2DEG in the structure is depleted;
  • the surface of the first semiconductor layer is further provided with a first dielectric layer, the gate electrode is disposed on the first dielectric layer, the gate electrode covers the entire channel length, and the two edge extensions of the gate electrode respectively exceed
  • the drain electrode and the source electrode are adjacent to an edge of the channel side, and the second dielectric layer is disposed between the gate electrode and the drain electrode and the source electrode.
  • the second dielectric layer is located only at an overlapping edge portion of the gate electrode and the drain electrode and the source electrode.
  • an intercalation layer for increasing the mobility of the two-dimensional electron gas of the heterojunction interface is further disposed between the first semiconductor layer and the second semiconductor layer.
  • the thickness of the intercalation layer may be about 1 nm.
  • the intercalation layer comprises an AlN layer.
  • the first semiconductor layer comprises an AlGaN layer or an AlN layer.
  • the second semiconductor layer comprises a GaN layer.
  • the first semiconductor layer is an AlGaN layer having a thickness of less than or equal to 5 nm, preferably 1 to 5 nm; and the second semiconductor layer is a GaN layer, and the thickness thereof may be any suitable value. For example, it can be 2 ⁇ m.
  • the first semiconductor layer is an AlN layer having a thickness of 5 nm; and the second semiconductor layer is a GaN layer having a thickness of 2 ⁇ m.
  • the first dielectric layer is Si 3 N 4 grown in situ when the heterostructure material is grown, and has a thickness of 5 to 25 nm.
  • a third dielectric layer is further disposed between the gate electrode and the first dielectric layer, and the third dielectric layer is used to further reduce a gate leakage current of the device.
  • the second dielectric layer comprises a SiO 2 layer.
  • the second dielectric layer may have a thickness of 100 nm.
  • the length of the second dielectric layer beyond the drain electrode and the source electrode toward the side edge of the channel is 0 to 2 ⁇ m, for example, preferably 0.5 ⁇ m.
  • the distance between the drain electrode and the source electrode may be about 2.5 ⁇ m.
  • the novel enhanced III-V heterojunction field effect transistor obtained by the foregoing embodiments of the present application obtains a depleted channel by using a thin barrier layer scheme, and adopts a MIS gate structure to re-inducing 2DEG with a high gate voltage, thereby achieving performance. Stable, enhanced device.
  • FIGS. 2 and 3 a structure of a novel enhanced III-V heterojunction field effect transistor can be seen in FIGS. 2 and 3, wherein FIG. 2 is a cross-sectional view of the device. 3 is its top view.
  • the novel enhanced III-V heterojunction field effect transistor includes a substrate material layer 1, a second semiconductor layer 2, a first semiconductor layer 3, a drain electrode 4, a source electrode 5, and a first dielectric layer 6, Two dielectric layers 7 and a gate electrode 8, wherein
  • a second semiconductor layer 2 is formed on the substrate material layer 1, a drain electrode 4 and a source electrode 5 are formed on the second semiconductor layer 2, and the drain electrode 4 and the source electrode 5 are connected by the first semiconductor layer 3 and a semiconductor layer 3 ohmic contact to form a channel; the first semiconductor layer 3 has a larger forbidden band width than the second semiconductor layer 2;
  • the second semiconductor layer 2 and the first semiconductor layer 3 are combined to form a heterostructure; the thickness of the first semiconductor layer 3 is not greater than the critical thickness of the two-dimensional electron gas 2DEG formed on the heterostructure, so that the first semiconductor layer 3 is different
  • the natural two-dimensional electron gas 2DEG in the mass structure is depleted; through the design of the thin first structure of the semiconductor layer, since the thickness of the first semiconductor layer is lower than the critical thickness, the natural concentration of the high concentration on the heterostructure is eliminated.
  • Dimensional electron gas 2DEG therefore, in the absence of external gate voltage, there is no 2DEG at the hetero interface of the first semiconductor layer and the second semiconductor layer, and can only be induced in the channel when the applied gate voltage exceeds a certain positive threshold voltage.
  • a high concentration of 2DEG is achieved, thereby achieving an enhanced morphology; thereby greatly simplifying the process of forming an enhanced device.
  • a first dielectric layer 6 is further disposed on the surface of the first semiconductor layer 3.
  • the first dielectric layer 6 is provided with a gate electrode 8 covering the entire channel length and the two edges of the gate electrode 8 extending beyond the drain electrode 4 and
  • the source electrode 5 is adjacent to the edge of the channel side, and a second dielectric layer 7 is provided between the gate electrode 8 and the drain electrode 4 and the source electrode 5. Due to the channel structure completely covered by the gate electrode, the gate voltage is completely controlled by the channel 2DEG, thereby realizing a device without current collapse effect.
  • the second dielectric layer 7 is located only at the overlapping edge portions of the gate electrode 8 and the drain electrode 4 and the source electrode 5.
  • the purpose of the second dielectric layer 7 is to prevent electrical connection between the gate electrode 8 and the drain electrode 4 and the source electrode 5, but the second dielectric layer 7 in turn affects the gate capacitance, thereby affecting the gate control capability and the amplification capability.
  • the structure allows the second dielectric layer 7 to cover only the overlapping edge portions of the gate electrode 8 and the drain electrode 4 and the source electrode 5, as compared with the second dielectric layer completely covering the first dielectric layer, under the premise of achieving good electrical isolation. It can ensure a larger gate capacitance and a larger device transconductance, which enables the device to have greater gate control and amplification.
  • the thickness of the second dielectric layer should be as small as possible.
  • the second dielectric layer is very small, minimizing the reduction in gate capacitance.
  • the implementation process of the novel enhanced III-V heterojunction field effect transistor is basically the same as that of the prior art HFET device, and no additional process complexity is required.
  • the device of the present application can be implemented by the following main process steps:
  • substrate material on a suitable substrate material (such as a Si substrate), a corresponding buffer layer, a second semiconductor layer, a selective growth insertion layer, a first semiconductor layer, an in-situ Si3N4 layer are grown according to a material growth rule. .
  • Second gate dielectric layer selective region etching Second gate dielectric layer selective region etching.
  • the process complexity of the device is not additionally increased, and the threshold voltage can be set by setting parameters such as the thickness of the first semiconductor layer and the thickness of the first dielectric layer, thereby realizing the device process.
  • the repeatability is beneficial to the industrial production of the device.
  • a novel III-V heterojunction field effect transistor provided by an embodiment of the present application is a normally-off type III-V heterojunction field effect transistor, which comprises a substrate material layer, a first semiconductor layer, a second semiconductor layer, and a medium. a template layer, a drain electrode, a source electrode, a first dielectric layer, a second dielectric layer, and a gate electrode, wherein
  • the first semiconductor layer includes a body and n protrusions formed along the body Starting part, n ⁇ 1;
  • the second semiconductor layer and the first semiconductor layer body are combined to form a heterojunction channel, and the two ends of the heterojunction channel are respectively connected to the drain electrode and the source electrode; the thickness of the first semiconductor layer body is not Forming a critical thickness greater than that of forming a two-dimensional electron gas 2DEG on the heterojunction channel, so that the natural two-dimensional electron gas 2DEG in the heterojunction channel is depleted;
  • the dielectric template layer is disposed on the first semiconductor layer body and equally formed with n windows, and the first semiconductor layer body is grown along the n windows to form the n convex portions; Partially causing the first semiconductor layer to exceed a critical thickness to form a two-dimensional electron gas 2DEG in a projected region of the convex portion, and forming n equally spaced two-dimensional electron gas 2DEG regions on the heterojunction channel;
  • the surface of the first semiconductor layer is further provided with a first dielectric layer, the gate electrode is disposed on the first dielectric layer, the gate electrode covers the entire channel length, and the two edge extensions of the gate electrode respectively exceed
  • the drain electrode and the source electrode are adjacent to an edge of the channel side, and the second dielectric layer is disposed between the gate electrode and the drain electrode and the source electrode.
  • the convex portion is continuously distributed or divided into m parts along the growth direction thereof, and m ⁇ 1.
  • the second dielectric layer is located only at an overlapping edge portion of the gate electrode and the drain electrode and the source electrode.
  • an intercalation layer for increasing the mobility of the two-dimensional electron gas of the heterojunction interface is further disposed between the first semiconductor layer and the second semiconductor layer.
  • the intercalation layer comprises an AlN layer.
  • the first semiconductor layer comprises an AlGaN layer or an AlN layer; the second semiconductor layer is a GaN layer.
  • the first dielectric layer is Si 3 N 4 grown in situ when the heterostructure material is grown, and has a thickness of 5 to 25 nm.
  • the dielectric template layer comprises a SiO 2 layer, such as an LPCVD grown SiO 2 layer.
  • the second dielectric layer comprises a SiO 2 layer.
  • the length of the second dielectric layer facing the side edge of the channel beyond the drain electrode and the source electrode is 0.5 ⁇ m.
  • the novel normally-off type III-V heterojunction field effect transistor provided by the foregoing embodiments of the present application obtains a discontinuous channel by using a specially designed barrier layer, and re-induced 2DEG by using a high gate voltage, thereby achieving a stable performance.
  • Type devices and can take flexible and diverse design according to the performance requirements of the device.
  • Figure 7 is a plan view.
  • the novel normally-off type III-V heterojunction field effect transistor of the present application comprises a substrate material layer 1, a second semiconductor layer 2, a first semiconductor layer body 3, a first semiconductor layer convex portion 9, and a two-dimensional electron gas 10,
  • the second semiconductor layer 2 is formed on the substrate material layer 1, the drain electrode 5 and the source electrode 4 are formed on the second semiconductor layer 2, and the first semiconductor layer body 3 is formed on the second semiconductor layer 2, A semiconductor layer body 3 and the second semiconductor layer 2 are combined to form a heterostructure; the drain electrode 5 and the source electrode 4 are connected by a channel formed between the first semiconductor layer body 3 and the second semiconductor 2;
  • the semiconductor layer has a larger forbidden band width than the second semiconductor layer; the thickness of the first semiconductor layer body 3 is not greater than the critical thickness of the two-dimensional electron gas 2DEG formed on the heterostructure.
  • a dielectric template layer 6 is formed on the first semiconductor layer body 3, and n windows are formed on the dielectric template layer 6 at equal intervals, and the first semiconductor layer body 3 is grown along the n windows to form the n convex portions. 4; the convex portion causes the first semiconductor layer to exceed a critical thickness to form a two-dimensional electron gas 2DEG in a projected region of the convex portion, and form n equally spaced two-dimensional electron gas on the heterojunction channel 2DEG area.
  • the heterostructure is insufficient to generate the two-dimensional electron gas 2DEG; since the first semiconductor layer portion 3 and the first semiconductor bump portion 4 are present where the first semiconductor bump portion 4 is present
  • the total thickness exceeds the critical thickness capable of generating the two-dimensional electron gas 2DEG, so there is a two-dimensional electron gas 2DEG at the heterojunction interface below the first semiconductor convex portion 4. Further, at the interface of the heterojunction, a discontinuous two-dimensional electron gas 2DEG is distributed. Due to the discontinuity of the two-dimensional electron gas 2DEG, in the absence of the gate voltage, the conductive channel does not form the HFET device as a normally-off type. Only when the gate voltage is greater than the threshold voltage, the two-dimensional electron gas 2DEG at the interface of the heterojunction will continue to form a conductive channel.
  • the gate electrode of the device realizes full coverage of the channel between the source and the drain, so when the device is in operation, the gate voltage can completely control the channel and realize the instantaneous switching of the channel, so that the maximum degree can be achieved. Avoid the "current collapse” effect.
  • the gate electrode of the device covers the source and drain electrodes, since the two-dimensional electron gas having the convex portion of the first semiconductor is often present, the equivalent gate length of the device is only convex on the first semiconductor. The length of the part, so the device gets a higher cutoff frequency.
  • the breakdown voltage of the device is positively correlated with the length between the source and drain electrodes, the device can simultaneously obtain a higher breakdown voltage.
  • the first semiconductor layer surface is further provided with a first dielectric layer 6, a first electrode layer 6 is provided with a gate electrode 8, the gate electrode 8 covers the entire channel length and the two edges of the gate electrode 8 extend beyond the drain electrode 5 and the source respectively
  • the electrode 4 is adjacent to the edge of the channel side, and a second dielectric layer 7 is provided between the gate electrode 8 and the drain electrode 5 and the source electrode 4. Due to the channel structure completely covered by the gate electrode, the gate voltage is completely controlled by the channel 2DEG, thereby realizing a device without current collapse effect.
  • the first semiconductor layer convex portion 9 may be continuously distributed in a direction perpendicular to the source and drain electrodes, or may be divided into m parts.
  • the dielectric layer template 6 exhibits discontinuity in the direction between the source and drain electrodes.
  • the second dielectric layer 7 is located only at the overlapping edge portions of the gate electrode 8 and the drain electrode 5 and the source electrode 4.
  • the purpose of the second dielectric layer 7 is to prevent the electrical connection between the gate electrode 8 and the drain electrode 5 and the source electrode 4, but the second dielectric layer 7 in turn affects the gate capacitance, thereby affecting the gate control capability and the amplification capability.
  • the structure allows the second dielectric layer 7 to cover only the overlapping edge portions of the gate electrode 8 and the drain electrode 5 and the source electrode 4, as compared with the second dielectric layer completely covering the first dielectric layer, under the premise of achieving good electrical isolation It can ensure a larger gate capacitance and a larger device transconductance, which enables the device to have greater gate control and amplification.
  • the thickness of the second dielectric layer should be as small as possible.
  • the second dielectric layer is very small, minimizing the reduction in gate capacitance.
  • the implementation process of the novel enhanced III-V heterojunction field effect transistor of the present application is basically the same as that of the prior art HFET device, and there is no need to additionally increase the process complexity of the device.
  • the device of the present application can be implemented by the following main process steps:
  • substrate material on a suitable substrate material (such as a Si substrate), a corresponding buffer layer, a second semiconductor layer, a selective growth insertion layer, a first semiconductor layer body 3, and a dielectric template are grown according to a material growth rule.
  • a suitable substrate material such as a Si substrate
  • a second semiconductor layer such as a Si substrate
  • a selective growth insertion layer such as a first semiconductor layer body 3
  • a dielectric template is grown according to a material growth rule.
  • Second dielectric layer growth and selective etching Second dielectric layer growth and selective etching.
  • a normally-off type device can be realized by adopting the above technical solution; and since the channel material of the device is grown without an etching process as used in the trench gate device, it is not different The interface of the junction is destroyed, which is beneficial to improve device performance.
  • a novel III-V heterojunction field effect transistor provided by an embodiment of the present application is a normally-off type III-V heterojunction field effect transistor having a composite barrier layer structure, including a substrate material layer and a second semiconductor layer a dielectric wall (which may also be considered as another form of dielectric template layer), a drain electrode, a source electrode, and a gate electrode, wherein
  • the second semiconductor layer on the substrate material layer Forming the second semiconductor layer on the substrate material layer, and constructing a drain electrode and a source electrode on the second semiconductor layer; the second semiconductor layer and the first semiconductor layer body are combined to form a heterogeneity a junction channel, the two ends of the heterojunction channel are respectively connected to the drain electrode and the source electrode; the thickness of the first semiconductor layer body is not greater than a critical thickness of forming a two-dimensional electron gas 2DEG on the heterojunction channel, so that The natural two-dimensional electron gas 2DEG in the heterojunction channel is depleted;
  • the dielectric wall is only distributed in an area covered by the projection of the gate electrode, the number of the dielectric walls is n, n is greater than or equal to 1, and at least one dielectric wall is in the grid
  • the dimension in the width direction is greater than or equal to the gate width;
  • the first semiconductor layer body is grown along the outer side of the dielectric wall to form a convex portion;
  • the convex portion causes the first semiconductor layer to exceed a critical thickness so as to be in the convex portion
  • the projection area forms a two-dimensional electron gas 2DEG, and at least two discontinuous two-dimensional electron gas 2DEG regions are formed on the heterojunction channel, that is, a portion where the source electrode and the drain electrode edge are connected;
  • the gate electrode is disposed on the first semiconductor, and the gate electrode covers only a portion of the entire heterojunction channel in which the two-dimensional electron gas is interrupted.
  • a first dielectric layer is further disposed between the gate electrode and the first semiconductor.
  • the portion of the raised portion within the projected coverage of the gate electrode is continuously distributed or divided into m portions along the growth direction thereof, and m is greater than or equal to one.
  • an interposer layer for increasing the mobility of the two-dimensional electron gas 2DEG of the heterojunction interface is further disposed between the first semiconductor layer and the second semiconductor layer.
  • the interposer layer includes an AlN layer, but is not limited thereto.
  • the first semiconductor layer may include, but is not limited to, an AlGaN layer, an AlN layer, or the like.
  • the second semiconductor layer can include, but is not limited to, a GaN layer.
  • the first dielectric layer comprises Si 3 N 4 grown in situ when the heterostructure material is grown.
  • the first dielectric layer has a thickness of 5 to 25 nm.
  • the dielectric wall forms n windows by photolithography or etching processes.
  • FIG. 8 is a schematic cross-sectional view of the device
  • the device comprises a substrate material layer 1, a second semiconductor layer 2, a first semiconductor layer body 3, a first semiconductor layer convex portion 9, a two-dimensional electron gas 10, a dielectric wall 11', and a first dielectric layer 6 , gate electrode 8, source electrode 4, drain electrode 5.
  • the second semiconductor layer 2 is formed on the substrate material layer 1, the drain electrode 5 and the source electrode 4 are formed on the second semiconductor layer 2, and the first semiconductor layer body 3 is formed on the second semiconductor layer 2, A semiconductor layer body 3 and the second semiconductor layer 2 are combined to form a heterostructure; the drain electrode 5 and the source electrode 4 are connected by a channel formed between the first semiconductor layer body 3 and the second semiconductor 2;
  • the semiconductor layer has a larger forbidden band width than the second semiconductor layer; the thickness of the first semiconductor layer body 3 is not greater than the critical thickness of the two-dimensional electron gas 2DEG formed on the heterostructure.
  • the heterostructure is insufficient to generate a two-dimensional electron gas 2DEG;
  • the semiconductor bump portion 9 is, the total thickness of the first semiconductor layer body 3 and the first semiconductor bump portion 9 exceeds a critical thickness capable of generating a two-dimensional electron gas 2DEG, so that there is below the first semiconductor bump portion 9
  • a two-dimensional electron gas 2DEG At the interface of the heterojunction, there is a two-dimensional electron gas 2DEG.
  • a discontinuous two-dimensional electron gas 2DEG is distributed. Due to the discontinuity of the two-dimensional electron gas 2DEG, the conductive channel is not formed when there is no gate voltage, and the HFET device is normally closed.
  • the dielectric wall is only distributed in the area covered by the projection of the gate electrode, that is, the portion where the drain electrode and the source electrode are connected to each other to form a convex portion of the first semiconductor, so that the heterojunction channel is close to the source.
  • the portion of the electrode and the drain electrode forms a two-dimensional electron gas 2DEG, so that the gate electrode covers only the portion of the entire heterojunction channel in which the two-dimensional electron gas is interrupted, and the conduction and the cutoff of the heterojunction channel can be controlled. Therefore, in the device of the foregoing embodiment of the present application, no dielectric layer isolation is required between the gate electrode and the drain electrode and the source electrode, which greatly simplifies the production process and greatly increases the breakdown voltage of the transistor.
  • the surface of the first semiconductor layer is further provided with a first dielectric layer 6, and the first dielectric layer 6 is provided with a gate electrode 8 covering the two-dimensional electron gas interruption in the entire composite barrier layer. In part, it can be ensured that the source and drain electrodes are turned on by the two-dimensional electron gas 2DEG when a certain gate voltage is applied.
  • the first semiconductor layer convex portion 9 may be continuously distributed in a direction perpendicular to the source and drain electrodes, or may be divided into m parts.
  • the implementation process of the novel enhanced III-V heterojunction field effect transistor of the present application is basically the same as that of the prior art HFET device, and there is no need to additionally increase the process complexity of the device.
  • the device of the present application can be implemented by the following main process steps:
  • substrate material on a suitable substrate material (such as a Si substrate), a corresponding buffer layer, a second semiconductor layer, a selective growth insertion layer, a first semiconductor layer body 3, and a structural medium are grown according to a material growth rule.
  • a suitable substrate material such as a Si substrate
  • a second semiconductor layer such as a Si substrate
  • a selective growth insertion layer such as a first semiconductor layer body 3
  • a structural medium are grown according to a material growth rule.
  • a normally-off type device can be realized; and, since the channel material of the device is grown without an etching process as used in the trench gate device, no damage is formed to the heterojunction interface, thereby Helps improve device performance.
  • the normally-off type III-V heterojunction field effect transistor having a composite barrier layer structure provided by the foregoing embodiment of the present application obtains a discontinuous channel by using a specially designed barrier layer, and re-induced 2DEG by using a high gate voltage.
  • a normally-off device with stable performance is realized. And can take flexible and diverse design according to the performance requirements of the device.
  • the gate electrode covers only the portion of the two-dimensional electron gas discontinuity in the entire heterojunction channel, the production process is greatly simplified, and the dielectric layer isolation is not required between the gate electrode and the drain electrode and the source electrode, thereby greatly improving the breakdown voltage of the transistor. .
  • Embodiment 1 This embodiment of the novel enhanced III-V heterojunction field effect transistor includes the following parts: the substrate material comprises a Si material and a low temperature AlN buffer layer grown thereon, and the second semiconductor layer is a GaN material layer ( The thickness is about 2 ⁇ m), the first semiconductor layer is an AlGaN layer (having a thickness of about 1 to 5 nm), and an AlN intercalation layer (having a thickness of about 1 nm) is provided between the first and second semiconductor layers for improving the electrical power of 2DEG. characteristic.
  • the first dielectric layer is an in-situ Si 3 N 4 layer having a thickness of about 5 to 25 nm.
  • the source and drain electrodes are formed by metal deposition and high temperature thermal annealing using Ti/Al/Ni/Au (20/120/50/200 nm). The distance between the source and drain electrodes was 2.5 ⁇ m.
  • the second dielectric layer is a SiO 2 layer having a thickness of about 100 nm. The length of the second dielectric layer facing the center of the channel beyond the source and drain electrodes is 0.5 ⁇ m.
  • the gate electrode is Ni/Au (50/150 nm).
  • the device is prepared by first growing a low temperature AlN buffer layer on a substrate material containing Si, then growing a second semiconductor layer-GaN layer, then growing a first semiconductor AlGaN layer, and then growing an in-situ Si 3 N 4 layer as The first dielectric layer.
  • the first dielectric layer at the source and drain electrodes is then etched and an ohmic contact is prepared.
  • the second dielectric layer is then regrown and lithographically etched to leave only the second dielectric layer at the source and drain edges, and finally the gate electrode is prepared.
  • the novel enhanced III-V heterojunction field effect transistor of the present embodiment includes the following parts: the substrate material comprises a SiC material and a low temperature AlN buffer layer grown thereon, and the second semiconductor layer is a GaN material layer ( The thickness is about 2 ⁇ m, the first semiconductor layer is an AlN layer (having a thickness of about 5 nm), and the first dielectric layer is an in-situ Si 3 N 4 layer having a thickness of about 5 to 25 nm.
  • the source and drain electrodes are formed by metal deposition and high temperature thermal annealing using Ti/Al/Ni/Au (20/120/50/200 nm). The distance between the source and drain electrodes was 2.5 ⁇ m.
  • the second dielectric layer is a SiO 2 layer having a thickness of about 100 nm.
  • the length of the second dielectric layer facing the center of the channel beyond the source and drain electrodes is 0.5 ⁇ m.
  • the gate electrode is Ni/Au (50/150 nm).
  • the novel normally-off type III-V heterojunction field effect transistor of the present embodiment includes the following parts: the substrate material comprises a Si material and a low temperature AlN buffer layer grown thereon, and the second semiconductor layer is a GaN material layer (having a thickness of about 2 ⁇ m), the first portion of the first semiconductor layer is an AlGaN layer (having a thickness of about 3 nm), and an AlN intercalation layer (having a thickness of about 1 nm) is provided between the first semiconductor layer and the first portion of the second semiconductor layer. Used to improve the electrical properties of 2DEG.
  • the first dielectric layer is an in-situ Si3N4 layer having a thickness of about 10 nm, and the second dielectric layer is hfO 2 and has a thickness of 100 nm.
  • the source and drain electrodes are formed by metal deposition and high temperature thermal annealing using Ti/Al/Ni/Au (20/120/50/200 nm).
  • the distance between the source and drain electrodes was 2.5 ⁇ m.
  • the length of the second dielectric layer facing the center of the channel beyond the source and drain electrodes is 0.5 ⁇ m.
  • the gate electrode is Ni/Au (50/150 nm).
  • the device is prepared by first growing a low temperature AlN buffer layer on a substrate material containing Si, then growing a second semiconductor layer-GaN layer, then growing a bulk portion of the first semiconductor AlGaN layer, and then growing a dielectric template layer-LPCVD (low pressure chemical vapor deposition) growth of the SiO 2 layer, followed by photolithography and etching processes, leaving the dielectric wall, then exposing the second epitaxial window, and then re-injecting the material into the material growth device, in the window The raised portion of the first semiconductor is regrown.
  • LPCVD low pressure chemical vapor deposition
  • An in-situ Si 3 N 4 layer is then grown as the first dielectric layer.
  • the first dielectric layer at the source and drain electrodes is then etched and an ohmic contact is prepared.
  • the second dielectric layer hfO 2 is then regrown and photolithographically etched to leave only the second dielectric layer at the source and drain edges, and finally the gate electrode is prepared.
  • the novel normally-off type III-V heterojunction field effect transistor of the present embodiment includes the following parts: the substrate material comprises a SiC material and a low temperature AlN buffer layer grown thereon, and the second semiconductor layer is a GaN material layer (Thickness is about 2 ⁇ m), and the first portion of the first semiconductor layer is an AlN layer (having a thickness of about 3 nm).
  • the first dielectric layer is an in-situ Si 3 N 4 layer having a thickness of about 10 nm
  • the second dielectric layer is hfO 2 and has a thickness of 100 nm.
  • the source and drain electrodes are formed by metal deposition and high temperature thermal annealing using Ti/Al/Ni/Au (20/120/50/200 nm). The distance between the source and drain electrodes was 2.5 ⁇ m. The length of the second dielectric layer facing the center of the channel beyond the source and drain electrodes is 0.5 ⁇ m.
  • the gate electrode is Ni/Au (50/150 nm).
  • the normally-off type III-V heterojunction field effect transistor having the composite barrier layer structure of the embodiment includes the following parts: the substrate material comprises a Si material and a low-temperature AlN buffer layer grown thereon, and second The semiconductor layer is a GaN material layer (having a thickness of about 2 ⁇ m), the body portion of the first semiconductor layer is an AlGaN layer (having a thickness of about 3 nm), and an AlN insertion layer is provided between the second semiconductor layer and the body portion of the first semiconductor layer. (Thickness is about 1 nm) for improving the electrical properties of 2DEG.
  • the first dielectric layer is an in-situ Si3N4 layer having a thickness of about 10 nm.
  • the source and drain electrodes are formed by metal deposition and high temperature thermal annealing using Ti/Al/Ni/Au (20/120/50/200 nm). The distance between the source and drain electrodes was 2.5 ⁇ m.
  • the gate electrode is Ni/Au (50/150 nm).
  • the normally-off type III-V heterojunction field effect transistor having the composite barrier layer structure of the embodiment includes the following parts: the substrate material comprises a SiC material and a low-temperature AlN buffer layer grown thereon, and second The semiconductor layer is a GaN material layer (having a thickness of about 2 ⁇ m), and the first portion of the first semiconductor layer is an AlN layer (having a thickness of about 3 nm).
  • the length in the connecting direction is 20 ⁇ m.
  • the first dielectric layer is an in-situ Si 3 N 4 layer having a thickness of about 10 nm.
  • the source and drain electrodes are formed by metal deposition and high temperature thermal annealing using Ti/Al/Ni/Au (20/120/50/200 nm). The distance between the source and drain electrodes was 2.5 ⁇ m.
  • the gate electrode is Ni/Au (50/150 nm).

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Abstract

一种III‐V异质结场效应晶体管，其包括衬底材料层（1），第一半导体层（3）、第二半导体层（2），漏电极（4）、源电极（5）、栅电极（8），第一介质层（6）、第二介质层（7）等；其中第一半导体层（3）具有比第二半导体层（2）更大的禁带宽度，第二半导体层（2）和第一半导体层（3）结合在一起构成异质结构。第一半导体层（3）的厚度不大于在异质沟道中形成二维电子气2DEG的临界厚度，使异质沟道中天然的二维电子气2DEG被耗尽。该III‐V异质结场效应晶体管具有结构简洁，制备工艺简单，性能稳定，可靠性高等优点。

Description

一种新型III-V异质结场效应晶体管 技术领域
本申请涉及半导体器件技术领域，尤其涉及一种新型III-V异质结场效应晶体管。
背景技术
某些III族和V族元素构成的二元或者三元化合物(甚至多元化合物)具有自发极化和压电极化效应，当它们结合在一起构成异质结时(如AlGaN/GaN)，会在异质结的界面处形成高浓度的二维电子气(2DEG)，以异质结界面处的2DEG为导电机构的器件称为异质结场效应管(HFET)，也可以称为高电子迁移率晶体管(HEMT)。
HFET器件具有高电子迁移率、器件工作频率高以及高效率的特点。在微波功率发射极传输以及电力电子领域具有非常重要的应用前景。但是，迄今为止，HFET器件存在一个天然的缺憾，以AlGaN/GaN HFET为例，由于极强的自发极化和压电极化，在无任何外加电压的情况下，异质结界面形成了高浓度的2DEG，HFET器件天然为耗尽型(常开型)。HFET器件的缺陷限制了器件在逻辑电路和电力电子电路中的应用，前者需要常关型或增强型和耗尽型(常开型)的逻辑互补，而后者出于安全性及节能的考虑，更需要的是常关型或增强型器件。参阅图1，所示为现有技术耗尽型III-V HFET器件的剖视图，包含衬底材料层9，第二半导体层10，第一半导体层14，二维电子气11，漏电极12，源电极13，栅介质层15和栅电极16，其中，第二半导体层10和第一半导体层14之间构成异质结构，由于现有技术中第一半导体层14的厚度超过临界厚度，所以在不加任何外加电压的情况下，由于材料体系的压电极化和自发极化，在异质结界面，即第一半导体和第二半导体的界面处，即存在高浓度的二维电子气2DEG。
现有技术为了实现增强型HFET器件，通常有以下几种方式获得：
栅下沟道F离子注入技术：即在栅极下部的势垒层中注入F的负离子，靠负电势将栅下的沟道电子耗尽，实现器件的正向阈值(增强型)。
槽栅技术：用干法刻蚀技术将栅下部分势垒层刻薄，当厚度低于临界厚度时，栅下的2DEG将耗尽。只有当栅压高于某一电压时，才会重新诱导出2DEG。实现了增强型器件。
利用P-AlGaN层的器件，这种器件是在栅下部位增加了一层p-AlGaN层，由于能带的均衡作用，使沟道的2DEG耗尽。
以上几种技术存在不同的劣势，其中F离子注入技术在可靠性及获得较大的阈值方面存在问题，槽栅技术在工艺控制方面存在较大难度，P-AlGaN技术存在材料生长困难、器件开关频率低等缺点。
故，针对目前现有技术中存在的上述缺陷，实有必要进行研究，以提供一种方案，解决现有技术中存在的缺陷。
发明内容
有鉴于此，本申请的主要目的在于提供一种新型III-V异质结场效应晶体管，以解决上述问题。本申请实施例提供了一种新型III-V异质结场效应晶体管，其包括衬底材料层、第二半导体层、第一半导体层、漏电极、源电极、第一介质层，第二介质层和栅电极，其中，
在所述衬底材料层上形成所述第二半导体层，在所述第二半导体层上构造出漏电极和源电极，所述漏电极和源电极之间通过第一半导体层相连且与第一半导体层欧姆接触从而形成沟道；所述第一半导体层比所述第二半导体层具有更大的禁带宽度；
所述第二半导体层和所述第一半导体层结合在一起构成异质结构；所述第一半导体层的厚度不大于在异质结构上形成二维电子气2DEG的临界厚度，使所述异质结构中天然的二维电子气2DEG被耗尽；
所述第一半导体层表面还设有第一介质层，所述第一介质层上设有所述栅电极，所述栅电极覆盖整个沟道长度且所述栅电极的两个边缘延伸分别超过所述漏电极和源电极靠近沟道一侧的边缘，在所述栅电极与所述漏电极、源电极之间设有所述第二介质层。
本申请实施例提供了一种新型III-V异质结场效应晶体管，其包括衬底材料层、第一半导体层、第二半导体层、介质模板层、漏电极、源电极、第一介质层，第二介质层和栅电极，其中，在所述衬底材料层上形成所述第二半导体层，在所述第二半导体层上构造出漏电极和源电极；所述第二半导体层和第一半导体层本体结合在一起形成异质结沟道，该异质结沟道两端分别连接所述漏电极和源电极；所述第一半导体层本体的厚度不大于在异质结沟道上形成二维电子气2DEG的临界厚度，使所述异质结沟道中天然的二维电子气2DEG被耗尽；
所述第一半导体层包括本体和沿该本体生长形成的n个凸起部分，n大于等于1；
所述介质模板层设置在所述第一半导体层本体上并形成有n个窗口，所述n个窗口生长形成所述n个凸起部分；所述凸起部分使所述第一半导体层超出临界厚度从而在所述凸起部分的投影区域形成二维电子气2DEG，在所述异质结沟道上形成n个间隔设置的二维电子气2DEG区域；
所述第一介质层上设有所述栅电极。
在一些较为具体的实施方案中，一种新型III-V异质结场效应晶体管为常关型III-V异质结场效应晶体管，其包括衬底材料层、第二半导体层、介质模板层、漏电极、源电极、第一介质层，第二介质层和栅电极，其中，
在所述衬底材料层上形成所述第二半导体层，在所述第二半导体层上构造出漏电极和源电极；所述第一半导体层包括本体和沿该本体生长形成的n个凸起部分，n≥1；
所述第二半导体层和第一半导体层本体结合在一起形成异质结沟道，该异质结沟道两端分别连接所述漏电极和源电极；所述第一半导体层本体的厚度不大于在异质结沟道上形成二维电子气2DEG的临界厚度，使所述异质结沟道中天然的二维电子气2DEG被耗尽；
所述介质模板层设置在所述第一半导体层本体上并等间隔形成n个窗口，所述第一半导体层本体沿所述n个窗口生长形成所述n个凸起部分；所述凸起部分使所述第一半导体层超出临界厚度从而在所述凸起部分的投影区域形成二维电子气2DEG，在所述异质结沟道上形成n个等间隔的二维电子气2DEG区域；
所述第一半导体层表面还设有第一介质层，所述第一介质层上设有所述栅电极，所述栅电极覆盖整个沟道长度且所述栅电极的两个边缘延伸分别超过所述漏电极和源电极靠近沟道一侧的边缘，在所述栅电极与所述漏电极、源电极之间设有所述第二介质层。
在一些较为具体的实施方案中，所述介质模板层中至少于两个相邻窗口之间分布有一个介质墙，所述介质墙仅分布于栅电极投影所能覆盖的区域，介质墙的数目为n，n大于等于1，且至少有1个介质墙在栅宽方向上的尺度大于等于栅宽；所述第一半导体层本体沿介质墙的外侧生长形成凸起部分；所述凸起部分使所述第一半导体层超出临界厚度从而在所述凸起部分的投影区域形成二维电子气2DEG，在所述异质结沟道上形成至少2个不连续的二维电子气2DEG区域，也即源电极和漏电极边缘连接的部分；
所述第一半导体上设有所述栅电极，所述栅电极仅覆盖整个异质结沟道中二维电子气间断的部分。
相对于现有技术，本申请提供的新型III-V异质结场效应晶体管具有结构简洁，制备工艺简单，性能稳定，可靠性高等优点。
附图说明
图1是现有技术常规增强型III-V HFET器件的剖面示意图。
图2是本申请新型增强型III-V异质结场效应晶体管的剖面示意图。
图3是本申请新型增强型III-V异质结场效应晶体管的俯视图。
图4是本申请新型常关型III-V异质结场效应晶体管的剖面示意图。
图5是本申请新型常关型III-V异质结场效应晶体管，n＝3、m＝1时，第一半导体和第二半导体部分以及介质模板部分的左视图。
图6是本申请新型常关型III-V异质结场效应晶体管，n＝3、m＝1时，第一半导体和第二半导体部分以及介质模板部分的主视图。
图7是本申请新型常关型III-V异质结场效应晶体管，n＝3、m＝1时，第一半导体和第二半导体部分以及介质模板部分的俯视图。
图8是本申请具有复合势垒层结构的常关型III-V异质结场效应晶体管的剖面示意图。
图9是本申请具有复合势垒层结构的常关型III-V异质结场效应晶体管，n＝3，m＝2时，第一半导体和第二半导体部分以及介质墙部分的主视图。
图10是本申请具有复合势垒层结构的常关型III-V异质结场效应晶体管，n＝3，m＝2时，第一半导体和第二半导体部分以及介质墙部分的左视图。
图11是本申请具有复合势垒层结构的常关型III-V异质结场效应晶体管，n＝3，m＝2时，第一半导体和第二半导体部分以及介质墙部分的俯视图。
具体实施方式
本案发明人对现有技术中HFET器件的结构进行了持续而深入的研究，本案发明人发现，常规器件的势垒层，即第一半导体层的厚度超过临界厚度，所以在不加任何外加电压的情况下，由于材料体系的压电极化和自发极化，在异质结界面，即第一半导体和第二半导体的界面处，即存在高浓度的二维电子气2DEG。要想获得增强型器件，必须采用槽栅、F离子注入掺杂等特殊工艺。这些工艺存在难以精确控制和额外延长工艺周期的缺点，另外，槽栅结构由于工艺过程中要采用刻蚀工艺，对器件沟道存在损伤，因此，对于器件的性能有损伤，另外，在器件的可靠性方面也存在一定隐患。F注入工艺很难进行精确的控制，并且在可靠性方面存在隐患。
鉴于现有HFET器件存在的前述缺陷，本案发明人经长期研究和大量实践，得以提出本申请的技术方案，如下将予以详细解释说明。
本申请实施例提供的一种新型III-V异质结场效应晶体管为增强型III-V异质结场效应晶体管，其包括衬底材料层、第二半导体层、第一半导体层、漏电极、源电极、第一介质层，第二介质层和栅电极，其中，
在所述衬底材料层上形成所述第二半导体层，在所述第二半导体层上构造出漏电极和源电极，所述漏电极和源电极之间通过第一半导体层相连且与第一半导体层欧姆接触从而形成沟道；所述第一半导体层比所述第二半导体层具有更大的禁带宽度；
所述第二半导体层和所述第一半导体层结合在一起构成异质结构；所述第一半导体层的厚度不大于在异质结构上形成二维电子气2DEG的临界厚度，使所述异质结构中天然的二维电子气2DEG被耗尽；
所述第一半导体层表面还设有第一介质层，所述第一介质层上设有所述栅电极，所述栅电极覆盖整个沟道长度且所述栅电极的两个边缘延伸分别超过所述漏电极和源电极靠近沟道一侧的边缘，在所述栅电极与所述漏电极、源电极之间设有所述第二介质层。
优选地，所述第二介质层仅位于所述栅电极与所述漏电极和源电极的交迭的边缘部分。
优选地，所述第一半导体层与第二半导体层之间还设有用以提高异质结界面的二维电子气的迁移率的插入层。
优选的，所述插入层的厚度可以约为1nm。
优选地，所述插入层包括AlN层。
优选地，所述第一半导体层包括AlGaN层或AlN层。
优选的，所述第二半导体层包括GaN层。
例如，在一些实施方案中，所述第一半导体层为AlGaN层，其厚度小于或等于5nm，优选为1～5nm；所述第二半导体层为GaN层，其厚度可以是任意合适的数值，例如可以为2μm。例如，在一些具体实施案例中，所述第一半导体层为AlN层，其厚度为5nm；所述第二半导体层为GaN层，其厚度为2μm。
优选地，所述第一介质层为生长异质结构材料时原位生长的Si3N4，其厚度为5～25nm。
优选地，所述的栅电极和第一介质层之间还设有第三介质层，所述第三介质层用于进一步降低器件的栅泄漏电流。
优选地，所述第二介质层包括SiO2层。在一些具体实施案例中，所述第二介质层的厚度可以为100nm。
优选地，所述第二介质层朝向沟道一侧边缘分别超出所述漏电极、源电极的长度均为0～2μm，例如可以优选为0.5μm。
优选地，所述漏电极与所述源电极之间的距离可以为约2.5μm。
本申请前述实施例提供的新型增强型III-V异质结场效应晶体管利用薄势垒层方案获得耗尽的沟道，并采用MIS栅结构，采用高栅电压重新诱导出2DEG，从而实现性能稳定的增强型器件。
在前述实施例的一些更为具体的实施方案中，一种新型增强型III-V异质结场效应晶体管的结构可以参见图2和图3所示，其中图2为器件的剖面图，图3为其俯视图。
其中，所述新型增强型III-V异质结场效应晶体管包括衬底材料层1、第二半导体层2、第一半导体层3、漏电极4、源电极5、第一介质层6，第二介质层7和栅电极8，其中，
在衬底材料层1上形成第二半导体层2，在第二半导体层2上构造出漏电极4和源电极5，漏电极4和源电极5之间通过第一半导体层3相连且与第一半导体层3欧姆接触从而形成沟道；第一半导体层3比第二半导体层2具有更大的禁带宽度；
第二半导体层2和第一半导体层3结合在一起构成异质结构；第一半导体层3的厚度不大于在异质结构上形成二维电子气2DEG的临界厚度，使第一半导体层3异质结构中天然的二维电子气2DEG被耗尽；通过薄结构的第一半导体层的设计，由于第一半导体层的厚度低于临界厚度，消除了在异质结构上天然存在高浓度的二维电子气2DEG，因此，在无外加栅压的情况下，第一半导体层和第二半导体层的异质界面不存在2DEG，只有当外加栅压超过某一正阈值电压，才能在沟道中诱导出高浓度的2DEG，从而实现了增强型形态；从而大大简化了形成增强型器件的工艺。
第一半导体层3表面还设有第一介质层6，第一介质层6上设有栅电极8，栅电极8覆盖整个沟道长度且栅电极8的两个边缘延伸分别超过漏电极4和源电极5靠近沟道一侧的边缘，在栅电极8与漏电极4、源电极5之间设有第二介质层7。由于采用栅电极完全覆盖的沟道结构，实现了栅电压对于沟道2DEG的完全控制，从而实现无电流崩塌效应的器件。
在一种优选实施方式中，第二介质层7仅位于栅电极8与漏电极4和源电极5的交迭的边缘部分。第二介质层7的目的是为了阻止栅电极8与漏电极4和源电极5的电连通，但第二介质层7又会对栅电容造成影响，进而影响栅控能力和放大能力。该结构使第二介质层7仅仅覆盖栅电极8与漏电极4和源电极5的交迭的边缘部分，与第二介质层完全覆盖第一介质层相比，在实现良好电隔离的前提下，能够保证更大的栅电容，具有更大的器件跨导，使器件具有更大的栅控能力和放大能力。优选地，第二介质层的厚度应尽量小。这样，在栅的正投影下方，第二介质层非常少，使栅电容的减少降到最低。
同时，所述新型增强型III-V异质结场效应晶体管的实现工艺与现有技术HFET器件的工艺基本相同，无需额外增加器件的工艺复杂程度。本申请的器件可通过如下主要工艺步骤实现：
(1)基片材料生长：在合适衬底材料上(如Si衬底)，按照材料生长规律生长相应缓冲层、第二半导体层、选择性生长插入层、第一半导体层、原位Si3N4层。
(2)基片材料清洗：采用合适的清洗方案，获得洁净的材料表面。
(3)源漏电极构造。
(4)第二介质层生长。
(5)第二栅介质层选区刻蚀。
(6)栅电极构造。
(7)钝化及封装。
在本申请的前述实施例中，因采用上述技术方案，并没有额外增加器件的工艺复杂程度，阈值电压可通过设置第一半导体层厚度和第一介质层厚度等参数设定，实现了器件工艺的可重复性，有利于器件的工业生产。
本申请实施例提供的一种新型III-V异质结场效应晶体管为常关型III-V异质结场效应晶体管，其包括衬底材料层、第一半导体层、第二半导体层、介质模板层、漏电极、源电极、第一介质层，第二介质层和栅电极，其中，
在所述衬底材料层上形成所述第二半导体层，在所述第二半导体层上构造出漏电极和源电极；所述第一半导体层包括本体和沿该本体生长形成的n个凸起部分，n≥1；
所述第二半导体层和第一半导体层本体结合在一起形成异质结沟道，该异质结沟道两端分别连接所述漏电极和源电极；所述第一半导体层本体的厚度不大于在异质结沟道上形成二维电子气2DEG的临界厚度，使所述异质结沟道中天然的二维电子气2DEG被耗尽；
所述介质模板层设置在所述第一半导体层本体上并等间隔形成n个窗口，所述第一半导体层本体沿所述n个窗口生长形成所述n个凸起部分；所述凸起部分使所述第一半导体层超出临界厚度从而在所述凸起部分的投影区域形成二维电子气2DEG，在所述异质结沟道上形成n个等间隔的二维电子气2DEG区域；
所述第一半导体层表面还设有第一介质层，所述第一介质层上设有所述栅电极，所述栅电极覆盖整个沟道长度且所述栅电极的两个边缘延伸分别超过所述漏电极和源电极靠近沟道一侧的边缘，在所述栅电极与所述漏电极、源电极之间设有所述第二介质层。
优选地，所述凸起部分为连续分布或者沿其生长方向分为m份，m≥1。
优选地，所述第二介质层仅位于所述栅电极与所述漏电极和源电极的交迭的边缘部分。
优选地，所述第一半导体层与第二半导体层之间还设有用以提高异质结界面的二维电子气的迁移率的插入层。
优选地，所述插入层包括AlN层。
优选地，所述第一半导体层包括AlGaN层或AlN层；所述第二半导体层为GaN层。
优选地，所述第一介质层为生长异质结构材料时原位生长的Si3N4，其厚度为5～25nm。
优选地，所述介质模板层包括SiO2层，例如LPCVD生长的SiO2层。
优选地，所述第二介质层包括SiO2层。
优选地，所述第二介质层朝向沟道一侧边缘分别超出所述漏电极、源电极的长度均为0.5μm。本申请前述实施例提供的新型常关型III-V异质结场效应晶体管利用特殊设计的势垒层获得不连续的沟道，采用高栅电压重新诱导出2DEG，从而实现性能稳定的常关型器件，并可以根据器件的性能需求，采取灵活多样的设计方案。
在前述实施例的一些更为具体的实施方案中，一种新型常关型III-V异质结场效应晶体管的结构可以参见图4、图5、图6和图7所示，其中图4为器件的剖面示意图，图5-至图6为n＝2、m＝1时第一半导体和第二半导体以及介质模板部分的三视图，其中，图5为左视图，图6为主视图，图7为俯视图。本申请新型常关型III-V异质结场效应晶体管包括衬底材料层1，第二半导体层2，第一半导体层本体3，第一半导体层凸起部分9，二维电子气10，介质模板11，第一介质层6，第二介质层7，栅电极8，源电极4，漏电极5。
其中，在衬底材料层1上形成第二半导体层2，在第二半导体层2上构造出漏电极5和源电极4，且在第二半导体层2上形成第一半导体层本体3，第一半导体层本体3与第二半导体层2结合在一起构成异质结构；漏电极5和源电极4之间通过第一半导体层本体3与第二半导体2之间形成的沟道相连；第一半导体层比第二半导体层具有更大的禁带宽度；第一半导体层本体3的厚度不大于在异质结构上形成二维电子气2DEG的临界厚度。
在第一半导体层本体3之上构造介质模板层6，并使介质模板层6上并等间隔形成n个窗口，第一半导体层本体3沿该n个窗口生长形成所述n个凸起部分4；凸起部分使所述第一半导体层超出临界厚度从而在所述凸起部分的投影区域形成二维电子气2DEG，在所述异质结沟道上形成n个等间隔的二维电子气2DEG区域。
如果仅存在第一半导体层本体3，异质结构中不足以产生二维电子气2DEG；由于在存在第一半导体凸起部分4的地方，第一半导体层本体3和第一半导体凸起部分4的总厚度超过能够产生二维电子气2DEG的临界厚度，所以在存在第一半导体凸起部分4的下方的异质结界面处，存在二维电子气2DEG。进而在异质结界面处，分布有不连续的二维电子气2DEG。由于二维电子气2DEG的不连续，在无栅电压时，导电沟道没有形成HFET器件为常关型。只有当栅电压大于阈值电压时，异质结界面处的二维电子气2DEG才会连续，形成导电沟道。
采用上述技术方案，本器件的栅电极实现了对源、漏之间沟道的全覆盖，所以当器件工作时，栅电压可以完全控制沟道，实现沟道的瞬时开关，所以，可以最大程度避免“电流崩塌”效应。另外，虽然本器件的栅电极覆盖在源、漏电极之间，由于第一半导体有凸起部分的二维电子气是常存在的，所以器件的等效栅长仅为第一半导体上无凸起部分的长度，所以，该器件获得较高的截止频率。同时，由于器件的击穿电压与源、漏电极之间的长度正相关，所以，该器件可以同时获得较高的击穿电压。
第一半导体层表面还设有第一介质层6，第一介质层6上设有栅电极8，栅电极8覆盖整个沟道长度且栅电极8的两个边缘延伸分别超过漏电极5和源电极4靠近沟道一侧的边缘，在栅电极8与漏电极5、源电极4之间设有第二介质层7。由于采用栅电极完全覆盖的沟道结构，实现了栅电压对于沟道2DEG的完全控制，从而实现无电流崩塌效应的器件。
在一种优选实施方式中，在垂直于源、漏电极相连的方向上，第一半导体层凸起部分9可以是连续分布的，也可以被分成m份。所述介质层模板6在源、漏电极之间的方向上呈现不连续。
在一种优选实施方式中，第二介质层7仅位于栅电极8与漏电极5和源电极4的交迭的边缘部分。第二介质层7的目的是为了阻止栅电极8与漏电极5和源电极4的电连通，但第二介质层7又会对栅电容造成影响，进而影响栅控能力和放大能力。该结构使第二介质层7仅仅覆盖栅电极8与漏电极5和源电极4的交迭的边缘部分，与第二介质层完全覆盖第一介质层相比，在实现良好电隔离的前提下，能够保证更大的栅电容，具有更大的器件跨导，使器件具有更大的栅控能力和放大能力。优选地，第二介质层的厚度应尽量小。这样，在栅的正投影下方，第二介质层非常少，使栅电容的减少降到最低。
同时，本申请新型增强型III-V异质结场效应晶体管的实现工艺与现有技术HFET器件的工艺基本相同，无需额外增加器件的工艺复杂程度。本申请的器件可通过如下主要工艺步骤实现：
(1)基片材料生长：在合适衬底材料上(如Si衬底)，按照材料生长规律生长相应缓冲层、第二半导体层、选择性生长插入层、第一半导体层本体3、介质模板层6。
(2)对介质模板层进行光刻及刻蚀，形成第一半导体层凸起部分9的生长窗口。
(3)生长第一半导体层凸起部分9。
(4)源漏电极构造。
(5)第一介质层生长。
(6)第二介质层生长及选区刻蚀。
(7)栅电极构造。
(8)钝化及封装。
在本申请的前述实施例中，通过采用上述技术方案可实现常关型器件；并且由于器件的沟道材料采用的是生长而没有如槽栅器件中使用的刻蚀工艺，所以不会对异质结界面形成破坏，从而有利于提高器件性能。
本申请实施例提供的一种新型III-V异质结场效应晶体管为具有复合势垒层结构的常关型III-V异质结场效应晶体管，其包括衬底材料层、第二半导体层、介质墙(亦可认为是另一种形式的介质模板层)、漏电极、源电极和栅电极，其中，
在所述衬底材料层上形成所述第二半导体层，在所述第二半导体层上构造出漏电极和源电极；所述第二半导体层和第一半导体层本体结合在一起形成异质结沟道，该异质结沟道两端分别连接所述漏电极和源电极；所述第一半导体层本体的厚度不大于在异质结沟道上形成二维电子气2DEG的临界厚度，使所述异质结沟道中天然的二维电子气2DEG被耗尽；
在所述第一半导体层本体上设置所述介质墙，介质墙仅分布于栅电极投影所能覆盖的区域，介质墙的数目为n，n大于等于1，且至少有1个介质墙在栅宽方向上的尺度大于等于栅宽；所述第一半导体层本体沿介质墙的外侧生长形成凸起部分；所述凸起部分使所述第一半导体层超出临界厚度从而在所述凸起部分的投影区域形成二维电子气2DEG，在所述异质结沟道上形成至少2个不连续的二维电子气2DEG区域，也即源电极和漏电极边缘连接的部分；
所述第一半导体上设有所述栅电极，所述栅电极仅覆盖整个异质结沟道中二维电子气间断的部分。
在前述实施例的一些实施方案中，所述栅电极和第一半导体之间还设有第一介质层。
在前述实施例的一些实施方案中，所述凸起部分在栅电极投影覆盖之内的部分为连续分布或者沿其生长方向分为m份，m大于等于1。
在前述实施例的一些实施方案中，所述第一半导体层与第二半导体层之间还设有用以提高异质结界面的二维电子气2DEG的迁移率的插入层。
所述插入层包括AlN层，但不限于此。
在前述实施例的一些实施方案中，所述第一半导体层可以包括但不限于AlGaN层、AlN层等。
在前述实施例的一些实施方案中，所述第二半导体层可以包括但不限于GaN层。
在前述实施例的一些实施方案中，所述第一介质层包括生长异质结构材料时原位生长的Si3N4。优选的，所述第一介质层的厚度为5～25nm。
在前述实施例的一些实施方案中，所述介质墙通过光刻或刻蚀工艺形成n个窗口。
请参阅图8、图9、图10和图11示出了前述这些实施例的一个具体实施案例，其涉及一种具有复合势垒层结构的常关型III-V异质结场效应晶体管(如下简称“器件”)。参阅图8为该器件的剖面示意图，图9-图11为n＝5,m＝2时第一半导体和第二半导体以及介质墙部分的三视图，其中，图9为主视图，图10为左视图，图11为俯视图。进一步的，该器件包括衬底材料层1，第二半导体层2，第一半导体层本体3，第一半导体层凸起部分9，二维电子气10，介质墙11’，第一介质层6，栅电极8，源电极4，漏电极5。
其中，在衬底材料层1上形成第二半导体层2，在第二半导体层2上构造出漏电极5和源电极4，且在第二半导体层2上形成第一半导体层本体3，第一半导体层本体3与第二半导体层2结合在一起构成异质结构；漏电极5和源电极4之间通过第一半导体层本体3与第二半导体2之间形成的沟道相连；第一半导体层比第二半导体层具有更大的禁带宽度；第一半导体层本体3的厚度不大于在异质结构上形成二维电子气2DEG的临界厚度。
在第一半导体层本体3之上构造介质层，并通过光刻、刻蚀工艺构造出介质墙11’，第一半导体层本体3沿介质墙的外侧生长形成所述凸起部分9；凸起部分使所述第一半导体层超出临界厚度从而在所述凸起部分的投影区域形成二维电子气2DEG，在所述异质结沟道上形成间隔分布的二维电子气2DEG区域。
如果仅存在第一半导体层本体3，异质结构中不足以产生二维电子气2DEG；由于在存在第一 半导体凸起部分9的地方，第一半导体层本体3和第一半导体凸起部分9的总厚度超过能够产生二维电子气2DEG的临界厚度，所以在存在第一半导体凸起部分9的下方的异质结界面处，存在二维电子气2DEG。进而在异质结界面处，分布有不连续的二维电子气2DEG。由于二维电子气2DEG的不连续，在无栅电压时，导电沟道没有形成，HFET器件为常关型。只有当栅电压大于阈值电压时，异质结界面处的二维电子气2DEG才会连续，形成导电沟道。本申请的前述实施例中，介质墙仅分布在栅电极投影覆盖的区域，也即漏电极和源电极相接的部分均生长形成第一半导体的凸起部分，使异质结沟道靠近源电极和漏电极的部分形成二维电子气2DEG，从而栅电极仅覆盖整个异质结沟道中二维电子气间断的部分，就能控制异质结沟道的导通和截止。因而，本申请前述实施例的器件中，栅电极和漏电极、源电极之间无需介质层隔离，大大简化了生产工艺，同时大大提高了晶体管的击穿电压。
在一种优选实施方式中，第一半导体层表面还设有第一介质层6，第一介质层6上设有栅电极8，栅电极8覆盖整个复合势垒层中二维电子气间断的部分，能保证器件在施加一定栅电压时源漏电极经二维电子气2DEG导通。
在一种优选实施方式中，在垂直于源、漏电极相连的方向上，第一半导体层凸起部分9可以是连续分布的，也可以被分成m份。给器件的设计带来极大的灵活性。同时，本申请新型增强型III-V异质结场效应晶体管的实现工艺与现有技术HFET器件的工艺基本相同，无需额外增加器件的工艺复杂程度。本申请的器件可通过如下主要工艺步骤实现：
(1)基片材料生长：在合适衬底材料上(如Si衬底)，按照材料生长规律生长相应缓冲层、第二半导体层、选择性生长插入层、第一半导体层本体3、构造介质墙11’所需要的介质层。
(2)对介质层进行光刻及刻蚀，形成介质墙11’。
(3)生长第一半导体层凸起部分9。
(4)源、漏电极构造。
(5)第一介质层生长。
(6)栅电极构造。
(7)钝化及封装。
采用上述技术方案，可实现常关型器件；并且，由于器件的沟道材料采用的是生长而没有如槽栅器件中使用的刻蚀工艺，所以不会对异质结界面形成破坏，从而有利于提高器件性能。本申请前述实施例提供的具有复合势垒层结构的常关型III-V异质结场效应晶体管，利用特殊设计的势垒层获得不连续的沟道，采用高栅电压重新诱导出2DEG，从而实现性能稳定的常关型器件。并可以根据器件的性能需求，采取灵活多样的设计方案。同时，由于栅电极仅覆盖整个异质结沟道中二维电子气间断的部分，大大简化了生产工艺，栅电极和漏电极、源电极之间无需介质层隔离，大大提高了晶体管的击穿电压。
以下将结合若干较佳实施例及相应附图对本申请的技术方案作进一步的描述，但本申请并不限于这些实施例。
实施例1：本实施例新型增强型III-V异质结场效应晶体管包括以下几部分：衬底材料包含Si材料和在其上生长的低温AlN缓冲层，第二半导体层为GaN材料层(厚度约为2μm)，第一半导体层为AlGaN层(厚度约为1～5nm)，在第一和第二半导体层之间设有AlN插入层(厚度约为1nm)，用于提高2DEG的电学特性。第一介质层为原位生长Si3N4层，厚度约为5～25nm。源、漏电极都采用Ti/Al/Ni/Au(20/120/50/200nm)经金属淀积与高温热退火形成。源漏电极之间的距离为2.5μm。第二介质层为SiO2层，其厚度约为100nm。第二介质层朝向沟道中心一层边缘超出源、漏电极的长度皆为0.5μm。栅电极采用Ni/Au(50/150nm)。该器件的制备过程如下：首先在包含Si的衬底材料上生长低温AlN缓冲层，然后生长第二半导体层-GaN层，然后生长第一半导体AlGaN层，然后生长原位Si3N4层作为第一介质层。然后刻蚀源漏电极处的第一介质层，并制备欧姆接触。然后再生长第二介质层，并经过光刻、刻蚀，仅留下源、漏边缘处的第二介质层，最后再制备栅电极。
实施例2：本实施例新型增强型III-V异质结场效应晶体管包括以下几部分：衬底材料包含SiC材料和在其上生长的低温AlN缓冲层，第二半导体层为GaN材料层(厚度约为2μm)，第一半导体层为AlN层(厚度约为5nm)，第一介质层为原位生长Si3N4层，厚度约为5～25nm。源、漏电极都采用Ti/Al/Ni/Au(20/120/50/200nm)经金属淀积与高温热退火形成。源漏电极之间的距离为2.5μm。第二介质层为SiO2层，其厚度约为100nm。第二介质层朝向沟道中心一层边缘超出源、漏电极的长度皆为0.5μm。栅电极采用Ni/Au(50/150nm)。
实施例3：本实施例新型常关型III-V异质结场效应晶体管包括以下几部分：衬底材料包含Si材料和在其上生长的低温AlN缓冲层，第二半导体层为GaN材料层(厚度约为2μm)，第一半导体层的第一部分为AlGaN层(厚度约为3nm)，在第一半导体层和第二半导体层第一部分之间设有AlN插入层(厚度约为1nm)，用于提高2DEG的电学特性。介质模板层为LPCVD(低压力化学气相沉积法)生长的SiO2层，其上取窗口的数值n＝2,m＝1,窗口沿源、漏电极相连方向上的长度为0.5μm，沿垂直于源、漏电极相连方向上的长度为100μm。第一介质层为原位生长Si3N4层，厚度约为10nm，第二介质层为hfO2，厚度为100nm。源、漏电极都采用Ti/Al/Ni/Au(20/120/50/200nm)经金属淀积与高温热退火形成。源漏电极之间的距离为2.5μm。第二介质层朝向沟道中心一层边缘超出源、漏电极的长度皆为0.5μm。栅电极采用Ni/Au(50/150nm)。该器件的制备过程如下：首先在包含Si的衬底材料上生长低温AlN缓冲层，然后生长第二半导体层-GaN层，然后生长第一半导体AlGaN层的本体部分，然后生长介质模板层-LPCVD(低压力化学气相沉积法)生长的SiO2层,然后进行光刻及刻蚀工艺，留下介质墙，然后露出第二次外延的窗口，然后将材料重新放入材料生长设备，在窗口中重新生长第一半导体的凸起部分。然后生长原位Si3N4层作为第一介质层。然后刻蚀源漏电极处的第一介质层，并制备欧姆接触。然后再生长第二介质层hfO2，并经过光刻、刻蚀，仅留下源、漏边缘处的第二介质层，最后再制备栅电极。
实施例4：本实施例新型常关型III-V异质结场效应晶体管包括以下几部分：衬底材料包含SiC材料和在其上生长的低温AlN缓冲层，第二半导体层为GaN材料层(厚度约为2μm)，第一半导体层的第一部分为AlN层(厚度约为3nm)。介质模板层为LPCVD生长的SiO2层，其上取窗口的数值n＝2,m＝3,窗口沿源、漏电极相连方向上的长度为0.5μm，沿垂直于源、漏电极相连方向上的长度为20μm。第一介质层为原位生长Si3N4层，厚度约为10nm，第二介质层为hfO2，厚度为100nm。源、漏电极都采用Ti/Al/Ni/Au(20/120/50/200nm)经金属淀积与高温热退火形成。源漏电极之间的距离为2.5μm。第二介质层朝向沟道中心一层边缘超出源、漏电极的长度皆为0.5μm。栅电极采用Ni/Au(50/150nm)。
实施例5：本实施例具有复合势垒层结构的常关型III-V异质结场效应晶体管包括以下几部分：衬底材料包含Si材料和在其上生长的低温AlN缓冲层，第二半导体层为GaN材料层(厚度约为2μm)，第一半导体层的本体部分为AlGaN层(厚度约为3nm)，在第二半导体层和第一半导体层的本体部分之间设有AlN插入层(厚度约为1nm)，用于提高2DEG的电学特性。介质墙为采用LPCVD(低压力化学气相沉积法)生长的SiO2层，取介质墙的数目n＝2,凸起部分的数目m＝1,窗口沿源、漏电极相连方向上的长度为0.5μm，沿垂直于源、漏电极相连方向上的长度为100μm。第一介质层为原位生长Si3N4层，厚度约为10nm。源、漏电极都采用Ti/Al/Ni/Au(20/120/50/200nm)经金属淀积与高温热退火形成。源漏电极之间的距离为2.5μm。栅电极采用Ni/Au(50/150nm)。
实施例6：本实施例具有复合势垒层结构的常关型III-V异质结场效应晶体管包括以下几部分：衬底材料包含SiC材料和在其上生长的低温AlN缓冲层，第二半导体层为GaN材料层(厚度约为2μm)，第一半导体层的第一部分为AlN层(厚度约为3nm)。介质墙为LPCVD生长的SiO2层，取介质墙的数目n＝1,凸起部分的数目m＝1,窗口沿源、漏电极相连方向上的长度为0.5μm，沿垂直于源、漏电极相连方向上的长度为20μm。第一介质层为原位生长Si3N4层，厚度约为10nm。源、漏电极都采用Ti/Al/Ni/Au(20/120/50/200nm)经金属淀积与高温热退火 形成。源漏电极之间的距离为2.5μm。栅电极采用Ni/Au(50/150nm)。
以上实施例的说明只是用于帮助理解本申请的方法及其核心思想。应当指出，对于本技术领域的普通技术人员来说，在不脱离本申请原理的前提下，还可以对本申请进行若干改进和修饰，这些改进和修饰也落入本申请权利要求的保护范围内。对这些实施例的多种修改对本领域的专业技术人员来说是显而易见的，本申请中所定义的一般原理可以在不脱离本申请的精神或范围的情况下在其它实施例中实现。因此，本申请将不会被限制于本申请所示的这些实施例，而是要符合与本申请所公开的原理和新颖特点相一致的最宽的范围。

Claims (20)

  1. 一种新型III-V异质结场效应晶体管，其特征在于包括衬底材料层、第二半导体层、第一半导体层、漏电极、源电极、第一介质层，第二介质层和栅电极，其中，
    在所述衬底材料层上形成所述第二半导体层，所述第二半导体层和所述第一半导体层结合在一起构成异质结构，所述第一半导体层比所述第二半导体层具有更大的禁带宽度，在所述第二半导体层上构造出漏电极和源电极，所述漏电极和源电极之间通过第一半导体层相连且与第一半导体层欧姆接触从而形成沟道；
    所述第一半导体层的厚度不大于在异质结构上形成二维电子气2DEG的临界厚度，使所述异质结构中天然的二维电子气2DEG被耗尽；
    所述第一半导体层表面还设有第一介质层，所述第一介质层上设有所述栅电极，所述栅电极覆盖整个沟道长度且所述栅电极的两个边缘延伸分别超过所述漏电极和源电极靠近沟道一侧的边缘，在所述栅电极与所述漏电极、源电极之间设有所述第二介质层。
  2. 根据权利要求1所述的新型III-V异质结场效应晶体管，其特征在于：所述第二介质层仅位于所述栅电极与所述漏电极和源电极的交迭的边缘部分。
  3. 根据权利要求1所述的新型III-V异质结场效应晶体管，其特征在于：所述第一半导体层与第二半导体层之间还设有用以提高异质结界面的二维电子气的迁移率的插入层；优选的，所述插入层包括AlN层。
  4. 根据权利要求1所述的新型III-V异质结场效应晶体管，其特征在于：所述第一半导体层包括AlGaN层或AlN层；所述第二半导体层包括GaN层。
  5. 根据权利要求1或4所述的新型III-V异质结场效应晶体管，其特征在于：所述第一半导体层的厚度小于5nm，优选为1～5nm。
  6. 根据权利要求1所述的新型III-V异质结场效应晶体管，其特征在于：所述第一介质层为生长异质结构材料时原位生长的Si3N4，其厚度为5～25nm。
  7. 根据权利要求1所述的新型III-V异质结场效应晶体管，其特征在于：所述的栅电极和第一介质层之间还设有第三介质层。
  8. 根据权利要求1所述的新型III-V异质结场效应晶体管，其特征在于：所述第二介质层包括SiO2层。
  9. 根据权利要求1所述的新型III-V异质结场效应晶体管，其特征在于：所述第二介质层朝向沟道一侧边缘分别超出所述漏电极、源电极的长度均为0～2μm。
  10. 一种新型III-V异质结场效应晶体管，其特征在于包括衬底材料层、第一半导体层、第二半导体层、介质模板层、漏电极、源电极、第一介质层，第二介质层和栅电极，其中，
    在所述衬底材料层上形成所述第二半导体层，在所述第二半导体层上构造出漏电极和源电极；所述第二半导体层和第一半导体层本体结合在一起形成异质结沟道，该异质结沟道两端分别连接所述漏电极和源电极；所述第一半导体层本体的厚度不大于在异质结沟道上形成二维电子气2DEG的临界厚度，使所述异质结沟道中天然的二维电子气2DEG被耗尽；
    所述第一半导体层包括本体和沿该本体生长形成的n个凸起部分，n大于等于1；
    所述介质模板层设置在所述第一半导体层本体上并形成有n个窗口，所述n个窗口生长形成所述n个凸起部分；所述凸起部分使所述第一半导体层超出临界厚度从而在所述凸起部分的投影区域形成二维电子气2DEG，在所述异质结沟道上形成n个间隔设置的二维电子气2DEG区域；
    所述第一介质层上设有所述栅电极。
  11. 根据权利要求10所述的新型III-V异质结场效应晶体管，其特征在于：所述栅电极覆盖整个沟道长度且所述栅电极的两个边缘延伸分别超过所述漏电极和源电极靠近沟道一侧的边 缘，在所述栅电极与所述漏电极、源电极之间设有所述第二介质层。
  12. 根据权利要求10所述的新型III-V异质结场效应晶体管，其特征在于：所述介质模板层设置在所述第一半导体层本体上并等间隔形成n个窗口，在所述异质结沟道上形成n个等间隔的二维电子气2DEG区域。
  13. 根据权利要求10所述的新型III-V异质结场效应晶体管，其特征在于：在栅长方向上，所述介质模板层中至少于两个相邻窗口之间分布有一个介质墙，其中至少有1个介质墙在栅宽方向上的尺度大于等于栅宽；所述第一半导体层本体沿介质墙的外侧生长形成凸起部分；所述凸起部分使所述第一半导体层超出临界厚度从而在所述凸起部分的投影区域形成二维电子气2DEG，在所述异质结沟道上形成至少2个不连续的二维电子气2DEG区域，也即源电极和漏电极边缘连接的部分，所述栅电极仅覆盖整个异质结沟道中二维电子气间断的部分。
  14. 根据权利要求10所述的新型III-V异质结场效应晶体管，其特征在于：所述凸起部分为连续分布或者沿其生长方向分为m份，m大于等于1。
  15. 根据权利要求10所述的新型III-V异质结场效应晶体管，其特征在于：所述第二介质层仅位于所述栅电极与所述漏电极和源电极的交迭的边缘部分。
  16. 根据权利要求10所述的新型III-V异质结场效应晶体管，其特征在于：所述第一半导体层与第二半导体层之间还设有用以提高异质结界面的二维电子气的迁移率的插入层；优选的，所述插入层包括AlN层。
  17. 根据权利要求10所述的新型III-V异质结场效应晶体管，其特征在于：所述第一半导体层包括AlGaN层或AlN层；所述第二半导体层包括GaN层。
  18. 根据权利要求10所述的新型III-V异质结场效应晶体管，其特征在于：所述第一半导体层表面还设有第一介质层，所述第一介质层上设有所述栅电极。
  19. 根据权利要求18所述的新型III-V异质结场效应晶体管，其特征在于：所述第一介质层为生长异质结构材料时原位生长的Si3N4，其厚度为5～25nm。
  20. 根据权利要求10所述的新型III-V异质结场效应晶体管，其特征在于：所述介质模板层或第二介质层包括SiO2层。
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