CN106024880B - 一种图形化栅结构的微波晶体管及其制备方法 - Google Patents

一种图形化栅结构的微波晶体管及其制备方法 Download PDF

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CN106024880B
CN106024880B CN201610520962.9A CN201610520962A CN106024880B CN 106024880 B CN106024880 B CN 106024880B CN 201610520962 A CN201610520962 A CN 201610520962A CN 106024880 B CN106024880 B CN 106024880B
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grid
barrier layer
patterned area
grooves
drain electrode
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CN106024880A (zh
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刘胜厚
叶念慈
黄侯魁
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Integrated Circuit Co Ltd Is Pacified By Xiamen City Three
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Abstract

本发明公开了一种图形化栅结构的微波晶体管，该晶体管在势垒层于源极和漏极之间具有一图形化区域，图形化区域内设置有复数个由势垒层表面沿厚度方向部分下凹形成的凹槽，栅极覆设于图形化区域上，且栅极长度大于该些凹槽于栅极长度方向上的长度以完全覆盖该些凹槽，一方面借由凹槽的设置增强器件的栅控能力，抑制短沟道效应；另一方面栅极下方原始的异质结构得到了保留，避免二维电子气密度下降引起导电能力降低，从而在实现抑制短沟道效应的同时保证了器件的电流输出能力。本发明还公开了上述微波晶体管的制备方法。

Description

一种图形化栅结构的微波晶体管及其制备方法
技术领域
本发明涉及半导体器件，特别是涉及一种图形化栅结构的微波晶体管及其制备方法。
背景技术
高电子迁移率晶体管(HEMT)包括衬底、缓冲层、沟道层、势垒层及设置于势垒层上的源极、漏极和栅极等结构，是利用沟道层和势垒层之间的异质结界面存在的二维电子气层(2-2DEG)，在源极和漏极之间通过改变栅极加压控制2-DEG的电子浓度，从而控制工作状态。HEMT是新一代的晶体管，由于其优异的性能成为高频、高压、高温和大功率应用方面的首选。
目前，基于普通的HEMT结构，微波器件的频率性能的提升主要依赖于减小栅长，现在的技术已经实现了栅长30-50nm的器件。而一般情况下势垒层的厚度在20nm左右。因此，在这个尺度下，面临着器件短沟道效应带来的巨大挑战，这会限制器件的输出功率。为了增强器件的栅控能力、抑制短沟道效应，一是采用凹槽栅工艺，即将栅极区域的势垒层整体减薄，缩短栅极到二维电子气沟道的距离，从而使栅极对二维电子气沟道的控制能力增强。但是随着势垒层厚度的减小，导电沟道中二维电子气的密度也会随着降低，限制器件的最大输出功率。另一个方法是基于沟道阵列的结构设计，即将栅极下方部分区域的势垒层完全去除，并通过将栅金属覆盖在沟道的顶部和两边的侧壁形成环栅结构，实现栅极对导电沟道的三维控制，从而增强了对沟道的调制能力。但由于栅极下方部分导电区域被去除，去除的这部分区域不能参与导电，降低了器件的导电能力，从而影响器件的输出功率。还有一种方法是外延结构的设计，即在沟道下方生长一层不同于势垒层组份的背势垒层，从沟道下方增强对沟道内二维电子气的束缚作用，抑制器件的短沟道效应。但是这对外延工艺提出了非常高的要求，因为不同半导体晶体材料具有不同的生长温度，温度的频繁切换会影响外延材料最后的质量。上述方法均无法较好的解决存在的问题。
发明内容
本发明的目的在于克服现有技术之不足，提供一种图形化栅结构的微波晶体管及其制备方法。
本发明解决其技术问题所采用的技术方案是：一种图形化栅结构的微波晶体管，由下至上包括衬底、缓冲层、沟道层及势垒层，势垒层上设置有源极、漏极及栅极，且栅极位于源极和漏极之间；所述势垒层于源极和漏极之间具有一图形化区域，所述图形化区域内设置有复数个由势垒层表面沿厚度方向部分下凹形成的凹槽；所述栅极覆设于所述图形化区域上，且栅极长度大于该些凹槽于所述栅极长度方向上的长度以完全覆盖该些凹槽。
优选的，该些凹槽占所述栅极覆盖的图形化区域面积的25％～75％。
优选的，该些凹槽是条形结构且等距离间隔平行排列。
优选的，所述栅极于所述复数个凹槽底部的厚度与于所述势垒层表面的厚度相同。
优选的，所述复数个凹槽的侧壁由凹槽开口向底部方向向内倾斜0～60度，所述栅极覆盖所述复数个凹槽的侧壁。
优选的，所述沟道层和势垒层为可形成异质结的半导体材料制成；所述源极、漏极及栅极由金属制成且源极和漏极与势垒层形成欧姆接触，栅极与势垒层形成肖特基接触。
一种上述图形化栅结构的微波晶体管的制备方法包括以下步骤：
(1)于一衬底上依次形成缓冲层、沟道层及势垒层；
(2)于势垒层表面上形成源极和漏极；
(3)于源极和漏极之间定义一图形化区域，蚀刻所述图形化区域的势垒层形成所述复数个凹槽；
(4)于所述图形化区域上形成栅极，且栅极长度大于该些凹槽于所述栅极长度方向上的长度以完全覆盖所述复数个凹槽。
优选的，步骤(2)具体包括以下子步骤：
通过电子束蒸镀的方法于所述势垒层表面的两个区域分别蒸镀上Ti/Al/Ni/Au多金属层，其中所述Ti/Al/Ni/Au的厚度分别是20/150/50/100nm；
于800-950℃下退火20-45秒形成欧姆接触，形成所述源极和漏极。
优选的，步骤(3)中，是通过干法蚀刻和/或湿式蚀刻的方式形成该些凹槽。
优选的，步骤(4)中，所述栅极是金属，通过磁控溅镀、离子蒸镀或电弧离子蒸镀的方法沉积于所述图形化区域上并与势垒层形成肖特基接触。
本发明的有益效果是：
1.本发明在源极和漏极之间设置一图形化区域，图形化区域内设置复数个由势垒层表面沿厚度方向部分下凹形成的凹槽，栅极设置于图形化区域上且栅极长度大于凹槽于栅极长度方向上的长度以完全覆盖该些凹槽，一方面借由凹槽的设置增强器件的栅控能力，抑制短沟道效应；另一方面栅极下方原始的异质结构得到了保留，避免导电能力的降低及二维电子气密度的下降，从而在实现抑制短沟道效应的同时保证了器件的电流输出能力，提升了微波器件的频率性能。
2.栅极覆盖于凹槽的底部及侧壁上，形成环形栅结构，由底部及侧壁对二维电子气沟道实现三维调控，进一步增强了调制能力。
3.制程简单常规，无特殊工艺要求，不影响外延材料的最终质量，可控性强，适于实际生产应用。
附图说明
图1为本发明一实施例之俯视结构示意图；
图2为本发明一实施例之势垒层俯视结构示意图；
图3为图1中A-A方向的截面示意图；
图4为图1中A’-A’方向的截面示意图
图5为图1中B-B方向的截面部分结构示意图。
具体实施方式
以下结合附图及实施例对本发明作进一步详细说明。本发明的各附图仅为示意以更容易了解本发明，其具体比例可依照设计需求进行调整。文中所描述的图形中相对元件的上下关系，在本领域技术人员应能理解是指构件的相对位置而言，因此皆可以翻转而呈现相同的构件，此皆应同属本说明书所揭露的范围。此外，图中所示的元件及结构的个数，均仅为示例，并不以此对数目进行限制，实际可依照设计需求进行调整。
参考图1至图5，一实施例的图形化栅结构的微波晶体管由下至上包括衬底1、缓冲层2、沟道层3及势垒层4，势垒层4上设置有源极5、漏极6及栅极7，栅极7位于源极5和漏极6之间。以源极至漏极方向栅极的跨度为栅极长度，以栅极沿源极和漏极延伸方向的跨度为栅极宽度，通常认为栅极长度方向和栅极宽度方向垂直。势垒层4于源极5和漏极6之间具有一图形化区域L，图形化区域L内设置有复数个由势垒层4表面沿厚度方向部分下凹形成的凹槽41。栅极7覆设于图形化区域L上，且栅极长度大于该些凹槽41于栅极长度方向上的长度以完全覆盖该些凹槽41。于凹槽41内，栅极7与二维电子气沟道的距离缩短，提高了栅极对二维电子气沟道的控制能力；于凹槽外，栅极下方的势垒层不变，二维电子气的密度以及势垒层的导电能力得到了保持，从而保持了器件的输出功率。
在本实施例中，该些凹槽41是条形结构，开口为长方形，且沿栅极宽度方向等距离间隔平行排列，该些凹槽开口的总面积占栅极7覆盖的图形化区域面积的25％～50％。举例来说，各凹槽41的长度在20nm～40nm之间，宽度与相邻凹槽的间距相同或相近，从而形成阵列式排布，栅极长度在30nm～50nm之间，两侧边缘与凹槽两侧边缘之间具有一定距离，从而实现了完全覆盖，凹槽41完全在栅极7的调控范围之内。如果栅极7不能完全将凹槽41覆盖，则栅极7外的凹槽41部分所引起的2-DEG降低不能被栅极7所调控，这会影响器件的电流密度，从而影响器件的输出功率。此外，条形凹槽阵列还可以是沿栅极长度方向排布，或者斜向排布，或者多列并排等其他排布方式。条形凹槽阵列的设置，一方面整体分布较为均匀，从而使得电流相对均匀分布，避免非均匀分布导致的局部电流过大，引起器件局部结温过高，带来器件可靠性问题；一方面便于加工。此外，根据实际需求，凹槽亦可以是其他规则或不规则的形状，其排布亦可以是有序排布或者无序排布，并不以此为限。
各凹槽41的侧壁411由凹槽开口向底部412方向向内倾斜0°～60°，栅极覆盖于凹槽41的侧壁411和底部412上，于垂直的底部方向及斜向的侧壁方向同时实现对二维电子气沟道的调制，形成了环栅效应。倾斜的侧壁增大了器件的调控能力，进而提高了器件的频率性能。栅极7于凹槽底部412的厚度与于势垒层4表面的厚度相同，且由于倾斜侧壁的设置，其弯折处均为钝角，避免了尖角效应，整体厚度趋于均匀，并呈现与图形化区域相应的表面形貌，性能均一而稳定。举例来说，势垒层的厚度为20nm左右，凹槽41的深度为10nm左右，栅极的厚度为500nm，可实现较好的协同作用。
衬底及缓冲层为习知之材料及结构，例如衬底可以是硅、碳化硅及蓝宝石等。缓冲层可以是AlxGa1-xN，0≤x≤1。沟道层3和势垒层4为可形成异质结的半导体材料形成，例如GaN/AlGaN，GaAs/AlGaAs等。源极5和漏极6为金属并与势垒层4之间形成欧姆接触，栅极7亦为金属并与势垒层4之间形成肖特基接触。
制备上述图形化栅结构的微波晶体管的方法，是首先于衬底1上依次形成缓冲层2、沟道层3及势垒层4。清洗该试片后在势垒层4上形成源极5和漏极6，具体是使用电子束蒸镀机蒸镀上Ti/Al/Ni/Au多金属层，各层厚度分别是20/150/50/100nm，然后放入快速退火机，在850℃下30s退火形成欧姆接触，从而形成了源极和漏极。此外，源极和漏极亦可以是其他金属、合金或叠层结构。接着，在源极和漏极之间的势垒层上蚀刻凹槽，可以通过干法蚀刻、湿式蚀刻或两者相结合的技术来实现。干法蚀刻可用机台为RIE、ICP等，且通过控制蚀刻的功率、压力、气氛等条件来控制凹槽的深度以及侧壁的倾斜度。湿式蚀刻可用氢氧化钠、氢氧化钾等溶液来进行，并通过控制溶液的浓度、蚀刻时间等来控制凹槽的深度以及侧壁的倾斜度。再在图形化区域上沉积栅极，栅极可以是金属，通过磁控溅镀、离子蒸镀或电弧离子蒸镀的方法沉积于图形化区域上并形成肖特基接触。
上述实施例仅用来进一步说明本发明的一种图形化栅结构的微波晶体管及其制备方法，但本发明并不局限于实施例，凡是依据本发明的技术实质对以上实施例所作的任何简单修改、等同变化与修饰，均落入本发明技术方案的保护范围内。

Claims (10)

1.一种图形化栅结构的微波晶体管，所述晶体管由下至上包括衬底、缓冲层、沟道层及势垒层，势垒层上设置有源极、漏极及栅极，且栅极位于源极和漏极之间，其特征在于：所述势垒层于源极和漏极之间具有一图形化区域，所述图形化区域内设置有复数个由势垒层表面沿厚度方向部分下凹形成的凹槽，该些凹槽沿栅极宽度方向等距离间隔平行排列；所述栅极覆设于所述图形化区域上，且栅极长度大于该些凹槽于所述栅极长度方向上的长度以完全覆盖该些凹槽。
2.根据权利要求1所述的图形化栅结构的微波晶体管，其特征在于：该些凹槽占所述栅极覆盖的图形化区域面积的25％～75％。
3.根据权利要求1所述的图形化栅结构的微波晶体管，其特征在于：该些凹槽是条形结构且等距离间隔平行排列。
4.根据权利要求1所述的图形化栅结构的微波晶体管，其特征在于：所述栅极于所述复数个凹槽底部的厚度与所述势垒层表面的厚度相同。
5.根据权利要求1所述的图形化栅结构的微波晶体管，其特征在于：所述复数个凹槽的侧壁由凹槽开口向底部方向向内倾斜0～60度，所述栅极覆盖所述复数个凹槽的侧壁。
6.根据权利要求1所述的图形化栅结构的微波晶体管，其特征在于：所述沟道层和势垒层为可形成异质结的半导体材料制成；所述源极、漏极及栅极由金属制成且源极和漏极与势垒层形成欧姆接触，栅极与势垒层形成肖特基接触。
7.一种如权利要求1～6任一项所述的图形化栅结构的微波晶体管的制备方法，其特征在于包括以下步骤：
(1)于一衬底上依次形成缓冲层、沟道层及势垒层；
(2)于势垒层表面上形成源极和漏极；
(3)于源极和漏极之间定义一图形化区域，蚀刻所述图形化区域的势垒层形成所述复数个凹槽；
(4)于所述图形化区域上形成栅极，且栅极长度大于该些凹槽于所述栅极长度方向上的长度以完全覆盖所述复数个凹槽。
8.根据权利要求7所述的制备方法，其特征在于：步骤(2)具体包括以下子步骤：
通过电子束蒸镀的方法于所述势垒层表面的两个区域分别蒸镀上Ti/Al/Ni/Au多金属层，其中所述Ti/Al/Ni/Au的厚度分别是20/150/50/100nm；
于800-950℃下退火20-45秒形成欧姆接触，形成所述源极和漏极。
9.根据权利要求7所述的制备方法，其特征在于：步骤(3)中，是通过干法蚀刻和/或湿式蚀刻的方式形成该些凹槽。
10.根据权利要求7所述的制备方法，其特征在于：步骤(4)中，所述栅极是金属，通过磁控溅镀、离子蒸镀或电弧离子蒸镀的方法沉积于所述图形化区域上并与势垒层形成肖特基接触。
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