WO2017206812A1 - 沟槽栅极引出结构及其制造方法 - Google Patents

沟槽栅极引出结构及其制造方法 Download PDF

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Publication number
WO2017206812A1
WO2017206812A1 PCT/CN2017/086136 CN2017086136W WO2017206812A1 WO 2017206812 A1 WO2017206812 A1 WO 2017206812A1 CN 2017086136 W CN2017086136 W CN 2017086136W WO 2017206812 A1 WO2017206812 A1 WO 2017206812A1
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Prior art keywords
trench
polysilicon
gate
dielectric layer
substrate
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English (en)
French (fr)
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卞铮
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CSMC Technologies Fab1 Co Ltd
CSMC Technologies Fab2 Co Ltd
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CSMC Technologies Fab1 Co Ltd
CSMC Technologies Fab2 Co Ltd
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Priority to JP2018560711A priority Critical patent/JP6567784B2/ja
Priority to US16/064,522 priority patent/US10475893B2/en
Publication of WO2017206812A1 publication Critical patent/WO2017206812A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H10D30/0297—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using recessing of the gate electrodes, e.g. to form trench gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113—Isolations within a component, i.e. internal isolations
    • H10D62/115—Dielectric isolations, e.g. air gaps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/512—Disposition of the gate electrodes, e.g. buried gates
    • H10D64/513—Disposition of the gate electrodes, e.g. buried gates within recesses in the substrate, e.g. trench gates, groove gates or buried gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
    • H10D64/518—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers characterised by their lengths or sectional shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/661—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation
    • H10D64/662—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0281—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of lateral DMOS [LDMOS] FETs
    • H10D30/0289—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of lateral DMOS [LDMOS] FETs using recessing of the gate electrodes, e.g. to form trench gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/65—Lateral DMOS [LDMOS] FETs
    • H10D30/658—Lateral DMOS [LDMOS] FETs having trench gate electrodes

Definitions

  • the present invention relates to semiconductor fabrication techniques, and more particularly to a trench gate extraction structure and a method of fabricating a trench gate extraction structure.
  • VDMOS vertical double-diffused metal oxide semiconductor field effect transistor
  • the end portion size of the extraction trench is mostly increased by cost, and the trench gate is taken out by the contact hole.
  • the advantage of this solution is that it can be carried out using the existing mask level of the product process without increasing the mask level cost.
  • the disadvantage is that the larger the size of the end of the extraction groove, the thicker the polysilicon to be deposited, resulting in an increase in cost, thereby limiting the application of this conventional solution.
  • a trench gate extraction structure comprising a substrate, a trench on a surface of the substrate, and a first dielectric layer on the substrate, further comprising a gate oxide layer on the inner surface of the trench and a polysilicon gate on the gate oxide layer a trench, the trench is partially filled by the polysilicon gate, so there is a recess on a surface of the polysilicon gate, the recess is filled with a second dielectric layer, and the trench gate lead-out structure further includes a metal plug The metal plug is inserted through the first dielectric layer and inserted between the second dielectric layer and the polysilicon gate to be connected to the polysilicon gate.
  • a method of fabricating a trench gate extraction structure includes: forming a trench on a surface of the substrate, the inner surface of the trench is formed with a gate oxide layer; filling the inner surface of the trench with polysilicon and not filling the trench, Forming a recess on the surface of the polysilicon in the trench; forming an insulating medium on the substrate and the trench; photolithing and etching the insulating medium to form a dielectric hole such that polysilicon of the sidewall of the trench is exposed, and the insulating medium Divided into a first dielectric layer on the substrate and a second dielectric layer in the trench; performing contact hole etching, the polysilicon around the second dielectric layer is partially removed, and the second dielectric layer A gap is formed between the polysilicon on both sides; a contact hole is filled, and a metal fills the dielectric hole and the gap forms a metal plug connected to the polysilicon gate.
  • the polysilicon gate does not need to fill the trench, and the thickness of the polysilicon deposition is only related to the width setting of the cell trench, so that the thickness can be greatly reduced, and the polysilicon layer can be improved. Accumulate capacity and reduce costs.
  • FIG. 1 is a schematic cross-sectional view showing a trench gate extraction structure in an embodiment
  • FIG. 2 is a flow chart showing a method of fabricating a trench gate extraction structure in an embodiment
  • Figure 3 is a cross-sectional view of the device after completion of step S320 in an embodiment
  • 4a to 4d are respectively cross-sectional views of the device after completion of steps S332 to S338 in an embodiment
  • Figure 5 is a flow chart of each substep of step S330 in an embodiment
  • Figure 6 is a cross-sectional view of the device after completion of step S340;
  • Figure 7 is a cross-sectional view of the device after completion of step S350.
  • FIG. 1 is a schematic cross-sectional view showing a trench gate extraction structure in an embodiment.
  • a substrate 10 (indicated by a blank area in the drawing), a trench (not shown) on the surface of the substrate 10, a first dielectric layer 22 on the substrate 10, a gate oxide layer 33 on the inner surface of the trench, and a gate oxide layer 33 are included.
  • the upper polysilicon gate 31, the second dielectric layer 41 partially surrounded by the polysilicon gate 31 in the trench, and the lower through the first dielectric layer 22 are inserted between the second dielectric layer 41 and the polysilicon gate 31.
  • the trench is partially filled by the polysilicon gate 31, so that a recess that follows the recess of the trench is formed on the surface of the polysilicon gate 31, and the recess is filled with the second dielectric layer 41.
  • the lower and upper portions of the second dielectric layer 41 in FIG. 1 use different filling patterns, but in some embodiments, the lower and upper portions of the second dielectric layer 41 may be of the same material and deposited in the same step, specifically It is detailed in the manufacturing method below.
  • the polysilicon gate 31 does not need to fill the trench, and the thickness of the polysilicon deposition is only related to the width setting of the cell trench, so that the thickness thereof can be greatly reduced, and the polysilicon deposition productivity can be improved. cut costs.
  • the above-mentioned trench gate lead-out structure is particularly suitable for a wider trench, so that the line width requirement for the hole level can also be relaxed, and the photolithography can replace the DUV (deep ultraviolet light) with a general i-line device. Equipment to make, reduce production costs.
  • DUV deep ultraviolet light
  • the metal plug 50 adopts a structure in contact with the side surface of the polysilicon gate 31, so that the contact surface thereof is larger, the corresponding contact resistance is smaller, and the conduction is more reliable.
  • the trench gate extraction structure forms a second dielectric layer 41 in the polysilicon gate 31, which acts as a barrier layer during the contact hole polysilicon etching, so that the polysilicon gate 31 is not easily etched.
  • the polysilicon gate 31 located in the trench has a U-shaped cross section, and the second dielectric layer 41 is filled in a hollow portion of the U-shaped recess.
  • the metal plug 50 is a tungsten plug. In other embodiments, other metals known in the art for use as contact hole fills may also be employed.
  • the second dielectric layer 41 is a silicon dioxide layer deposited using tetraethyl orthosilicate (TEOS) as a reactant.
  • TEOS tetraethyl orthosilicate
  • the second dielectric layer 41 may also employ other insulating media such as phosphosilicate glass (PSG) / borophosphosilicate glass (BPSG), silicon oxynitride, silicon nitride, and the like.
  • trench gate extraction structure is particularly suitable for DMOS devices (including VDMOS and LDMOS). It can be understood that the trench gate extraction structure is also applicable to other semiconductor devices having a trench gate structure.
  • FIG. 2 is a flow chart showing a method of fabricating a trench gate extraction structure in an embodiment, including the following steps:
  • a trench is formed by etching on the surface of the provided wafer substrate.
  • the polysilicon is filled by a deposition process, and a layer of polysilicon is deposited on the inner surface of the trench, but the trench is not filled, thereby forming a natural recess.
  • a cross-sectional view of the device after completion of step S320 is shown in FIG. 3, and the polysilicon layer 32 in the trench has a U-shaped cross section. It can be understood that if the deposition of polysilicon is directly performed (ie, no photomask is used), a polysilicon layer is also formed on the substrate 10 outside the trench, but the polysilicon outside the trench is a polysilicon gate. extra. If a mask or a barrier layer is formed by photolithography, polysilicon can be deposited only in the trenches, but this generally leads to an increase in cost.
  • the step of forming the gate oxide layer 33 on the surface of the trench is further included between steps S310 and S320.
  • Polysilicon layer 32 is deposited on gate oxide layer 33.
  • the gate oxide layer can be formed by a conventional process such as thermal oxidation growth of the gate oxide layer.
  • step S330 in this embodiment specifically includes the following sub-steps:
  • a silicon dioxide layer is chemically deposited as a second dielectric layer 41 using tetraethyl orthosilicate (TEOS) as a reactant, and a cross-sectional view of the device after completion of step S332 is shown in FIG. 4a.
  • TEOS tetraethyl orthosilicate
  • the insulating medium may also be other insulating materials such as phosphosilicate glass (PSG) / borophosphosilicate glass (BPSG), silicon oxynitride, silicon nitride, and the like.
  • step S334 A cross-sectional view of the device after completion of step S334 is shown in Figure 4b.
  • the active region is exposed and the active region of the device is fabricated.
  • the active region fabrication process as known in the art can be used, and has nothing to do with the inventive point of the present invention, and has nothing to do with the trench gate lead-out structure, so it will not be described here.
  • a cross-sectional view of the device after completion of step S336 is shown in Figure 4c.
  • the polysilicon layer 32 in the trench is relatively thin (polysilicon is not filled but only covers one layer on its inner wall), this causes the polysilicon layer 32 to be etched (or even damaged) in the polysilicon etchback step of S336.
  • the role of the second dielectric layer 41 is mainly as a barrier layer during the etching of the polysilicon, ensuring that the polysilicon layer 32 in the trench is protected by the second dielectric layer 41 when the polysilicon etchback occurs, and the underlying polysilicon is not etched. .
  • an insulating medium is deposited again on the substrate 10, the remaining polysilicon layer 32, and the second dielectric layer 41.
  • the thickness of the deposited insulating medium should be such that it fills the opening of the trench.
  • the insulating medium deposited in step S338 may be the same material as step S332, or may be a different material, and the deposited insulating medium may be subsequently used as an interlayer dielectric (ILD). Since the insulating medium is deposited twice in this embodiment (steps S332 and S338), it is distinguished by two different filling patterns in Fig. 4d.
  • the deposition of the insulating medium is performed by the method shown in FIG. 5, and steps S320, S332, S334, S336, and S338 are not required to perform photolithography, and no additional polysilicon lithography layer is added, and a corresponding mask is not required. ), helping to save costs.
  • FIG. 6 A cross-sectional view of the device after completion of step S340 is shown in FIG. 6.
  • the insulating medium 40 is divided by the dielectric hole into a first dielectric layer 22 on the substrate 10, and a second dielectric layer 41 filled in a recess formed on the surface of the polysilicon layer 32. .
  • the polysilicon portion around the second dielectric layer 41 is removed by etching the polysilicon to form a polysilicon gate 31, as shown in FIG.
  • the metal plug 50 is a tungsten plug. In other embodiments, other metals known in the art for use as contact hole fills may also be employed.
  • the metal plug is also required to be etched back and the surface of the device is planarized.
  • the above-described method of fabricating the trench gate extraction structure is particularly suitable for DMOS devices (including VDMOS and LDMOS). It can be understood that the manufacturing method is equally applicable to other semiconductor devices having a trench gate structure.

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  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

一种沟槽栅极引出结构包括衬底（10）、衬底（10）表面的沟槽、以及所述衬底（10）上的第一介质层（22），还包括沟槽内表面的多晶硅栅极（31），所述沟槽被所述多晶硅栅极（31）部分填充，故在所述多晶硅栅极（31）上方的沟槽内存在凹陷，所述凹陷内填充有第二介质层（41），所述沟槽栅极引出结构还包括金属塞（50），所述金属塞（50）向下穿过所述第一介质层（22）后插入所述第二介质层（41）与所述多晶硅栅极（31）之间，从而与所述多晶硅栅极（31）连接。

Description

沟槽栅极引出结构及其制造方法
【技术领域】
本发明涉及半导体制造技术，特别是涉及一种沟槽栅极引出结构，还涉及一种沟槽栅极引出结构的制造方法。
【背景技术】
传统的沟槽型VDMOS（垂直双扩散金属氧化物半导体场效应晶体管）产品因成本原因，大多采用加大引出沟槽的端部尺寸，在其上打接触孔的方式将沟槽栅极引出。该方案的优点是可以利用产品工艺已有的光罩（mask）层次进行，无需增加光罩层次成本。但其缺点是引出沟槽端部的尺寸越大，需要淀积的多晶硅就越厚，导致成本增加，从而限制了此传统方案的应用。
【发明内容】
基于此，有必要针对大尺寸的沟槽栅极淀积的多晶硅较厚，导致成本增加的问题，提供一种沟槽栅极引出结构及其制造方法。
一种沟槽栅极引出结构，包括衬底、衬底表面的沟槽、以及所述衬底上的第一介质层，还包括沟槽内表面的栅氧化层以及栅氧化层上的多晶硅栅极，所述沟槽被所述多晶硅栅极部分填充，故在所述多晶硅栅极的表面存在凹陷，所述凹陷内填充有第二介质层，所述沟槽栅极引出结构还包括金属塞，所述金属塞向下穿过所述第一介质层后插入所述第二介质层与所述多晶硅栅极之间，从而与所述多晶硅栅极连接。
一种沟槽栅极引出结构的制造方法，包括：在衬底表面形成沟槽，所述沟槽的内表面形成有栅氧化层；向沟槽内表面填充多晶硅且不将沟槽填满，沟槽内的多晶硅表面形成凹陷；在衬底和沟槽上形成绝缘介质；光刻并刻蚀所述绝缘介质，形成介质孔，使得所述沟槽侧壁的多晶硅露出，且所述绝缘介质被分割为所述衬底上的第一介质层和沟槽内的第二介质层；进行接触孔刻蚀，所述第二介质层四周的多晶硅被部分去除，在所述第二介质层和其两侧的多晶硅之间形成空隙；进行接触孔填充，金属填入所述介质孔和所述空隙内形成与多晶硅栅极连接的金属塞。
上述沟槽栅极引出结构及其制造方法，多晶硅栅极不需要将沟槽填满，多晶硅淀积的厚度仅与元胞沟槽的宽度设定相关，因此可以大幅降低其厚度，提升多晶硅淀积产能，降低成本。
【附图说明】
通过附图中所示的本发明的优选实施例的更具体说明，本发明的上述及其它目的、特征和优势将变得更加清晰。在全部附图中相同的附图标记指示相同的部分，且并未刻意按实际尺寸等比例缩放绘制附图，重点在于示出本发明的主旨。
图1是一实施例中沟槽栅极引出结构的剖面示意图；
图2是一实施例中沟槽栅极引出结构的制造方法的流程图；
图3是一实施例中步骤S320完成后器件的剖视图；
图4a~图4d分别是一实施例中步骤S332~S338完成后器件的剖视图；
图5是一实施例中步骤S330的各子步骤流程图；
图6是步骤S340完成后器件的剖视图；
图7是步骤S350完成后器件的剖视图。
【具体实施方式】
为了便于理解本发明，下面将参照相关附图对本发明进行更全面的描述。附图中给出了本发明的首选实施例。但是，本发明可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本发明的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本发明的技术领域的技术人员通常理解的含义相同。本文中在本发明的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本发明。本文所使用的术语“及／或”包括一个或多个相关的所列项目的任意的和所有的组合。
需要说明的是，当元件被称为“固定于”另一个元件，它可以直接在另一个元件上或者也可以存在居中的元件。当一个元件被认为是“连接”另一个元件，它可以是直接连接到另一个元件或者可能同时存在居中元件。本文所使用的术语“竖直的”、“水平的”、“上”、“下”、“左”、“右”以及类似的表述只是为了说明的目的。
图1是一实施例中沟槽栅极引出结构的剖面示意图。包括衬底10（图中用空白区域表示），衬底10表面的沟槽（未标示），衬底10上的第一介质层22，沟槽内表面的栅氧化层33以及栅氧化层33上的多晶硅栅极31，沟槽内被多晶硅栅极31半包围的第二介质层41，以及向下穿过第一介质层22后插入第二介质层41与多晶硅栅极31之间而与多晶硅栅极31连接的金属塞50。具体地，沟槽被多晶硅栅极31部分填充，故在多晶硅栅极31的表面形成跟随沟槽下凹的凹陷，凹陷内填充有第二介质层41。图1中第二介质层41的下部和上部使用了不同的填充图案，但在一些实施例中，第二介质层41的下部和上部可以为同样材质且在同一步骤中淀积形成，具体会在下文的制造方法中详述。
上述沟槽栅极引出结构，多晶硅栅极31不需要将沟槽填满，多晶硅淀积的厚度仅与元胞沟槽的宽度设定相关，因此可以大幅降低其厚度，提升多晶硅淀积产能，降低成本。
可以理解的，上述沟槽栅极引出结构特别适用于较宽的沟槽，因此其对孔层次的线宽要求也可放宽，光刻可以使用一般的i-line设备替代DUV（深紫外光）设备来制作，降低生产成本。
金属塞50采用与多晶硅栅极31侧面接触的结构，因此其接触面更大，相应的接触电阻更小，导通更可靠。
现有结构的一个缺点是，对于符合某些条件的沟槽尺寸，接触孔容易打穿沟槽端部（即打穿多晶硅栅极）。上述沟槽栅极引出结构，在多晶硅栅极31内形成第二介质层41，可以在接触孔多晶硅刻蚀时起到阻挡层的作用，使得多晶硅栅极31不易被蚀穿。
在图1所示实施例中，位于沟槽内的多晶硅栅极31的横截面为U型结构，第二介质层41填充于U型结构内陷的中空部位。
在其中一个实施例中，金属塞50为钨塞。在其他实施例中，也可以采用本领域习知的其他用作接触孔填充的金属。
在其中一个实施例中，第二介质层41是以正硅酸乙酯（TEOS）为反应剂淀积的二氧化硅层。在其他实施例中，第二介质层41也可以采用其他绝缘介质，例如磷硅玻璃（PSG）/硼磷硅玻璃（BPSG）、氮氧化硅、氮化硅等。
上述沟槽栅极引出结构尤其适用于DMOS器件（包括VDMOS和LDMOS）。可以理解的，该沟槽栅极引出结构同样适用于其他具有沟槽栅极结构的半导体器件。
图2是一实施例中沟槽栅极引出结构的制造方法的流程图，包括下列步骤：
S310，在衬底表面形成沟槽。
在提供的晶圆衬底表面通过刻蚀形成沟槽。
S320，向沟槽内表面填充多晶硅且不将沟槽填满，沟槽内的多晶硅表面形成凹陷。
通过淀积工艺进行多晶硅的填充，在沟槽内表面淀积一层多晶硅，但不将沟槽填满，从而形成自然凹陷。步骤S320完成后器件的剖视图如图3所示，沟槽内的多晶硅层32的横截面为U型结构。可以理解的，如果是直接进行多晶硅的淀积（即不使用光罩），则在沟槽外的衬底10上同样会形成多晶硅层，但这些沟槽外的多晶硅对多晶硅栅极来说是多余的。如果是通过光刻形成掩膜或阻挡层，则可以只在沟槽内淀积多晶硅，但这样做通常会导致成本上升。
在本实施例中，步骤S310和S320之间还包括在沟槽表面形成栅氧化层33的步骤。多晶硅层32是淀积在栅氧化层33上。栅氧化层的形成可以采用习知的工艺，例如热氧化法生长栅氧化层。
S330，在衬底和沟槽上形成绝缘介质。
如果是只在沟槽内淀积多晶硅，或者将沟槽外的多晶硅去除后，则步骤S330完成后的器件剖视图如图4d所示，可以直接淀积一层绝缘介质40（绝缘介质40包括下方填充图案为方格的部分）。但如前述，本实施例中为了降低成本，多晶硅的淀积是直接进行的，无需增加多晶硅光罩层次成本。因此本实施例中步骤S330具体包括如下子步骤：
S332，在沟槽内淀积绝缘介质。
确保淀积的绝缘介质厚度能够将沟槽填满。在本实施例中是以正硅酸乙酯（TEOS）为反应剂化学气相淀积二氧化硅层作为第二介质层41，步骤S332完成后器件的剖视图如图4a所示。在其他实施例中绝缘介质也可以是其他绝缘材料，例如磷硅玻璃（PSG）/硼磷硅玻璃（BPSG）、氮氧化硅、氮化硅等。
S334，对溢出沟槽的绝缘介质进行回刻，将沟槽外衬底和多晶硅上的绝缘介质去除。
可以使用干法或者湿法刻蚀。需要确保淀积于沟槽外衬底和多晶硅上的绝缘介质被完全去除并露出下方的多晶硅层32，但同时要求保证沟槽开口内仍然留有足量的绝缘介质，以在步骤S336中回刻时对多晶硅层32进行保护。步骤S334完成后器件的剖视图如图4b所示。
S336，进行多晶硅回刻，将沟槽外衬底上的多晶硅去除，使有源区露出。
将有源区暴露出来后进行器件有源区的制作。可以采用本领域习知的有源区制作工艺，因与本发明的发明点无关，且与沟槽栅极引出结构也没什么关系，故此处不赘述。步骤S336完成后器件的剖视图如图4c所示。
由于沟槽内的多晶硅层32较薄（多晶硅未填满而仅仅是在其内壁覆盖了一层），这就导致了多晶硅层32在S336的多晶硅回刻步骤会被大量刻蚀（乃至损伤到其下的栅氧化层33）。第二介质层41的作用主要是作为多晶硅回刻时的阻挡层，保证当多晶硅回刻发生时，沟槽内的多晶硅层32被第二介质层41所保护，不会刻蚀到下方的多晶硅。
S338，在衬底、剩余的多晶硅和绝缘介质上再次淀积绝缘介质。
有源区的制作完成后，在衬底10、剩余的多晶硅层32及第二介质层41上再次淀积绝缘介质。淀积的绝缘介质的厚度应确保其能填满沟槽的开口。步骤S338淀积的绝缘介质可以与步骤S332为相同的材质，也可以为不同的材质，淀积的绝缘介质后续可以作为层间介质（ILD）。由于在本实施例中绝缘介质是分两次淀积（步骤S332和S338），故在图4d中用两种不同的填充图案来区分。
采用如图5所示的方法进行绝缘介质的淀积，则步骤S320、S332、S334、S336、S338都无需进行光刻，不会增加额外的多晶硅光刻层次，不需要相应的光罩（mask），有助于节约成本。
S340，光刻并刻蚀绝缘介质，形成介质孔，绝缘介质被分割为第一、第二介质层。
要求介质孔有一定的过量刻蚀（over etch），确保沟槽侧壁的多晶硅层32可以露出。步骤S340完成后器件的剖视图如图6所示，绝缘介质40被介质孔分割为衬底10上的第一介质层22，以及填充于多晶硅层32的表面形成的凹陷内的第二介质层41。
S350，进行接触孔刻蚀，在第二介质层和其两侧的多晶硅之间形成空隙。
通过刻蚀多晶硅，将第二介质层41四周的多晶硅部分去除，形成多晶硅栅极31，如图7所示。
S360，进行接触孔填充，金属填入介质孔和空隙内形成与多晶硅栅极连接的金属塞。
参照图1。在其中一个实施例中，金属塞50为钨塞。在其他实施例中，也可以采用本领域习知的其他用作接触孔填充的金属。
本实施例中在金属填充完成后，还需要进行金属塞的回刻及对器件表面进行平坦化处理。
上述沟槽栅极引出结构的制造方法尤其适用于DMOS器件（包括VDMOS和LDMOS）。可以理解的，该制造方法同样适用于其他具有沟槽栅极结构的半导体器件。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (10)

  1. 一种沟槽栅极引出结构，包括：
    衬底；
    沟槽，位于衬底表面；
    第一介质层，位于所述衬底上；
    栅氧化层，位于所述沟槽内表面；
    多晶硅栅极，位于所述栅氧化层上，所述沟槽被所述多晶硅栅极部分填充，故在所述多晶硅栅极的表面存在凹陷；
    第二介质层，填充于所述凹陷内；以及
    金属塞，向下穿过所述第一介质层后插入所述第二介质层与所述多晶硅栅极之间，从而与所述多晶硅栅极连接。
  2. 根据权利要求1所述的沟槽栅极引出结构，其特征在于，所述第二介质层是以正硅酸乙酯为反应剂淀积的二氧化硅层。
  3. 根据权利要求1所述的沟槽栅极引出结构，其特征在于，所述金属塞为钨塞。
  4. 根据权利要求1所述的沟槽栅极引出结构，其特征在于，所述沟槽栅极引出结构应用于垂直双扩散金属氧化物半导体场效应管或横向双扩散金属氧化物半导体场效应管。
  5. 根据权利要求1所述的沟槽栅极引出结构，其特征在于，位于所述沟槽内的多晶硅栅极的横截面为U型结构，所述第二介质层填充于所述U型结构内陷的中空部位。
  6. 一种沟槽栅极引出结构的制造方法，包括：
    在衬底表面形成沟槽；
    在所述沟槽的内表面形成栅氧化层；
    向沟槽内表面填充多晶硅且不将沟槽填满，沟槽内的多晶硅表面形成凹陷；
    在衬底和沟槽上形成绝缘介质；
    光刻并刻蚀所述绝缘介质，形成介质孔，使得所述沟槽侧壁的多晶硅露出，且所述绝缘介质被分割为所述衬底上的第一介质层和沟槽内的第二介质层；
    进行接触孔刻蚀，所述第二介质层四周的多晶硅被部分去除，在所述第二介质层和其两侧的多晶硅之间形成空隙；以及
    进行接触孔填充，金属填入所述介质孔和所述空隙内形成与多晶硅栅极连接的金属塞。
  7. 根据权利要求6所述的方法，其特征在于，所述在衬底和沟槽上形成绝缘介质的步骤包括：
    在所述沟槽内淀积绝缘介质；
    对溢出所述沟槽的绝缘介质进行回刻，将沟槽外所述衬底和多晶硅上的绝缘介质去除；
    进行多晶硅回刻，将所述沟槽外衬底上的多晶硅去除，使有源区露出；以及
    在所述衬底、剩余的多晶硅和绝缘介质上再次淀积绝缘介质。
  8. 根据权利要求7所述的方法，其特征在于，所述在所述沟槽内淀积绝缘介质的步骤是以正硅酸乙酯为反应剂化学气相淀积二氧化硅层。
  9. 根据权利要求6所述的方法，其特征在于，所述光刻并刻蚀所述绝缘介质的步骤通过对所述绝缘介质进行过量刻蚀以保证所述多晶硅露出。
  10. 根据权利要求6所述的方法，其特征在于，所述进行接触孔填充的步骤之后，还包括进行平坦化处理的步骤。
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