WO2017185953A1 - 数字分频锁相环 - Google Patents

数字分频锁相环 Download PDF

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Publication number
WO2017185953A1
WO2017185953A1 PCT/CN2017/079446 CN2017079446W WO2017185953A1 WO 2017185953 A1 WO2017185953 A1 WO 2017185953A1 CN 2017079446 W CN2017079446 W CN 2017079446W WO 2017185953 A1 WO2017185953 A1 WO 2017185953A1
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digital
frequency division
frequency
signal
locked loop
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PCT/CN2017/079446
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English (en)
French (fr)
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高鹏
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华为技术有限公司
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Publication of WO2017185953A1 publication Critical patent/WO2017185953A1/zh
Priority to US16/169,378 priority Critical patent/US10419007B2/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
    • H03L7/1974—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division
    • H03L7/1976—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division using a phase accumulator for controlling the counter or frequency divider
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/0802—Details of the phase-locked loop the loop being adapted for reducing power consumption
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
    • H03L7/0992—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider comprising a counter or a frequency divider
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
    • H03L2207/50—All digital phase-locked loop

Definitions

  • the present application relates to the field of electronic information, and in particular to a digital frequency division phase locked loop.
  • a frequency synthesizer based on a Phase-Locked Loop (PLL) structure is widely used to generate a Local Oscillator (LO) signal for completion.
  • the frequency shift operation of the RF signal Due to several advantages such as lock time, integral phase noise and design flexibility, digital fractional phase-locked loops that can achieve not only integer frequency division but also fractional frequency division can be realized with respect to integer frequency division phase-locked loops. A wide range of applications.
  • Time-to-Digital Converter In the digital fractional phase-locked loop, Time-to-Digital Converter (TDC) is one of the important analog components, and its linear performance is the main factor affecting the linear performance of the entire phase-locked loop system. Because the closer to linear, the least noise, therefore, improving the linear performance of the TDC is a key factor in ensuring that the digital fractional phase-locked loop is maintained at a low noise level.
  • the reasons for its linearity mainly include device mismatch and layout design mismatch.
  • the present application provides a digital frequency division phase-locked loop and a nonlinear correction method thereof, aiming at realizing nonlinear correction of the digital frequency division phase-locked loop with a small implementation cost.
  • a first aspect of the present application provides a digital frequency division phase locked loop comprising: a time to digital converter, a digital loop filter, a digitally controlled oscillator, a feedback frequency divider, a sigma-delta modulator, and a correction device.
  • the time-to-digital converter is configured to receive a reference clock signal and a feedback clock signal, and discriminate a phase difference between the reference clock signal and the feedback clock signal to obtain a digital signal indicating the phase difference.
  • the correcting means is configured to receive the digital signal, a frequency control word, and a frequency division control word generated by the Sigma-Delta modulator, and compensate the digital signal based on the frequency control word and the frequency division control word A correction signal is obtained.
  • the digital loop filter is configured to receive the correction signal and digitally filter the correction signal to obtain an oscillator frequency control signal.
  • the digitally controlled oscillator is configured to receive the oscillator frequency control signal and generate an oscillating signal as an output signal of the digital frequency division phase locked loop under the control of the oscillator frequency control signal.
  • the feedback frequency divider is configured to divide the oscillating signal to obtain the feedback clock signal.
  • the Sigma-Delta modulator And for receiving the frequency control word and generating the frequency division control word based on the frequency control word.
  • the frequency control word is used to indicate a nominal frequency division value of the digital frequency division phase locked loop, and the nominal frequency division value is a ratio of a frequency of the oscillation signal to a frequency of the reference clock signal
  • the frequency division control word is used to indicate an actual frequency division value of the feedback frequency divider, and the actual frequency division value is a ratio of a frequency of the oscillation signal to a frequency of the feedback clock signal. Since the correction device is used to compensate the digital signal output by the time-to-digital converter based on the frequency control word and the frequency division control word without modifying the time-to-digital converter, the digital frequency division lock can be realized with a small implementation cost. Nonlinear correction of the ring.
  • the correcting means is configured to obtain a time domain deviation between the reference clock signal and the feedback clock signal based on the frequency control word and the frequency division control word, and based on the time domain
  • the offset compensates the digital signal to obtain the correction signal.
  • the correcting device compensates the digital signal according to the time domain deviation between the reference clock signal and the feedback clock signal, which is simple and easy to implement, and has high implementability.
  • the correcting means includes: a measurer for obtaining a time domain deviation between the reference clock signal and the feedback clock signal based on the frequency control word and the frequency division control word, and And a compensator for determining a nonlinear compensation value corresponding to the time domain deviation by a mapping relationship, and compensating the digital signal by using the nonlinear compensation value to obtain the correction signal.
  • the compensator includes: a mapping unit configured to determine, by the mapping relationship, a nonlinear compensation value corresponding to the time domain deviation, and a calibrator for compensating with the nonlinear compensation value The digital signal is used to obtain the correction signal.
  • the calibrator includes an adder for adding a negative value of the non-linear compensation value to the digital signal to obtain the correction signal.
  • mapping relationship is embodied in a lookup table.
  • the lookup table is preset in the mapping unit.
  • the correction device further includes a calculator for estimating the nonlinear error from the time domain deviation to the digital signal, and generating the nonlinearity according to the nonlinear error generation The lookup table of the error.
  • mapping unit is further configured to determine that the time domain deviation is not present in the lookup table.
  • the calculator is further configured to obtain a nonlinear compensation value corresponding to the time domain deviation by using linear interpolation, and send the obtained nonlinear compensation value to the calibrator.
  • the digital frequency division phase locked loop further includes: a controller, configured to turn off the measurer and the calculator after the calculator obtains the nonlinear error. Since the functions of the measurer and the calculator have been completed after the nonlinear error is obtained, in this case, turning off both can save power.
  • the measurer includes an adder, an integrator, and a multiplier.
  • the adder is configured to add a negative value of the frequency control word to the frequency division control word to obtain an actual frequency division value and a location of the feedback frequency divider indicated by the frequency division control word. The difference between the nominal frequency division values of the digital frequency division phase locked loop indicated by the frequency control word.
  • the integrator is configured to perform time domain integration on the difference to obtain an integrated value.
  • the multiplier is configured to multiply the integrated value by a period of the oscillating signal to obtain the time domain deviation.
  • the digital frequency division phase locked loop is a digital fractional phase locked loop.
  • the correcting means is configured to receive the digital signal, a frequency control word, and a frequency division control word generated by the Sigma-Delta modulator at a preset frequency point, and control the word and the location based on the frequency
  • the frequency division control word compensates the digital signal to obtain a correction signal at the preset frequency point.
  • the preset frequency point is selected according to: the preset frequency point is such that a time domain deviation of the frequency control word and the frequency division control word is within a preset range, and the preset range is such that the time domain is The deviation and the digital signal satisfy the constituent conditions of the transfer function of the TDC. Correcting at a preset frequency point can improve the accuracy of nonlinear correction, and at the same time reduce the cost of implementation.
  • a second aspect of the present application provides a chip comprising a plurality of logic gate circuits or transistor circuits, and the above-described digital frequency division phase locked loop.
  • FIG. 1 is a schematic structural diagram of a digital fractional frequency division phase-locked loop disclosed in an embodiment of the present application
  • FIG. 2 is a schematic diagram of phase discrimination of a digital fractional frequency division phase locked loop disclosed in an embodiment of the present application
  • FIG. 3 is a schematic structural diagram of a measuring device of a digital fractional frequency division phase-locked loop disclosed in an embodiment of the present application;
  • FIG. 4 is a schematic diagram of an input sequence and an output sequence of a digital fractional phase-locked loop disclosed in an embodiment of the present application;
  • FIG. 5 is a schematic diagram of a transfer function curve of a TDC of a digital fractional frequency division phase locked loop disclosed in an embodiment of the present application;
  • FIG. 6 is a schematic diagram showing a relationship between a linear approximation function and a transfer function of a TDC of a digital fractional phase-locked loop disclosed in an embodiment of the present application;
  • FIG. 7 is a schematic diagram showing the relationship between a nonlinear error function of a TDC of a digital fractional phase-locked loop disclosed in an embodiment of the present application;
  • FIG. 8 is a schematic structural diagram of a compensator for a digital fractional frequency division phase locked loop according to an embodiment of the present application.
  • FIG. 9 is a schematic diagram of the effect of the digital fractional phase-locked loop disclosed in the embodiment of the present application on noise improvement.
  • FIG. 1 is a schematic structural diagram of a digital fractional frequency division phase locked loop according to an embodiment of the present application, including a TDC, a digital loop filter (DLF), a digital oscillator (DCO), and a feedback frequency division. (Feedback Divider, DIV), Sigma-Delta Modulator SDM and calibration device.
  • the TDC is for receiving the reference clock signal CLK_REF and the feedback clock signal CLK_DIV and discriminating the phase difference between CLK__REF and CLK_DIV to obtain a digital signal TDC_OUT indicating the phase difference.
  • the correcting means is configured to receive the digital signal TDC_OUT, the frequency control word FCW and the frequency division control word SDM_OUT generated by the SDM, and compensate the digital signal TDC_OUT based on the frequency control word FCW and the frequency division control word SDM_OUT A correction signal TDC_CAL is obtained.
  • the frequency control word FCW is used to indicate a nominal frequency division value of the digital frequency division phase locked loop, where the standard The frequency division value is a ratio of a frequency of the oscillation signal F_DCO to a frequency of the reference clock signal CLK_REF, and the frequency division control word FCW is used to indicate an actual frequency division value of the feedback frequency divider DIV, the actual frequency The frequency value is a ratio of the frequency of the oscillation signal F_DCO to the frequency of the feedback clock signal CLK_DIV.
  • the DLF is for receiving the correction signal TDC_CAL and digitally filtering the correction signal to obtain an oscillator frequency control signal DLF_OUT.
  • the DCO is used to receive the oscillator frequency control signal DLF_OUT and generate an oscillating signal DCO_OUT as an output signal of the digital frequency division phase locked loop under the control of DLF_OUT.
  • the feedback divider DIV is configured to divide the oscillation signal DCO_OUT to obtain the feedback clock signal CLK_DIV.
  • a sigma-delta modulator is configured to receive the frequency control word FCW and generate a frequency division control word SDM_OUT of the feedback frequency divider DIV based on the frequency control word FCW.
  • the correcting means obtains a time domain deviation TDC_INX between the reference clock signal CLK_REF and the feedback clock signal CLK_DIV based on the frequency control word FCW and the frequency division control word SDM_OUT, and based on the time domain deviation TDC_INX
  • the digital signal TDC_OUT is compensated to obtain the correction signal TDC_CAL.
  • the calibration device includes a measurer, a calculator, and a compensator.
  • the measurer in the calibration apparatus of FIG. 1 is configured to obtain a time domain deviation TDC_INX between the reference clock signal CLK_REF and the feedback clock signal CLK_DIV based on the frequency control word FCW and the frequency division control word SDM_OUT.
  • the time domain deviation TDC_INX is the theoretical input signal of the TDC.
  • the amount of time for the instantaneous input of the TDC can be calculated from the period T DCO_OUT of the output signal DCO_OUT at the frequency point and the integral value of the difference value N QERR [k] of the transient division value of the DIV and the system nominal division value. .
  • FIG. 2 is a phase-correction diagram of the digital fractional phase-locked loop.
  • the feedback clock signal CLK_DIV is controlled by the Sigma-Delta modulator, and its transient period will be in the locked phase of the phase-locked loop. There are regular changes.
  • the instantaneous period of the reference clock signal CLK_REF is stable.
  • the input at the kth sampling instant is determined by the absolute time of the active edge (eg, rising edge) of the reference clock CLK_REF and the feedback clock CLK_DIV, that is, the input time of the TDC at the kth sampling time point.
  • the quantity is:
  • T TDC [k] t DIV [k]-t REF [k] (2)
  • t DIV [k] is the absolute time of the kth sampling time point CLK_DIV
  • t REF [k] is the absolute time of the kth sampling time point CLK_REF signal.
  • Absolute time is the time in the usual sense. Absolute time is different from relative time. Relative time indicates the time difference.
  • t DIV [k] and t REF [k] can be expressed as:
  • N DIV [k] is the instantaneous division ratio of the kth time point DIV, that is, the current division ratio of the kth time point DIV.
  • This division ratio is controlled by the Sigma-Delta modulator and will change regularly over time. In theory, this division ratio value can be broken down into two parts:
  • N DIV [k] N NORM +N QERR [k] (5)
  • N NORM is the frequency division ratio of the digital fractional phase-locked loop nominal, namely:
  • N NORM is a non-integer. Bringing equations (5) and (6) into equation (3), you can get:
  • the TDC instantaneous input time amount (corresponding to the specific value of the time domain deviation TDC_INX at a certain time) is independent of the operating frequency of the TDC, but the applicant's research finds that the frequency is different.
  • the calibration accuracy obtained by the points is different. Therefore, in practical applications, in order to improve the accuracy of the nonlinear correction, and also to reduce the cost of the solution implementation, the preset frequency point can be selected for measurement.
  • the basic basis for the frequency point selection is: 1 selected
  • the frequency point should be such that the respective input time quantities in the sequence of the TDC (including the input sequence and the output sequence) are distributed over a sufficiently large range such that each value in the input sequence (the time domain sequence corresponding to the immediate domain deviation TDC_INX) a corresponding output sequence (ie, a digital signal pair output by the time-to-digital converter)
  • the value in the time domain sequence of the response satisfies the constitutional condition of the transfer function of the TDC, that is, the nonlinear characteristic of the TDC can be sufficiently observed at the frequency point
  • 2 the measurement data obtained at the selected frequency point can be as Simplify subsequent calculation operations.
  • the structure of the measurer is as shown in FIG. 3, and includes an adder, an integrator, and a multiplier.
  • the value of the FCW input at the preset frequency point is the frequency division ratio N NORM
  • the signal SDM_OUT is the output signal of the Sigma-Delta modulator at the preset frequency point, and the value thereof is the feedback frequency divider DIV.
  • Instantaneous frequency division ratio N DIV [k]. Enter the value of the negative FCW (refer to the prior art for the specific operation mode of FCW negative) and the value of the SDM_OUT signal into the adder, that is, get N QERR [k], and input N QERR [k] into the integrator.
  • T DCO_OUT can be obtained by measuring the DCO_OUT by the measuring device, or can be stored in advance in a storage medium in the measuring device (not shown in FIG. 3). It can be seen that the input measurement unit final output signal TDC_INX is the input time amount T TDC [k] of the TDC at the preset frequency point and the kth sampling time point.
  • the measurer performs measurement at a plurality of sampling time points respectively, and an input sequence including K sampling time points as shown in FIG. 4 (ie, the reference clock signal CLK measured by K sampling points) can be obtained.
  • -_REF and the time domain deviation between the feedback clock signal CLK_DIV) the correspondence between the input sequence and the output sequence is as shown in FIG. 4:
  • the calculator in the correction device of FIG. 1 can be used to estimate the nonlinear error from the time domain deviation TDC_INX to the digital signal TDC_OUT, and according to The nonlinear error generates a lookup table (LUT) capable of compensating the nonlinear error, and the specific lookup table generation process includes:
  • Input data sorting As can be seen from the sequence shown in Figure 4, due to the control of the sigma-delta modulator in the fractional phase-locked loop, the data in the input sequence is not monotonic and does not directly reflect the TDC module. Transfer function relationship. Therefore, after the input module obtains the input sequence, the input sequence is sorted according to the order of the values from large to small:
  • TDC_INX x TDC [1], x TDC [2],...,x TDC [m-1],x TDC [m],...,x TDC [M] (9)
  • TDC_OUT y TDC [1], y TDC [2],...,y TDC [m-1],y TDC [m],...,y TDC [M] (10)
  • (9) is an input value of TDC from small to large, and (10) is an output value one-to-one corresponding to the input value in (9).
  • Transfer function composition After the above sorting and averaging processing, the input sequence and the output sequence of the TDC obtained from the measurement module can be arranged into a form that can characterize the TDC transfer function.
  • This transfer function can be represented by the function F:
  • the transfer function curve of TDC is shown in Fig. 5, in which black solid lines represent averaged data and gray fills represent sorted data.
  • Linear regression calculation As can be seen from Figure 5, the nonlinear characteristics between the TDC input and output. In order to compensate for the nonlinear characteristic, in the present embodiment, the linear regression calculation is performed on the transfer function, that is, the linear approximation expression of the transfer function is fitted according to the nonlinear function, and the difference between the actual data and the linear approximation data is calculated.
  • the evaluation of the linearity error is not necessarily achieved by linear regression calculation or nonlinear function fitting.
  • other methods of evaluating the nonlinearity between input-output of a digital signal circuit can also be provided in the prior art.
  • the linear error evaluation method is not limited in this embodiment.
  • the nonlinear error function characterizes the difference between the TDC transfer function and its linear approximation function, which defines the nonlinearity of the TDC transfer function. It can be seen from the nonlinear error function shown in Fig. 7 that the corresponding nonlinear error value is also determined for the input value of the TDC. If this error value is compensated in the system, a linear TDC transmission characteristic can be fitted at the TDC output to improve the linearity of the TDC.
  • the above error function can be set in the form of a table in the mapping unit
  • the mapping unit determines a nonlinear compensation value corresponding to the time domain deviation by a certain mapping relationship to compensate for nonlinearity of the phase locked loop.
  • the error function is therefore stored in the mapping unit of the compensator in the form of a mapping relationship.
  • a table such as that described in Table 1 can be set:
  • the previously described calculator is not a required component of an embodiment of the invention.
  • the function of the calculator is simply to obtain the lookup table and to enter the lookup table into the mapping unit in the compensator that follows. If the calculator does not exist in the correction device, the mapping unit may also preset the lookup table.
  • the setting of the lookup table can be set by those skilled in the art based on experience and in combination with actual measurements.
  • the lookup table may be specifically preset in the mapping unit in a circuit form.
  • the compensator in the calibration apparatus of FIG. 1 queries according to the theoretical input value of the TDC measured by the measurement measurer (ie, the time domain deviation between the reference clock signal CLK_REF and the feedback clock signal CLK_DIV)
  • the lookup table determines the compensation value corresponding to the theoretical input value and compensates for the output signal of the TDC.
  • the mapping unit determines, by the mapping relationship, a nonlinear compensation value corresponding to the time domain deviation. For example, the mapping unit stores a lookup table. After obtaining the theoretical input value of the TDC at the sampling time k from the measuring device, the mapping unit determines and outputs the nonlinear compensation value TDC_ERR corresponding to the input value by querying the lookup table. The adder adds a negative (take negative value see prior art) compensation value to the output sequence TDC_OUT of the TDC to obtain a compensated output sequence, which is specifically the value of the correction signal TDC_CAL.
  • the value of the input value of the TDC is related to the frequency value of the phase-locked loop output. Different output frequency values, TDC input values are also different. Since the nonlinear characteristics of the TDC are relatively stable, it is not necessary to make different lookup tables for different output frequency points. In this case, for input values that are not in the lookup table, a table lookup operation can be performed by linear interpolation. For example, for an input value x' TDC of any TDC, this value is not within a limited set of discrete input values of an existing lookup table, ie:
  • the linear interpolation method can be used to realize the table lookup of any TDC input value. That is to say, the calibration apparatus described in this embodiment only needs to make a set of lookup tables on the output frequency point of a specific phase-locked loop to meet the needs of the operation of each output frequency point of the phase-locked loop system. Therefore, the lookup table related search algorithm provided in this embodiment can be flexibly adjusted.
  • the generated lookup table may not need to be updated.
  • the lookup table can also be updated, which can be performed by the calculator, but usually no update is required. If the lookup table is not updatable, as described above, the lookup table can be preset within the mapping unit so that the calculator can be omitted.
  • the lookup table method is only an implementation method in which the mapping unit obtains the nonlinear compensation value.
  • the mapping unit may also implement the calculation of the nonlinear compensation value by means of a logic operation circuit, without necessarily being implemented by the lookup table function shown in FIG.
  • the logic operation circuit may include a plurality of transistors or logic gates, and the mapping circuit is implemented in the mapping unit in the form of an algorithm circuit, and the algorithm circuit in the mapping unit acquires a theoretical input value (the time domain deviation) The calculation is performed to calculate the nonlinear compensation value, which is not limited in this embodiment.
  • the digital fractional phase-locked loop shown in FIG. 1 may further include a controller (not shown in FIG. 1) for turning off the measurer and the calculator after the calculator obtains the nonlinear error, Achieve the goal of reducing power consumption.
  • FIG. 9 is a schematic diagram showing the effect of the digital fractional frequency-locked phase-locked loop shown in FIG. 1 on noise improvement. It can be seen from the figure that the phase noise of the system of the TDC is obvious after being corrected by the calibration apparatus described in this embodiment. The reduction is, and closer to, the ideal system phase noise of the TDC.
  • each device or part in the digital fractional phase-locked loop mentioned in this embodiment may include a plurality of transistors to perform corresponding signal processing.
  • the digital fractional phase-locked loop can be included in a chip composed of a plurality of logic gate circuits or transistor circuits, such as a radio frequency chip (RFIC), which can be used for various communication devices such as a wireless base station or a wireless terminal.
  • RFIC radio frequency chip
  • digital fractional frequency-locked phase-locked loop in this embodiment can also implement the function of integer frequency division. Therefore, the embodiment of the present invention can be applied to cover the integer frequency division and the fractional frequency division. Digital crossover phase-locked loop.

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  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

本申请提供了一种数字分频锁相环，包括：时间数字转换器、数字环路滤波器、数字控振荡器、反馈分频器、Sigma-Delta调制器和校正装置。其中，校正装置基于频率控制字和Sigma-Delta调制器生成的分频控制字补偿时间数字转换器输出的数字信号以得到校正信号。数字环路滤波器对校正信号进行数字滤波以得到振荡器频率控制信号，作为数字控振荡器的输出信号。因为使用校正装置基于频率控制字和分频控制字对时间数字转换器输出的数字信号进行补偿，而无需对时间数字转换器改进，所以，能以较小的实施代价实现数字分频锁相环的非线性校正。

Description

数字分频锁相环
本申请要求于2016年04月25日提交中国专利局、申请号为201610260615.7、发明名称为“数字分频锁相环”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及电子信息领域，尤其涉及一种数字分频锁相环。
背景技术
无线射频(Radio Frequency，RF)收发信机中，广泛采用基于锁相环(Phase-Locked Loop，PLL)结构的频率综合器，用以产生本地振荡(Local Oscillator，LO)信号，从而用于完成射频信号的频率搬移操作。由于锁定时间、积分相位噪声以及设计灵活性等几个方面的优势，可实现不仅整数分频也可实现小数分频的数字小数分频锁相环相对于整数分频锁相环，得到了更加广泛的应用。
在数字小数分频锁相环中，时间数字转换器(Time-to-Digital Converter，TDC)作为重要的模拟组件之一，其线性性能是影响整个锁相环系统线性性能的主因。因为越接近线性，噪声最小，因此，提升TDC的线性性能，是确保数字小数分频锁相环维持在低噪声水平的关键因素。
而对于目前常见的TDC结构，影响其线性度的原因主要包括器件失配、版图设计失配等几个方面，为了提升TDC的线性度，通常需要在功耗、面积及复杂度等方面付出比较大的代价，所以实施难度很大。
发明内容
本申请提供了一种数字分频锁相环及其非线性校正方法，目的在于以较小的实施代价实现数字分频锁相环的非线性校正。
为了实现上述目的，本申请提供了以下技术方案：
本申请的第一方面提供了一种数字分频锁相环，包括：时间数字转换器、数字环路滤波器、数字控振荡器、反馈分频器、Sigma-Delta调制器和校正装置。其中，所述时间数字转换器用于接收参考时钟信号和反馈时钟信号，鉴别所述参考时钟信号和所述反馈时钟信号之间的相位差以得到指示该相位差的数字信号。所述校正装置用于接收所述数字信号、频率控制字和所述Sigma-Delta调制器生成的分频控制字，并基于所述频率控制字和所述分频控制字补偿所述数字信号以得到校正信号。所述数字环路滤波器用于接收所述校正信号，并对所述校正信号进行数字滤波以得到振荡器频率控制信号。所述数字控振荡器用于接收所述振荡器频率控制信号，并在所述振荡器频率控制信号的控制下生成振荡信号作为所述数字分频锁相环的输出信号。所述反馈分频器用于对所述振荡信号进行分频以得到所述反馈时钟信号。所述Sigma-Delta调制器 用于接收所述频率控制字，并基于所述频率控制字生成所述分频控制字。其中，所述频率控制字用于指示所述数字分频锁相环的标称分频值，所述标称分频值为所述振荡信号的频率与所述参考时钟信号的频率的比值，所述分频控制字用于指示所述反馈分频器的实际分频值，该实际分频值为所述振荡信号的频率与所述反馈时钟信号的频率的比值。因为使用校正装置基于频率控制字和分频控制字对时间数字转换器输出的数字信号进行补偿，而无需对时间数字转换器进行改进，所以，能够以较小的实施代价实现数字分频锁相环的非线性校正。
在一个实现方式中，所述校正装置用于基于所述频率控制字和所述分频控制字得到所述参考时钟信号和所述反馈时钟信号之间的时域偏差，并基于所述时域偏差补偿所述数字信号以得到所述校正信号。校正装置依据参考时钟信号和所述反馈时钟信号之间的时域偏差对数字信号进行补偿，简单易行，可实施性高。
在一个实现方式中，所述校正装置包括：测量器，用于基于所述频率控制字和所述分频控制字得到所述参考时钟信号和所述反馈时钟信号之间的时域偏差，以及补偿器，用于通过映射关系确定与所述时域偏差对应的非线性补偿值，并利用所述非线性补偿值补偿所述数字信号以得到所述校正信号。
在一个实现方式中，所述补偿器包括：映射单元，用于通过所述映射关系确定与所述时域偏差对应的非线性补偿值，以及校准器，用于利用所述非线性补偿值补偿所述数字信号以得到所述校正信号。
在一个实现方式中，所述校准器包括加法器，用于将所述非线性补偿值的负值与所述数字信号相加以得到所述校正信号。
在一个实现方式中，所述映射关系以查找表的方式体现。
在一个实现方式中，所述查找表被预置在所述映射单元中。
在一个实现方式中，所述校正装置还包括计算器，用于估计从所述时域偏差到所述数字信号的所述非线性误差，并根据所述非线性误差生成能够补偿所述非线性误差的所述查找表。
在一个实现方式中，所述映射单元还用于，确定所述时域偏差不存在所述查找表中。所述计算器还用于，使用线性插值的方式获得所述时域偏差对应的非线性补偿值，并将获得的非线性补偿值发给所述校准器。
在一个实现方式中，数字分频锁相环还包括：控制器，用于在所述计算器得到所述非线性误差后，关闭所述测量器和所述计算器。因为在得到所述非线性误差后，测量器和计算器的功能已经完成，在此情况下，关闭两者，能够节省功耗。
在一个实现方式中，所述测量器包括加法器、积分器和乘法器。其中，所述加法器用于将所述频率控制字的负值与所述分频控制字相加，以得到所述分频控制字所指示的所述反馈分频器的实际分频值和所述频率控制字所指示的所述数字分频锁相环的标称分频值的差值。所述积分器用于对所述差值做时域积分得到积分值。所述乘法器用于将所述积分值与所述振荡信号的周期相乘得到所述时域偏差。
在一个实现方式中，所述数字分频锁相环是数字小数分频锁相环。
在一个实现方式中，所述校正装置用于在预设频点接收所述数字信号，频率控制字和所述Sigma-Delta调制器生成的分频控制字，并基于所述频率控制字和所述分频控制字补偿所述数字信号以得到在所述预设频点的校正信号。其中，预设频点的选择依据为：所述预设频点使得所述频率控制字和所述分频控制字的时域偏差在预设范围内，所述预设范围使得所述时域偏差与所述数字信号满足所述TDC的传输函数的构成条件。在预设频点进行校正，能够提高非线性校正的精度，同时也为了降低方案实现的代价。
本申请的第二方面提供了一种芯片，包括多个逻辑门电路或晶体管电路，以及上述数字分频锁相环。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例公开的数字小数分频锁相环的结构示意图；
图2为本申请实施例公开的数字小数分频锁相环的鉴相示意图；
图3为本申请实施例公开的数字小数分频锁相环的测量器的结构示意图；
图4为本申请实施例公开的数字小数分频锁相环的输入序列与输出序列的示意图；
图5为本申请实施例公开的数字小数分频锁相环的TDC的传输函数曲线的示意图；
图6为本申请实施例公开的数字小数分频锁相环的TDC的线性近似函数与传输函数的关系示意图；
图7为本申请实施例公开的数字小数分频锁相环的TDC的非线性误差函数的关系示意图；
图8为本申请实施例公开的数字小数分频锁相环的补偿器的结构示意图；
图9为本申请实施例公开的数字小数分频锁相环对于噪声的改善作用的示意图。
具体实施方式
图1为本申请实施例公开的数字小数分频锁相环的结构示意图，包括TDC、数字环路滤波器(Digital Loop Filter，DLF)、数字振荡器(Digital Controlled Oscillator，DCO)、反馈分频器(Feedback Divider，DIV)、Sigma-Delta调制器SDM和校正装置。
具体地，TDC用于接收参考时钟信号CLK_REF和反馈时钟信号CLK_DIV并鉴别CLK-_REF与CLK_DIV之间的相位差，以得到指示该相位差的数字信号TDC_OUT。
校正装置用于接收所述数字信号TDC_OUT、频率控制字FCW和所述SDM生成的分频控制字SDM_OUT，并基于所述频率控制字FCW和所述分频控制字SDM_OUT补偿所述数字信号TDC_OUT以得到校正信号TDC_CAL。
其中，所述频率控制字FCW用于指示所述数字分频锁相环的标称分频值，所述标 称分频值为所述振荡信号F_DCO的频率与所述参考时钟信号CLK_REF的频率的比值，所述分频控制字FCW用于指示所述反馈分频器DIV的实际分频值，该实际分频值为所述振荡信号F_DCO的频率与所述反馈时钟信号CLK_DIV的频率的比值。
DLF用于接收所述校正信号TDC_CAL，并对所述校正信号进行数字滤波，以得到振荡器频率控制信号DLF_OUT。
DCO用于接收振荡器频率控制信号DLF_OUT，并在DLF_OUT的控制下生成振荡信号DCO_OUT作为所述数字分频锁相环的输出信号。
反馈分频器DIV用于对所述振荡信号DCO_OUT进行分频以得到所述反馈时钟信号CLK_DIV。
Sigma-Delta调制器用于接收所述频率控制字FCW，并基于所述频率控制字FCW生成反馈分频器DIV的分频控制字SDM_OUT。
具体地，校正装置基于所述频率控制字FCW和所述分频控制字SDM_OUT得到所述参考时钟信号CLK_REF和所述反馈时钟信号CLK_DIV之间的时域偏差TDC_INX，并基于所述时域偏差TDC_INX补偿所述数字信号TDC_OUT以得到所述校正信号TDC_CAL。在一个具体的实施例中，如图1所示，校正装置中包括测量器、计算器和补偿器。
其中，图1的校正装置中的测量器用于基于所述频率控制字FCW和所述分频控制字SDM_OUT得到所述参考时钟信号CLK_REF和所述反馈时钟信号CLK_DIV之间的时域偏差TDC_INX，所述时域偏差TDC_INX即为TDC的理论输入信号。
申请人在研究的过程中得出结论：当小数分频锁相环锁定在一个特定频率点时，对于第k个时刻点，TDC瞬时输入时间量TTDC[k](即TDC_INX所表示的值)为：
Figure PCTCN2017079446-appb-000001
也就是说，TDC瞬时输入的时间量可由该频率点的输出信号DCO_OUT的周期TDCO_OUT及DIV的瞬态分频值和系统标称分频值的差值NQERR[k]的积分值计算出来。
上述结论的推导过程如下：
图2为数字小数分频锁相环的鉴相示意图，从图2中可以看出，反馈时钟信号CLK_DIV由于受到Sigma-Delta调制器的控制，在锁相环锁定工作状态下，其瞬时周期会有规律的变化。而参考时钟信号CLK_REF的瞬时周期是稳定不变的。
对于TDC来说，在第k个采样时刻的输入是由该时刻参考时钟CLK_REF和反馈时钟CLK_DIV有效沿(例如上升沿)的绝对时间决定的，即在第k个采样时刻点，TDC的输入时间量为：
TTDC[k]＝tDIV[k]-tREF[k]   (2)
其中，tDIV[k]为第k个采样时刻点CLK_DIV的绝对时间，tREF[k]为第k个采样时刻点CLK_REF信号的绝对时间。绝对时间即是通常意义上所说的时间，绝对时间与相对时 间不同，相对时间指示的是时间差。tDIV[k]和tREF[k]分别可以表示为：
tDIV[k]＝tDIV[k-1]+TDCO_OUT×NDIV[k]   (3)
tREF[k]＝TREF×k   (4)
其中，NDIV[k]是第k个时刻点DIV的瞬时分频比率，也就是第k个时刻点DIV的当前分频比。此分频比率受Sigma-Delta调制器控制，会随着时间有规律的变化。理论上，可将此分频比率数值分解为两部分：
NDIV[k]＝NNORM+NQERR[k]   (5)
其中，NNORM为数字小数分频锁相环标称的分频比，即：
Figure PCTCN2017079446-appb-000002
由数字小数分频锁相环的原理可知，NNORM为一个非整数。将式(5)、(6)带入式(3)中，可得：
Figure PCTCN2017079446-appb-000003
将其中的递归操作分解成积分模式，容易得到：
Figure PCTCN2017079446-appb-000004
将上式及式(7)带入式(5)中，可得到在第k个采样时刻点，TDC瞬时输入时间量为：
Figure PCTCN2017079446-appb-000005
需要说明的是，从上述推导过程可以看出，TDC瞬时输入时间量(对应时域偏差TDC_INX在某个时刻的具体取值)与TDC的工作频率无关，但是，申请人研究发现，在不同频点得到的校正精度不同，所以，实际应用中，为了提高非线性校正的精度，同时也为了降低方案实现的代价，可以选择预设频点进行测量，频点选择的基本依据为：①选定的频率点应当使得TDC的序列(包括输入序列和输出序列)中的各个输入时间量分布在足够大的范围内，这个范围使得输入序列(即时域偏差TDC_INX对应的时域序列)中的各个数值与其对应的输出序列(即所述时间数字转换器输出的数字信号对 应的时域序列)中的数值满足所述TDC的传输函数的构成条件，即在此频率点上能够充分观察TDC的非线性特征；②在选定频点上获得的测量数据，能够尽可能的简化后续的计算操作。
基于上式(1)，测量器的结构如图3所示，包括加法器、积分器和乘法器。图3中，在预设频点输入的FCW的值即为分频比NNORM，信号SDM_OUT为Sigma-Delta调制器在此预设频点的输出信号，其值即为反馈分频器DIV的瞬时分频比NDIV[k]。将负的FCW的值(FCW取负的具体操作方式参见现有技术)和SDM_OUT信号的值输入加法器中，即得到NQERR[k]，将NQERR[k]输入积分器中得到
Figure PCTCN2017079446-appb-000006
再通过乘法器得到
Figure PCTCN2017079446-appb-000007
其中，TDCO_OUT可以由测量器测量DCO_OUT得到，也可以预先存储在测量器中的存储介质中(图3中未画出)。可见，输入测量单元最终输出信号TDC_INX为TDC在预设频点及第k个采样时刻点的输入时间量TTDC[k]。
基于上述测量过程，测量器在多个采样时刻点分别进行测量，可以得到如图4所示的包括K个采样时刻点的、输入序列(即K个采样点测量到的所述参考时钟信号CLK-_REF和所述反馈时钟信号CLK_DIV之间的时域偏差)，输入序列与输出序列的对应关系如图4所示：
输入序列：TDC_INX∈{TTDC[1],TTDC[2],...,TTDC[k-1],TTDC[k],...,TTDC[K]}
输出序列：TDC_OUT∈{DTDC[1],DTDC[2],...,DTDC[k-1],DTDC[k],...,DTDC[K]}
在测量器得到TDC在预设频点的输入序列后，图1的校正装置中的计算器可以用来估计从所述时域偏差TDC_INX到所述数字信号TDC_OUT的所述非线性误差，并根据所述非线性误差生成能够补偿所述非线性误差的查找表(LUT)，具体的查找表生成过程包括：
1、输入数据排序：从图4所示的序列可以看出，由于小数锁相环中Sigma-Delta调制器的控制作用，输入序列中的各个数据并不具备单调性，也没有直接反映TDC模块的传输函数关系。所以，计算模块在获得输入序列后，按照数值从大到小的顺序，对输入序列进行排序：
TDC_INX＝xTDC[1],xTDC[2],...,xTDC[m-1],xTDC[m],...,xTDC[M]   (9)
TDC_OUT＝yTDC[1],yTDC[2],...,yTDC[m-1],yTDC[m],...,yTDC[M]   (10)
其中，(9)为从小到大的TDC的输入值，(10)为与(9)中的输入值一一对应的输出值。
2、平均化处理：测量模块中获得的依时间次序排列的数据中，可能出现重复的数据，因此本实施例中，将相同的TDC_INX值对应的TDC_OUT值做平均化处理。例如，如果原始数据中存在N个等值的输入数据：
xTDC[m]＝TTDC[k1]＝TTDC[k2]＝,...,＝TTDC[kN]   (11)
则对应的TDC_OUT为：
Figure PCTCN2017079446-appb-000008
3、传输函数构成：经过上述排序及平均化处理，可将从测量模块中获得的TDC的输入序列和输出序列排列成可以表征TDC传输函数的形式。这个传输函数可以用函数F表示：
yTDC＝F(xTDC)   (13)
TDC的传输函数曲线如图5所示，其中，黑色实线表示平均化数据，灰色填充表示排序数据。
4、线性回归计算：从图5可以看出，TDC输入与输出之间的非线性特征。为了补偿非线性特征，本实施例中，先对传输函数进行线性回归计算，即根据非线性函数拟合出传输函数的线性近似表达式，再计算出实际数据与线性近似数据的差值。当然，可以理解，对线性误差的评估不一定通过线性回归计算或非线性函数拟合来实现，例如现有技术中也可以提供其他如何评估一个数字信号电路的输入-输出之间的非线性的线性误差评估方法，本实施例对此不作限定。
假设TDC传输函数的线性近似可以用函数
Figure PCTCN2017079446-appb-000009
表示：
Figure PCTCN2017079446-appb-000010
其中α即为TDC的线性增益，β为偏移量。得到的线性近似函数与传输函数的关系如图6所示。
计算TDC实际的传输函数与线性近似函数的差值，即可获得TDC的非线性误差函数，如图7所示：
Figure PCTCN2017079446-appb-000011
从式(15)可知，非线性误差函数表征的是TDC传输函数与其线性近似函数之间的差值，即定义了TDC传输函数的非线性的特性。从图7所示的非线性误差函数可以看出，对于TDC特定的输入值，其对应的非线性误差值也是确定的。如果在系统中对此误差值进行补偿，即可在TDC输出端拟合出线性的TDC传输特性，从而改善TDC的线性特性。
5、生成查找表：芯片设计中，可以将上述误差函数以表格的形式设置在映射单元 中，该映射单元通过一定的映射关系确定与所述时域偏差对应的非线性补偿值以补偿所述锁相环的非线性。因此误差函数以映射关系的形式存储在所述补偿器的映射单元中。可设置例如表1所述的表格：
表1
输入值 输出值
xTDC[1] εTDC[1]
xTDC[2] εTDC[2]
…… ……
xTDC[m-1] εTDC[m-1]
xTDC[m] εTDC[m]
…… ……
xTDC[M] εTDC[M]
可替换地，之前所述的计算器并不是本发明实施例所必需的部件。计算器的功能仅仅是为了获取所述查找表并将所述查找表输入到后面的补偿器中的映射单元中。如果校正装置中不存在所述计算器，则所述映射单元也可以被预置所述查找表。该查找表的设置可以由本领域技术人员依照经验和结合实际测量和来设定。该查找表可以具体以电路形式被预置在所述映射单元中。
在生成查找表后，图1的校正装置中的补偿器依据测量测量器测量得到的TDC的理论输入值(即所述参考时钟信号CLK_REF和所述反馈时钟信号CLK_DIV之间的时域偏差)查询查找表，确定与理论输入值对应的补偿值，对TDC的输出信号进行补偿。
图8为补偿器的结构示意图的示例，包括映射单元和校准器，具体地，校准器包括图8中所示的加法器。其中映射单元通过所述映射关系确定与所述时域偏差对应的非线性补偿值。例如映射单元中存储有查找表，在从测量器获得TDC在采样时刻k的理论输入值后，映射单元通过查询查找表，确定与输入值对应的非线性补偿值TDC_ERR并输出。加法器将负的(取负值参见现有技术)补偿值与TDC的输出序列TDC_OUT相加，得到补偿后的输出序列，该补偿后的输出序列具体是校正信号TDC_CAL的取值。
需要说明的是，对于数字小数分频锁相环，TDC的输入值的取值，与锁相环输出的频率值有关。不同的输出频率值，TDC的输入值也不同。由于TDC的非线性特征是比较稳定的，因此可以不必针对不同的输出频率点，制作不同的查找表。在这种情况下，对于不在查找表中的输入值，可采用线性插值的方式进行查表操作。例如，对于任意TDC的输入值x′TDC，此数值不在已有查找表有限个离散的输入值集合内，即：
Figure PCTCN2017079446-appb-000012
但查找表输入值集合中，必然存在两个连续值，使得x′TDC在这两个值之间：
xTDC[i]＜x′TDC＜xTDC[i+1]   (17)
对于此输入值，其对应的输出值可通过线性插值方式获得：
Figure PCTCN2017079446-appb-000013
根据上式可知，采用线性插值的方法，即可实现任意TDC输入值的查表。也就是说，本实施例所述的校正装置，仅仅需要在某一特定锁相环输出频率点上制作一套查找表，即可满足锁相环系统各个输出频率点工作的需要。因此，本实施例提供的查找表相关查找算法是可以灵活调整的。
另外，因为TDC的非线性特征是比较稳定的，所以，生成的查找表可以无需更新。当然查找表也可以被更新，该更新可以由所述计算器执行，但通常情况下无需做更新。如果查找表不可更新，则如前所述，映射单元内可以预设所述查找表，使得计算器可以被省略。
当然查找表方式只是映射单元获取非线性补偿值的一种实现方式。可替换地，映射单元也可以通过逻辑运算电路的方式实现计算非线性补偿值，而不一定通过图8所示的查找表功能来实现。具体地，逻辑运算电路可以是包括大量晶体管或逻辑门，通过将所述映射关系以算法电路的形式实现在映射单元中，映射单元中的所述算法电路获取理论输入值(所述时域偏差)执行运算来计算得到非线性补偿值，本实施例对此不作限制。
图1所示的数字小数分频锁相环中还可以包括控制器(图1中未画出)，用于在所述计算器得到所述非线性误差后，关闭测量器和计算器，以实现降低功耗的目的。
图9为图1所示的数字小数分频锁相环对于噪声的改善作用的示意图，从图中可以看出，经过本实施例所述的校正装置校正后，TDC的系统相位噪声有了明显的降低，并且，更加接近TDC的理想系统相位噪声。
需要说明的是，本实施例中提到的数字小数分频锁相环中的各个器件或部分可以包括多个晶体管以执行相应信号处理。该数字小数分频锁相环可以包括在一个由多个逻辑门电路或晶体管电路构成芯片，如射频芯片(RFIC)内，该RFIC可以被用于例如无线基站或无线终端等各类通信设备。
需要说明的是，本实施例所述的数字小数分频锁相环，还可以实现整数分频的功能，因此本发明实施例是是可以推广应用至涵盖整数分频和小数分频在内的数字分频锁相环。

Claims (12)

  1. 一种数字分频锁相环，其特征在于，包括：时间数字转换器、数字环路滤波器、数字控振荡器、反馈分频器、Sigma-Delta调制器和校正装置；其中：
    所述时间数字转换器用于接收参考时钟信号和反馈时钟信号，鉴别所述参考时钟信号和所述反馈时钟信号之间的相位差以得到指示该相位差的数字信号；
    所述校正装置用于接收所述数字信号、频率控制字和所述Sigma-Delta调制器生成的分频控制字，并基于所述频率控制字和所述分频控制字补偿所述数字信号以得到校正信号，所述频率控制字用于指示所述数字分频锁相环的标称分频值，所述标称分频值为所述振荡信号的频率与所述参考时钟信号的频率的比值，所述分频控制字用于指示所述反馈分频器的实际分频值，该实际分频值为所述振荡信号的频率与所述反馈时钟信号的频率的比值；
    所述数字环路滤波器用于接收所述校正信号，并对所述校正信号进行数字滤波以得到振荡器频率控制信号；
    所述数字控振荡器用于接收所述振荡器频率控制信号，并在所述振荡器频率控制信号的控制下生成振荡信号作为所述数字分频锁相环的输出信号；
    所述反馈分频器用于对所述振荡信号进行分频以得到所述反馈时钟信号；
    所述Sigma-Delta调制器用于接收所述频率控制字，并基于所述频率控制字生成所述分频控制字。
  2. 根据权利要求1所述的数字分频锁相环，其特征在于，所述校正装置用于基于所述频率控制字和所述分频控制字得到所述参考时钟信号和所述反馈时钟信号之间的时域偏差，并基于所述时域偏差补偿所述数字信号以得到所述校正信号。
  3. 根据权利要求2所述的数字分频锁相环，其特征在于，所述校正装置包括：
    测量器，用于基于所述频率控制字和所述分频控制字得到所述参考时钟信号和所述反馈时钟信号之间的时域偏差；
    补偿器，用于通过映射关系确定与所述时域偏差对应的非线性补偿值，并利用所述非线性补偿值补偿所述数字信号以得到所述校正信号。
  4. 根据权利要求3所述的数字分频锁相环，其特征在于，所述补偿器包括：
    映射单元，用于通过所述映射关系确定与所述时域偏差对应的非线性补偿值；
    校准器，用于利用所述非线性补偿值补偿所述数字信号以得到所述校正信号。
  5. 根据权利要求4所述的数字分频锁相环，其特征在于，所述校准器包括加法器，用于将所述非线性补偿值的负值与所述数字信号相加以得到所述校正信号。
  6. 根据权利要求4或5所述的数字分频锁相环，其特征在于，所述映射关系以查找表的方式体现。
  7. 根据权利要求6所述的数字分频锁相环，其特征在于，所述查找表被预置在所述映射单元中。
  8. 根据权利要求6所述的数字分频锁相环，其特征在于，所述校正装置还包括计 算器，用于估计从所述时域偏差到所述数字信号的所述非线性误差，并根据所述非线性误差生成能够补偿所述非线性误差的所述查找表。
  9. 根据权利要求8所述的数字分频锁相环，其特征在于，还包括：
    控制器，用于在所述计算器得到所述非线性误差后，关闭所述测量器和所述计算器。
  10. 根据权利要求3至9中任一项所述的数字分频锁相环，其特征在于，所述测量器包括加法器、积分器和乘法器；其中，
    所述加法器用于将所述频率控制字的负值与所述分频控制字相加，以得到所述分频控制字所指示的所述反馈分频器的实际分频值和所述频率控制字所指示的所述数字分频锁相环的标称分频值的差值；
    所述积分器用于对所述差值做时域积分得到积分值；
    所述乘法器用于将所述积分值与所述振荡信号的周期相乘得到所述时域偏差。
  11. 根据权利要求1至10中任一项所述的数字分频锁相环，其特征在于，所述数字分频锁相环是数字小数分频锁相环。
  12. 一种芯片，包括多个逻辑门电路或晶体管电路，其特征在于，所述芯片包括根据权利要求1至11中任一项所述的数字分频锁相环。
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