WO2017181945A1 - Nand memory structure, method for forming same and three-dimensional memory structure - Google Patents

Nand memory structure, method for forming same and three-dimensional memory structure Download PDF

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Publication number
WO2017181945A1
WO2017181945A1 PCT/CN2017/080989 CN2017080989W WO2017181945A1 WO 2017181945 A1 WO2017181945 A1 WO 2017181945A1 CN 2017080989 W CN2017080989 W CN 2017080989W WO 2017181945 A1 WO2017181945 A1 WO 2017181945A1
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Prior art keywords
selection transistor
source selection
vertical channel
source
drain
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PCT/CN2017/080989
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English (en)
French (fr)
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Liyang PAN
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Tsinghua University
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Definitions

  • the present disclosure pertains to a field of information storage technology, and in particular relates to a method for forming a NAND memory, a NAND memory structure and a method for forming the same, and a three-dimensional memory array.
  • BiCS Bit Cost Scalable
  • Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory edited by H. Tanaka et al., and published by Symposium on VLSI Technology Digest of Technical Papers, pp. 14-15, dated on 2007; and [2] US7,852,675 whose title is Three Dimensional Stacked Nonvolatile Semiconductor Memory and which discloses a method and structure of arranging vertically the BICS.
  • US7,852,675 as shown in Fig.
  • a memory string with a traditional planar NAND structure is turned by 90 degree to arrange vertically, of which a bottom layer is a source selection transistor, a top layer is a bit line selection transistor and a middle layer is a word line.
  • a source of the structure is extended from a substrate.
  • a thin protection layer made of non-crystalline silicon is deposited after depositing ONO (silicon oxide-silicon nitride-silicon oxide) dielectric layer, and a polycrystalline channel is deposited after the ONO dielectric at the bottom is removed by etching.
  • ONO silicon oxide-silicon nitride-silicon oxide
  • this manufacture process requires steps of depositing the protection layer made of non-crystalline silicon, etching the ONO dielectric at the bottom and so on.As a result, it may cause a drop in ONO quality of a sidewall and an increasing in complexity of the manufacture process. Furthermore, it limits a reduction of channel size and an improvement of integration density.
  • a P-BiCS (pipe-shaped Bit Cost Scalable) technology is provided in the related art, shown as structures and equivalent circuits in Figs. 2 (1) , (2) , (3) and (4) .
  • related documents for example, there are three documents: [1] US7,983,084 titled by Three-dimensionally Stacked Nonvolatile Semiconductor Memory; [2] US8,199,573 titled by Nonvolatile Semiconductor Memory Device; and [3] Pipe-shaped BiCS Flash Memory with 16 Stacked Layers and Multi-Level-Cell Operation for Ultra High Density Storage Devices, edited by Ryota Katsumata et al., published by Symposium on VLSI Technology Digest of Technical Papers, pp.
  • a P-BiCS structure defines a U-shaped structure as cited "two memory columns, of which the upper ends are connected with BL and SL respectively, and the lower ends are connected with each other" , and further defines a connection structure as cited "a third conductive thin layer functions as a gate of the connection structure and joints of the two memory columns function as channels” .
  • a schematic diagram showing a process for forming the connection structure between the channel and the bottom region of the memory column is shown in Figs. 3 (1) , (2) and (3) . It can be seen that, it is difficult to achieve an active connection of the connection structure due to a close of an upper opening during the depositing process, which may cause a fail of the memory structure.
  • TCAT Transmissionbit Cell Array Transistor
  • Fig. 4 a TCAT (Terabit Cell Array Transistor) technology in some related arts, as shown in Fig. 4.
  • Fig. 4 there are three documents: [1] US8,344,385 titled by Vertical-type Semiconductor Device, which discloses a structure of TCAT and a flow of a gate replacement process; [2] US8,530,959 titled by Three-dimensional Semiconductor Memory Device; and [3] Vertical Cell Array using TCAT (Terabit Cell Array Transistor) Technology for Ultra High Density NAND Flash Memory, edited by Jaehoon Jang et al., published by Symposium on VLSI Technology Digest of Technical Papers, pp. 192-193, dated on 2009.
  • the TCAT technology is a manufacture process characteristic of "first channel and late gate” realized by the "gate replacement” technology. That is, first multilayer sacrificial gates are formed and a connection between a polycrystalline channel and a substrate is formed in a vertical hole. Then, the sacrificial gates are removed by etching and a final multilayer word line structure is formed by depositing an ONO/ANO gate dielectric and a metal gate.
  • the "gate replacement" process increases steps of depositing multiple layers of dielectric and etching, thus the complexity of the manufacture process is significant high.
  • Embodiments of the present disclosure seek to solve at least one of the problems existing in the related art to at least some extent. Therefore, there is a need to provide a method for forming a NAND memory structure by the present disclosure. With the method, a manufacture complexity and a manufacture cost may be reduced and an integration density may be improved.
  • the present disclosure further provides a NAND memory structure and a method for forming the NAND memory structure.
  • an aspect of the present disclosure provides a method for forming a NAND memory structure.
  • the method includes: forming a plurality of source selection transistors in a semiconductor substrate, in which each source selection transistor includes a gate of the source selection transistor arranged along a direction of X and formed on the semiconductor substrate, a source of the source selection transistor in a first doping type formed in the semiconductor substrate and arranged along the direction of X, and a drain of the source selection transistor in the first doping type formed in the semiconductor substrate; forming memory cells with a longitudinal stacked structure above the plurality of source selection transistors, in which each memory cell includes a vertical channel along a direction of Z, multilayer memory gate dielectric, a gate of a bit line selection transistor and a stacked word line both arranged horizontally along the direction of X and formed outside the vertical channel; and the drain of the source selection transistor contacts the multilayer memory gate dielectric located at the bottom of the vertical channel; forming a plurality of bit lines arranged along a direction of Y above
  • the breakdown voltage to the multilayer memory gate dielectric between the drain of the source selection transistor and the vertical channel to break down the multilayer memory gate dielectric, an electrical contact part between the drain of the source selection transistor and the vertical channel is formed. Therefore, it does not need to add a process of connecting with the channel, which reduces a manufacture complexity and a manufacture cost and contributes to reducing a channel aperture and improving an integration density.
  • the vertical channel is made of a single-crystalline semiconductor material or a polycrystalline semiconductor material.
  • the multilayer memory gate dielectric includes a barrier oxide layer, a silicon nitride trapping layer, and a tunnel oxide layer.
  • the multilayer memory gate dielectric includes a barrier oxide layer, a monolayer trapping layer or multilayer trapping layer with a high dielectric constant and a tunnel oxide layer.
  • applying, via the bit line and the drain of the source selection transistor, a breakdown voltage to the multilayer memory gate dielectric between the drain of the source selection transistor and the vertical channel specifically includes: connecting the bit line with the breakdown voltage, connecting the stacked word line and the gate of the bit line selection transistor with a high voltage and simultaneously grounding the source of the source selection transistor, and connecting the gate of the source selection transistor with a supply voltage, to apply the breakdown voltage to the multilayer memory gate dielectric between the drain of the source selection transistor and the vertical channel.
  • applying, via the bit line and the drain of the source selection transistor, a breakdown voltage to the multilayer memory gate dielectric between the drain of the source selection transistor and the vertical channel specifically includes: grounding the bit line, connecting the stacked word line and the gate of the bit line selection transistor with a supply voltage and simultaneously connecting the source of the source selection transistor with the breakdown voltage, and connecting the gate of the source selection transistor with a high voltage, to apply the breakdown voltage to the multilayer memory gate dielectric between the drain of the source selection transistor and the vertical channel.
  • applying, via the bit line and the drain of the source selection transistor, a breakdown voltage to the multilayer memory gate dielectric between the drain of the source selection transistor and the vertical channel specifically includes: grounding the bit line, connecting the stacked word line and the gate of the bit line selection transistor with a supply voltage and simultaneously suspending the source of the source selection transistor and the gate of the source selection transistor, and applying the breakdown voltage to the semiconductor substrate, to apply the breakdown voltage to the multilayer memory gate dielectric between the drain of the source selection transistor and the vertical channel.
  • the breakdown voltage or the high voltage is applied to the bit line or the gate of the bit line selection transistor in sequence by a scanning way, which may reduce an instant current.
  • the high voltage is equal to or greater than the breakdown voltage.
  • the NAND memory structure includes: memory cells with a longitudinal stacked structure, in which each memory cell includes a vertical channel along a direction of Z, multilayer memory gate dielectric, and a gate of a bit line selection transistor and a stacked word line both arranged horizontally along a direction of X and formed outside the vertical channel; a source selection transistor below the memory cells, in which the source selection transistor includes a gate of the source selection transistor arranged along the direction of X and formed on the semiconductor substrate, a source of the source selection transistor in a first doping type formed in a semiconductor substrate and arranged along the direction of X, and a drain of the source selection transistor in the first doping type formed in the semiconductor substrate; and a bit line layer arranged along a direction of Y and formed above the memory cells; in which an electrical contact part is formed between the drain of the source selection transistor and the vertical channel by electrically breaking down the multilayer memory gate dielectric.
  • the NAND memory structure of the present disclosure by forming a capacitance typed structure of "source selection transistor-memory gate dielectric layer-vertical channel layer" and by breaking down the memory gate dielectric between the drain of the source selection transistor and the vertical channel using an electrical breakdown method, it does not need to add a process of connecting with the channel so as to reduce a manufacture complexity and a manufacture cost and contribute to reducing a channel aperture and improving an integration density.
  • the vertical channel is made of a single-crystalline semiconductor material or a polycrystalline semiconductor material.
  • a still another aspect of the present disclosure provides an implementation method for forming a NAND memory structure.
  • the implementation method includes: (a) providing a semiconductor substrate, and forming an active area; (b) forming a gate structure of a source selection transistor on the semiconductor substrate; (c) forming a source structure and a drain structure of the source selection transistor by injecting a first type of ions, in which the source and the drain structure includes a common source line and a local source; (d) forming a contact hole of the local source by etching, depositing and etching electrode materials to form a lower electrode of the local source; (e) depositing insulating dielectric and gate materials in sequence to form a multilayer gate structure; (f) forming the multilayer gate structure by etching, and depositing a passivation layer; (g) etching the multilayer gate structure to form a plurality of vertical channel holes; (h) depositing multilayer memory gate dielectric layer, a vertical channel layer and an inner dielectric layer inside
  • a yet another aspect of the present disclosure provides a three-dimensional memory array.
  • the three-dimensional memory array includes a plurality of the above NAND memory structures.
  • the three-dimensional memory array of the present disclosure by employing the above NAND memory structure, it does not need to add a process of connecting with the channel so as to reduce a manufacture complexity and a manufacture cost.
  • Fig. 1 is a schematic diagram illustrating a NAND memory structure based on a BiCS technology in the related art
  • Figs. 2 (1) , (2) , (3) and (4) are schematic diagrams each illustrating a NAND memory structure based on a P-BiCS technology in the related art
  • Figs. 3 (1) , (2) and (3) are schematic diagrams each illustrating a process for forming a connection structure between a channel and a bottom region of a memory column based on a P-BiCS technology in the related art;
  • Fig. 4 is a schematic diagram illustrating a NAND memory structure based on a TCAT technology in the related art
  • Figs. 5 (1) , (2), (3) and (4) are schematic diagrams each illustrating a step of a manufacture process of a TCAT technology in the related art
  • Fig. 6 is schematic diagram illustrating a NAND memory structure according to an embodiment of the present disclosure
  • Fig. 7 is a schematic diagram illustrating a memory cell with a longitudinal stacked structure shown in Fig. 6 according to an embodiment of the present disclosure
  • Fig. 8 is a top view of a structure 300 (PC) shown in Fig. 6 according to an embodiment of the present disclosure
  • Fig. 9 is an enlarged view of an electrical contact part 150 (SC) shown in Fig. 6 according to an embodiment of the present disclosure
  • Fig. 10 is a schematic diagram illustrating an equivalent circuit diagram of a NAND memory structure according to an embodiment of the present disclosure
  • Fig. 11 is a flow chart showing a method for forming a NAND memory structure according to an embodiment of the present disclosure
  • Fig. 12 is a schematic diagram illustrating an equivalent circuit diagram of a NAND memory structure after a Forming operation is performed on the NAND memory structure according to an embodiment of the present disclosure
  • Fig. 13 is a schematic diagram illustrating voltage-current characteristics of a capacitor of an ONO dielectric layer during forward and reverse breakdown according to an embodiment of the present disclosure
  • Fig. 14 is a schematic diagram illustrating an equivalent circuit diagram of a NAND memory structure in which a forward breakdown voltage is applied between a drain of a source selection transistor and a vertical channel via the bit line and staked word line according to an embodiment of the present disclosure
  • Fig. 15 is a schematic diagram illustrating an equivalent circuit diagram of a NAND memory structure in which a reverse breakdown voltage is applied between a drain of a source selection transistor and a vertical channel via the bit line and staked word line according to an embodiment of the present disclosure
  • Fig. 16 is a schematic diagram illustrating an equivalent circuit diagram of a NAND memory structure in which a reverse breakdown voltage is applied between a drain of a source selection transistor and a vertical channel via the bit line and staked word line according to an embodiment of the present disclosure
  • Fig. 17 is a corresponding sheet of applied voltages of erasing, reading, writing operations on a NAND memory structure according to an embodiment of the present disclosure
  • Fig. 18 is a schematic diagram illustrating a substrate according to an embodiment of the present disclosure.
  • Fig. 19 is a schematic diagram illustrating a process step of forming a gate of a source selection transistor on a substrate according to an embodiment of the present disclosure
  • Fig. 20 is a schematic diagram illustrating a process step of forming a source and a drain of a source selection transistor according to an embodiment of the present disclosure
  • Fig. 21 is a schematic diagram illustrating a process step of forming a contact hole of a local source and a lower electrode of a local source according to an embodiment of the present disclosure
  • Fig. 22 is a schematic diagram illustrating a process step of depositing insulating dielectric and gate materials in sequence according to an embodiment of the present disclosure
  • Fig. 23 is a schematic diagram illustrating a process step of forming a multilayer gate structure and a passivation layer according to an embodiment of the present disclosure
  • Fig. 24 is a schematic diagram illustrating a process step of etching a multilayer gate structure to form a plurality of channel holes according to an embodiment of the present disclosure
  • Fig. 25 is a schematic diagram illustrating a process step of depositing multilayer memory gate dielectric layer, a vertical channel layer and an inner dielectric layer inside a vertical channel in sequence within a channel hole to form a vertical channel structure according to an embodiment of the present disclosure
  • Fig. 26 is a schematic diagram illustrating a process step of forming a drain and a metal bit line at the top of a vertical channel structure according to an embodiment of the present disclosure
  • Fig. 27 is a schematic diagram illustrating a process step of forming an electrical contact part according to an embodiment of the present disclosure.
  • Fig. 28 is a schematic diagram illustrating a three-dimensional memory structure according to an embodiment of the present disclosure.
  • a method for forming a NAND memory, a NAND memory structure and a method for forming the NAND memory structure are described with reference to the drawings.
  • Fig. 6 is a schematic diagram illustrating a NAND memory structure according to an embodiment of the present disclosure.
  • the NAND memory structure 100 includes a memory cell with a longitudinal stacked structure, a source selection transistor and a bit line layer 400 (BL) .
  • BL bit line layer 400
  • the memory cell with a longitudinal stacked structure includes a vertical channel along the direction of Z and multilayer memory gate dielectric.
  • a structure 300 (PC) shown in Fig. 6 includes a gate 210 (BSG0) of a bit line selection transistor and a stacked word line 200 (WL) that are both arranged horizontally along a direction of X, formed outside the vertical channel and with a longitudinal continuous multilayer structure.
  • Fig. 7 shows a schematic diagram illustrating a memory cell with a longitudinal stacked structure shown in Fig. 6.
  • the vertical channel may be made of a polycrystalline material.
  • the vertical channel may be made of a polycrystalline Si or Ge or SiGe material, such as a P-typed polycrystalline material 320 and an N-typed polycrystalline material 330 shown in Fig. 7.
  • Fig. 8 is a top view of a structure 300 (PC) shown in Fig. 6.
  • Multilayer memory gate dielectric 310 generally includes a barrier oxide layer 311, a charge trapping layer 312, a tunnel oxide layer 313.
  • the multilayer memory gate dielectric 310 includes a silicon oxide, silicon nitride, silicon oxide (ONO) dielectric layer.
  • the charge trapping layer or the barrier layer may be made of another metal-oxide material (even a combination of multilayer metal-oxide material) .
  • the memory cell further includes an inner dielectric layer 340 inside the channel.
  • the stacked word line 200 (WL) may be made of a polycrystalline silicon, or made of metal gate dielectric.
  • the source selection transistor is below the memory cell with the longitudinal stacked structure.
  • the source selection transistor includes a gate SSG of the source selection transistor formed on the substrate and arranged along a direction of X, a source GSL of the source selection transistor in a first doping type formed in the substrate and arranged along the direction of X, and a drain LSL of the source selection transistor in the first doping type formed in the substrate.
  • the source selection transistor includes the gate (SSG) , a common source 120 (GSL) , a local source 130 (LSL) and a lower electrode 140 (LSL) of the local source.
  • the lower electrode 140 (LSL) of the local source may be made of an N-typed polycrystalline dielectric or a P-typed polycrystalline dielectric, or may be made of a refractory metal, such as TiN and the like. Furthermore, the lower electrode 140 (LSL) may be removed and the drain of the source selection transistor may function as the lower electrode directly.
  • the bit line layer 400 (BL) are arranged along the direction of Y and are disposed above the memory cell with the longitudinal stacked structure.
  • FIG. 6 there is an electrical contact part 150 (SC) resulted from an electrical breakdown between the source selection transistor and the vertical channel.
  • An enlarged view of the electrical contact part 150 (SC) shown in Fig. 6 is shown in Fig. 9.
  • the electrical contact between the drain 140 (LSL) of the source selection transistor and the vertical channel is realized by breaking down ONO dielectric layer via a Forming operation based on an electrical breakdown method.
  • the NAND memory structure 100 is an improvement over the NAND memory structure in the related art.
  • connection relationships among terminals of components such as a common connection among sources of a plurality of source selection transistors, a connection relationship between an upper of a channel and a bit line, and the like.
  • a direction of a line such as a source line, a word line, a bit line in the structure, can be defined with reference to a definition in the related art or according to a specific condition.
  • the NAND memory structure 100 is equivalent to a capacitance typed connection structure of "lower electrode-ONO-polycrystalline channel" with a variable resistance between the vertical channel and the drain of the source selection transistor. Further, the NAND memory structure 100 employs the electrical breakdown method for breaking down the ONO dielectric layer to realize the electrical connection between the drain 140 (LSL) of the source selection transistor and the vertical channel. Therefore, it does not need to add a step of connecting with the channel, so as to reduce a manufacture complexity and a manufacture cost and contribute to reducing a channel aperture and improving an integration density.
  • Fig. 10 is a schematic diagram illustrating an equivalent circuit diagram of a NAND memory structure according to an embodiment of the present disclosure.
  • the memory cell includes a stacked word line. That is, a plurality of gates of word line in each memory cell is in a longitudinal staked structure.
  • the vertical channel is a vertical polycrystalline channel. And the area of a unit equivalent to a known planar NAND memory structure may be reduced and a bit cost may be reduced.
  • the NAND memory structure 100 includes a capacitance typed connection structure of "lower electrode-multilayer memory gate-vertical channel" .
  • the capacitance typed connection structure is broken down by applying a high voltage across two ends of the capacitance typed connection structure.
  • the high voltage is set to be VPPF.
  • the VPPF is between 10V and 20V.
  • the source selection transistor at the bottom is pre-disposed on the substrate 101 (Sub) along the horizontal direction prior to manufacturing the memory cell.
  • the substrate may be a single-crystalline silicon substrate.
  • the number of layers of a longitudinal gate structure is reduced by one compared with that made based on BICS technology and TCAT technology, thereby reducing a height of the gate structure and a complexity of the manufacture process.
  • the source selection transistor is embedded below the word line in advance, which does not occupy a chip area and does not increase the area of the equivalent unit.
  • the source selection transistor and a peripheral circuit transistor of the memory are simultaneously formed on the single-crystalline silicon substrate, which does not increase steps of the manufacture process and a manufacture cost.
  • the gate dielectric of the transistor employs silicon oxide dielectric, which has a better reliability.
  • a potential of the vertical channel may be changed by applying an operation voltage to the substrate via the electrical contact part 150 (SC) , thereby improving a performance of an erasing operation.
  • Fig. 11 is a flow chart showing a method for forming a NAND memory structure according to an embodiment of the present disclosure. The method includes followings.
  • a semiconductor substrate is provided.
  • the semiconductor substrate is a P-typed silicon substrate.
  • a plurality of source selection transistors are formed in the semiconductor substrate.
  • the source selection transistor is a MOS transistor.
  • the source selection transistor includes a gate of the source selection transistor formed in the substrate and arranged along the direction of X, a source in a first doping type formed in the substrate and arranged along the direction of X, and a drain in the first doping type formed in the substrate.
  • memory cells with a longitudinal stacked structure are formed above the source selection transistors.
  • the memory cell with the longitudinal stacked structure includes a vertical channel along the direction of Z, multilayer memory gate dielectric, a gate of a bit line selection transistor and a stacked word line both arranged horizontally along the direction of X and formed outside the vertical channel.
  • the drain of the source selection transistor contacts the multilayer memory gate dielectric that is at the bottom of the vertical channel.
  • a plurality of bit lines arranged along the direction of Y are formed above the memory cells with the longitudinal stacked structure.
  • a breakdown voltage is applied, via the bit line and the drain of the source selection transistor, to the multilayer memory gate dielectric that is between the drain of the source selection transistor and the vertical channel, such that an electrical contact part is formed between the drain of the source selection transistor and the vertical channel.
  • the electrical contact part is formed between the drain of the source selection transistor and the vertical channel. Therefore, it does not need to add a process of connecting with the channel so as to reduce a manufacture complexity and a manufacture cost and contribute to reducing a channel aperture and improving an integration density.
  • the vertical channel includes a single-crystalline semiconductor material or a polycrystalline semiconductor material.
  • the multilayer memory gate dielectric includes a barrier oxide layer, a silicon nitride trapping layer, and a tunnel oxide layer.
  • the multilayer memory gate dielectric includes a barrier oxide layer, a monolayer trapping layer or multilayer trapping layer with a high dielectric constant and a tunnel oxide layer.
  • Fig. 12 is a schematic diagram illustrating an equivalent circuit diagram of a NAND memory structure after a Forming operation is performed on the NAND memory structure according to an embodiment of the present disclosure.
  • a Forming method i.e. applying a high voltage
  • the electrical connection is formed between the drain of the source selection transistor and the vertical channel. Therefore, regarding to the equivalent circuit, the NAND memory structure according to the present disclosure is electrically similar to a known NAND memory structure.
  • Fig. 13 is schematic diagram illustrating voltage-current characteristics of a capacitor of an ONO dielectric layer during forward and reverse breakdown according to an embodiment of the present disclosure. As shown in Fig. 13, a positive or negative high voltage may be applied across two ends of the ONO capacitor to break down the ONO dielectric, such that a connection with a low resistance is formed between an upper electrode and a lower electrode.
  • the breakdown voltage is applied, via the bit line and the drain of the source selection transistor, to the multilayer memory gate dielectric between the drain of the source selection transistor and the vertical channel to form the electrical contact part between the drain of the source selection transistor and the vertical channel.
  • the breakdown voltage is equal to the high voltage.
  • the capacitance typed connection structure of "source-multilayer memory gate-vertical channel” undergoes forward breakdown. That is, the bit line is connected with the breakdown voltage, the stacked word line and the gate of the bit line selection transistor are both connected with the high voltage, and simultaneously the source of the source selection transistor is grounded, and the gate of the source selection transistor is connected with a supply voltage VDD.
  • the breakdown voltage is applied to the multilayer memory gate dielectric between the drain of the source selection transistor and the vertical channel, such that the multilayer memory gate dielectric, such as an ONO structure, between the drain of the source selection transistor and the vertical channel is broken down to form the electrical contact part.
  • Fig. 14 shows a schematic diagram illustrating an equivalent circuit diagram of a NAND memory structure in which a forward breakdown voltage is applied to multilayer memory gate dielectric between a drain of a source selection transistor and a vertical channel via the bit line and staked word line according to an embodiment of the present disclosure. As shown in Fig.
  • the high voltage VPPF is applied to the bit line BL
  • the high voltage VPPF is applied to the stacked word line WL and the gate BSG of the bit line selection transistor
  • the voltage of the bit line BL is transmitted to a vertical polycrystalline channel (that is, the upper electrode of the electrical contact part SC)
  • the common source GSL is grounded
  • the supply voltage VDD is applied to the gate SSG of the source selection transistor, such that the source selection transistor is turned on and a grounded voltage is transmitted to the local source LSL (that is, the lower electrode of the electrical contact part SC) .
  • a forward breakdown voltage VPPF is formed on the electrical contact part SC so as to break down the electrical contact part SC.
  • the connection with the low resistance is formed between the vertical channel and the lower electrode of the source selection transistor.
  • the capacitance typed connection structure of "lower electrode-multilayer memory gate-vertical channel” undergoes reverse breakdown. That is, the bit line is grounded, the stacked word line and the gate of the bit line selection transistor are both connected with the supply voltage VDD, and simultaneously the source of the source selection transistor is connected with the breakdown voltage, and the gate of the source selection transistor is connected with the high voltage. As a result, the breakdown voltage is applied to the multilayer memory gate dielectric between the drain of the source selection transistor and the vertical channel.
  • Fig. 15 shows a schematic diagram illustrating an equivalent circuit diagram of a NAND memory structure in which a reverse breakdown voltage is applied between a drain of a source selection transistor and a vertical channel via the bit line and staked word line according to an embodiment of the present disclosure. As shown in Fig.
  • the bit line BL is grounded, the supple voltage VDD is applied to the stacked word line WL and the gate BSG of the bit line selection transistor to transmit the grounded voltage of the bit line BL to the vertical polycrystalline channel (that is, the upper electrode of the electrical contact part SC) , the high voltage VPPF is applied to the common source GSL, and the high voltage VPPF is applied to the gate SSG of the source selection transistor, such that the source selection transistor is turned on and the high voltage VPPF is transmitted to the local source LSL (that is, the lower electrode of the electrical contact part SC) .
  • a reverse breakdown voltage (-VPPF) is formed on the electrical contact part SC and the electrical contact part SC is broken down to form the connection with the low resistance.
  • the capacitance typed connection structure of "lower electrode-multilayer memory gate-vertical channel” undergoing reverse breakdown is still taken as an example.
  • the bit line is grounded, the stacked word line and the gate of the bit line selection transistor are both connected with the supply voltage VDD, and simultaneously the source and the gate of the source selection transistor are suspended, and the breakdown voltage is applied on the substrate.
  • the breakdown voltage is applied on the multilayer memory gate dielectric between the drain of the source selection transistor and the vertical channel.
  • Fig. 16 shows a schematic diagram illustrating an equivalent circuit diagram of a NAND memory structure in which a reverse breakdown voltage is applied to the multilayer memory gate dielectric between a drain of a source selection transistor and a vertical channel via a bit line and a staked word line according to an embodiment of the present disclosure. As shown in Fig.
  • the bit line BL is grounded, the supply voltage VDD is applied to the stacked word line WL and the gate BSG of the bit line selection transistor to transmit the grounded voltage of the bit line BL to the vertical polycrystalline channel (that is, the upper electrode of the electrical contact part SC) , the common source GSL and the source selection transistor are suspended, the high voltage VPPF is applied to the P-typed substrate and the high voltage VPPF is transmitted to the local source LSL (that is, the lower electrode of the electrical contact part SC) via a forwardly conducted PN junction.
  • a reverse breakdown voltage (-VPPF) is formed on the electrical contact part SC, such that the electrical contact part SC is broken down to form the connection with the low resistance.
  • the breakdown voltage or the high voltage may be applied to the bit line or the gate of the bit line selection transistor in sequence via a scanning way. It may reduce an instant current when performing the Forming operation by scanning the bit line BL or the gate BSG of the bit line selection transistor.
  • the memory cell may employ operations same with those of a known NAND array to perform the erasing, writing, reading operations.
  • Fig. 17 shows a corresponding sheet of applied voltages of erasing, reading, writing operations on a NAND memory structure according to an embodiment of the present disclosure.
  • a process for manufacturing the NAND memory structure according to embodiments of the present disclosure includes followings.
  • a semiconductor substrate is provided and an active area is formed.
  • a P-typed Si substrate 101 (Sub) is prepared to form a STI field oxide isolation (arranged inside the substrate and parallel to a direction of Y and perpendicular to the direction of X, and not shown) , and the active area is formed.
  • a gate structure of a source selection transistor is formed on the substrate. As shown in Fig. 19, an oxide gate dielectric and a gate structure 110 (SSG) of the source selection transistor are formed on the P-typed Si substrate.
  • a source structure and a drain structure of the source selection transistor are formed by injecting a first type of ions.
  • the source structure and the drain structure includes a common source line 120 (GSL) and a local source 130 (LSL) .
  • a contact hole of the local source is formed by etching. As shown in Fig. 21, electrode materials are deposited and the lower electrode 140 (LSL) of the local source is formed by etching.
  • Insulating dielectric and a gate material are deposited in sequence to form a multilayer gate structure.
  • the insulating dielectric, a polycrystalline/metal gate material are deposited in sequence to form the multilayer gate structure 200 (WL) and the gate 210 (BSG) of the bit line selection transistor.
  • the multilayer gate structure is formed by etching, and a passivation layer is deposited. As shown in Fig. 23.
  • a plurality of vertical channel holes are formed by etching the multilayer gate structure. That is, the channel hole along the direction Z is formed, as shown in Fig, 24.
  • a vertical channel structure is formed by depositing multilayer memory gate dielectric layer, a vertical channel layer and an inner dielectric layer inside the vertical channel in sequence within the channel hole.
  • the multilayer memory gate dielectric includes a barrier layer, a charge trapping layer, and a tunnel layer.
  • the barrier oxide layer, the silicon nitride trapping layer, the tunnel oxide layer, the polycrystalline channel layer and the inner dielectric layer inside the vertical channel are deposited in sequence within the channel hole to form a vertical polycrystalline channel structure 300 (PC) .
  • a drain is formed at the top of the vertical channel structure by injecting the first type of ions, and bit line metal materials are deposited to form the bit line by etching.
  • bit line metal materials are deposited to form the bit line by etching.
  • an N-typed drain is formed at the top of the vertical channel by injecting the ions, and the metal bit line 400 (BL) is formed by etching after a bit line metal material is deposited.
  • a breakdown voltage is applied between the lower electrode of the local source and the vertical channel via bit line and the drain of the source selection transistor, and an electrical contact part is formed by breaking down the multilayer memory gate dielectric between the lower electrode of the local source and the vertical channel based on an electrical breakdown method.
  • the ONO dielectric between the lower electrode 140 (LSL) of the local source and the vertical polycrystalline channel structure 300 (PC) is broken down with a Forming operation to form the electrical contact part 150 (SC) .
  • the method for forming the NAND memory structure includes methods for forming the source selection transistor on the silicon substrate, multilayer polycrystalline gates and the gate of the bit line selection transistor, the ONO structure and the polycrystalline channel, and the bit line, and the Forming operation for forming the electrical contact part.
  • the source selection transistor at the bottom is pre-disposed on the substrate 101 (Sub) along the horizontal direction prior to manufacturing the memory cell.
  • the substrate may be a single-crystalline silicon substrate.
  • the number of layers of a longitudinal gate structure is reduced by one compared with that made based on BICS technology and TCAT technology, thereby reducing a height of the gate structure and a complexity of the manufacture process.
  • the source selection transistor is embedded below the word line in advance, which does not occupy a chip area and does not increase the area of the equivalent unit.
  • the source selection transistor and a peripheral circuit transistor of the memory are simultaneously formed on the single-crystalline silicon substrate, which does not increase steps of the manufacture process and a manufacture cost.
  • the gate dielectric of the transistor employs silicon oxide dielectric, which has a better reliability.
  • a potential of the vertical channel may be changed by applying an operation voltage to the substrate via the electrical contact part 150 (SC) , thereby improving a performance of an erasing operation.
  • a yet still another aspect of embodiments of the present disclosure provides a three-dimensional memory array.
  • the three-dimensional memory array includes a plurality of the above NAND memory structures. That is, the three-dimensional memory array is configured by employing the above-mentioned NAND memory structure.

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