WO2017154388A1 - 光電変換装置 - Google Patents
光電変換装置 Download PDFInfo
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- WO2017154388A1 WO2017154388A1 PCT/JP2017/002385 JP2017002385W WO2017154388A1 WO 2017154388 A1 WO2017154388 A1 WO 2017154388A1 JP 2017002385 W JP2017002385 W JP 2017002385W WO 2017154388 A1 WO2017154388 A1 WO 2017154388A1
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- 238000006243 chemical reaction Methods 0.000 title claims abstract description 98
- 238000012545 processing Methods 0.000 claims abstract description 61
- 230000015654 memory Effects 0.000 claims description 23
- 239000003990 capacitor Substances 0.000 claims description 22
- 125000004122 cyclic group Chemical group 0.000 claims description 7
- 101710170230 Antimicrobial peptide 1 Proteins 0.000 description 15
- 230000003321 amplification Effects 0.000 description 13
- 238000003199 nucleic acid amplification method Methods 0.000 description 13
- 238000000034 method Methods 0.000 description 7
- 230000000052 comparative effect Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 4
- 238000003384 imaging method Methods 0.000 description 4
- 230000006870 function Effects 0.000 description 3
- 230000035945 sensitivity Effects 0.000 description 3
- 239000004020 conductor Substances 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14603—Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
- H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
- H04N25/772—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising A/D, V/T, V/F, I/T or I/F converters
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14643—Photodiode arrays; MOS imagers
- H01L27/14645—Colour imagers
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
- H04N25/617—Noise processing, e.g. detecting, correcting, reducing or removing noise for reducing electromagnetic interference, e.g. clocking noise
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
- H04N25/67—Noise processing, e.g. detecting, correcting, reducing or removing noise applied to fixed-pattern noise, e.g. non-uniformity of response
- H04N25/671—Noise processing, e.g. detecting, correcting, reducing or removing noise applied to fixed-pattern noise, e.g. non-uniformity of response for non-uniformity detection or correction
- H04N25/677—Noise processing, e.g. detecting, correcting, reducing or removing noise applied to fixed-pattern noise, e.g. non-uniformity of response for non-uniformity detection or correction for reducing the column or line fixed pattern noise
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/709—Circuitry for control of the power supply
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
- H04N25/75—Circuitry for providing, modifying or processing image signals from the pixel array
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
- H04N25/766—Addressed sensors, e.g. MOS or CMOS sensors comprising control or output lines used for a plurality of functions, e.g. for pixel output, driving, reset or power
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
- H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
- H04N25/771—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising storage means other than floating diffusion
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
- H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
- H04N25/778—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising amplifiers shared between a plurality of pixels, i.e. at least one part of the amplifier must be on the sensor array itself
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
- H04N25/78—Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
Definitions
- the present invention relates to a photoelectric conversion device.
- a photoelectric conversion device includes a pixel block in which a pixel including a photoelectric conversion element that performs photoelectric conversion according to incident light and a charge-voltage conversion unit that converts photoelectrically converted charge into voltage is two-dimensionally arranged, and the pixel block And a plurality of signal processings for processing the signal output from.
- CMOS Complementary Metal Oxide Semiconductor
- Such a photoelectric conversion device is used as an imaging device (image sensor) in various imaging devices such as a video camera, a digital camera, and a copying machine.
- the image sensor mounted on the imaging device is restricted in the layout area of the substrate on which the image sensor can be arranged while noise reduction is desired to achieve high image quality.
- Patent Document 1 discloses a configuration in which horizontal transfer bus lines intersect on a column AD circuit, and suppresses an increase in layout area while reducing noise caused by crosstalk from the column AD circuit to the horizontal transfer bus line. A configuration to be made is proposed.
- an object of the present invention is to provide a photoelectric conversion device capable of reducing the size in the short direction.
- a horizontally long photoelectric conversion device is a pixel block in which a plurality of pixels are arranged, and a signal output from the pixel block is processed.
- a plurality of signal processing blocks arranged in parallel in the short direction of the photoelectric conversion device, a power supply voltage supply block for supplying a power supply voltage to the pixel block and the plurality of signal processing blocks, and electrodes connected to the power supply voltage supply block And a pad,
- Each of the plurality of pixels includes a charge-voltage conversion unit including a photoelectric conversion element that performs photoelectric conversion according to incident light and an amplifier that converts the photoelectrically converted charge into a voltage
- a predetermined number of pixels are set as one column which is a group of signal processing units, and a plurality of the columns are arranged in parallel in the longitudinal direction of the photoelectric conversion device,
- a plurality of vertical power supply wirings are provided to enable the power supply voltage output from the power supply voltage supply block to be supplied from
- the size in the lateral direction can be reduced in the photoelectric conversion device.
- FIG. 2 is a detailed view in a pixel block of the photoelectric conversion device of FIG. 1.
- FIG. 4 is a circuit diagram in a case where switches and amplifiers in the pixel block of FIG. 3 are configured by transistors.
- the photoelectric conversion apparatus which concerns on 2nd Embodiment of this invention.
- the specific circuit diagram in case a signal processing block is a cyclic A / D converter.
- FIG. 1 shows a photoelectric conversion device according to the first embodiment of the present invention.
- the photoelectric conversion device of the present invention functions as a CMOS sensor used in various imaging devices such as a video camera, a digital camera, and a copying machine.
- the photoelectric conversion device 1 shown in FIG. 1 includes a pixel block 10, signal processing blocks 20A to 20Z, a power supply voltage supply block 30, and an electrode pad 40.
- pixels (Pixels) that convert the incident light amount into pixel signals are two-dimensionally arranged.
- the signal processing blocks 20A to 20Z process the signal output from the pixel block 10.
- the plurality of signal processing blocks 20A to 20Z are arranged (parallel) side by side in the lateral direction of the photoelectric conversion device 1.
- the power supply voltage supply block 30 supplies a power supply voltage to each of these blocks.
- the electrode pad 40 supplies a power supply voltage to the power supply voltage supply block 30.
- the photoelectric conversion device to which the present invention is applied has a horizontally long rectangular shape having a pair of long sides and a pair of short sides.
- the pixel block 10, the signal processing blocks 20A to 20Z, the power supply voltage supply block 30, and the electrode pad 40 are arranged in order from the top to the bottom in the short side direction (vertical direction in FIG. 1). Yes.
- the power supply voltage output from the power supply voltage supply block 30 can be fed to the plurality of columns (PU1 to PUn) of the pixel block 10 in the short side direction (short direction, vertical direction in FIG. 1) of the photoelectric conversion device 1.
- a plurality of vertical feed lines VL1 to VLn are provided.
- the column indicates a minimum unit of a signal processing system in which a plurality of photoelectric conversion elements are grouped (a group of signal processing units: ProcessingProcessUnit).
- a system for processing six photoelectric conversion elements two pixels each of R (red), G (green), and B (blue) is one column.
- the number per column is not limited to six, and may be other numbers.
- a plurality of columns PU1 to PUn which are signal processing units set in this way, are arranged side by side (in parallel) in the long side direction (left and right direction in FIG. 1) of the photoelectric conversion device 1.
- a plurality of lateral power feeds that enable the power source voltage output from the power source voltage supply block 30 to be fed to the pixel block 10 and the plurality of signal processing blocks 20A to 20Z in the long side direction (longitudinal direction) of the photoelectric conversion device 1.
- a wiring HL is provided.
- the vertical power supply wiring VL extending in the short direction and transmitting the power supply voltage from the power supply voltage supply block 30 are connected to the horizontal power supply wiring HL extending in the longitudinal direction.
- lateral power feeding means power feeding (power feeding from the longitudinal direction to each block) in the longitudinal direction (left-right direction in FIG. 1) of the photoelectric conversion device, and vertical power feeding is a short direction (see FIG. 1) of the photoelectric conversion device. 1 (up and down direction of 1) means power supply (power supply from the short direction to each block).
- both vertical power supply and horizontal power supply are performed in a mesh shape with all the wirings.
- FIG. 2 shows a photoelectric conversion device according to a comparative example.
- power is fed only by lateral power feeding.
- the longitudinal direction of the photoelectric conversion device is limited by the number of installed photoelectric conversion elements and the size per photoelectric conversion element. Specifically, in order to reduce the size in the longitudinal direction, the number of mounted photoelectric conversion elements is reduced or the size of one photoelectric conversion element is reduced.
- the aspect ratio of “longitudinal direction: short direction” may range from 10: 1 to sometimes 100: 1.
- the required wiring metal width B ( ⁇ m) is “B ( ⁇ m)> D ( ⁇ m) ⁇ C ( ⁇ / ⁇ ) / A ( ⁇ m)”
- the required wiring metal width is proportional to the length in the longitudinal direction of the photoelectric conversion device.
- the present invention adopts a configuration in which vertical feeding and lateral feeding are used together as shown in FIG. Specifically, the power supply voltage supply block 30 and the electrode pad 40 are arranged below the signal processing blocks 20A to 20Z, and from there, the pixel block 10 and the plurality of signal processing blocks 20A to 20Z are vertically fed for each column. Vertical power supply and horizontal power supply are used in combination.
- FIG. 3 is a detailed view inside the pixel block 10 of the photoelectric conversion device of FIG.
- RE, RO, GE, GO, BE, and BO configured by six pixels 11 and six analog memories are described as one column PUx.
- the number is not limited to this number.
- RE and RO indicate two pixel units in which a red (R) transmissive color filter is provided above the light receiving element.
- GE and GO indicate two pixel units provided with a green (G) transmissive color filter.
- BE and BO represent two pixel units provided with a blue (B) transmissive color filter.
- the pixel units RE, RO, GE, GO, BE, and BO include a pixel 11 and an analog memory 12.
- the internal configuration of the pixel unit will be described below using the pixel unit RO, but the configuration is the same for other pixel units.
- the pixel is an active pixel sensor that performs charge-voltage conversion and amplification in the circuit.
- the pixel 11 includes a photoelectric conversion element PD, a float diffusion region FD, and the like.
- the photoelectric conversion element (light receiving element) PD accumulates charges generated by the incidence of light.
- the float diffusion region FD functions as a charge-voltage converter that performs charge-voltage conversion by transferring the charge to a junction stray capacitance in the pixel 11 when reading out the charge.
- the anode of the photoelectric conversion element PD is connected to the ground voltage, and the cathode of the photoelectric conversion element PD is connected to one end of the transfer switch SW1.
- the other end of the transfer switch SW1 is connected to the first amplifier AMP1 and the reset switch SW2.
- a region to which the transfer switch SW1, the first amplifier AMP1, and the reset switch SW2 are connected is referred to as a float diffusion region FD.
- One end of the first amplifier AMP1 is connected to the current source 13.
- a drive signal Vrd that is a reset voltage is applied to the other end of the reset switch SW2 that is not connected to the transfer switch SW1 and the first amplifier AMP1.
- a color filter and a microlens are formed on the photoelectric conversion element PD.
- These transfer switch SW1, reset switch SW2, photoelectric conversion element PD, first amplifier AMP1, color filter, and microlens are collectively referred to as a pixel. Note that the microlens may not be formed.
- the provision of the analog memory 12 makes it possible to temporarily store signals, and any order of R / G / B signal levels and reset levels stored in the analog memory (for example, R reset level ⁇ signal level ⁇ G Can be read at a reset level of.
- the pixel selection switch SW6, capacitance selection switches SW4 and SW5, capacitors C1 and C2, and memory write selection switch SW3 shown in FIG. 3 are collectively referred to as an analog memory.
- capacitance selection switches SW4 and SW5 are connected to one ends of capacitors C1 and C2, respectively.
- the other ends of the capacitors C1 and C2 are connected to a predetermined memory reference voltage Vm.
- One end of the first amplifier AMP1 in the pixel 11 is connected to the first current source 13, and via the memory write selection switch SW3, selection switches SW4 and SW5 for selecting the capacitors C1 and C2. Are connected to a pixel selection switch SW6 for selecting a pixel.
- the pixel selection switches SW6 of the plurality of analog memories 12 are connected to the second amplifier 15 and the second current source 14.
- a column signal processing unit 16 is connected to the second amplifier 15.
- the power supply for the first amplifier AMP1 and the power supply for the second amplifier 15 use vertical power supply (for example, power supply 2 in FIG. 5).
- the reset voltage Vrd applied to the reset switch SW2 of each pixel 11, the first current source 13, and the second current source 14 use lateral power feeding (power feeding 1 in FIG. 5).
- the memory reference voltage Vm connected to the capacitors C1 and C2 of the analog memory 12 may be generated by being drawn from the ground terminal, or a lateral power supply (power supply 1 in FIG. 5) may be used.
- the configuration in which both the vertical power supply and the horizontal power supply are used in one column can reduce the width of the horizontal power supply wiring HL, thereby reducing the size of the photoelectric conversion device in the short direction. it can. Therefore, the number of chips removed per wafer is increased and the cost can be reduced.
- FIG. 4 is a circuit diagram in the case where the switches and amplifiers in the pixel block of FIG. 3 are configured by transistors.
- each of the switches SW1 to SW6 is composed of one transistor (Tr).
- the circuit for realizing the configuration of FIG. 3 may be a CMOS switch using Nch-Tr and Pch-Tr in consideration of transistor ON resistance and charge injection.
- a switch may be configured with Pch-Tr. For example, when the reset voltage Vrd is high, the potential of the memory write selection transistor SW3 is also high, so that the ON resistance can be lowered by using a Pch type switch rather than an Nch type.
- MOS capacitors As the capacitors C1 and C2 in consideration of area efficiency.
- the capacitors C1 and C2 use Nch type MOS transistors (MOS capacitors). It is preferable to do this.
- the memory reference voltage Vm at one end of the capacitors C1 and C2 may be shared with the ground voltage of other circuits. However, if the memory reference voltage Vm fluctuates, the voltage fluctuation directly appears in the output depending on the timing. Therefore, it is more preferable to separate the memory reference voltage Vm from the ground voltage of other circuits.
- FIG. 4 shows an example in which the second amplifier 15 is configured by one Nch type MOS transistor.
- the back gate of a transistor (referred to as a second amplification transistor) 15 constituting the second amplifying unit is normally connected to the source in consideration of the back gate effect, but this is a trade-off with the area, and the back gate There may be cases where the gate is not connected.
- a Pch type can also be configured.
- the current flowing through the transistor (referred to as the first amplification transistor) AMP1 and the second amplification transistor 15 constituting the first amplification unit can be varied.
- the size of the second amplifying transistor 15 common in the column does not affect the conversion gain as much as the first amplifying transistor AMP1. Therefore, considering the noise characteristics (flicker noise, thermal noise, RTS noise, etc.), it is preferable that the second amplification transistor 15 is as large as possible. Further, the size of the second amplification transistor 15 has little influence on the size of the entire chip. Therefore, the second amplifying transistor 15 is preferably larger than the first amplifying transistor AMP1.
- the first current source 13 and the second current source 14 are composed of a plurality of transistors.
- the power supply for the first amplification transistor AMP1 and the power supply for the second amplification transistor 15 use vertical power supply (power supply 2) (see FIG. 5).
- the reset voltage Vrd applied to the reset transistor SW2 of each pixel 11, the first current source 13, and the second current source 14 use lateral power feeding (power feeding 1).
- FIG. 5 shows a photoelectric conversion device according to the second embodiment of the present invention.
- vertical power feeding is performed from the power supply voltage supply block 30 to another block (alternately with the pixel block 10 and the plurality of signal processing blocks 20A to 20Z) for each column.
- the pixel block 10 and each of the plurality of signal processing blocks 20A to 20Z are supplied with power via different vertical power supply wirings VL for each column.
- the power supply voltage is supplied to the pixel block 10 via a vertical power supply wiring (vertical power supply wiring for pixel block) VL1 (VL1 (p)) corresponding to columns (for example, columns PU1 and Pn) in a predetermined column.
- a vertical power supply wiring (vertical power supply wiring for signal processing block) VL2 (corresponding to a column (for example, columns PU2, PUn-1) different from the predetermined column (PU1)).
- the power supply voltage is supplied via VL2 (p)).
- VLx (p) for example, VL1 (p), VLn (p)
- VLx (s) for example, VL2 (s), VLn-1 (s)
- VLx (s) for example, VL2 (s), VLn-1 (s)
- the vertical power supply and the horizontal power supply are not shared in a mesh shape between the pixel block 10 and the signal processing blocks 20A to 20Z. Since the lateral power feeding is performed independently via another wiring, noise interference does not affect each other, and noise interference during power feeding can be further reduced as compared with the first embodiment.
- the signal processing block 20A is a noise source
- the noise may directly cause the power of the pixel block 10 to shake.
- the wiring resistance between the pixel block 10 and the power supply voltage supply block 30 is 200 ⁇
- the wiring resistance between the signal processing block 20A and the power supply voltage supply block 30 is 150 ⁇
- the signal processing block 20A and the pixel block 10 are connected.
- the wiring resistance of the path through which the noise propagates is 50 ⁇ in the configuration of FIG.
- the image quality can be further improved by supplying the power through the wiring in which the noise and the pixel block are independent.
- bypass capacitor for connecting the power supply line and the ground (terminal) is arranged in the power supply voltage supply block 30 for the purpose of avoiding fluctuations in the voltage of the DC power supply when the circuit operates. May be.
- the noise with respect to the power source in the signal processing blocks 20A to 20Z is designed to be suppressed to within 1 LSB (least significant bit) equivalent in terms of 10-bit output.
- the pixel block 10 When the pixel block 10 is mounted via the power source shared by the 1 LSB noise, it may appear as 1 LSB noise in the output of the pixel block 10 as it is. Usually, since the signal output from the pixel block 10 may apply a gain of about 10 times, the noise which was originally 1LSB becomes 10LSB.
- the wiring resistance is set so that the noise can be suppressed to 1/10, that is, the cut-off frequency is 1/10.
- the wiring resistance from the pixel block 10 to the power supply voltage supply block 30 is Y ( ⁇ ) and the wiring resistance from the signal processing blocks 20A to 20Z to the power supply voltage supply block 30 is Z ( ⁇ ), “Z + Y> 10 * If the wiring resistance satisfies (YZ) ”, the influence on the image is reduced.
- the noise is 1 LSB or less in terms of 10 bits, and the influence on the image is reduced.
- 0.1 LSB is obtained in terms of 10-bit output and the influence on the image is eliminated. That is, Z + Y> 100 * (Y ⁇ Z) may be satisfied. With this setting, the noise becomes 0.1 LSB or less in terms of 10 bits, and the influence on the image is almost eliminated.
- FIG. 6 shows a photoelectric conversion device when a plurality (30A, 30B) of power supply voltage supply blocks 30 are provided. As shown in FIG. 6, the number of power supply voltage supply blocks 30 is not necessarily one.
- the power supply block corresponding to the power supply source corresponding to each type of the power supply destination block that is, each of the pixel block 10 and the signal processing block 20 (20A to 20Z).
- 30A and 30B can be separated. Therefore, it becomes difficult to be affected by the difference in power supply voltage value, and it is possible to further prevent noise from being mixed during power feeding.
- FIG. 7 shows a photoelectric conversion device when there are a plurality of electrode pads 40. As shown in FIG. 7, the number of the electrode pads 40 and the power supply voltage supply block 30 is not necessarily one.
- the power source of the supply source to be supplied for each type of the power supply destination block that is, the pixel block 10 and the signal processing block 20 (20A to 20Z).
- the supply blocks 30A and 30B and the electrode pads 40A and 40B can be separated. Therefore, it becomes difficult to be affected by the difference in power supply voltage value, and it is possible to further prevent noise from being mixed during power feeding.
- FIG. 8 shows a schematic diagram of a power feeding method in the pixel block 10.
- the photoelectric conversion device of the present invention is assumed to be mounted on one chip.
- the photoelectric conversion element PD in the pixel 11 is affected by the stress (stress), and the image characteristics may be deteriorated. There is sex.
- a blank area B that does not include the pixel 11 is disposed above the pixel area A that includes the pixel 11 including the photoelectric conversion element PD as illustrated in FIG. And the pixel area A may be separated from the chip edge CE.
- the vertical power supply signal traverses the pixel 11 and the aperture of the pixel becomes narrow and sensitivity is lowered.
- horizontal power supply (power supply 1 using HL1) is provided to the block (margin region B) arranged above the pixel region A including the pixel 11, and vertical power supply (VL1) is provided to the block (margin region C) below the pixel. It is effective to separate the power supply method (using the wiring HL2) and the power supply method.
- the pixel block 10 at least a portion closer to the power supply voltage supply block 30 than the plurality of pixels 11 is vertically fed using the vertical feed wiring VL ⁇ b> 1, and at least a plurality of pixels 11 are separated from the power supply voltage supply block 30.
- the portion is fed using the lateral feed wiring HL1.
- the signal passing through the vertical power supply wiring VL1 can secure the aperture of the pixel and the photoelectric sensitivity without traversing the pixel.
- FIG. 9 is a specific example in the case where only lateral power feeding is used for the noise source.
- 9A shows a photoelectric conversion device
- FIG. 9B is an enlarged view of the signal processing block A
- FIG. 9C shows an example in which the signal processing block is configured by a cyclic A / D converter. Show.
- the vertical power supply is performed by supplying the power supply voltage from the power supply voltage supply block 30 to both the signal processing blocks 20A to 20Z and the pixel block 10 through the common vertical power supply wiring VL. Power is being supplied.
- the noise source when the sensitive circuit 21 and the noise source 22 are separated from each other in the signal processing block 20A, the noise source is set to perform only lateral power feeding. That is, vertical power feeding is not performed on the noise sources of the signal processing blocks 20A to 20Z.
- the power supply 3 using the horizontal power supply wiring HL3 is used as the noise source 22, and the power supply using the vertical power supply wiring VL2 is used. 4 is used in the sensitive circuit 21 that is easily affected by noise.
- FIG. 10 shows a specific circuit diagram when the signal processing block is a cyclic A / D converter.
- the control logic 26 and the D / A converter (DAC) 23 are noise sources 22, capacitors Cin1, Cin2, Cout, switches SW10 to SW40, amplifiers 24 and the comparator 25 correspond to the sensitive circuit 21.
- the capacitors Cin1, Cin2, Cout, the switches SW10 to SW40, and the amplifier 24 function as switched capacitors.
- This circuit is a general cyclic A / D converter.
- the input signal from the block arranged in the upper stage input to the switch SW10 is sampled and held by the switches SW10 to SW40, and the voltage is converted by repeating the comparison and amplification. Assume that digital data is output to the lower stage.
- the amplifier 24 and the comparator 25 in the switched capacitor which are sensitive elements, use the vertical power supply (power supply 4) for power supply.
- the DAC 23 and the control logic 26 have a signal level that swings from GND to the power supply voltage, so that noise easily occurs during transmission and becomes a noise source. Therefore, the DAC 23 and the control logic 26 are separated from the power supply of other highly sensitive elements.
- the lateral power supply HL power supply 3
- the vertical power supply is used for the purpose of reducing the wiring resistance.
- the reference voltage used for the clock and the amplifier can be supplied using the vertical wiring by the same means.
- the present invention has been described based on each embodiment, but the present invention is not limited to the requirements shown in the above embodiment. With respect to these points, the gist of the present invention can be changed without departing from the scope of the present invention, and can be appropriately determined according to the application form.
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Abstract
Description
前記複数の画素の夫々は、入射光に応じて光電変換を行う光電変換素子および光電変換された電荷を電圧に変換する増幅器を含む電荷電圧変換部を備え、
前記画素ブロックでは、所定の数毎の画素が一纏りの信号処理単位である1つのカラムとして設定され、複数の該カラムが当該光電変換装置の長手方向に並列されており、
前記電源電圧供給ブロックから出力される前記電源電圧を、前記短手方向から、前記画素ブロックの複数のカラム毎へ給電可能にする、複数の縦給電配線が設けられ、前記電源電圧供給ブロックから出力される前記電源電圧を、前記長手方向から、前記画素ブロック及び前記複数の信号処理ブロックへ、給電可能である、複数の横給電配線が設けられ、前記縦給電配線と前記横給電配線とは接続されていることを特徴とする
光電変換装置を提供する。
図1は、本発明の第1実施形態に係る光電変換装置を示す。本発明の光電変換装置は、例えば、ビデオカメラやデジタルカメラ、複写機等、さまざまな撮像機器に用いられる、CMOSセンサとして機能する。
図2は、比較例に係る光電変換装置を示す。この比較例では、横長の光電変換装置において、横給電のみで給電を行っている。
「B(μm) > D(μm)×C(Ω/□)/A(μm)」
となり、必要な配線メタル幅は光電変換装置の長手方向の長さに比例する。
下記、画素ブロック内のカラムの構成について説明する。図3は、図1の光電変換装置の画素ブロック10内の詳細図である。
図4に、図3の画素ブロック内のスイッチや増幅器をトランジスタで構成した場合の回路図を示す。
図5は、本発明の第2実施形態に係る光電変換装置を示す。
本光電変換装置をCMOSセンサとして光電検出に用いる場合など、信号処理ブロック20A~20Z内での電源に対するノイズは、10bit出力換算で1LSB(least significant bit)相当以内に抑えるように設計している。
図6は、電源電圧供給ブロック30が複数(30A,30B)設けられる場合の光電変換装置を示す。図6に示すように、必ずしも電源電圧供給ブロック30は1つである必要はない。
図7は、電極パッド40が複数ある場合の光電変換装置を示す。図7に示すように、必ずしも電極パッド40や電源電圧供給ブロック30は1つである必要はない。
図8は、画素ブロック10内の給電方法の概略図を示す。
図9は、ノイズ源に対しては横給電のみを利用した場合の具体例である。図9において、(a)は光電変換装置を示し、(b)は信号処理ブロックAの拡大図であり、(c)は信号処理ブロックをサイクリック型A/Dコンバータで構成した場合の例を示す。
10 画素ブロック
20 信号処理ブロック
30 電源電圧供給ブロック
40,40A,40B 電極パッド
PU1,PU2,,,PUx,PUn カラム
RE,RO 赤色画素ユニット
GE,GO 緑色画素ユニット
BE,BO 緑色画素ユニット
11 画素
PD 光電変換素子
SW1 リセットスイッチ、リセットトランジスタ
SW2 転送スイッチ、転送トランジスタ
AMP1 第1の増幅器、第1の増幅トランジスタ
FD フロートディフュージョン領域(電荷電圧変換部)
12 アナログメモリ
SW3 メモリ書き込み選択スイッチ、メモリ書き込み選択トランジスタ
SW4,SW5 容量選択スイッチ、容量選択トランジスタ
SW6 画素選択スイッチ、画素選択トランジスタ
C1,C2 コンデンサ(容量),トランジスタ容量
13 第1の電流源
14 第2の電流源
15 第2の増幅器,第2の増幅トランジスタ
16 カラム信号処理部
Vrd リセット電圧、リセットドレイン電圧
Vm メモリ基準電圧
A 画素領域
B,C 余白領域
20A サイクリックA/Dコンバータ
21 センシティブ回路
22 ノイズ源
23 D/Aコンバータ(DAC)
25 コントロールロジック
HL 横給電配線
VL(VL1~VLn) 縦給電配線
VLx(p) 画素ブロック用縦給電配線
VLx(s) 信号処理ブロック用縦給電配線
Claims (8)
- 横長の長方形形状の光電変換装置であって、
複数の画素が配置された画素ブロックと、
前記画素ブロックから出力された信号を処理する、当該光電変換装置の短手方向に並列された複数の信号処理ブロックと、
前記画素ブロック及び前記複数の信号処理ブロックへ電源電圧を供給する電源電圧供給ブロックと、
前記電源電圧供給ブロックに接続される電極パッドと、を備えており、
前記複数の画素の夫々は、入射光に応じて光電変換を行う光電変換素子および光電変換された電荷を電圧に変換する増幅器を含む電荷電圧変換部を備え、
前記画素ブロックでは、所定の数毎の画素が一纏りの信号処理単位である1つのカラムとして設定され、複数の該カラムが当該光電変換装置の長手方向に並列されており、
前記電源電圧供給ブロックから出力される前記電源電圧を、前記短手方向から、前記画素ブロックの複数のカラム毎へ給電可能にする、複数の縦給電配線が設けられ、
前記電源電圧供給ブロックから出力される前記電源電圧を、前記長手方向から、前記画素ブロック及び前記複数の信号処理ブロックへ給電可能にする、複数の横給電配線が設けられ、
前記縦給電配線と前記横給電配線とは接続されていることを特徴とする
光電変換装置。 - 前記画素ブロックと、前記複数の信号処理ブロックの夫々のブロックとは、カラム毎に、異なる縦給電配線を介して給電される、
請求項1に記載の光電変換装置。 - 前記画素ブロックから前記電源電圧供給ブロックまでの前記縦給電配線の配線抵抗をY(Ω)、前記短手方向に並列される複数の信号処理ブロックのうち、前記画素ブロックに最も近接して配置される信号処理ブロックから、前記電源電圧供給ブロックまでの前記縦給電配線の配線抵抗をZ(Ω)とした際、「Z+Y>10*(Y-Z)」を満たすように配置する、
請求項2に記載の光電変換装置。 - 前記画素ブロックから前記電源電圧供給ブロックまでの前記縦給電配線の配線抵抗をY(Ω)、前記短手方向に並列される複数の信号処理ブロックのうち、前記画素ブロックに最も近接して配置される信号処理ブロックから、前記電源電圧供給ブロックまでの前記縦給電配線の配線抵抗をZ(Ω)とした際、「Z+Y>100*(Y-Z)」を満たすように配置する、
請求項2に記載の光電変換装置。 - 前記画素ブロックにおいて、前記複数の画素よりも、前記電源電圧供給ブロックから離れた部分に素子が配置される場合、
前記画素ブロックにおいて、少なくとも前記複数の画素よりも前記電源電圧供給ブロックに近接した部分について前記縦給電配線を用いて給電し、少なくとも前記複数の画素よりも前記電源電圧供給ブロックに離間した部分を、前記横給電配線を用いて給電する、
請求項1乃至4のいずれか一項に記載の光電変換装置。 - 前記各カラムにおいて、前記複数の画素には、夫々アナログメモリが接続され、前記複数のアナログメモリに共通して1つの電流源、及び1つの第2の増幅器に接続されており、前記複数の画素にある夫々の第1の増幅器への給電、前記光電変換素子への接地、前記電流源、及び前記第2の増幅器を、前記横給電配線を用いて給電する、
請求項5に記載の光電変換装置。 - 前記複数の信号処理ブロックの少なくとも1つの信号処理ブロックはサイクリック型A/Dコンバータであり、該サイクリック型A/Dコンバータ内において、D/Aコンバータとコントロールロジックの電源は横給電、その他の素子の電源は縦給電である、
請求項1乃至6のいずれか一項に記載の光電変換装置。 - 電源電圧供給ブロックの、前記電源電圧供給ブロックに近接する部分は、バイパスコンデンサを配置する、
請求項1乃至7のいずれか一項に記載の光電変換装置。
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