WO2017149956A1 - 信号出力回路 - Google Patents

信号出力回路 Download PDF

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Publication number
WO2017149956A1
WO2017149956A1 PCT/JP2017/001215 JP2017001215W WO2017149956A1 WO 2017149956 A1 WO2017149956 A1 WO 2017149956A1 JP 2017001215 W JP2017001215 W JP 2017001215W WO 2017149956 A1 WO2017149956 A1 WO 2017149956A1
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Prior art keywords
noise
output
circuit
signal
voltage
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PCT/JP2017/001215
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English (en)
French (fr)
Japanese (ja)
Inventor
典正 岡
博史 川合
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株式会社デンソー
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Application filed by 株式会社デンソー filed Critical 株式会社デンソー
Priority to CN201780014257.4A priority Critical patent/CN108702149B/zh
Priority to US16/065,199 priority patent/US10425069B2/en
Publication of WO2017149956A1 publication Critical patent/WO2017149956A1/ja

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K4/00—Generating pulses having essentially a finite slope or stepped portions
    • H03K4/06—Generating pulses having essentially a finite slope or stepped portions having triangular shape
    • H03K4/08—Generating pulses having essentially a finite slope or stepped portions having triangular shape having sawtooth shape
    • H03K4/48—Generating pulses having essentially a finite slope or stepped portions having triangular shape having sawtooth shape using as active elements semiconductor devices
    • H03K4/50—Generating pulses having essentially a finite slope or stepped portions having triangular shape having sawtooth shape using as active elements semiconductor devices in which a sawtooth voltage is produced across a capacitor
    • H03K4/56—Generating pulses having essentially a finite slope or stepped portions having triangular shape having sawtooth shape using as active elements semiconductor devices in which a sawtooth voltage is produced across a capacitor using a semiconductor device with negative feedback through a capacitor, e.g. Miller integrator
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/16—Modifications for eliminating interference voltages or currents
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018521—Interface arrangements of complementary type, e.g. CMOS
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H03K5/04—Shaping pulses by increasing duration; by decreasing duration
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H03K5/12—Shaping pulses by steepening leading or trailing edges
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/125—Discriminating pulses
    • H03K5/1252—Suppression or limitation of noise or interference
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks

Definitions

  • This disclosure relates to a signal output circuit that outputs a signal corresponding to the level of a control signal.
  • slope control is performed to control the rising and falling slopes (hereinafter referred to as slope) of an output signal for the purpose of suppressing radiation noise.
  • the slope control is generally performed by charging / discharging a capacitor and obtaining a desired slope waveform using the terminal voltage of the capacitor.
  • the capacitor is connected between the drain and gate of the output transistor whose drain is connected to the signal output terminal, the apparent capacitance when viewed from the input side (hereinafter simply referred to as capacitance) due to the Miller effect. Also called). Therefore, a desired slope waveform can be obtained using a capacitor having a relatively small capacity. However, in this configuration, when noise is superimposed on the output terminal, the noise propagates to the internal circuit through the capacitor and may cause malfunction.
  • Patent Document 1 discloses a technique for preventing the above-described malfunction.
  • the internal node voltage and the internal node where the slope-controlled signal is generated and the output terminal for outputting the signal are connected without adding the current mirror circuit or the like. Make the output terminal voltage equal. With such a configuration, the occurrence of malfunction when noise is superimposed on the output terminal can be prevented while realizing slope control of the output signal.
  • the minimum operating voltage is increased by the threshold voltage Vt of the transistors configuring the current mirror circuit.
  • a communication driver for in-vehicle communication such as LIN (Local Interconnect Network)
  • LIN Local Interconnect Network
  • An object of the present disclosure is to provide a signal output circuit that can prevent malfunction due to noise superimposed on an output terminal while suppressing an increase in circuit scale and an increase in minimum operating voltage.
  • the signal output circuit controls the drive of the output transistor based on a control signal input from the outside, so that the control signal is output from the output terminal connected to one main terminal of the output transistor.
  • An output signal having a level corresponding to the level of the signal is output.
  • the signal output circuit includes a feedback capacitor, a slope control circuit, a noise detection circuit, and a malfunction prevention circuit.
  • the feedback capacitor has a first terminal and a second terminal, and the first terminal is connected to the output terminal.
  • the slope control circuit charges and discharges the feedback capacitor according to the level of the control signal, and controls the slope of the output signal by driving the output transistor using the voltage of the second terminal of the feedback capacitor.
  • the noise detection circuit detects noise superimposed on the output terminal.
  • the malfunction prevention circuit drives the output transistor so that when a noise is detected by the noise detection circuit, an output signal having a level corresponding to the level of the control signal is output regardless of the output transistor being driven by the slope control circuit. Performs forced drive operation.
  • the output transistor when noise is superimposed on the output terminal, the output transistor is forcibly driven by the malfunction prevention circuit regardless of the drive of the output transistor by the slope control circuit. Therefore, even if the noise propagates to the slope control circuit through the feedback capacitor and the noise affects the operation of the slope control circuit, a malfunction that the output signal becomes an unintended level does not occur.
  • the noise detection circuit and the malfunction prevention circuit can be configured by elements that operate with the same power supply as other internal circuits. Therefore, according to the above configuration, even when the output side voltage is higher than the operating voltage of the internal circuit, it is not necessary to use a high breakdown voltage element, and an increase in circuit scale can be suppressed. Further, the above configuration does not require a current mirror circuit for determining the voltage of the output terminal, so that there is no restriction that the minimum operating voltage becomes high.
  • FIG. 1 is a diagram schematically showing a configuration of a signal output circuit according to the first embodiment.
  • FIG. 2 is a diagram showing a specific configuration of the noise detection circuit
  • FIG. 3 is a diagram showing a specific configuration of the malfunction prevention circuit
  • FIG. 4 is a diagram showing a truth table of the logic circuit constituting the malfunction prevention circuit
  • FIG. 5 is a waveform diagram of each part for explaining the noise detection operation.
  • FIG. 6 is a waveform diagram of each part for explaining the stop of the forced drive operation.
  • FIG. 7 is a waveform diagram showing an output signal, FIG.
  • FIG. 8 is a diagram illustrating a specific configuration of the noise detection circuit according to the second embodiment.
  • FIG. 9 is a diagram illustrating a specific configuration example of the voltage converter
  • FIG. 10 is a waveform diagram of each part for explaining the noise detection operation.
  • FIG. 11 is a diagram illustrating a specific configuration of the noise detection circuit according to the third embodiment.
  • FIG. 12 is a waveform diagram of each part for explaining the noise detection operation.
  • FIG. 13 is a diagram schematically showing a configuration of a signal output circuit in which the configuration of the output stage is changed
  • FIG. 14 is a first diagram illustrating another specific configuration example of the voltage converter
  • FIG. 15 is a second diagram illustrating another specific configuration example of the voltage conversion unit.
  • the signal output circuit 1 controls the drive of the N-channel type MOS transistor 3 based on the control signal IN inputted from the outside through the input terminal 2, thereby controlling the control signal IN from the output terminal 4.
  • the output signal OUT of a level corresponding to the level of is output.
  • the control signal IN and the output signal OUT are both digital signals that represent a binary value at two voltage levels: a high level (hereinafter referred to as H level) and a low level (hereinafter referred to as L level). Therefore, the level described above corresponds to a voltage level.
  • the transistor 3 corresponds to an output transistor, and its source is connected to the ground GND as a reference potential of the circuit, and its drain is connected to the output terminal 4 and to the power source VB via the resistor 5.
  • the power source VB is supplied from, for example, a battery (not shown), and the steady value of the voltage is about + 12V.
  • the driving of the transistor 3 is controlled by the slope control circuit 6 or the malfunction prevention circuit 7. Therefore, the gate of the transistor 3 is connected via the buffer 8 to the node N1 to which the output of the slope control circuit 6 is applied, and to the node N2 to which the output of the malfunction prevention circuit 7 is applied.
  • the drain of the transistor 3 corresponds to one main terminal, and the gate corresponds to a conduction control terminal.
  • a capacitor 9 is connected between the output terminal 4 and the node N1.
  • the capacitor 9 corresponds to a feedback capacitor, and of the two terminals, the terminal on the output terminal 4 side corresponds to the first terminal, and the terminal on the node N1 side corresponds to the second terminal.
  • the slope control circuit 6 includes a current source 10, a P channel type MOS transistor 11, an N channel type MOS transistor 12, and a current source 13 connected in series between a power supply VDD and a ground GND.
  • the power supply VDD is a power supply for operation of the signal output circuit 1, and the steady value of the voltage is about + 5V.
  • the drains of the transistors 11 and 12 are connected to the node N 1, and the gates are connected to the input terminal 2.
  • the input terminal 2 is supplied with a control signal IN from a control circuit (not shown) that controls the operation of the signal output circuit 1.
  • the slope control circuit 6 charges the capacitor 9 when the control signal IN is at the L level, and discharges the capacitor 9 when the control signal IN is at the H level.
  • the voltage Vc at the second terminal of the capacitor 9 that is charged and discharged in this way is applied to the gate of the transistor 3 via the buffer 8. Therefore, the transistor 3 is driven in accordance with the voltage Vc that changes with the charging / discharging of the capacitor 9, and as a result, the slope of the output signal OUT is controlled.
  • the values of the currents I1 and I2 output from the current sources 10 and 13 are appropriately set according to a desired control amount of the slope, that is, a desired inclination of the output signal OUT.
  • the noise detection circuit 14 indirectly detects noise superimposed on the output terminal OUT based on the voltage Vc, and determines whether or not the noise has periodicity.
  • the noise detection signal Sa output from the noise detection circuit 14 is given to the malfunction prevention circuit 7.
  • the noise detection signal Sa becomes H level when periodic noise is detected.
  • the noise detection circuit 14 can be configured by a comparison circuit 15, a count unit 16, a periodicity determination unit 17, and a detection cancellation unit 18, as shown in FIG.
  • the comparison circuit 15, the count unit 16, the periodicity determination unit 17, and the detection release unit 18 all operate with the supply of the power supply VDD.
  • the comparison circuit 15 composed of a comparator or the like compares the voltage Vc and the voltage Vth, and outputs a pulse signal Sb that is inverted when the voltage Vc reaches the voltage Vth.
  • the voltage Vth is switched according to the level of the control signal IN. Specifically, during the period when the control signal IN is at the H level, that is, during the off period of the transistor 3, it is higher than the steady value of the voltage Vc during that period and than the value of the voltage Vc when the transistor 3 starts to turn on. Is also set to a low voltage. Further, during the period when the control signal IN is at L level, that is, the ON period of the transistor 3, the voltage is lower than the steady value of the voltage Vc in that period and higher than the voltage Vc when the transistor 3 starts to turn OFF. Set to
  • the counting unit 16 including a counter counts the number of rising or falling edges of the pulse signal Sb, that is, the number of pulses of the pulse signal Sb.
  • the period of the pulse signal Sb counted by the counting unit 16 is approximately equal to the period of noise. Therefore, the number of counts by the count unit 16 corresponds to the number of noise cycles.
  • the detection canceling unit 18 including a logic circuit or the like starts measuring the predetermined end determination period Ta from the time when the voltage Vc reaches the voltage Vth and the pulse signal Sb is inverted.
  • the end determination period Ta is measured based on the clock signal CLK.
  • the detection cancellation unit 18 outputs a cancellation signal Sc when the pulse signal Sb is not inverted during the end determination period Ta. Further, when the pulse signal Sb is inverted during the end determination period Ta, the detection canceling unit 18 resets the measurement value to zero at that time and newly starts measuring the end determination period Ta.
  • the periodicity determination unit 17 sets the noise detection signal Sa to the L level.
  • the malfunction prevention circuit 7 executes the forced drive operation when the noise detection signal Sa given from the noise detection circuit 14 is at the H level.
  • the forced drive operation is an operation of driving the transistor 3 so that the output signal OUT having a level corresponding to the level of the control signal IN is output regardless of the drive of the transistor 3 by the slope control circuit 6.
  • the malfunction prevention circuit 7 performs a forced drive operation when the noise detection circuit 14 detects periodic noise.
  • the malfunction prevention circuit 7 stops executing the forced drive operation when the noise detection signal Sa is at the L level. That is, the malfunction prevention circuit 7 does not execute the forcible driving operation in a period in which noise is not detected by the noise detection circuit 14 and a period in which noise having no periodicity is detected. Further, the malfunction prevention circuit 7 ends the forced drive operation when the state in which no noise is detected by the noise detection circuit 14 continues for the end determination period Ta after the forced drive operation is started.
  • Such a malfunction prevention circuit 7 can be constituted by a CMOS circuit 19 and a logic circuit 20 as shown in FIG.
  • the P-channel type MOS transistor 21 and the N-channel type MOS transistor 22 constituting the CMOS circuit 19 are connected in series between the power supply VDD and the ground GND.
  • the drains of the transistors 21 and 22 are connected to the gate of the transistor 3.
  • Drive signals HG and LG output from the logic circuit 20 are applied to the gates of the transistors 21 and 22, respectively.
  • the noise detection signal Sa and the control signal IN are input to the logic circuit 20.
  • the logic circuit 20 generates and outputs drive signals HG and LG based on the input signals Sa and IN. Specifically, as shown in FIG. 4, when the noise detection signal Sa is at the L level, the logic circuit 20 is a drive signal for turning off the transistors 21 and 22 regardless of the level of the control signal IN. HG and LG are output. That is, when the noise detection signal Sa is at the L level, the forced drive operation is not executed.
  • the logic circuit 20 turns on one of the transistors 21 and 22 according to the level of the control signal IN, and forcibly drives the transistor 3 on or off. . That is, when the noise detection signal Sa is at the H level, the forced drive operation is executed.
  • the noise detection signal Sa turns to H level.
  • the malfunction prevention circuit 7 executes a forced drive operation.
  • the signal output circuit 1 outputs an output signal OUT having a level corresponding to the level of the control signal IN. However, slope control is not performed on the output signal OUT at this time.
  • the release signal Sc is output from the detection release unit 18 at the time t2 when the measurement is finished. Is done.
  • the periodicity determination unit 17 sets the noise detection signal Sa to the L level, and as a result, the malfunction prevention circuit 7 ends the forced drive operation. Therefore, the signal output circuit 1 outputs an output signal OUT that is at a level corresponding to the level of the control signal IN and is slope-controlled.
  • the signal output circuit 1 of the present embodiment described above the following effects can be obtained.
  • the forced drive operation by the malfunction prevention circuit 7 is executed. For this reason, even if the superimposed noise propagates to the slope control circuit 6 through the capacitor 9 and the noise affects the operation of the slope control circuit 6, a malfunction that the output signal OUT becomes an unintended level may occur. Absent. That is, even if noise is superimposed on the output terminal 4, the signal output circuit 1 outputs the output signal OUT having a level corresponding to the level of the control signal IN only by losing the slope control. The main operation can be continued.
  • the slope of the output signal OUT is not necessarily lost. This is because even if the forced drive operation is performed during the period in which the level of the output signal OUT does not change, that is, during the period when the output signal OUT is stable at the H level or the L level, as in the period Tb of FIG. Can output the output signal OUT having a waveform having a slope as in the normal state.
  • the periphery of the signal output circuit 1 is considered to be a noise environment. In such an environment, since it is less necessary to suppress noise radiated from the circuit, the slope control of the signal output circuit 1 is lost, and even if the radiated noise increases, no serious problem occurs. .
  • the noise detection circuit 14 and the malfunction prevention circuit 7 are composed of elements that operate with the same power supply VDD as other circuits constituting the signal output circuit 1. Therefore, according to the signal output circuit 1, even when the output side voltage is higher than the operation voltage of the circuit as in the present embodiment, it is not necessary to use a high breakdown voltage element, and an increase in circuit scale can be suppressed.
  • the signal output circuit 1 does not require a current mirror circuit for determining the voltage at the output terminal 4, so that there is no restriction that the minimum operating voltage becomes high.
  • the malfunction prevention circuit 7 is configured to execute a forced drive operation when noise having a periodicity is detected by the noise detection circuit 14. Therefore, it is possible to prevent a malfunction such that a forced drive operation is performed based on erroneous detection of noise. For example, even if the voltage Vc reaches the voltage Vth due to overshoot or undershoot due to an operation such as normal slope control, the forced drive operation is not immediately executed.
  • the noise detection circuit 14 uses a count unit 16 that counts the number of pulses of the pulse signal Sb and a periodicity determination unit 17 that sets the noise detection signal Sa to the H level when the count number exceeds a predetermined number. It is configured to detect characteristic noise. These configurations can be configured by a counter and a small-scale logic circuit. Therefore, it is possible to suppress an increase in the circuit size of the noise detection circuit 14 and thus the signal processing circuit 1.
  • the malfunction prevention circuit 7 starts the forced drive operation, when no noise is detected, the forced drive operation is terminated. Thereby, when noise disappears, slope control is quickly recovered, and noise emission by the signal output circuit 1 can be suppressed. Further, in this case, the signal output circuit 1 is configured to end the forced drive operation when the state in which no noise is detected continues for the end determination period Ta. According to such a configuration, it is possible to prevent the execution and termination of the forced drive operation by the malfunction prevention circuit 7 from being repeated when noise generated intermittently with a relatively short interval is superimposed.
  • the signal output circuit 1 can be applied to a communication driver for in-vehicle communication, for example, a LIN communication driver.
  • the assumed noise is a sine wave noise of about 1 MHz to 1 GHz, and its cycle is shorter than 1 ⁇ s.
  • the cycle of the pulse signal Sb counted by the counting unit 16 is approximately equal to the cycle of noise. Therefore, when such noise is superimposed on the output terminal 4, the time required until the noise is detected by the noise detection circuit 14 is about 4 ⁇ s at most.
  • the communication rate of LIN is about 10 kHz, and the pulse width of the pulse signal used for the communication is about 50 ⁇ s.
  • the signal output circuit 1 is applied to a LIN communication driver, the period required for the noise detection circuit 14 to determine that the noise superimposed on the output terminal 4 has periodicity is a communication period. Compared to the period, the period is extremely short.
  • the signal output circuit 1 performs the forcible driving operation after detecting periodic noise, a microcomputer or the like that receives the output signal OUT serving as a communication signal and performs some processing, It is possible to prevent the occurrence of a problem of erroneously determining the OUT level, so-called bit corruption.
  • the end determination period Ta measured by the detection canceling unit 18 may be set to a period shorter than the communication cycle (for example, 8 ⁇ s). In this way, after the noise disappears, the slope control is quickly recovered, and the noise radiated from the signal output circuit 1 can be appropriately suppressed.
  • the signal output circuit 1 has a configuration in which a buffer 8 is interposed between the node N1 and the gate of the transistor 3.
  • the main path through which the noise propagates is the capacitor 9.
  • a parasitic capacitance (not shown) exists between the drain and gate of the transistor 3. Since the transistor 3 is provided in the output stage, the transistor 3 has a large size for ensuring driving capability, and the parasitic capacitance is relatively large. Therefore, the noise superimposed on the output terminal 4 may propagate to an internal circuit such as the slope control circuit 6 through the parasitic capacitance.
  • the buffer 8 By providing the buffer 8 as described above, the noise propagation path through the parasitic capacitance is cut off, so that the transistor 3 malfunctions due to the noise and the output signal OUT becomes an unintended level. Can be prevented. In addition, by providing the buffer 8, the impedance of the gate node of the transistor 3 is lowered, and the noise amplitude can be suppressed.
  • the noise detection circuit 31 includes a voltage conversion unit 32, a comparison circuit 33, and a periodicity determination unit 34.
  • the voltage conversion unit 32 When the voltage Vc changes due to noise superimposed on the output terminal 4, the voltage conversion unit 32 generates a voltage Va that gradually increases every time the change occurs. That is, the voltage Va corresponds to the sum of the number of noise cycles.
  • the comparison circuit 33 including a comparator compares the voltage Va and the voltage Vth, and outputs a pulse signal Sd that becomes H level when the voltage Va reaches the voltage Vth.
  • the voltage Vth corresponds to a determination voltage.
  • the voltage Vth is switched according to the level of the control signal IN. Specifically, it is set to a predetermined voltage higher than GND and lower than VDD while the control signal IN is at the H level. Further, the voltage is set to a predetermined voltage higher than VDD while the control signal IN is at the L level.
  • the periodicity determination unit 34 sets the noise detection signal Sa to the H level and outputs the reset signal Se.
  • the voltage conversion unit 32 resets the voltage Va to zero.
  • the periodicity determination unit 34 starts measuring the reset period Te from the time when the reset signal Se is output.
  • the reset period Te is set to a period longer than the period required for the voltage Va to rise from zero to the voltage Vth when the assumed periodic noise is superimposed on the output terminal 4. If the pulse signal Sd changes to the H level again until the measurement of the reset period Te is completed, the periodicity determination unit 34 again outputs and resets the reset signal Se while keeping the noise detection signal Sa at the H level.
  • the measurement of the cycle Te is started.
  • the periodicity determination unit 34 sets the noise detection signal Sa to the L level if the pulse signal Sd does not turn to the H level again until the measurement of the reset period Te is completed.
  • the voltage Va rises again to the voltage Vth until the measurement of the reset period Te by the periodicity determination unit 34 is completed, and the H level of the noise detection signal Sa is maintained, so that the forced drive operation is continued. To be implemented. Therefore, the operation of the entire signal output circuit 1 at this time is the same as that of the first embodiment.
  • the noise detection circuit 31 detects the noise based on whether or not the voltage Va corresponding to the sum of the number of noise cycles reaches the voltage Vth. Therefore, according to the present embodiment, it is possible to detect noise having a frequency sufficiently higher than the frequency characteristics regardless of the frequency characteristics of the comparator or the like constituting the comparison circuit 33.
  • the noise detection circuit 41 is different from the noise detection circuit 14 of the first embodiment in that it includes a periodicity determination unit 42 instead of the count unit 16 and the periodicity determination unit 17.
  • the periodicity determination unit 42 starts measuring a predetermined periodicity determination period Tf from time t1 when the pulse signal Sb is first inverted.
  • the periodicity determination unit 42 sets the noise detection signal Sa to the H level at the end time t2 of the measurement period.
  • the noise detection circuit 41 of the present embodiment whether periodic noise is superimposed based on whether or not the edge of the pulse signal Sb is continuously detected during the predetermined periodicity determination period Tf. Since it is determined whether or not, the period required for the determination is constant regardless of the period of noise. Thus, according to the present embodiment, since it is possible to detect the presence or absence of periodic noise within a predetermined period regardless of the period of the noise, even when low frequency noise is superimposed, the detection up to the detection is possible. Time does not become unnecessarily long.
  • the pulse width of the pulse signal Sb in the first and third embodiments changes according to a period during which the voltage Vc exceeds the voltage Vth. In other words, the pulse width changes based on a temporal change in noise. I was supposed to.
  • the pulse width of the pulse signal Sb may be fixed. For example, if a configuration is adopted in which the pulse signal is turned to H level when the voltage Vc reaches the voltage Vth, and the pulse signal is turned to L level after a predetermined fixed period has elapsed from that point, the pulse of the pulse signal Sb The width can be fixed. In this way, the pulse signal Sb having a constant pulse width is generated regardless of how the noise changes, so that a pulse omission such that a pulse that should originally be generated is not generated does not occur.
  • the N-channel MOS transistor 3 is used as the output transistor and the drain thereof is pulled up by the resistor 5, that is, the signal output circuit having the low-side drive configuration.
  • the resistor 5 that is, the signal output circuit having the low-side drive configuration.
  • a configuration in which a P-channel type MOS transistor 52 is used as an output transistor and its drain is pulled down by a resistor 53, that is, a high side drive configuration may be used.
  • the noise detection circuit does not need to determine whether or not there is noise periodicity. That is, a configuration may be adopted in which a forced drive operation is immediately executed when it is detected that noise is superimposed on the output terminal 4.
  • the buffer 8 may not be provided.
  • a configuration as shown in FIGS. 14 and 15 may be adopted.
  • the configuration of FIG. 14 is obtained by adding a resistor R1 to the configuration of FIG.
  • the resistor R1 is for discharging the electric charge charged in the capacitor C1, and is connected in parallel to the capacitor C1. If such a configuration is adopted, the operation for canceling the forced drive operation by the periodicity determination unit 34 can be changed as follows.
  • the periodicity determination unit 34 is configured to turn the noise detection signal Sa to the L level when the voltage Va decreases to a threshold such as the voltage Vth. In this way, the forced drive operation can be canceled with a simpler configuration. In this case, the release time until the forced drive operation is completed can be adjusted by setting threshold values such as the capacitance value of the capacitor C1, the resistance value of the resistor R1, and the voltage Vth.
  • the 15 includes a diode D2, a capacitor C2, and a resistor R2.
  • the diode D2 is connected between the input node to which the voltage Vc is applied and the output node that outputs the voltage Va with the output node side as an anode.
  • the capacitor C2 is connected between the output node and the ground.
  • the resistor R2 is for charging the capacitor C2, and is connected in parallel to the diode D2.
  • the capacitor C2 is charged through the resistor R2 in a normal state in which noise is not superimposed, and the voltage Va is close to VDD.
  • the capacitor C2 is discharged through the diode D2 each time, and the voltage Va gradually decreases. Thereafter, when the voltage Va reaches the voltage Vth, the noise detection signal Sa changes to H level, and the malfunction prevention circuit 7 executes the forced drive operation.
  • the operation for canceling the forced drive operation by the periodicity determination unit 34 can be changed as follows. That is, in the configuration of FIG. 15, when noise is not superimposed, the discharge of the capacitor C ⁇ b> 2 is stopped and the voltage Va increases according to the RC time constant. Therefore, the periodicity determination unit 34 is configured to turn the noise detection signal Sa to the L level when the voltage Va rises to a threshold value such as the voltage Vth. In this way, the forced drive operation can be canceled with a simpler configuration. In this case as well, the release time can be adjusted by setting each circuit constant as in the configuration of FIG.

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PCT/JP2017/001215 2016-03-01 2017-01-16 信号出力回路 WO2017149956A1 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN201780014257.4A CN108702149B (zh) 2016-03-01 2017-01-16 信号输出电路
US16/065,199 US10425069B2 (en) 2016-03-01 2017-01-16 Signal output circuit

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2016-038953 2016-03-01
JP2016038953A JP6638474B2 (ja) 2016-03-01 2016-03-01 信号出力回路

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US (1) US10425069B2 (zh)
JP (1) JP6638474B2 (zh)
CN (1) CN108702149B (zh)
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JP2017158010A (ja) 2017-09-07
JP6638474B2 (ja) 2020-01-29
CN108702149B (zh) 2022-03-22
CN108702149A (zh) 2018-10-23
US10425069B2 (en) 2019-09-24
US20190020332A1 (en) 2019-01-17

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