WO2017143998A1 - 晶体管的驱动电路 - Google Patents

晶体管的驱动电路 Download PDF

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Publication number
WO2017143998A1
WO2017143998A1 PCT/CN2017/074625 CN2017074625W WO2017143998A1 WO 2017143998 A1 WO2017143998 A1 WO 2017143998A1 CN 2017074625 W CN2017074625 W CN 2017074625W WO 2017143998 A1 WO2017143998 A1 WO 2017143998A1
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Prior art keywords
voltage power
circuit
high voltage
power supply
transistor
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PCT/CN2017/074625
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English (en)
French (fr)
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傅平
高飞
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比亚迪股份有限公司
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Application filed by 比亚迪股份有限公司 filed Critical 比亚迪股份有限公司
Priority to EP17755827.7A priority Critical patent/EP3422546B1/en
Publication of WO2017143998A1 publication Critical patent/WO2017143998A1/zh
Priority to US16/110,147 priority patent/US10574224B2/en

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
    • H02H9/045—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
    • H03K17/081—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
    • H03K17/08104—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit in field-effect transistor switches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
    • H03K17/081—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
    • H03K17/0814—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the output circuit
    • H03K17/08142—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the output circuit in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
    • H03K17/082—Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit
    • H03K17/0822—Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/16—Modifications for eliminating interference voltages or currents
    • H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches
    • H03K17/162—Modifications for eliminating interference voltages or currents in field-effect transistor switches without feedback from the output circuit to the control circuit
    • H03K17/163—Soft switching
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/16—Modifications for eliminating interference voltages or currents
    • H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches
    • H03K17/165—Modifications for eliminating interference voltages or currents in field-effect transistor switches by feedback from the output circuit to the control circuit
    • H03K17/166—Soft switching
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only

Definitions

  • the present application relates to the field of driving circuit technologies, and in particular, to a driving circuit for a transistor.
  • High-voltage transistor driver chip mainly used to drive MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), IGBT (Insulated Gate Bipolar Transistor) and other power devices, commonly used In the field of industrial and home appliance frequency conversion. Since the high-voltage transistor driver chip has two power domains of high and low voltage, the static electricity between the power domains needs to be discharged through the high-voltage device, but the withstand voltage of the device is increased, and its own ESD (Electrostatic Discharge) capability is lowered, so it is high. ESD capabilities between low-voltage power domains are not strong.
  • MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor
  • IGBT Insulated Gate Bipolar Transistor
  • the chip contains two power domains: a low-voltage power domain (VCC is a low-voltage power supply, VSS is a low-voltage ground), a high-voltage power supply domain (VB is a high-voltage power supply, and VS is a high-voltage ground), and the two power domains pass between
  • the level shifting circuit, the level-shifter circuit (level shifting, internally structured, two independent level-shifter1, level-shifter2) and high voltage ESD devices are connected together. Inside the independent power domain, there is a separate ESD device between the power supply and ground VB-VS, VCC-VSS (commonly used diodes, transistors, CMOS tubes, etc.) for venting ESD.
  • Level-shifter mainly includes: DMOS (M1, M2 in Figure 7), DMOS source device (source in Figure 7 is grounded), DMOS drain detection circuit (in Figure 7 by sense resistor R1, R2 and Zener Z1) , Z2 constitutes).
  • DMOS-M1, M2 is turned on and off, and the voltage on the detecting resistors R1, R2 is changed, thereby realizing the conversion of the low voltage signal to the high voltage signal.
  • the level-shifter circuit When there is static electricity between the high-voltage power supply domain and the low-voltage power supply domain, the level-shifter circuit is used to bleed and discharge, and the ESD capability of the circuit device itself is used to vent static energy, but DMOS's own ESD bleed capability is weak and easily damaged. The overall ESD capability of the chip is not strong.
  • the present application aims to solve at least one of the technical problems in the related art to some extent.
  • the purpose of the present application is to propose a driving circuit for a transistor.
  • the driving circuit of the transistor has the advantage of strong antistatic capability, thereby improving the stability and reliability of the driving circuit of the transistor.
  • an embodiment of the present application discloses a driving circuit for a transistor, including: a high voltage power supply and a low voltage power supply; a high voltage power domain circuit and a low voltage power domain circuit, wherein the high voltage power domain circuit is connected to the high voltage power supply.
  • the low-voltage power domain circuit is connected to the low-voltage power source; the static electricity discharge device is respectively disposed between two poles of the high-voltage power source, between two poles of the low-voltage power source, and a positive pole of the high-voltage power source Between the negative poles of the low voltage power supply; a level shifting circuit, the level shifting circuit includes a level detecting circuit, a current limiting module, a bleeder module, and a switch tube, and the level detecting circuit and the positive pole of the high voltage power supply Connected to and connected to the current limiting module, the bleeder module, and the high voltage power domain circuit, the current limiting module is further connected to the first end of the switch tube, and the bleeder module is further a negative pole of the high voltage power supply is connected, a control end of the switch tube is connected to the low voltage power domain circuit, and a second end of the switch tube is opposite to a negative pole of the low voltage power supply
  • the current limiting module is configured to limit a bleeder
  • a current limiting module is added to the level shifting circuit to increase the internal resistance of the path for electrostatic discharge through the level shifting circuit, thereby limiting the path during static discharge.
  • the current prevents the level shift circuit from being damaged.
  • the electrostatic discharge device such as a high voltage ESD device
  • the electrostatic discharge device is turned on, and the partial energy is amplified, thereby protecting the driving circuit of the transistor.
  • the bleeder module is added in the level shifting circuit to provide a low-resistance path from the negative pole of the high-voltage power supply to the drain of the switch tube.
  • the module can clamp the potential of the level detection circuit to prevent the potential from being lower than the negative voltage of the high voltage power supply.
  • the driving circuit of the transistor has strong antistatic capability, thereby improving the stability and reliability of the driving circuit of the transistor.
  • FIG. 1 is a structural diagram of a driving circuit of a transistor according to an embodiment of the present application.
  • FIG. 2 is a circuit diagram of a driving circuit of a transistor according to a first embodiment of the present application
  • FIG. 3 is a circuit diagram of a driving circuit of a transistor according to a second embodiment of the present application.
  • FIG. 4 is a circuit diagram of a driving circuit of a transistor according to a third embodiment of the present application.
  • FIG. 5 is a circuit diagram of a driving circuit of a transistor according to a fourth embodiment of the present application.
  • FIG. 6 is a circuit diagram of a driving circuit of a transistor according to a fifth embodiment of the present application.
  • Fig. 7 is a circuit diagram of a drive circuit of a transistor in the related art.
  • a driving circuit 100 for a transistor according to an embodiment of the present application includes: a high voltage power supply 110, a low voltage power supply 120, a high voltage power domain circuit 130, a low voltage power domain circuit 140, and an electrostatic discharge device. 150 and level shifting circuit 160.
  • the high voltage and low voltage in the high voltage power supply and the low voltage power supply are used to represent two different voltage power sources.
  • the high voltage and low voltage in the high voltage power domain circuit and the low voltage power domain circuit are used to indicate two different Voltage domain circuit.
  • the voltage of the high-voltage power supply can be 20V
  • the voltage of the low-voltage power supply can be 10V
  • the voltage of the high-voltage power supply domain circuit can be 20V
  • the voltage of the low-voltage power supply domain circuit can be 10V
  • the voltage of the high-voltage power supply domain circuit can be 10V
  • the voltage of the low-voltage power supply domain circuit can be 10V
  • the voltage can be 7V
  • the voltage of the high voltage power domain circuit can be 10V
  • the voltage of the low voltage power domain circuit can be 7V.
  • the high voltage power domain circuit 130 is connected to the high voltage power source 110
  • the low voltage power domain circuit 140 is connected to the low voltage power source 120.
  • the static electricity discharge device 150 is disposed between the two poles of the high voltage power source 110 (ie, between the positive electrode VB and the negative electrode VS), between the two poles of the low voltage power source 120 (ie, between the positive electrode VCC and the negative electrode VSS), and the positive electrode VB of the high voltage power source 110. Between the negative electrode VSS of the low voltage power supply 120.
  • the level shifting circuit 160 includes a level detecting circuit 161, a current limiting module 162, a bleeder module 163, and a switch 164.
  • the first end of the level detecting circuit 161 is connected to the positive terminal VB of the high voltage power supply 110 and The second end is connected to the first end of the current limiting module 162, the first end of the bleeder module 163, and the high voltage power domain circuit 130.
  • the second end of the current limiting module 162 is connected to the first end of the switch tube 164, and is vented.
  • the second end of the module 163 is connected to the negative pole VS of the high voltage power supply 130.
  • the control end of the switch tube 164 is connected to the low voltage power domain circuit 140 and the second end is connected to the negative pole VSS of the low voltage power supply 120.
  • the current limiting module 162 is used in the driving circuit.
  • the bleeder current is limited when electrostatic discharge is performed, and the bleeder module 163 is configured to form an auxiliary bleed passage between the negative electrode VS of the high voltage power source 110 and the first end of the switch tube 164 to assist in electrostatic discharge of the drive circuit.
  • the level detecting circuit 161 includes a Zener diode Z1 and a first resistor R1, and the cathode of the Zener diode Z1 is connected to the anode VB of the high voltage power source 110, and the Zener diode Z1
  • the anode is connected to the high voltage power domain circuit 130 (ie, the anode of the Zener Z1 is connected to the high voltage power domain circuit 130 through the detection point A1), and the first resistor R1 is connected in parallel with the Zener diode Z1.
  • the current limiting module 162 includes a current limiting resistor R3.
  • the bleeder module 163 includes a first diode D3, the cathode of the first diode D3 is connected to the anode of the Zener diode Z1, and the anode of the first diode D3 is high
  • the negative electrode VS of the voltage source 110 is connected.
  • the switch transistor 164 is the second MOS transistor M1. Further, the control terminal of the switch transistor 164 is the gate G of the second MOS transistor M1, and the first terminal is the drain of the second MOS transistor M1. D, the second end is the source S of the second MOS transistor M1.
  • the electrostatic discharge device 150 includes a third electrostatic discharge device 151, a fourth electrostatic discharge device 152, and a fifth electrostatic discharge device 153.
  • the third static electricity discharge device 151 and the fourth static electricity discharge device 152 are ESD devices (Electrostatic Discharge).
  • the fifth electrostatic discharge device 153 is, for example, a high voltage Isolation Junction shown in FIG. 2.
  • the third static electricity discharge device 151 is an ESD device disposed between the two poles of the high voltage power source 110, that is, between the positive electrode VB and the negative electrode VS of the high voltage power source 110.
  • the fourth static electricity discharge device 152 is an ESD device disposed between the two poles of the low voltage power source 110, that is, between the positive electrode VCC and the negative electrode VSS of the low voltage power source 120.
  • the fifth static electricity discharge device 153 is disposed between the positive electrode VB of the high voltage power source 110 and the negative electrode VSS of the low voltage power source 120, that is, the high voltage ESD device 153 disposed between the positive electrode VB of the high voltage power source 110 and the negative electrode VSS of the low voltage power source 120.
  • a driving circuit 100 including transistors of two level shifting circuits 160 connected in parallel and having the same structure is shown.
  • the other level shifting circuit 160 is composed of a Zener diode Z2, a resistor R2, a resistor R4, a diode D4, and a MOS transistor M2. I will not repeat them here.
  • the high voltage power domain circuit 130 and the low voltage power domain circuit 140 are connected by a level shift circuit 160, while the high voltage power domain circuit 130 and the low voltage power domain circuit 140 also pass a high voltage ESD. Device connection.
  • the level shifting circuit 160 mainly performs level shifting to convert a signal in a low voltage region to a high voltage region, thereby realizing signal transmission.
  • there are two parallel level shifting circuits 160 one of which has a high voltage device DMOS (Double-Diffused MOSFET), that is, a gate of the second MOS transistor M1.
  • DMOS Double-Diffused MOSFET
  • the pole signal is generated by the low voltage power domain circuit 140, the source of the second MOS transistor M1 is connected to the cathode VSS of the low voltage power source 120, the drain is connected to the other end of the resistor R3, and the end of the resistor R3 is connected to the anode of the Zener diode Z1.
  • the cathode of Z1 is connected to the positive electrode VB of the high voltage power supply 110, the first resistor R1 is connected in parallel with the Zener diode Z1, the anode of the Zener diode Z1 is the detection point A1, and the electrical signal of the detection point A1 is used as the input signal of the high voltage power domain circuit 130.
  • the cathode of a diode D3 is connected to the detection point A1, and the anode is connected to the negative electrode VS of the high voltage power supply 110.
  • the high voltage device DMOS of the other level shifting circuit 160 that is, the gate signal of the MOS transistor M2 is generated by the low voltage power domain circuit 140, the source is connected to the negative electrode VSS of the low voltage power supply 120, the drain is connected to the other end of the resistor R4, and one end of the resistor R4 is connected.
  • the cathode of the Zener Z2 is connected to the positive VB of the high voltage power supply 110, the resistance R2 is connected in parallel with the Zener Z2, the anode of the Zener Z2 is the detection point A2, and the electrical signal of the detection point A2 is used as the high voltage.
  • Input signal of power domain circuit 130, diode D4 The pole is connected to the detection point A2, and the anode is connected to the cathode VS of the high voltage power source 110.
  • the second MOS transistor M1 of the high voltage device DMOS by controlling the second MOS transistor M1 of the high voltage device DMOS, a varying voltage signal is generated on the first resistor R1 connected to the drain of the second MOS transistor M1, and input to the high voltage power domain. Processing is performed in circuit 130 to effect the transfer of low voltage signals to high voltage signals.
  • the first diode D3 provides a low-resistance path of the negative electrode VS of the high-voltage power source 110 to the drain of the second MOS transistor M1.
  • the discharge path of the negative electrode VS of the high-voltage power source 110 to the low-voltage power source region includes: VS ⁇ VB ⁇ DMOS/high-voltage ESD device ⁇ VSS ⁇ VCC bleed path, including VS ⁇ DMOS ⁇ VSS ⁇ VCC auxiliary bleed path, which helps ESD bleed and shunt, which helps ESD vent
  • the shunt is discharged while the first diode D3 can clamp the potential of the detection point A1 to prevent the potential of the detection point A1 from being lower than the voltage of the negative electrode VS of the high voltage power source 110.
  • the Zener Z1 is connected in parallel with the first resistor R1 to clamp the voltage across the resistor to avoid damage to the chip beyond the power supply range of the high voltage power domain.
  • the current limiting resistor R3 can limit the current of the DMOS path of the high voltage device during the electrostatic discharge, so that the high voltage device DMOS second MOS tube M1 is not easily damaged, and at the same time, a certain voltage can be superimposed on the drain of the second MOS transistor M1, when the high voltage power supply
  • the anode VB voltage of 110 reaches the trigger voltage of the high voltage ESD device 153
  • the high voltage ESD device 153 is triggered, and most of the static electricity can be discharged through the high voltage ESD device 153, thereby protecting the drive circuit 100 of the transistor.
  • Another level shifting circuit is similar and will not be described here.
  • the high voltage ESD device 153 is similar to a reverse biased high voltage diode between the positive VB of the high voltage power supply 110 and the negative VSS of the low voltage power supply 120, and has a high withstand voltage and a strong overcurrent capability. When there is static electricity between the two power domains, it is necessary to trigger the high voltage ESD device 153 as much as possible, which facilitates the discharge of static electricity and protects the drive circuit 100 of the transistor.
  • the second MOS transistor M1 of the high voltage device DMOS when electrostatic discharge occurs, the second MOS transistor M1 of the high voltage device DMOS is preferentially turned on due to the coupling effect, current flows through the first resistor R1, and the current limiting resistor R3 generates a voltage.
  • the drain voltage of the second MOS transistor M1 the sum of the voltages of the first resistor R1 and the current limiting resistor R3 reaches the trigger voltage of the high voltage ESD device 153, the high voltage ESD device 153 triggers to bleed a portion of the energy, thus passing through the second MOS transistor.
  • the venting path of the M1 and high voltage ESD device 153 acts simultaneously, the second MOS transistor M1 bleeds a small portion of the energy, and the high voltage ESD device 153 bleeds a portion of the energy, that is, the high voltage device that passes through the level shifting circuit 160 when the electrostatic bleed is discharged.
  • DMOS bleed is a secondary electrostatic discharge path, which is discharged into the main electrostatic discharge path through the high-voltage ESD device 153.
  • the two bleed modes work together to greatly increase the high voltage and, in turn, greatly improve the drive circuit of the transistor. 100 static discharge capacity.
  • Another level shifting circuit is similar and will not be described here.
  • a current limiting module is added to the level shifting circuit to increase the internal resistance of the path for electrostatic discharge through the level shifting circuit, thereby limiting the path during static discharge.
  • the current prevents the level shift circuit from being damaged.
  • the electrostatic discharge device such as a high voltage ESD device
  • the electrostatic discharge device is turned on, and the partial energy is amplified, thereby protecting the driving circuit of the transistor.
  • the bleeder module is added to provide a low-resistance path from the negative pole of the high-voltage power supply to the drain of the switch tube.
  • an electrostatic discharge path is added to shunt the electrostatic discharge, and the bleeder module can clamp the level detection circuit.
  • the potential prevents the potential from being lower than the negative voltage of the high voltage power supply.
  • the driving circuit of the transistor has strong antistatic capability, thereby improving the stability and reliability of the driving circuit of the transistor.
  • the driving circuit 100 of the transistor further includes: a protection circuit 165 (ie, a device and an ESD device), and the protection circuit 170 is disposed at the second of the switching transistor 164.
  • the terminal is between the negative electrode VSS of the low voltage power supply 120. That is, the source of the high voltage device DMOS is connected to the negative VSS of the low voltage power supply 120 through the device, and the ESD device and the device are connected in parallel.
  • the source of the second MOS transistor M1 is further connected to the negative electrode VSS connected to the low voltage power supply 120 through the connection device and the ESD device connected in parallel with the device.
  • the path of the high voltage device DMOS is preferentially turned on due to the coupling effect. Since the source of the second MOS transistor M1 of the high voltage device DMOS is connected to the device, there is a source at the source. The higher the voltage, when the voltage exceeds the trigger voltage of the ESD device in parallel with the device, the ESD device is turned on, and the ESD energy is quickly discharged to the negative VSS of the low-voltage power supply 120, preventing the high-voltage device DMOS and the device from being damaged, and increasing at the same time. High voltage device DMOS path through ESD current capability.
  • the protection circuit includes a second resistor and a first static discharge device such as a second resistor R5 and an ESD device, or a second resistor R6 and an ESD device.
  • a first static discharge device such as a second resistor R5 and an ESD device, or a second resistor R6 and an ESD device.
  • the second resistor R5 is connected in parallel with the ESD device, one end of the second resistor R5 is connected to the second end of the switch tube 164, and the other end of the second resistor R5 is connected to the cathode VSS of the low voltage power source 120.
  • the first static discharge device is connected in parallel with the second resistor R5.
  • the gate signal of the high voltage device DMOS is generated by the low voltage power domain circuit 140.
  • the source is connected to the negative VSS of the low voltage power supply 120 through the connection resistor R5 and the ESD device connected in parallel with the resistor.
  • the second resistor R5 is connected in parallel with the ESD device.
  • the ESD device When the source voltage of the second MOS transistor M1 exceeds the trigger voltage of the ESD device in parallel with the second resistor R5, the ESD device is turned on, and the ESD energy is quickly discharged to the negative VSS of the low voltage power supply 120 to prevent damage of the high voltage device DMOS and the ESD device. At the same time, it also increases the ESD current capability of the high-voltage device DMOS path.
  • the second resistor R5 can limit the ESD path current, while limiting the high-voltage device DMOS switching current and reducing the switching power consumption during normal operation.
  • the protection circuit includes a high voltage device DMOS (such as a first MOS transistor M3 or a first MOS transistor M4) and a second electrostatic discharge device (such as an ESD device).
  • DMOS such as a first MOS transistor M3 or a first MOS transistor M4
  • ESD device such as an ESD device
  • One end of the second static electricity discharge device is connected to the drain of the first MOS transistor M3, and the other end of the second static electricity discharge device is connected to the source of the first MOS transistor M3.
  • the gate of the first MOS transistor of the high voltage device DMOS is connected to a constant VG, and the first MOS transistor of the high voltage device DMOS is controlled by controlling the first MOS transistor M3 to change the source voltage. Switch.
  • the first MOS transistor M3 is connected in parallel with the ESD device.
  • the source of the transistor M1 is connected to the ESD device, and the source has a higher voltage.
  • the source voltage of the first MOS transistor M1 exceeds the trigger voltage of the ESD device connected in parallel to the first MOS transistor M1, the ESD device is turned on, and the ESD energy is very high. It is quickly vented to the negative VSS of the low-voltage power supply 120 to prevent DMOS damage and also increase the DMOS path's ability to pass ESD current.
  • level shifting circuit 160 includes one or more level shifting circuits in parallel.
  • a driving circuit including transistors of the N level shifting circuits 160 is shown in FIG. Where N is a positive integer.
  • the driving circuit of the transistor according to the embodiment of the present application has the advantage of strong antistatic capability, thereby improving the stability and reliability of the driving circuit of the transistor.
  • the description with reference to the terms “one embodiment”, “some embodiments”, “example”, “specific example”, or “some examples” and the like means a specific feature described in connection with the embodiment or example.
  • a structure, material or feature is included in at least one embodiment or example of the application.
  • the terms “first” and “second” are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated.
  • features defining “first” or “second” may include at least one of the features, either explicitly or implicitly.
  • the meaning of "a plurality" is at least two, such as two, three, etc., unless specifically defined otherwise.

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Abstract

一种晶体管的驱动电路（100），包括：高压电源（110）和低压电源（120）、高压电源域电路（130）和低压电源域电路（140）、静电泄放装置（150）以及电平转移电路（160），其中，高压电源域电路与高压电源相连，低压电源域电路与低压电源相连，静电泄放装置分别设置在高压电源的两极（VB、VS）之间、低压电源的两极（VCC、VSS）之间和高压电源的正极（VB）与低压电源的负极（VSS）之间，电平转移电路包括电平检测电路（161）、限流模块（162）、泄放模块（163）和开关管（164），电平检测电路与高压电源的正极相连且分别与限流模块、泄放模块以及高压电源域电路相连，限流模块还与开关管的第一端相连，泄放模块还与高压电源的负极相连，开关管的控制端与低压电源域电路相连且开关管的第二端与低压电源的负极相连，限流模块用于在驱动电路进行静电泄放时限制泄放电流，泄放模块用于在高压电源的负极和开关管的第一端之间形成辅助泄放通路以辅助驱动电路的静电泄放。该晶体管的驱动电路抗静电能力强，进而提升了晶体管的驱动电路的稳定性和可靠性。

Description

晶体管的驱动电路
相关申请的交叉引用
本申请基于申请号为201610100870.5、申请日为2016年2月24日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本申请涉及驱动电路技术领域，特别涉及一种晶体管的驱动电路。
背景技术
高压晶体管驱动芯片，主要用于驱动MOSFET(Metal-Oxide-Semiconductor Field-Effect Transistor，金属氧化物半导体场效应晶体管)，IGBT(Insulated Gate Bipolar Transistor，绝缘栅双极型晶体管)等功率器件，普遍应用于工业及家电变频等领域。由于高压晶体管驱动芯片有高低压两个电源域，电源域间的静电需要通过高压器件来泄放，但器件的耐压提升，其自身的ESD(Electrostatic Discharge，静电放电)能力会下降，所以高低压电源域之间的ESD能力都不强。
如图7所示，芯片包含两个电源域：低压电源域(VCC为低压电源，VSS为低压地)，高压电源域(VB为高压电源，VS为高压地)，两个电源域之间通过电平转移电路，即level-shifter电路(电平移位，图中内部有两个结构一样、独立的level-shifter1，level-shifter2)及高压ESD器件连接在一起。独立电源域内部，电源及地VB-VS，VCC-VSS之间有独立的ESD器件(常用的有二极管，三极管，CMOS管等)，用于泄放ESD。
Level-shifter主要包含：DMOS(图7中的M1，M2)，DMOS源极器件(图7中源极接地)，DMOS漏极检测电路(图7中由检测电阻R1，R2和稳压管Z1，Z2构成)。通过控制DMOS-M1，M2的开通，关断，改变检测电阻R1，R2上的电压，从而实现低压信号到高压信号的转换。
当高压电源域和低压电源域之间有静电时，通过level-shifter电路去泄放，靠电路器件自身的ESD能力去泄放静电能量，但DMOS自身的泄放ESD能力较弱，很容易损坏，造成芯片整体ESD能力不强。
发明内容
本申请旨在至少在一定程度上解决相关技术中的技术问题之一。
为此，本申请的目的在于提出一种晶体管的驱动电路。该晶体管的驱动电路具有抗静电能力强的优点，进而提升了晶体管的驱动电路的稳定性和可靠性。
为了实现上述目的，本申请的实施例公开了一种晶体管的驱动电路，包括：高压电源和低压电源；高压电源域电路和低压电源域电路，所述高压电源域电路与所述高压电源相连，所述低压电源域电路与所述低压电源相连；静电泄放装置，所述静电泄放装置分别设置在所述高压电源的两极间、所述低压电源的两极间以及所述高压电源的正极与所述低压电源的负极之间；电平转移电路，所述电平转移电路包括电平检测电路、限流模块、泄放模块和开关管，所述电平检测电路与所述高压电源的正极相连且分别与所述限流模块、所述泄放模块以及所述高压电源域电路相连，所述限流模块还与所述开关管的第一端相连，所述泄放模块还与所述高压电源的负极相连，所述开关管的控制端与所述低压电源域电路相连且所述开关管的第二端与所述低压电源的负极相连，所述限流模块用于在所述驱动电路进行静电泄放时限制泄放电流，所述泄放模块用于在所述高压电源的负极和所述开关管的第一端之间形成辅助泄放通路以辅助所述驱动电路的静电泄放。
根据本申请实施例的晶体管的驱动电路，在电平转移电路中加入限流模块，增加了通过电平转移电路进行静电泄放的通路的内阻，从而在静电泄放时，限制该通路上的电流，阻止电平转移电路损坏，当电压达到静电泄放装置(如高压ESD器件)的触发电压时，静电泄放装置开启，泄放大部分能量，进而保护晶体管的驱动电路。另外，在电平转移电路中增加泄放模块，提供高压电源的负极到开关管的漏极一个低阻的通路，因此，多了一个静电泄放通路以便对静电泄放进行分流，同时泄放模块可以钳制电平检测电路的电位，防止电位低于高压电源的负极电压。该晶体管的驱动电路抗静电能力强，进而提升了晶体管的驱动电路的稳定性和可靠性。
附图说明
图1是根据本申请一个实施例的晶体管的驱动电路的结构图；
图2是根据本申请第一个实施例的晶体管的驱动电路的电路图；
图3是根据本申请第二个实施例的晶体管的驱动电路的电路图；
图4是根据本申请第三个实施例的晶体管的驱动电路的电路图；
图5是根据本申请第四个实施例的晶体管的驱动电路的电路图；
图6是根据本申请第五个实施例的晶体管的驱动电路的电路图；以及
图7是相关技术中一种晶体管的驱动电路的电路图。
具体实施方式
下面详细描述本申请的实施例，所述实施例的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施例是示例性的，旨在用于解释本申请，而不能理解为对本申请的限制。
以下结合附图描述根据本申请实施例的晶体管的驱动电路。
图1是根据本申请一个实施例的晶体管的驱动电路的结构框图。图2是根据本申请一个实施例的晶体管的驱动电路的电路图。如图1所示，并结合图2，根据本申请一个实施例的晶体管的驱动电路100，包括：高压电源110、低压电源120、高压电源域电路130、低压电源域电路140、静电泄放装置150和电平转移电路160。
可以理解的是，高压电源与低压电源中的高压和低压，用于表示两个不同电压的电源，同理，高压电源域电路与低压电源域电路中的高压和低压，用于表示两个不同电压的电源域电路。比如，高压电源的电压可为20V，低压电源的电压可为10V，高压电源域电路的电压可为20V，低压电源域电路的电压可为10V；或者，高压电源的电压可为10V，低压电源的电压可为7V，高压电源域电路的电压可为10V，低压电源域电路的电压可为7V。其中，高压电源域电路130与高压电源110相连，低压电源域电路140与低压电源120相连。静电泄放装置150分别设置在高压电源110的两极间(即：正极VB和负极VS之间)、低压电源120的两极间(即：正极VCC和负极VSS之间)以及高压电源110的正极VB与低压电源120的负极VSS之间。电平转移电路160包括电平检测电路161、限流模块162、泄放模块163和开关管164，在具体实施例中，电平检测电路161的第一端与高压电源110的正极VB相连且第二端分别与限流模块162的第一端、泄放模块163的第一端以及高压电源域电路130相连，限流模块162的第二端与开关管164的第一端相连，泄放模块163的第二端与高压电源130的负极VS相连，开关管164的控制端与低压电源域电路140相连且第二端与低压电源120的负极VSS相连，限流模块162用于在驱动电路进行静电泄放时限制泄放电流，泄放模块163用于在高压电源110的负极VS和开关管164的第一端之间形成辅助泄放通路以辅助驱动电路的静电泄放。
作为一个具体的示例，如图1和2所示，电平检测电路161包括稳压管Z1和第一电阻R1，稳压管Z1的阴极与高压电源110的正极VB相连，稳压管Z1的阳极与高压电源域电路130相连(即：稳压管Z1的阳极通过检测点A1与高压电源域电路130相连)，第一电阻R1与稳压管Z1并联。限流模块162包括限流电阻R3，限流电阻R3的一端与稳压管Z1的阳极相连，限流电阻R3的另一端与开关管164的第一端相连。泄放模块163包括第一二极管D3，第一二极管D3的阴极与稳压管Z1的阳极相连，第一二极管D3的阳极与高 压电源110的负极VS相连。
进一步地，结合图2所示，开关管164为第二MOS管M1，进而，开关管164的控制端为第二MOS管M1的栅极G，第一端为第二MOS管M1的漏极D，第二端为第二MOS管M1的源极S。
再次结合图2，静电泄放装置150包括：第三静电泄放器件151、第四静电泄放器件152和第五静电泄放器件153。其中，第三静电泄放器件151和第四静电泄放器件152为ESD器件(Electrostatic Discharge)。第五静电泄放器件153例如为图2中所示的高压ESD器件(High Voltage Isolation Junction)。第三静电泄放器件151为设置在高压电源110的两极间，即设置在高压电源110的正极VB和负极VS之间的ESD器件。第四静电泄放器件152为设置在低压电源110的两极间，即设置在低压电源120的正极VCC和负极VSS之间的ESD器件。第五静电泄放器件153为设置在高压电源110的正极VB与低压电源120的负极VSS之间，即设置在高压电源110的正极VB和低压电源120的负极VSS之间的高压ESD器件153。
另外，结合图1，图2中示出了包括两个并联并且结构相同的电平转移电路160的晶体管的驱动电路100。另一个电平转移电路160由稳压管Z2、电阻R2、电阻R4、二极管D4和MOS管M2组成。此处不做赘述。
在描述了本申请实施例的晶体管的驱动电路100的结构之后，以下对本申请实施例的晶体管的驱动电路100的工作原理进行说明。
具体而言，结合图1，如图2所示，高压电源域电路130和低压电源域电路140通过电平转移电路160连接，同时，高压电源域电路130和低压电源域电路140也通过高压ESD器件连接。电平转移电路160主要是进行电平转换，将低压区域的信号转换到高压区域，从而实现信号的传递。图2中有两个并联的电平转移电路160，其中一个电平转移电路160的高压器件DMOS(Double-Diffused MOSFET，双重扩散金属氧化物半导体场效应管)，即第二MOS管M1的栅极信号由低压电源域电路140产生，第二MOS管M1的源极连接低压电源120的负极VSS，漏极连接电阻R3的另一端，电阻R3的一端连接稳压管Z1的阳极，稳压管Z1的阴极接高压电源110的正极VB，第一电阻R1与稳压管Z1并联，稳压管Z1的阳极为检测点A1，检测点A1的电信号作为高压电源域电路130的输入信号，第一二极管D3的阴极接检测点A1，阳极接高压电源110的负极VS。另一个电平转移电路160的高压器件DMOS，即MOS管M2的栅极信号由低压电源域电路140产生，源极连接低压电源120的负极VSS，漏极连接电阻R4另一端，电阻R4的一端连接稳压管Z2的阳极，稳压管Z2的阴极接高压电源110的正极VB，电阻R2与稳压管Z2并联，稳压管Z2的阳极为检测点A2，检测点A2的电信号作为高压电源域电路130的输入信号，二极管D4阴 极接检测点A2，阳极接高压电源110的负极VS。
对于其中一个电平转移电路160，通过控制高压器件DMOS的第二MOS管M1，在与第二MOS管M1的漏极连接的第一电阻R1上会产生变化的电压信号，输入到高压电源域电路130中进行处理，从而实现了低压信号到高压信号的转移。另外，第一二极管D3提供高压电源110的负极VS到第二MOS管M1的漏极的一个低阻的通路，因此，高压电源110的负极VS到低压电源域的泄放通路不但包括：VS→VB→DMOS/高压ESD器件→VSS→VCC的泄放通路，还包括VS→DMOS→VSS→VCC的辅助泄放通路，这样有助于ESD的泄放分流，这样有助于ESD的泄放分流，同时第一二极管D3可以钳制检测点A1的电位，防止检测点A1电位低于高压电源110的负极VS的电压。稳压管Z1与第一电阻R1并联，可以钳位电阻两端的电压，以免超出高压电源域的供电范围而造成芯片的损坏。限流电阻R3在静电泄放时可以限制高压器件DMOS通路的电流，让高压器件DMOS第二MOS管M1不易损坏，同时又可以在第二MOS管M1的漏极叠加一定的电压，当高压电源110的阳极VB电压达到高压ESD器件153触发电压时，高压ESD器件153被触发，大部分的静电可以通过高压ESD器件153进行泄放，从而保护晶体管的驱动电路100。另一个电平转移电路类似，此处不做赘述。
其中，高压ESD器件153在高压电源110的正极VB与低压电源120的负极VSS之间，类似于一个反偏的高压二极管，具有较高的耐压，过电流能力比较强。当两个电源域之间有静电时，需要尽可能地将高压ESD器件153触发，这样有利于静电的泄放，保护晶体管的驱动电路100。
对于其中一个电平转移电路160，当静电泄放发生时，高压器件DMOS的第二MOS管M1由于耦合效应，优先开启，电流流过第一电阻R1，限流电阻R3，产生电压，当第二MOS管M1的漏极电压，第一电阻R1和限流电阻R3上的电压之和达到高压ESD器件153的触发电压时，高压ESD器件153触发，泄放大部分能量，这样通过第二MOS管M1和高压ESD器件153的泄放通路就同时发生作用，第二MOS管M1泄放小部分能量，高压ESD器件153泄放大部分能量，即静电泄放时，通过电平转移电路160的高压器件DMOS泄放为次要的静电泄放路径，通过高压ESD器件153泄放为主要的静电泄放路径，两种泄放方式共同作用，极大地提高了高压，进而，极大地提高晶体管的驱动电路100的静电泄放能力。另一个电平转移电路类似，此处不做赘述。
根据本申请实施例的晶体管的驱动电路，在电平转移电路中加入限流模块，增加了通过电平转移电路进行静电泄放的通路的内阻，从而在静电泄放时，限制该通路上的电流，阻止电平转移电路损坏，当电压达到静电泄放装置(如高压ESD器件)的触发电压时，静电泄放装置开启，泄放大部分能量，进而保护晶体管的驱动电路。另外，在电平转移电路 中增加泄放模块，提供高压电源的负极到开关管的漏极一个低阻的通路，因此，多了一个静电泄放通路以便对静电泄放进行分流，同时泄放模块可以钳制电平检测电路的电位，防止电位低于高压电源的负极电压。该晶体管的驱动电路抗静电能力强，进而提升了晶体管的驱动电路的稳定性和可靠性。
在本申请的一个实施例中，结合图1，如图3所示，晶体管的驱动电路100还包括：保护电路165(即：器件和ESD器件)，保护电路170设置在开关管164的第二端与低压电源120的负极VSS之间。即：高压器件DMOS的源极通过器件连接到低压电源120的负极VSS，并且ESD器件和器件并联。如：第二MOS管M1的源极通过连接器件和与器件并联的ESD器件进而连接到连接低压电源120的负极VSS。当静电泄放由高压电源域至低压电源域进行泄放时，高压器件DMOS的通路因耦合效应优先开启，由于高压器件DMOS的第二MOS管M1的源极连接有器件，在源极会有较高的电压，当电压超过与器件并联的ESD器件的触发电压时，ESD器件开启，ESD能量很快地泄放到低压电源120的负极VSS，防止高压器件DMOS及器件损坏，同时增大了高压器件DMOS通路过ESD电流能力。
作为一个具体的示例，如图4所示，保护电路包括：第二电阻和第一静电泄放器件，如第二电阻R5和与ESD器件，或者第二电阻R6和ESD器件。以第二电阻R5和ESD器件为例，第二电阻R5与ESD器件并联，第二电阻R5的一端与开关管164的第二端相连，第二电阻R5的另一端与低压电源120的负极VSS相连。第一静电泄放器件与第二电阻R5并联。高压器件DMOS的栅极信号由低压电源域电路140产生，源极通过连接电阻R5和与电阻并联的ESD器件进而连接到低压电源120的负极VSS，第二电阻R5与ESD器件并联，当静电泄放由高压电源域至低压电源域泄放时，高压器件DMOS通路因耦合效应优先开启，由于高压器件DMOS的第二MOS管M1的源极连接有ESD器件，在源极会有较高的电压，第二MOS管M1源极电压超过与第二电阻R5并联的ESD器件触发电压时，ESD器件开启，ESD能量很快地泄放到低压电源120的负极VSS，防止高压器件DMOS及ESD器件损坏，同时也增大了高压器件DMOS通路过ESD电流能力。第二电阻R5可以限制ESD通路电流，同时正常工作时，限制高压器件DMOS开关电流，降低开关功耗。
在本申请的另一个示例中，如图5所示，保护电路包括：高压器件DMOS(如第一MOS管M3，或者第一MOS管M4)和第二静电泄放器件(如ESD器件)。以第一MOS管M3和ESD器件为例，第一MOS管M3的栅极与低压电源域电路140相连，第一MOS管M3的漏极与开关管164的第二端相连，第一MOS管M3的源极与低压电源120的负极VSS相连。第二静电泄放器件的一端与第一MOS管M3的漏极相连，第二静电泄放器件的另一端与第一MOS管M3的源极相连。高压器件DMOS的第一MOS管的栅极接恒定的VG，通过控制第一MOS管M3，改变源极电压从而控制高压器件DMOS的第一MOS管 的开关。第一MOS管M3与ESD器件并联，当静电泄放由高压电源域到低压电源域泄放时，高压器件DMOS的第一MOS管的通路因耦合效应优先开启，由于高压器件DMOS的第一MOS管M1的源极连接有ESD器件，在源极会有较高的电压，第一MOS管M1源极电压超过并联在第一MOS管M1的ESD器件触发电压时，ESD器件开启，ESD能量很快地泄放到低压电源120的负极VSS，防止DMOS损坏，同时也增大了DMOS通路过ESD电流能力。
如图6所示，电平转移电路160包括一个或多个并联的电平转移电路。如图6中示出了包括N个电平转移电路160的晶体管的驱动电路。其中，N为正整数。
根据本申请实施例的晶体管的驱动电路，具有抗静电能力强的优点，进而提升了晶体管的驱动电路的稳定性和可靠性。
在本说明书的描述中，参考术语“一个实施例”、“一些实施例”、“示例”、“具体示例”、或“一些示例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特点包含于本申请的至少一个实施例或示例中。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括至少一个该特征。在本申请的描述中，“多个”的含义是至少两个，例如两个，三个等，除非另有明确具体的限定。
尽管上面已经示出和描述了本申请的实施例，可以理解的是，上述实施例是示例性的，不能理解为对本申请的限制，本领域的普通技术人员在本申请的范围内可以对上述实施例进行变化、修改、替换和变型。

Claims (9)

  1. 一种晶体管的驱动电路，其特征在于，包括：
    高压电源和低压电源；
    高压电源域电路和低压电源域电路，所述高压电源域电路与所述高压电源相连，所述低压电源域电路与所述低压电源相连；
    静电泄放装置，所述静电泄放装置分别设置在所述高压电源的两极间、所述低压电源的两极间以及所述高压电源的正极与所述低压电源的负极之间；
    电平转移电路，所述电平转移电路包括电平检测电路、限流模块、泄放模块和开关管，所述电平检测电路与所述高压电源的正极相连且分别与所述限流模块、所述泄放模块以及所述高压电源域电路相连，所述限流模块还与所述开关管的第一端相连，所述泄放模块还与所述高压电源的负极相连，所述开关管的控制端与所述低压电源域电路相连且所述开关管的第二端与所述低压电源的负极相连，所述限流模块用于在所述驱动电路进行静电泄放时限制泄放电流，所述泄放模块用于在所述高压电源的负极和所述开关管的第一端之间形成辅助泄放通路以辅助所述驱动电路的静电泄放。
  2. 根据权利要求1所述的晶体管的驱动电路，其特征在于，其中，
    所述电平检测电路包括稳压管和第一电阻，所述稳压管的阴极与所述高压电源的正极相连，所述稳压管的阳极与所述高压电源域电路相连，所述第一电阻与所述稳压管并联；
    所述限流模块包括限流电阻，所述限流电阻的一端与所述稳压管的阳极相连，所述限流电阻的另一端与所述开关管的第一端相连；
    所述泄放模块包括第一二极管，所述第一二极管的阴极与所述稳压管的阳极相连，所述第一二极管的阳极与所述高压电源的负极相连。
  3. 根据权利要求1或2所述的晶体管的驱动电路，其特征在于，还包括：保护电路，所述保护电路设置在所述开关管的第二端与所述低压电源的负极之间。
  4. 根据权利要求3所述的晶体管的驱动电路，其特征在于，所述保护电路包括：
    第二电阻，所述第二电阻的一端与所述开关管的第二端相连，所述第二电阻的另一端与所述低压电源的负极相连；
    第一静电泄放器件，所述第一静电泄放器件与所述第二电阻并联。
  5. 根据权利要求3所述的晶体管的驱动电路，其特征在于，所述保护电路包括：
    第一MOS管，所述第一MOS管的栅极与所述低压电源域电路相连，所述第一MOS管的漏极与所述开关管的第二端相连，所述第一MOS管的源极与所述低压电源的负极相连；
    第二静电泄放器件，所述第二静电泄放器件的一端与所述第一MOS管的漏极相连，所述第二静电泄放器件的另一端与所述第一MOS管的源极相连。
  6. 根据权利要求1至5中任一项所述的晶体管的驱动电路，其特征在于，所述电平转移电路包括一个或多个并联的电平转移电路。
  7. 根据权利要求2所述的晶体管的驱动电路，其特征在于，所述开关管为第二MOS管，所述控制端为所述第二MOS管的栅极，所述第一端为所述第二MOS管的漏极，所述第二端为所述第二MOS管的源极。
  8. 根据权利要求1至7中任一项所述的晶体管的驱动电路，其特征在于，所述静电泄放装置包括：
    第三静电泄放器件，所述第三静电泄放器件设置在所述高压电源的两极间；
    第四静电泄放器件，所述第四静电泄放器件设置在所述低压电源的两极间；
    第五静电泄放器件，所述第五静电泄放器件设置在所述高压电源的正极与所述低压电源的负极之间。
  9. 根据权利要求8所述的晶体管的驱动电路，其特征在于，所述第五静电泄放器件为高压ESD器件。
PCT/CN2017/074625 2016-02-24 2017-02-23 晶体管的驱动电路 WO2017143998A1 (zh)

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