WO2017114113A1 - 一种集成肖特基二极管的SiC沟槽型MOSFET器件及其制造方法 - Google Patents

一种集成肖特基二极管的SiC沟槽型MOSFET器件及其制造方法 Download PDF

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WO2017114113A1
WO2017114113A1 PCT/CN2016/108849 CN2016108849W WO2017114113A1 WO 2017114113 A1 WO2017114113 A1 WO 2017114113A1 CN 2016108849 W CN2016108849 W CN 2016108849W WO 2017114113 A1 WO2017114113 A1 WO 2017114113A1
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drift layer
well
gate
layer
source
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French (fr)
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钮应喜
杨霏
温家良
潘艳
郑柳
李永平
王嘉铭
李玲
夏经华
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Global Energy Interconnection Research Institute Co Ltd
State Grid Shanghai Electric Power Co Ltd
State Grid Corp of China SGCC
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Global Energy Interconnection Research Institute Co Ltd
State Grid Shanghai Electric Power Co Ltd
State Grid Corp of China SGCC
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/101—Integrated devices comprising main components and built-in components, e.g. IGBT having built-in freewheel diode
    • H10D84/141—VDMOS having built-in components
    • H10D84/146—VDMOS having built-in components the built-in components being Schottky barrier diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/01—Manufacture or treatment
    • H10D12/031—Manufacture or treatment of IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H10D30/0297—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using recessing of the gate electrodes, e.g. to form trench gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H10D62/8325—Silicon carbide

Definitions

  • the present invention relates to semiconductor technology, and in particular to a SiC trench MOSFET device incorporating a Schottky diode and a method of fabricating the same.
  • Silicon carbide is a third-generation semiconductor material developed after the first-generation semiconductor materials silicon, germanium and second-generation semiconductor materials such as gallium arsenide and indium phosphide.
  • the wide band gap of silicon carbide materials is silicon and arsenic. Two to three times that of gallium enables semiconductor devices to operate at relatively high temperatures (above 500°C) and has the ability to emit blue light; its high breakdown field is an order of magnitude higher than silicon and gallium arsenide, which determines the semiconductor.
  • the high voltage and high power performance of the device; its high saturation electron drift speed and low dielectric constant determine the high frequency and high speed performance of the device;
  • the thermal conductivity of silicon carbide is 3.3 times that of silicon and 10 times that of gallium arsenide, meaning Its thermal conductivity is good, which can greatly improve the integration of the circuit and reduce the cooling and cooling system, thus reducing the volume of the whole machine. Therefore, with the continuous improvement of silicon carbide materials and device processes, some Si fields have been replaced by silicon carbide. Silicon carbide has wide bandgap, high critical breakdown field strength, high thermal conductivity, high electron saturation and escape rate, etc. It is especially suitable for high-power, high-voltage power electronic devices, and thus has become a research hotspot in the field of power electronics.
  • the theoretical maximum operating voltage range of SiC-based power devices is greater than 10kV, which is higher than the operating voltage of silicon-based insulated gate bipolar transistor (IGBT) devices; as a unipolar device, its switching speed is fast.
  • IGBT insulated gate bipolar transistor
  • the required epitaxial layer is reduced by tens of times the critical breakdown field of silicon, and is therefore considered an ideal alternative to silicon-based IGBT devices.
  • IGBTs metal oxide semiconductor field effect transistors
  • MOSFETs metal oxide semiconductor field effect transistors
  • FIG. 1 Schematic diagram of the power IGBT and diode anti-parallel.
  • Silicon-based IGBTs generally package the anti-parallel diodes into power modules at the same time, while silicon-based MOSFETs naturally form anti-parallel diodes due to the P-well and drift regions, so there is no need to add additional diodes for parallel packaging.
  • SiC-based MOSFETs also have naturally formed anti-parallel diodes, due to the high band gap of SiC, the turn-on voltage of PN junction diodes is high, reaching about 3V.
  • anti-parallel diodes inside SiC MOSFETs it will greatly increase.
  • SiC MOSFET devices it is generally necessary to have an anti-parallel SiC Schottky diode externally, but this will increase the fabrication cost of the device.
  • N-drift layer comprising P wells having N+ source regions isolated from each other;
  • the U-channel surface has an oxide layer with a gate therein;
  • the Schottky diode is a freewheeling diode.
  • the N+ substrate has a resistivity of 0.015 to 0.02 ohm cm.
  • the N-drift layer has a thickness of 10 to 500 ⁇ m and a doping concentration of 1 ⁇ 10 14 to 5 ⁇ 10 15 cm ⁇ 3 .
  • the distance between the P wells is 1 to 3 ⁇ m, and the well depth is 1 to 3 ⁇ m.
  • the width and depth of the N+ source region are both smaller than the P well.
  • the U-channel has a depth of 4 to 10 ⁇ m.
  • the oxide layer has a thickness of 50 to 150 ⁇ m; and the isolation layer has a thickness of 15 to 50 ⁇ m.
  • the gate is an n-type or p-type degenerately doped polysilicon.
  • a method of fabricating a SiC trench MOSFET device incorporating a Schottky diode comprising the steps of:
  • the embodiment of the invention has the following beneficial effects:
  • the source of the silicon carbide trench MOSFET of the embodiment of the present invention forms a Schottky contact with the epitaxial layer between the P wells, and the formed Schottky diode functions as a freewheeling diode when the device is operated, thereby improving Efficiency and reliability of circuit operation;
  • the integrated device of the embodiment of the present invention avoids the problem that the circuit conversion efficiency is low due to the high turn-on voltage of the SiC PN junction when the PN junction in the SiC MOSFET is used as a freewheeling diode;
  • the SiC Schottky diode of the embodiment of the invention is a unipolar device, which avoids the problem that the BPD dislocation is increased and the device reliability is reduced when the PN junction is operated;
  • 1 is a schematic circuit diagram of an IGBT and a diode in anti-parallel
  • FIG. 2 is a cross-sectional view showing an N-drift layer formed on an N+ substrate
  • FIG. 3 is a cross-sectional view showing formation of a P well by ion implantation of an N-drift layer
  • FIG. 4 is a cross-sectional view showing ion implantation in a P well to form an N+ source region
  • FIG. 5 is a cross-sectional view showing a U-shaped channel formed by etching outside the P well;
  • Figure 6 is a cross-sectional view showing the formation of an oxide film on the bottom and side walls of the trench;
  • Figure 7 is a cross-sectional view of the trench filled with polysilicon poly
  • Figure 8 is a cross-sectional view showing a deposition isolation layer on the N-drift layer
  • Figure 9 is a cross-sectional view of the lithographic partial isolation layer
  • Figure 10 is a cross-sectional view showing a source of a metal deposited on the front side
  • Figure 11 is a cross-sectional view showing the drain electrode deposited on the back side.
  • an N-drift layer is epitaxially grown on the N+ substrate. As shown in FIG. 2, the drift layer has a thickness of 12 ⁇ m and a doping concentration of 2 ⁇ 10 15 cm -3 .
  • the resistivity of the N+ substrate is 0.015-0.02 ohm cm.
  • the mask on the N-drift layer is used to etch a pattern to be doped, and the P-well ion implantation process is performed. As shown in FIG. 3, the distance between each P well is 1 ⁇ m, and the P well depth is 1 ⁇ m. This portion is used to form a Schottky contact with the metal.
  • the N+ source region pattern is photolithographically patterned using a mask to perform an ion implantation process in the N+ source region.
  • the depth of the N+ source region is less than that of the P well, which is 0.5 ⁇ m, and the width is also smaller than the P well, as shown in FIG.
  • a gate trench (U-channel) pattern is photolithographically patterned using a mask, and a trench is formed by reactive ion etching (RIE) or inductively coupled plasma etching (ICP), as shown in FIG. 5 ⁇ m.
  • RIE reactive ion etching
  • ICP inductively coupled plasma etching
  • an oxide film was formed on the bottom and sidewalls of the trench, as shown in Fig. 6, to a thickness of 100 nm.
  • a layer of Si 3 N 4 was grown as a spacer by plasma enhanced chemical vapor deposition (PECVD), and as shown in FIG. 8, the thickness of the spacer was 20 nm.
  • PECVD plasma enhanced chemical vapor deposition
  • a metal is deposited on the front side to form a Schottky contact as a source electrode as shown in FIG.
  • a metal is deposited on the back side to form an ohmic contact as a drain electrode as shown in FIG.
  • an N-drift layer is epitaxially grown on the N+ substrate. As shown in FIG. 2, the drift layer has a thickness of 15 ⁇ m and a doping concentration of 1 ⁇ 10 15 cm -3 .
  • the resistivity of the N+ substrate is 0.015-0.02 ohm cm.
  • the mask on the N-drift layer is used to lithography the pattern to be doped, and the ion implantation process of the P well is performed.
  • the distance between each P well is 1.5 ⁇ m, and the depth of the P well is 1 ⁇ m. . This portion is used to form a Schottky contact with the metal.
  • the N+ source region pattern is photolithographically patterned using a mask to perform an ion implantation process in the N+ source region.
  • the depth of the N+ source region is less than that of the P well, which is 0.5 ⁇ m, and the width is also smaller than the P well, as shown in FIG.
  • a gate trench (U-channel) pattern is photolithographically patterned using a mask, and a trench is formed by reactive ion etching (RIE) or inductively coupled plasma etching (ICP), as shown in FIG. 7 ⁇ m.
  • RIE reactive ion etching
  • ICP inductively coupled plasma etching
  • an oxide film was formed on the bottom and sidewalls of the trench, as shown in Fig. 6, to a thickness of 100 nm.
  • a layer of Si 3 N 4 was grown as a spacer by plasma enhanced chemical vapor deposition (PECVD), and as shown in FIG. 8, the thickness of the spacer was 30 nm.
  • PECVD plasma enhanced chemical vapor deposition
  • a metal is deposited on the front side to form a Schottky contact as a source electrode as shown in FIG.
  • a metal is deposited on the back side to form an ohmic contact as a drain electrode as shown in FIG.
  • an N-drift layer is epitaxially grown on the N+ substrate. As shown in FIG. 2, the drift layer has a thickness of 50 ⁇ m and a doping concentration of 8 ⁇ 10 14 cm -3 .
  • the resistivity of the N+ substrate is 0.015-0.02 ohm cm.
  • the mask on the N-drift layer is used to lithography the pattern to be doped, and the ion implantation process of the P well is performed. As shown in FIG. 3, the distance between each P well is 1.5 ⁇ m, and the P well depth is 1.5. Mm. The Part of it is used to form a Schottky contact with the metal.
  • the N+ source region pattern is photolithographically patterned using a mask to perform an ion implantation process in the N+ source region.
  • the depth of the N+ source region is less than that of the P well, which is 0.5 ⁇ m, and the width is also smaller than the P well, as shown in FIG.
  • a gate trench (U-channel) pattern is photolithographically patterned using a mask, and a trench is formed by reactive ion etching (RIE) or inductively coupled plasma etching (ICP), as shown in FIG. 10 ⁇ m.
  • RIE reactive ion etching
  • ICP inductively coupled plasma etching
  • an oxide film was formed on the bottom and sidewalls of the trench, as shown in Fig. 6, to a thickness of 100 nm.
  • a layer of Si 3 N 4 was grown as a spacer by plasma enhanced chemical vapor deposition (PECVD), and as shown in FIG. 8, the thickness of the spacer was 20 nm.
  • PECVD plasma enhanced chemical vapor deposition
  • a metal is deposited on the front side to form a Schottky contact as a source electrode as shown in FIG.
  • a metal is deposited on the back side to form an ohmic contact as a drain electrode as shown in FIG.
  • an N-drift layer is epitaxially grown on the N+ substrate. As shown in FIG. 2, the drift layer has a thickness of 100 ⁇ m and a doping concentration of 5 ⁇ 10 14 cm -3 .
  • the resistivity of the N+ substrate is 0.015-0.02 ohm cm.
  • a mask pattern on the N-drift layer is used to etch a pattern to be doped, and a P-well ion implantation process is performed. As shown in FIG. 3, the distance between each P well is 2 ⁇ m, and the P well depth is 2 ⁇ m. This portion is used to form a Schottky contact with the metal.
  • the N+ source region pattern is photolithographically patterned using a mask to perform an ion implantation process in the N+ source region.
  • the depth of the N+ source region is less than that of the P well, which is 0.5 ⁇ m, and the width is also smaller than the P well, as shown in FIG.
  • a gate trench (U-channel) pattern is photolithographically patterned using a mask, and a trench is formed by reactive ion etching (RIE) or inductively coupled plasma etching (ICP), as shown in FIG. Degree 10 ⁇ m.
  • RIE reactive ion etching
  • ICP inductively coupled plasma etching
  • an oxide film was formed on the bottom and sidewalls of the trench, as shown in Fig. 6, to a thickness of 100 nm.
  • a layer of Si 3 N 4 was grown as a spacer by plasma enhanced chemical vapor deposition (PECVD), and as shown in FIG. 8, the thickness of the spacer was 20 nm.
  • PECVD plasma enhanced chemical vapor deposition
  • a metal is deposited on the front side to form a Schottky contact as a source electrode as shown in FIG.
  • a metal is deposited on the back side to form an ohmic contact as a drain electrode as shown in FIG.
  • an N-drift layer is epitaxially grown on the N+ substrate. As shown in FIG. 2, the drift layer has a thickness of 112 ⁇ m and a doping concentration of 7 ⁇ 10 ⁇ 14 cm ⁇ 3 .
  • the resistivity of the N+ substrate is 0.015-0.02 ohm cm.
  • the mask on the N-drift layer is used to lithography the pattern to be doped, and the ion implantation process of the P well is performed.
  • the distance between each P well is 1.5 ⁇ m, and the depth of the P well is 2 ⁇ m. . This portion is used to form a Schottky contact with the metal.
  • the N+ source region pattern is photolithographically patterned using a mask to perform an ion implantation process in the N+ source region.
  • the depth of the N+ source region is less than that of the P well, which is 0.5 ⁇ m, and the width is also smaller than the P well, as shown in FIG.
  • a gate trench (U-channel) pattern is photolithographically patterned using a mask, and a trench is formed by reactive ion etching (RIE) or inductively coupled plasma etching (ICP), as shown in FIG. 10 ⁇ m.
  • RIE reactive ion etching
  • ICP inductively coupled plasma etching
  • an oxide film was formed on the bottom and sidewalls of the trench, as shown in Fig. 6, to a thickness of 100 nm.
  • a layer of Si 3 N 4 was grown as a spacer by plasma enhanced chemical vapor deposition (PECVD), and as shown in FIG. 8, the thickness of the spacer was 20 nm.
  • PECVD plasma enhanced chemical vapor deposition
  • a metal is deposited on the front side to form a Schottky contact as a source electrode as shown in FIG.
  • a metal is deposited on the back side to form an ohmic contact as a drain electrode as shown in FIG.
  • the embodiments of the present invention have the following beneficial effects: 1) the source of the silicon carbide trench MOSFET of the embodiment of the present invention forms a Schottky contact with the epitaxial layer between the P wells, and the formed Schottky diode is in operation of the device.
  • the function of the freewheeling diode improves the efficiency and reliability of the circuit operation; 2)
  • the integrated device of the embodiment of the invention avoids the circuit conversion caused by the high turn-on voltage of the SiC PN junction when the PN junction in the SiC MOSFET is used as a freewheeling diode The problem of low efficiency; 3)
  • the SiC Schottky diode of the embodiment of the present invention is a unipolar device, which avoids the problem of increased BPD dislocation caused by the operation of the PN junction, and the reliability of the device is lowered; 4)
  • the embodiment of the present invention The integrated fabrication of SiC Schottky diodes and SiC MOSFETs reduces the material and process cost of device fabrication.

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Abstract

一种集成肖特基二极管的SiC沟槽型MOSFET器件及其制造方法，器件包括：1）沟槽型MOSFET：N+衬底及其上的N-漂移层，N-漂移层包含彼此隔离的有N+源区的P阱；P阱外侧的U型沟道，U型沟道表面有氧化层，其内有栅极；栅极及部分N+源区上的隔离层；和正面的源极及背面的漏极；2)肖特基二极管： N-漂移层内的P阱间的N-漂移层与源极金属形成的肖特基接触。

Description

一种集成肖特基二极管的SiC沟槽型MOSFET器件及其制造方法
相关申请的交叉引用
本申请基于申请号为201511032546.6、申请日为2015年12月31日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本发明涉及半导体技术，具体涉及一种集成肖特基二极管的SiC沟槽型MOSFET器件及其制造方法。
背景技术
碳化硅(SiC)是继第一代半导体材料硅、锗和第二代半导体材料砷化镓、磷化铟后发展起来的第三代半导体材料，碳化硅材料的宽禁带是硅和砷化镓的2～3倍，使得半导体器件能在相当高的温度下(500℃以上)工作且具有发射蓝光的能力；其高击穿电场比硅和砷化镓均要高一个数量级，决定了半导体器件的高压、大功率性能；其高的饱和电子漂移速度和低介电常数决定了器件的高频、高速工作性能；碳化硅的导热率是硅的3.3倍、砷化镓的10倍，意味着其导热性能好，可以大大提高电路的集成度，减少冷却散热系统，从而减少整机的体积。因此随着碳化硅材料和器件工艺的不断完善，部分Si领域被碳化硅所替代指日可待。碳化硅具有宽带隙、高临界击穿场强、高的热导率、高的电子饱和飘逸速率等特点，特别适合大功率、高电压电力电子器件，因此成为当前电力电子领域的研究热点。
SiC基功率器件的理论最高工作电压范围大于10kV，高于硅基绝缘栅双极型晶体管(IGBT)器件的工作电压；作为单极性器件，其开关速度快 于双极型的硅基IGBT，所需外延层更是由于SiC十倍于硅基的临界击穿电场而减小，因此被视为替代硅基IGBT器件的理想选择。
对于可控开关型的电力电子器件如：IGBT、金属氧化层半导体场效应晶体管(MOSFET)等，其在应用时，往往与二极管反并联以在电路中起续流作用，如附图1所示的功率IGBT与二极管反并联的电路示意图。硅基IGBT一般是将反并联的二极管同时封装成为功率模块，而硅基MOSFET则由于P阱与漂移区自然形成了反并联二极管，因此不需额外增加二极管来并联封装。
SiC基MOSFET虽然也具有自然形成的反并联二极管，但是由于SiC的禁带宽度高，其PN结二极管的开启电压高，达到3V左右，当使用SiC MOSFET内部的反并联二极管时，会大大的增加电路中的功耗；同时，由于SiC材料中的基矢面位错会由于PN结的工作诱导出层错，因此，采用其内部PN结二极管作反并联二极管会影响器件的可靠性。使用SiC MOSFET器件时，一般需要在其外部反并联SiC肖特基二极管，但是这样会增加器件的制作成本。
发明内容
本发明的目的是提供一种集成肖特基器件的碳化硅沟槽型MOSFET及其制造方法，克服现有技术存在的上述缺陷，通过在沟槽型SiC MOSFET中引入肖特基二极管，在器件工作时，起续流二极管的作用，提高了电路工作的效率与可靠性，降低了电路制作成本。
为了达到上述目的，本发明实施例采用以下技术方案：
一种集成肖特基二极管的SiC沟槽型MOSFET器件，所述器件包括：
1)沟槽型MOSFET：
N+衬底及其上的N-漂移层，所述N-漂移层包含彼此隔离的有N+源区的P阱；
所述P阱外侧的U型沟道，所述U型沟道表面有氧化层，其内有栅极；
所述栅极及部分所述N+源区上的隔离层；和
正面的源极及背面的漏极；
2)肖特基二极管：所述N-漂移层内的所述P阱间的N-漂移层与所述源极金属形成的肖特基接触。
所述的器件的第一优选技术方案，所述肖特基二极管为续流二极管。
所述的器件的第二优选技术方案，所述N+衬底的电阻率为0.015～0.02欧姆厘米。
所述的器件的第三优选技术方案，所述N-漂移层的厚度为10～500μm，其掺杂浓度为1×1014～5×1015cm-3。
所述的器件的第四优选技术方案，所述P阱间的距离为1～3μm，其阱深为1～3μm。
所述的器件的第五优选技术方案，所述N+源区的宽度和深度均小于所述P阱。
所述的器件的第六优选技术方案，所述U型沟道的深度为4～10μm。
所述的器件的第七优选技术方案，所述氧化层的厚度为50～150μm；所述隔离层的厚度为15～50μm。
所述的器件的第八优选技术方案，所述栅极为n型或p型简并掺杂的多晶硅。
一种集成肖特基二极管的SiC沟槽型MOSFET器件的制造方法，所述方法包括如下步骤：
1)在N+衬底外延N-漂移层表面制作掩膜并图形化，注入杂质形成P阱；
2)在所述P阱表面制作掩膜并图形化，掺杂形成N+源区；
3)于所述N-漂移层上制作掩膜并图形化，刻蚀SiC形成U型沟道；
4)在所述沟道内表面沉积氧化层；
5)在所述具有氧化层的沟道内填充多晶硅poly，形成栅极；
6)于所述栅极及部分所述N+源区上淀积隔离层；
7)在所述漂移层正面和所述衬底背面淀积金属，分别形成源极和漏极。
与最接近的现有技术比，本发明实施例具有如下有益效果：
1)本发明实施例的碳化硅沟槽型MOSFET的源极在P阱之间与外延层形成肖特基接触，形成的肖特基二极管在器件工作时，起续流二极管的作用，提高了电路工作的效率与可靠性；
2)本发明实施例的集成器件避免了SiC MOSFET中的PN结作为续流二极管时，SiC PN结开启电压高引起的电路转换效率低的问题；
3)本发明实施例的SiC肖特基二极管为单极器件，避免了PN结工作时引起的BPD位错增大，器件可靠性降低的问题；
4)本发明实施例的SiC肖特基二极管与SiC MOSFET的集成制备，降低了器件制作的材料与工艺成本。
附图说明
图1为IGBT与二极管反并联的电路示意图；
图2为N+衬底上形成N-漂移层的剖面图；
图3为N-漂移层离子注入形成P阱的剖面图；
图4为P阱内离子注入形成N+源区的剖面图；
图5为P阱外侧刻蚀形成U型沟道的剖面图；
图6为沟道底部和侧壁形成氧化膜的剖面图；
图7为沟道内填充多晶硅poly的剖面图；
图8为N-漂移层上沉积隔离层的剖面图；
图9为光刻部分隔离层后的剖面图；
图10为正面沉积金属形成源极的剖面图；
图11为背面沉积金属形成漏极的剖面图。
具体实施方式
下面结合实例对本发明进行详细的说明，本发明并不局限于该具体实施例，本领域内的技术人员所熟知的一般替换也涵盖在本发明的保护范围内。
实施例1
首先在N+衬底上外延生成N-漂移层，如图2所示，该漂移层的厚度为12μm，掺杂浓度为2×1015cm-3。N+衬底的电阻率为0.015-0.02欧姆厘米。
然后在N-漂移层上的掩膜版光刻出需要掺杂的图形，进行P阱的离子注入工艺，如图3所示，各P阱之间的距离为1μm，P阱深为1μm。该部分用来与金属形成肖特基接触。
接着，利用掩膜版光刻出N+源区图形，进行N+源区的离子注入工艺，N+源区的深度小于P阱，为0.5μm，宽度也小于P阱，如图4所示。
接着，利用掩膜版光刻出栅槽(U型沟道)图形，采用反应离子刻蚀(RIE)或感应耦合等离子体刻蚀(ICP)形成沟槽，如图5所示，沟道深度5μm。
接着，在沟槽底部和侧壁形成氧化膜，如图6所示，厚度为100nm。
接着，在沟槽内填充多晶硅poly，如图7所示。
接着，通过等离子增强化学气相沉积(PECVD)生长一层Si3N4作为隔离层，如图8所示，隔离层厚度为20nm。
接着，通过光刻，曝露出除栅极和部分N+源区的其他部位，如图9所示。
接着，在正面沉积金属，形成肖特基接触，作为源极电极，如图10所示。
最后，在背面沉积金属，形成欧姆接触，作为漏极电极，如图11所示。
实施例2
首先在N+衬底上外延生成N-漂移层，如图2所示，该漂移层的厚度为15μm.掺杂浓度为1×1015cm-3。N+衬底的电阻率为0.015-0.02欧姆厘米。
然后在N-漂移层上的掩膜版光刻出需要掺杂的图形，进行P阱的离子注入工艺，如图3所示，各P阱之间的距离为1.5μm，P阱深为1μm。该部分用来与金属形成肖特基接触。
接着，利用掩膜版光刻出N+源区图形，进行N+源区的离子注入工艺，N+源区的深度小于P阱，为0.5μm，宽度也小于P阱，如图4所示。
接着，利用掩膜版光刻出栅槽(U型沟道)图形，采用反应离子刻蚀(RIE)或感应耦合等离子体刻蚀(ICP)形成沟槽，如图5所示，沟道深度7μm。
接着，在沟槽底部和侧壁形成氧化膜，如图6所示，厚度为100nm。
接着，在沟槽内填充多晶硅poly，如图7所示。
接着，等离子增强化学气相沉积(PECVD)生长一层Si3N4作为隔离层，如图8所示，隔离层厚度为30nm。
接着，通过光刻，曝露出除栅极和部分N+源区的其他部位，如图9所示。
接着，在正面沉积金属，形成肖特基接触，作为源极电极，如图10所示。
最后，在背面沉积金属，形成欧姆接触，作为漏极电极，如图11所示。
实施例3
首先在N+衬底上外延生成N-漂移层，如图2所示，该漂移层的厚度为50μm，掺杂浓度为8×1014cm-3。N+衬底的电阻率为0.015-0.02欧姆厘米。
然后在N-漂移层上的掩膜版光刻出需要掺杂的图形，进行P阱的离子注入工艺，如图3所示，各P阱之间的距离为1.5μm，P阱深为1.5μm。该 部分用来与金属形成肖特基接触。
接着，利用掩膜版光刻出N+源区图形，进行N+源区的离子注入工艺，N+源区的深度小于P阱，为0.5μm，宽度也小于P阱，如图4所示。
接着，利用掩膜版光刻出栅槽(U型沟道)图形，采用反应离子刻蚀(RIE)或感应耦合等离子体刻蚀(ICP)形成沟槽，如图5所示，沟道深度10μm。
接着，在沟槽底部和侧壁形成氧化膜，如图6所示，厚度为100nm。
接着，在沟槽内填充多晶硅poly，如图7所示。
接着，等离子增强化学气相沉积(PECVD)生长一层Si3N4作为隔离层，如图8所示，隔离层厚度为20nm。
接着，通过光刻，曝露出除栅极和部分N+源区的其他部位，如图9所示。
接着，在正面沉积金属，形成肖特基接触，作为源极电极，如图10所示。
最后，在背面沉积金属，形成欧姆接触，作为漏极电极，如图11所示。
实施例4
首先在N+衬底上外延生成N-漂移层，如图2所示，该漂移层的厚度为100μm，掺杂浓度为5×1014cm-3。N+衬底的电阻率为0.015-0.02欧姆厘米。
然后在N-漂移层上的掩膜版光刻出需要掺杂的图形，进行P阱的离子注入工艺，如图3所示，各P阱之间的距离为2μm，P阱深为2μm。该部分用来与金属形成肖特基接触。
接着，利用掩膜版光刻出N+源区图形，进行N+源区的离子注入工艺，N+源区的深度小于P阱，为0.5μm，宽度也小于P阱，如图4所示。
接着，利用掩膜版光刻出栅槽(U型沟道)图形，采用反应离子刻蚀(RIE)或感应耦合等离子体刻蚀(ICP)形成沟槽，如图5所示，沟道深 度10μm。
接着，在沟槽底部和侧壁形成氧化膜，如图6所示，厚度为100nm。
接着，在沟槽内填充多晶硅poly，如图7所示。
接着，等离子增强化学气相沉积(PECVD)生长一层Si3N4作为隔离层，如图8所示，隔离层厚度为20nm。
接着，通过光刻，曝露出除栅极和部分N+源区的其他部位，如图9所示。
接着，在正面沉积金属，形成肖特基接触，作为源极电极，如图10所示。
最后，在背面沉积金属，形成欧姆接触，作为漏极电极，如图11所示。
实施例5
首先在N+衬底上外延生成N-漂移层，如图2所示，该漂移层的厚度为112μm，掺杂浓度为7×10-14cm-3。N+衬底的电阻率为0.015-0.02欧姆厘米。
然后在N-漂移层上的掩膜版光刻出需要掺杂的图形，进行P阱的离子注入工艺，如图3所示，各P阱之间的距离为1.5μm，P阱深为2μm。该部分用来与金属形成肖特基接触。
接着，利用掩膜版光刻出N+源区图形，进行N+源区的离子注入工艺，N+源区的深度小于P阱，为0.5μm，宽度也小于P阱，如图4所示。
接着，利用掩膜版光刻出栅槽(U型沟道)图形，采用反应离子刻蚀(RIE)或感应耦合等离子体刻蚀(ICP)形成沟槽，如图5所示，沟道深度10μm。
接着，在沟槽底部和侧壁形成氧化膜，如图6所示，厚度为100nm。
接着，在沟槽内填充多晶硅poly，如图7所示。
接着，等离子增强化学气相沉积(PECVD)生长一层Si3N4作为隔离层，如图8所示，隔离层厚度为20nm。
接着，通过光刻，曝露出除栅极和部分N+源区的其他部位，如图9所示。
接着，在正面沉积金属，形成肖特基接触，作为源极电极，如图10所示。
最后，在背面沉积金属，形成欧姆接触，作为漏极电极，如图11所示。
最后应当说明的是：以上实施例仅用以说明本发明的技术方案而非对其限制，尽管参照上述实施例对本发明进行了详细的说明，所属领域的普通技术人员应当理解：依然可以对本发明的具体实施方式进行修改或者等同替换，而未脱离本发明精神和范围的任何修改或者等同替换，其均应涵盖在本发明的权利要求范围当中。
工业实用性
本发明实施例具有如下有益效果：1)本发明实施例的碳化硅沟槽型MOSFET的源极在P阱之间与外延层形成肖特基接触，形成的肖特基二极管在器件工作时，起续流二极管的作用，提高了电路工作的效率与可靠性；2)本发明实施例的集成器件避免了SiC MOSFET中的PN结作为续流二极管时，SiC PN结开启电压高引起的电路转换效率低的问题；3)本发明实施例的SiC肖特基二极管为单极器件，避免了PN结工作时引起的BPD位错增大，器件可靠性降低的问题；4)本发明实施例的SiC肖特基二极管与SiC MOSFET的集成制备，降低了器件制作的材料与工艺成本。

Claims (10)

  1. 一种集成肖特基二极管的SiC沟槽型MOSFET器件，所述器件包括：
    1)沟槽型MOSFET：
    N+衬底及其上的N-漂移层，所述N-漂移层包含彼此隔离的有N+源区的P阱；
    所述P阱外侧的U型沟道，所述U型沟道表面有氧化层，其内有栅极；
    所述栅极及部分所述N+源区上的隔离层；和
    正面的源极及背面的漏极；
    2)肖特基二极管：所述N-漂移层内的所述P阱间的N-漂移层与所述源极金属形成的肖特基接触。
  2. 根据权利要求书1所述的器件，其中，所述肖特基二极管为续流二极管。
  3. 根据权利要求书1所述的器件，其中，所述N+衬底的电阻率为0.015～0.02欧姆厘米。
  4. 根据权利要求书1所述的器件，其中，所述N-漂移层的厚度为10～500μm，其掺杂浓度为1×1014～5×1015cm-3。
  5. 根据权利要求书1所述的器件，其中，所述P阱间的距离为1～3μm，其阱深为1～3μm。
  6. 根据权利要求书1所述的器件，其中，所述N+源区的宽度和深度均小于所述P阱。
  7. 根据权利要求书1所述的器件，其中，所述U型沟道的深度为4～10μm。
  8. 根据权利要求书1所述的器件，其中，所述氧化层的厚度为 50～150μm；所述隔离层的厚度为15～50μm。
  9. 根据权利要求书1所述的器件，其中，所述栅极为n型或p型简并掺杂的多晶硅。
  10. 一种集成肖特基二极管的SiC沟槽型MOSFET器件的制造方法，所述方法包括如下步骤：
    1)在N+衬底外延N-漂移层表面制作掩膜并图形化，注入杂质形成P阱；
    2)在所述P阱表面制作掩膜并图形化，掺杂形成N+源区；
    3)于所述N-漂移层上制作掩膜并图形化，刻蚀SiC形成U型沟道；
    4)在所述沟道内表面沉积氧化层；
    5)在所述具有氧化层的沟道内填充多晶硅poly，形成栅极；
    6)于所述栅极及部分所述N+源区上淀积隔离层；
    7)在所述漂移层正面和所述衬底背面淀积金属，分别形成源极和漏极。
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