CN107851663A - 半导体器件和用于制造半导体器件的方法 - Google Patents

半导体器件和用于制造半导体器件的方法 Download PDF

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CN107851663A
CN107851663A CN201680041948.9A CN201680041948A CN107851663A CN 107851663 A CN107851663 A CN 107851663A CN 201680041948 A CN201680041948 A CN 201680041948A CN 107851663 A CN107851663 A CN 107851663A
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barrier layer
semiconductor devices
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semiconductor structure
carrier channels
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CN107851663B (zh
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张坤好
张宇昊
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Mitsubishi Electric Corp
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Abstract

一种半导体器件(100)包括：半导体结构(170)，其形成载流子沟道(140)；势垒层(171)，其接近半导体结构设置；以及一组电极(120、125、130)，其用于提供并控制载流子沟道中的载流子电荷。该势垒层由具有与载流子沟道的导电类型相反的导电类型的杂质至少部分地掺杂。该势垒层的材料具有比该半导体结构中的材料的带隙和热导率大的带隙和热导率。

Description

半导体器件和用于制造半导体器件的方法
技术领域
本发明总体涉及半导体器件，更具体地涉及具有诸如背势垒或盖层的势垒层的半导体器件。
背景技术
半导体器件在解决能量挑战中具有重要的角色。特别地，氮化物功率晶体管在先进运输系统、可靠能量输送网络以及用于高效率发电和转换的许多新方案的应用中具有极大的潜力。这些系统依赖于提高或降低电压的非常高效的转换器。这些器件中的大多数是由硅(Si)制成。然而，Si的有限击穿电压和频率响应及其较高的电阻使得当前可用的商业装置器件和电路非常庞大、沉重且不适于将来的功率用途。作为另选方案，氮化镓(GaN)器件对于电源应用已经实现高电压、高频率响应以及低导通电阻的记录组合。
诸如GaN基高电子迁移率晶体管(HEMT)这样的GaN功率器件被认为是用于高功率、高电压以及高频率应用的最有前途的候选中的一种。GaN HEMT已经以高的多的击穿电压(VB)和电流密度以及超过400GHz的高的截止频率实现了比GaAs HEMT高至10倍的功率密度。已经通过在2.9GHz下为800W和3.5GHz下超过500W的总输出功率在碳化硅(SiC)衬底上演示了现有技术的功率电平。然而，对于高功率应用，诸如高功率马达，期望较高的输出功率，即，3～5kW，这需要进一步提高半导体器件的输出功率。
发明内容
本发明的一些实施方式基于以下认识：多个方法可以用于提高半导体器件的输出功率。例如，可以通过由垂直电场耗尽半导体器件中的载流子沟道来增大半导体器件的击穿电压。用于提高器件功率能力的其他方法包括热管理以及降低由于载流子电荷的寄生泄露而导致的功率损失。然而，各方法仅可以在一定程度上提高半导体器件的功率能力。
本发明的一些实施方式基于以下认识：这些功率提高方法可以通过仔细选择形成半导体器件的材料的特性来实施。尽管有不同的功率提高方法使用不同材料的不同特性的事实，但认识到，如与例如材料的形状对照，材料的特性是这些功率提高方法背后的驱动力之一。
例如，载流子沟道的耗尽可以通过由具有与载流子沟道的导电类型相反的导电类型的杂质至少部分地对材料层掺杂来执行。半导体器件的热管理可以由具有比形成载流子沟道的半导体结构中的材料的热导率大的热导率的材料层来执行。类似地，载流子电荷的泄露可以由具有比形成载流子沟道的半导体结构中的材料的带隙大的带隙的材料层来减少。
本发明的一些实施方式基于以下认识：可以选择具有由不同功率装箱方法使用的特性的单个材料。这样，可以使用这种材料的单个层来在降低半导体器件的总成本的同时执行多个功率提高功能。
因此，一个实施方式公开了一种半导体器件，该半导体器件包括：半导体结构，该半导体结构形成载流子沟道；势垒层，该势垒层接近半导体结构设置；以及一组电极，该组电极用于提供并控制载流子沟道中的载流子电荷。势垒层由具有与载流子沟道的导电类型相反的导电类型的杂质至少部分地掺杂。势垒层的材料具有比半导体结构中的材料的带隙和热导率大的带隙和热导率。
由于较大的带隙、相反类型的掺杂以及高的热导率，势垒层可以强化沟道载流子约束，形成用于电场工程的表面降场(RESURF)结构，并且充当表面散热层。势垒层的示例包括背势垒或盖层。
本发明的一个实施方式公开了一种半导体器件，该半导体器件包括：半导体结构，该半导体结构形成载流子沟道；势垒层，该势垒层接近半导体结构设置，其中，势垒层由具有与载流子沟道的导电类型相反的导电类型的杂质至少部分地掺杂，其中，势垒层的材料具有比半导体结构中的材料的带隙和热导率大的带隙和热导率；以及一组电极，该组电极用于提供并控制载流子沟道中的载流子电荷。
另一个实施方式公开了一种半导体器件，该半导体器件包括：半导体结构，该半导体结构形成载流子沟道，其中，半导体结构是包括III-V沟道层和III-V势垒层的半导体异质结构，使得载流子沟道是二维电子气(2DEG)沟道；势垒层，该势垒层接近半导体结构设置，其中，势垒层至少部分p型掺杂，其中，势垒层具有比III-V沟道层中的材料的带隙和热导率大的带隙和热导率；以及一组电极，该组电极用于提供并控制载流子沟道中的载流子电荷。
又一个实施方式公开了一种用于制造半导体器件的方法，该方法包括以下步骤：提供衬底；制造半导体结构，该半导体结构至少包括在半导体结构中形成载流子沟道的III-V沟道层；接近半导体结构制造势垒层，其中，势垒层具有比III-V沟道层中的材料的带隙和热导率大的带隙和热导率；用具有与载流子沟道相反的导电类型的杂质掺杂势垒层；以及形成与载流子沟道电接触的电极。
附图说明
[图1]
图1是根据本发明的一个实施方式的半导体器件的截面图；
[图2]
图2是例示了具有多功能背势垒层的半导体器件的一个实施方式的截面图；
[图3]
图3是图2所示的实施方式内的截线AA’的能带图；
[图4]
图4是根据本发明的一个实施方式的、具有缩短多功能势垒层的半导体器件的截面图；
[图5A]
图5A是作为势垒层的掺杂浓度和厚度的函数的击穿电压(BV)的曲线图；
[图5B]
图5B是作为电荷密度的函数的BV的曲线图；
[图5C]
图5C是根据本发明的一些实施方式的BV对p-金刚石背势垒的长度的依赖关系的曲线图；
[图6]
图6是根据本发明的一个实施方式在不同衬底上具有多功能势垒层的III-V半导体器件的截面图；
[图7]
图7是具有多功能盖层的半导体器件的截面图；
[图8]
图8是图7所示的实施方式的沿着截线BB’的能带图；
[图9]
图9是根据本发明的一个实施方式的、具有多功能盖层和多功能背势垒的半导体器件的截面图；以及
[图10]
图10是根据本发明的一些实施方式的用于制造半导体器件的方法的框图。
具体实施方式
图1示出了根据本发明的一个实施方式的半导体器件100的截面图。在该实施方式中，半导体器件包括形成载流子沟道140的半导体结构170。例如，半导体结构是包括III-V沟道层173和III-V势垒层172的层结构，使得载流子沟道140是二维电子气(2DEG)沟道。例如，III-V沟道层的材料可以包括GaN或GaAs中的一种或组合。III-V势垒层的材料可以包括氮化镓铝(AlGaN)、氮化镓铟(InGaN)、氮化镓铝铟(InAlGaN)、氮化铝(AlN)、砷化镓铝(AlGaAs)、砷化镓铟(InGaAs)、砷化镓铝铟(InAlGaAs)中的一种或组合。
半导体器件100还包括接近半导体结构设置的势垒层171。势垒层与载流子沟道平行地延伸，以完全或仅部分交叠载流子沟道。
势垒层至少部分地掺杂有具有与载流子沟道的导电类型相反的导电类型的杂质。例如，势垒层可以至少部分p型掺杂有硼和镁中的一种或组合。在一个实施方式中，势垒层的厚度、掺杂浓度以及长度被选择成在半导体器件的击穿电压下完全耗尽载流子沟道中的电荷。
并且，势垒层的材料具有比半导体结构中的材料的带隙和热导率大的带隙和热导率。例如，势垒层的材料可以被选择成具有比III-V沟道层中的材料的带隙和热导率大的带隙和热导率。例如，势垒层的材料可以包括金刚石、氮化硼以及氮化铝中的一种或组合。
半导体器件100还包括一组电极，该组电极用于提供并控制载流子沟道中的载流子电荷。例如，一组电极可以包括：至少一个源电极120，其通过载流子沟道发送电子电荷；至少一个漏电极130，其接收电子电荷；以及至少一个栅电极125，其可操作地连接到半导体结构170以控制载流子电荷的传导。
半导体器件还可以包括其他层，例如衬底110。在一些实施方式中，势垒层171设置在衬底110与半导体结构170之间。在这些实施方式中，势垒层是背势垒层。另选地，势垒层可以为设置在半导体结构的顶部上的盖层。
本发明的一些实施方式基于以下认识：不同功率提高方法可以通过仔细选择形成半导体器件的材料的特性来实施。尽管有不同的功率提高方法使用不同材料的不同特性的事实，但认识到，如与例如材料的形状对照，材料的特性是这些功率提高方法背后的驱动力之一。
例如，载流子沟道的耗尽可以通过由具有与载流子沟道的导电类型相反的导电类型的杂质至少部分地对材料层掺杂来执行。半导体器件的热管理可以由具有比形成载流子沟道的半导体结构中的材料的热导率大的热导率的材料层来执行。类似地，载流子电荷的泄露可以由具有比形成载流子沟道的半导体结构中的材料的带隙大的带隙的材料层来减小。
本发明的一些实施方式基于以下认识：可以选择具有由不同功率装箱方法使用的特性的单个材料。这样，可以使用这种材料的单个层来在降低半导体器件的总成本的同时执行多个功率提高功能。
为此，一些实施方式在半导体器件中包括多功能势垒层171。由于较大的带隙、相反类型的掺杂以及高的热导率，势垒层可以强化沟道载流子约束，形成用于电场工程的表面降场(RESURF)结构，并且充当表面散热层。
图2示出了简化截面图，其例示了具有多功能背势垒层的III-V场效应晶体管(FET)的一个实施方式。区域10包括金刚石，并且可以为单个衬底层或包括多层，诸如衬底层与掺杂层11之间的过渡层。层11是可以同时提供多个功能的势垒层。
根据一些实施方式，可以对于金刚石区域10的形成采用各种方法，包括但不限于化学气相沉积(CVD)、金属有机化学气相沉积(MOCVD)、DC等离子体CVD、微波等离子体沉积系统。区域10可以未掺杂或可以特意掺杂有n型掺杂剂或p型掺杂剂，包括但不限于硼(B)、氮(N)以及磷(P)。金刚石背势垒层11以在10nm至10μm范围内的示例性厚度设置在所述金刚石区域10上。
背势垒金刚石层11由具有与载流子沟道的导电类型相反的导电类型的杂质完全或至少部分地掺杂。例如，在GaN基HEMT的一些实施方式中，金刚石背势垒层11可以以在从1×1016cm-3至1×1021cm-3范围内的示例性掺杂密度掺杂有p型掺杂剂，诸如B。层11中的掺杂剂可以在外延生长期间添加或可以在形成层11之后通过离子注入来添加。
在金刚石背势垒层11上设置有半导体或电介质区域12。区域12可以包括用于促进化合物半导体外延层在晶格失配金刚石上的生长的单层或多个缓冲层，包括黏附层、成核层、过渡层以及其它层。区域12的材料可以为电介质，诸如SiNx、Al2O3、SiO2；二元III-V材料，诸如AlN或GaN；三元III-V材料，诸如InGaN和AlGaN；以及四元III-V材料，诸如氮化镓铟铝(AlInGaN)。
在一些实施方式中，区域12中的过渡层可以为超晶格结构和成分梯度层。III-V半导体层13以在50nm至10μm范围内的示例性厚度设置在区域12上。在一些实施方式中，层13的材料可以为III氮化物或III砷化物材料。层13可以为n型(即，低程度掺杂的n型材料)掺杂的、非特意掺杂的、或p型掺杂的，但优选地为非特意掺杂的或具有与所述区域11相反的导电类型。
化合物半导体层14以在5nm至100nm范围内的示例性厚度设置在III-V半导体层13上。层14的材料与层13的材料相比具有不同的晶格常数和带隙能量。在一些实施方式中，层14的材料具有比层13的材料大的带隙能量，并且2DEG沟道形成在层14和层13的异质结构处。在一个实施方式中，层14和层13的材料可以为InAlGaN和GaN、AlGaN和GaN、AlN和Gan、或InGaN和GaN。
根据一些实施方式，对于化合物半导体区域13和14的形成可以采用各种方法，包括但不限于化学气相沉积(CVD)、金属有机化学气相沉积(MOCVD)、分子束外延(MBE)以及金属有机气相外延(MOVPE)。
一组电极包括用于2DEG沟道的源电极S 1、栅电极G 1以及漏电极D 1。源电极S 1和漏电极D 1可以被形成为延伸到层14中，甚至延伸到层13中，以形成对异质结构处的2DEG的连接。在一些实施方式中，在层14上和栅电极G 1下方可以设置电介质层15，以形成金属-绝缘体-半导体(MIS)或MOS栅堆。区域15的材料可以包括但不限于二氧化硅(SiO2)、氮化硅(SixNy)、氧化氮化硅氢(SixOyNzHw)、氧化铝(Al2O3)、二氧化铪(HfO2)。
用于2DEG沟道的栅堆可以为耗尽模式(D模式)或增强模式(E模式)。在一些实施方式中，栅堆G 1固有地为D模式，这意味着2DEG沟道的阈值电压(Vth)为负。在一些实施方式中，对于G 1可以使用各种方法来将D模式栅堆转换成E模式，包括但不限于：(a)部分蚀刻G1下方的层14和15；(b)将负离子注入到G 1下方的层13、14以及15中，离子包括但不限于氟和氯；(c)在层14与15之间插入p型半导体层。
在一些其他实施方式中，电介质区域16可以被形成为钝化层。区域16可以包括具有包括但不限于Al2O3、SiO2、AlN、SiNx、HfO2、纳米晶体金刚石的材料的单个或多个绝缘层。
图3示出了图2所示的实施方式内的截线AA’的能带图。如图所示，在由层13和14形成的异质结构之间的界面处，导带Ec下降至费米能级Ef以下。因此，由于压电效应和自发掺杂而感生的电子在异质结构处形成2DEG表层电荷区域。因为层11为p型并且具有比层13中的III-V材料大的带隙，所以与电子从2DEG朝向缓冲层11和衬底区域10的移动相反的大的势垒形成在层13与11之间。由此，背势垒层11可以增强2DEG电子约束。
并且，背势垒层11它还可以起RESURF结构的作用，因为其具有与沟道层13相反的掺杂类型。如以上所讨论的，垂直p-n结可以帮助在器件反向偏压时耗尽沟道层13，减小层13中的峰值电场，并且在不增大器件导通电阻的情况下增大器件击穿。最后，由于与传统III-V半导体相比金刚石的较大热导率，背势垒层11可以促进散热。通过插入金刚石背势垒层11，可以期望沟道峰值温度降低至少10％，虽然需要更详细的模拟、优化以及实验来充分利用金刚石的散热能力。
在本发明的一些实施方式中，势垒层与载流子沟道平行地延伸，以仅部分交叠载流子沟道。在另选实施方式中，势垒层被缩短且与载流子沟道平行地延伸，以仅部分交叠载流子沟道。
图4示出了具有缩短的多功能势垒层的根据本发明的一个实施方式的半导体器件的截面图。在该实施方式中，金刚石背势垒层11被缩短为仅部分地在源漏区域上方延伸。缩短的势垒层11可以通过借助注入掩膜将掺杂剂离子注入到金刚石区域10的顶部中或外延生长处理随后为蚀刻构图处理来形成。
对于p-金刚石背势垒s，本发明的一些实施方式使用的设计原理是在击穿时由p-n结完全耗尽n-沟道(例如，2DEG沟道)中的电荷。三个参数，背势垒厚度t、栅缘至势垒缘距离L以及掺杂浓度NA，是实现p-金刚石背势垒的优化设计的重要因素。为此，本发明的一些实施方式将势垒层的厚度、掺杂浓度以及长度选择成在半导体器件的击穿点处完全耗尽载流子沟道中的电荷。
图5A示出了作为势垒层的掺杂浓度NA和厚度的函数的击穿电压(BV)的曲线图。该曲线图示出了最大BV 510可以由不同的p-金刚石掺杂浓度NA利用相应的不同的优化p-金刚石背势垒厚度t来实现。
图5B示出了作为电荷密度的函数的击穿电压(BV)的曲线图。图5A所示的优化NA和t与类似的总电荷密度(NA·t)520对应，其等效于n-沟道载流子密度(在该示例中为2DEG密度)，这示出强电荷平衡效果。在优化设计中，两个相等的E场峰出现在栅缘和漏缘处。由此，对于已构图的p-金刚石背势垒，栅缘到背势垒缘距离L的优化设计可以在漏缘或栅缘处进一步减小峰值E场。
图5C示出了例示了BV对p-金刚石背势垒的长度L的依赖关系的曲线图。曲线图示出了金刚石势垒层的优化长度较短，即，较接近GaN势垒层的优化长度540。为此，本发明的一些实施方式缩短多功能势垒层的长度，即，势垒层与载流子沟道平行地延伸，以仅部分交叠载流子沟道，并且不达到漏电极。
例如，击穿可能在背势垒长度时发生在栅缘处，并且如果则发生在漏缘处。对于击穿可能发生在层11和层13的p-n异质结上的背势垒缘处，如以在层13中支持较扩展的E场。对于传统p-GaN背势垒，GaN中的峰值E场总是停留在2DEG沟道附近而不是朝向p-n结移动并且BV在背势垒延伸到漏侧时达到最大，观察不到该E场调制效应。这可能是由于与p-金刚石/n-GaN结中相比，在GaN p-n结中的较小的垂直E场。
图6示出了根据本发明的一个实施方式的在不同衬底上具有多功能势垒层的III-V半导体器件的一个实施方式的截面图。在该实施方式中，具有多功能背势垒的III-V半导体器件形成在不同的衬底上。衬底层18的材料包括但不限于GaN、硅(Si)、蓝宝石、碳化硅(SiC)、金刚石、氧化锌、氮化铝(AlN)、石墨烯。区域17与区域12类似，并且可以包括用于促进所述背势垒层17在衬底区域18上的生长或转移的单层或多层，包括黏附层、成核层、过渡层。区域17的材料可以为电介质，包括但不限于SiNx、Al2O3、SiO2；和化合物半导体，包括但不限于：二元III-V材料，诸如AlN或GaN；三元III-V材料，诸如InGaN和AlGaN；以及四元III-V材料，诸如氮化镓铟铝(AlInGaN)。在一些实施方式中，区域17中的过渡层可以为超晶格结构和成分梯度层。
具有多功能盖层的GaN基半导体器件
图7示出了具有多功能盖层的半导体器件的截面图。金刚石盖层20以10nm至10μm的示例性厚度设置在栅电介质层14上或直接设置在化合物半导体层14上。金刚石盖层20可以完全或部分交叠源-漏区域来延伸。金刚石盖层20由具有与载流子沟道的导电类型相反的导电类型的杂质完全或部分地掺杂。
在一个实施方式中，半导体器件是GaN基HEMT，金刚石盖层20`可以以1×1016cm-3至1×1021cm-3的示例性掺杂密度掺杂有诸如B这样的p型掺杂剂。所述层11中的掺杂剂可以在外延生长期间添加或可以在形成层20之后由离子注入来添加。
在一些实施方式中，栅电极G 1可以在盖层20的顶部上延伸，并且与盖层20形成欧姆或肖特基接触。在这些实施方式中，栅电极G 1对载流子沟道和盖层20具有同时且直接的控制。由于较大的带隙、相反类型的掺杂以及高的热导率，所述盖层20可以强化沟道载流子约束，对于电场工程形成RESURF结构，并且充当表面散热层。
在一些实施方式中，栅电极G 1设置在盖层20的顶部上，并且不直接控制载流子沟道。在这些实施方式中，由于盖层20具有与载流子沟道相反的导电类型，所以阈值电压可以被改变。例如，盖层20可以被完全或部分地p型掺杂，以将装置从耗尽模式(D模式)转换成增强模式(E模式)。
图8是图7所示的实施方式的沿着截线BB’的能带图。如图所示，p型盖层层20抬升能带，并且使得层13和14的异质结构处的导带下降能够高于费米能级Ef。因此，在零栅偏压下耗尽2DEG，实现了GaN基HEMT的E模式操作。
图9是具有多功能盖层和多功能背势垒的根据本发明的一个实施方式的半导体器件的截面图。在这些实施方式中，多功能盖势垒和背势垒层可以共存于同一III-V器件中。
制造方法
图10示出了根据本发明的一些实施方式的用于制造半导体器件的方法的框图。方法包括以下步骤：提供衬底1010；制造1020半导体结构，该半导体结构至少包括在半导体结构中形成载流子沟道的III-V沟道层；以及与半导体结构接近地制造1030势垒层。势垒层的材料具有比III-V沟道层中的材料的带隙和热导率大的带隙和热导率。在一些实施方式中，与III-V沟道层平行地设置势垒层，以仅部分交叠III-V沟道层。
进一步地，方法还包括以下步骤：用具有与载流子沟道相反的导电类型的杂质掺杂1040势垒层；以及形成1050与载流子沟道电接触的电极。电极可以使用电子束沉积、焦耳蒸发、化学气相沉积以及溅射处理中的一种或组合来形成。
另外，还可以与势垒层相邻地形成缓冲层。该缓冲层可以被形成为背势垒和/或盖层。在一些实施方式中，方法涉及衬底和在衬底顶面上生长和形成缓冲区域。根据一些实施方式，对于生长和形成可以采用各种方法，包括但不限于化学气相沉积(CVD)、金属有机化学气相沉积(MOCVD)、分子束外延(MBE)、金属有机气相外延(MOVPE)、等离子体增强化学气相沉积(PECVD)、以及微波等离子体沉积。
如对于所述衬底和缓冲区域的形成列出的，对于背势垒层的生长和形成可以采用各种方法。背势垒可以在外延生长期间掺杂或在形成背势垒之后通过离子注入来掺杂。III-V沟道结构可以外延生长在所述背势垒层的顶部上，或者可以从另一晶圆结构转移。可以从接触和访问区域部分地去除盖层。盖层可以在沉积/生长期间掺杂或在盖层形成之后由离子注入来掺杂。

Claims (20)

1.一种半导体器件，该半导体器件包括：
半导体结构，该半导体结构形成载流子沟道；
势垒层，该势垒层接近所述半导体结构设置，其中，所述势垒层由具有与所述载流子沟道的导电类型相反的导电类型的杂质至少部分地掺杂，其中，所述势垒层的材料具有比所述半导体结构中的材料的带隙和热导率大的带隙和热导率；以及
一组电极，该组电极用于提供并且控制所述载流子沟道中的载流子电荷。
2.根据权利要求1所述的半导体器件，所述半导体器件还包括：
衬底，其中，所述势垒层是设置在所述衬底与所述半导体结构之间的背势垒层。
3.根据权利要求1所述的半导体器件，其中，所述势垒层是设置在所述半导体结构的顶部上的盖层。
4.根据权利要求1所述的半导体器件，其中，所述势垒层的所述材料包括金刚石、氮化硼以及氮化铝中的一种或组合。
5.根据权利要求1所述的半导体器件，其中，所述势垒层的厚度在从10nm到10μm的范围内。
6.根据权利要求1所述的半导体器件，其中，所述势垒层的掺杂浓度在从1015cm-3到1022cm-3的范围内。
7.根据权利要求1所述的半导体器件，其中，所述势垒层与所述载流子沟道平行地延伸以完全交叠所述载流子沟道。
8.根据权利要求1所述的半导体器件，其中，所述势垒层与所述载流子沟道平行地延伸以仅部分地交叠所述载流子沟道。
9.根据权利要求1所述的半导体器件，其中，所述势垒层的厚度、掺杂浓度以及长度被选择成在所述半导体器件的击穿电压下完全耗尽所述载流子沟道中的电荷。
10.根据权利要求1所述的半导体器件，其中，所述半导体结构是包括III-V沟道层和III-V势垒层的半导体异质结构，使得所述载流子沟道是二维电子气2DEG沟道，其中，所述III-V势垒层的带隙大于所述III-V沟道层的带隙，其中，所述势垒层被完全或部分地p型掺杂，并且所述背势垒层所述材料具有比所述III-V沟道层的所述材料大的带隙和热导率。
11.根据权利要求10所述的半导体器件，其中，所述III-V沟道层的所述材料包括GaN或GaAs中的一种或组合，并且其中，所述III-V势垒层的所述材料包括氮化镓铝AlGaN、氮化镓铟InGaN、氮化镓铝铟InAlGaN、氮化铝AlN、砷化镓铝AlGaAs、砷化镓铟InGaAs、砷化镓铝铟InAlGaAs中的一种或组合。
12.一种半导体器件，该半导体器件包括：
半导体结构，该半导体结构形成载流子沟道，其中，所述半导体结构是包括III-V沟道层和III-V势垒层的半导体异质结构，使得所述载流子沟道是二维电子气2DEG沟道；
势垒层，该势垒层接近所述半导体结构设置，其中，所述势垒层至少部分地p型掺杂，其中，所述势垒层具有比所述III-V沟道层中的材料的带隙和热导率大的带隙和热导率；以及
一组电极，该组电极用于提供并控制所述载流子沟道中的载流子电荷。
13.根据权利要求12所述的半导体器件，其中，所述III-V沟道层的所述材料包括GaN或GaAs中的一种或组合，并且其中，所述III-V势垒层的所述材料包括氮化镓铝AlGaN、氮化镓铟InGaN、氮化镓铝铟InAlGaN、氮化铝AlN、砷化镓铝AlGaAs、砷化镓铟InGaAs、砷化镓铝铟InAlGaAs中的一种或组合。
14.根据权利要求12所述的半导体器件，其中，所述势垒层的所述p型掺杂剂包括硼和镁中的一种或组合。
15.根据权利要求12所述的半导体器件，其中，所述势垒层与所述III-V沟道层平行地延伸，以仅部分交叠所述III-V沟道层。
16.一种用于制造半导体器件的方法，该方法包括以下步骤：
提供衬底；
制造半导体结构，该半导体结构至少包括在所述半导体结构中形成载流子沟道的III-V沟道层；
接近所述半导体结构制造势垒层，其中，所述势垒层具有比所述III-V沟道层中的材料的带隙和热导率大的带隙和热导率；
用具有与所述载流子沟道相反的导电类型的杂质来掺杂所述势垒层；以及
形成与所述载流子沟道电接触的电极。
17.根据权利要求16所述的方法，所述方法还包括以下步骤：
与所述势垒层相邻地形成缓冲层。
18.根据权利要求16所述的方法，所述方法还包括以下步骤：
与所述III-V沟道层平行地设置所述势垒层，以部分地交叠所述III-V沟道层。
19.根据权利要求16所述的方法，其中，使用化学气相沉积CVD、金属有机化学气相沉积MOCVD、分子束外延MBE、金属有机气相外延MOVPE、等离子体增强化学气相沉积PECVD、以及微波等离子体沉积中的一种或组合来制造所述半导体结构和所述势垒层。
20.根据权利要求16所述的方法，其中，使用电子束物理气相沉积EBPVD、焦耳蒸发、化学气相沉积、以及溅射处理中的一种或组合来形成所述电极。
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108831922A (zh) * 2018-06-05 2018-11-16 大连芯冠科技有限公司 具有GaAs和GaN复合沟道的GaN HEMT器件及制备方法
JP2020027911A (ja) * 2018-08-16 2020-02-20 富士通株式会社 化合物半導体装置、化合物半導体装置の製造方法及び増幅器
CN112466944A (zh) * 2020-12-01 2021-03-09 西安电子科技大学 基于插指状p型掺杂金刚石的GaN HEMT及制备方法
CN113380877A (zh) * 2021-06-10 2021-09-10 四川美阔电子科技有限公司 一种双结型场板的功率器件
CN113939918A (zh) * 2019-06-18 2022-01-14 三菱电机株式会社 半导体装置及其制造方法

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102434697B1 (ko) * 2015-06-02 2022-08-22 삼성전자주식회사 2d 물질을 포함하는 광학소자 및 그 제조방법
US11430882B2 (en) * 2016-06-24 2022-08-30 Wolfspeed, Inc. Gallium nitride high-electron mobility transistors with p-type layers and process for making the same
US10192980B2 (en) 2016-06-24 2019-01-29 Cree, Inc. Gallium nitride high-electron mobility transistors with deep implanted p-type layers in silicon carbide substrates for power switching and radio frequency applications and process for making the same
US10892356B2 (en) 2016-06-24 2021-01-12 Cree, Inc. Group III-nitride high-electron mobility transistors with buried p-type layers and process for making the same
US10840334B2 (en) 2016-06-24 2020-11-17 Cree, Inc. Gallium nitride high-electron mobility transistors with deep implanted p-type layers in silicon carbide substrates for power switching and radio frequency applications and process for making the same
KR102651544B1 (ko) * 2016-11-21 2024-03-28 삼성전자주식회사 광대역 다기능 광학소자와 그 제조 및 동작방법
US10283931B2 (en) 2017-05-05 2019-05-07 International Business Machines Corporation Electro-optical device with III-V gain materials and integrated heat sink
JP6930229B2 (ja) * 2017-06-05 2021-09-01 富士通株式会社 半導体装置の製造方法
CN107731916B (zh) * 2017-10-12 2024-02-13 中国电子科技集团公司第十三研究所 半导体器件及利用异质结形成金刚石n型导电沟道的方法
US10418474B2 (en) * 2017-10-17 2019-09-17 Mitsubishi Electric Research Laboratories, Inc. High electron mobility transistor with varying semiconductor layer
US10886393B2 (en) * 2017-10-17 2021-01-05 Mitsubishi Electric Research Laboratories, Inc. High electron mobility transistor with tunable threshold voltage
US10644142B2 (en) * 2017-12-22 2020-05-05 Nxp Usa, Inc. Semiconductor devices with doped regions functioning as enhanced resistivity regions or diffusion barriers, and methods of fabrication therefor
US11552186B2 (en) * 2020-03-04 2023-01-10 Mitsubishi Electric Research Laboratoriesm Inc. Inverter based on electron interference
US11929428B2 (en) 2021-05-17 2024-03-12 Wolfspeed, Inc. Circuits and group III-nitride high-electron mobility transistors with buried p-type layers improving overload recovery and process for implementing the same
US20230141865A1 (en) * 2021-11-05 2023-05-11 Analog Devices, Inc. Lateral gallium nitride superjunction
CN117317000A (zh) * 2023-09-01 2023-12-29 中环领先半导体材料有限公司 一种高电子迁移率晶体管及其制备方法

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101136432A (zh) * 2006-09-01 2008-03-05 中国科学院半导体研究所 宽带隙氮化镓基异质结场效应晶体管结构及制作方法
JP2009071061A (ja) * 2007-09-13 2009-04-02 Toshiba Corp 半導体装置
US20090242873A1 (en) * 2008-03-28 2009-10-01 Ravi Pillarisetty Semiconductor heterostructures to reduce short channel effects
JP2012231002A (ja) * 2011-04-26 2012-11-22 Advanced Power Device Research Association 半導体装置
JP2012248753A (ja) * 2011-05-30 2012-12-13 Panasonic Corp スイッチ装置
US20130181224A1 (en) * 2009-09-15 2013-07-18 Fraunhofer-Gesellschaft Zur Foerderung Der Angewandten Forschung E.V. Semiconductor structure
CN103367422A (zh) * 2012-03-30 2013-10-23 富士通株式会社 化合物半导体器件及其制造方法
US20140110722A1 (en) * 2012-10-24 2014-04-24 The Government Of The United States Of America, As Represented By The Secretary Of The Navy Semiconductor Structure or Device Integrated with Diamond
CN104051519A (zh) * 2013-03-15 2014-09-17 三菱电机株式会社 器件、高电子迁移率晶体管及控制其工作的方法

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6100549A (en) 1998-08-12 2000-08-08 Motorola, Inc. High breakdown voltage resurf HFET
US6992319B2 (en) 2000-07-18 2006-01-31 Epitaxial Technologies Ultra-linear multi-channel field effect transistor
US6548333B2 (en) 2000-12-01 2003-04-15 Cree, Inc. Aluminum gallium nitride/gallium nitride high electron mobility transistors having a gate contact on a gallium nitride based cap segment
WO2003032397A2 (en) * 2001-07-24 2003-04-17 Cree, Inc. INSULTING GATE AlGaN/GaN HEMT
US7098490B2 (en) 2003-06-02 2006-08-29 Hrl Laboratories, Llc GaN DHFET
CN101155949A (zh) 2005-01-26 2008-04-02 阿波罗钻石公司 金刚石上的氮化镓发光装置
GB0505752D0 (en) 2005-03-21 2005-04-27 Element Six Ltd Diamond based substrate for gan devices
US7544963B2 (en) 2005-04-29 2009-06-09 Cree, Inc. Binary group III-nitride based high electron mobility transistors
US7339208B2 (en) 2005-05-13 2008-03-04 Coldwatt, Inc. Semiconductor device having multiple lateral channels and method of forming the same
US7709269B2 (en) * 2006-01-17 2010-05-04 Cree, Inc. Methods of fabricating transistors including dielectrically-supported gate electrodes
WO2008151138A1 (en) 2007-06-01 2008-12-11 The Regents Of The University Of California P-gan/algan/aln/gan enhancement-mode field effect transistor
US7915643B2 (en) 2007-09-17 2011-03-29 Transphorm Inc. Enhancement mode gallium nitride power devices
US7851857B2 (en) 2008-07-30 2010-12-14 Freescale Semiconductor, Inc. Dual current path LDMOSFET with graded PBL for ultra high voltage smart power applications
US7888171B2 (en) 2008-12-22 2011-02-15 Raytheon Company Fabricating a gallium nitride layer with diamond layers
US7892881B2 (en) 2009-02-23 2011-02-22 Raytheon Company Fabricating a device with a diamond layer
US8216924B2 (en) * 2009-10-16 2012-07-10 Cree, Inc. Methods of fabricating transistors using laser annealing of source/drain regions
US9257547B2 (en) * 2011-09-13 2016-02-09 Transphorm Inc. III-N device structures having a non-insulating substrate
EP2602827B1 (en) 2011-12-09 2016-02-03 Imec Enhancement mode III-nitride device and method for manufacturing thereof
US9009846B2 (en) 2012-02-01 2015-04-14 International Business Machines Corporation Virtual avatar authentication
US8575657B2 (en) 2012-03-20 2013-11-05 Northrop Grumman Systems Corporation Direct growth of diamond in backside vias for GaN HEMT devices
JP2013229449A (ja) * 2012-04-25 2013-11-07 Advanced Power Device Research Association 窒化物系半導体素子
US9035355B2 (en) 2012-06-18 2015-05-19 Infineon Technologies Austria Ag Multi-channel HEMT
KR101927411B1 (ko) 2012-09-28 2018-12-10 삼성전자주식회사 2ｄｅｇ와 2ｄｈｇ를 이용한 반도체 소자 및 제조방법
KR101922123B1 (ko) 2012-09-28 2018-11-26 삼성전자주식회사 반도체소자 및 그 제조방법
US8759879B1 (en) 2013-05-03 2014-06-24 Texas Instruments Incorporated RESURF III-nitride HEMTs

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101136432A (zh) * 2006-09-01 2008-03-05 中国科学院半导体研究所 宽带隙氮化镓基异质结场效应晶体管结构及制作方法
JP2009071061A (ja) * 2007-09-13 2009-04-02 Toshiba Corp 半導体装置
US20090242873A1 (en) * 2008-03-28 2009-10-01 Ravi Pillarisetty Semiconductor heterostructures to reduce short channel effects
US20130181224A1 (en) * 2009-09-15 2013-07-18 Fraunhofer-Gesellschaft Zur Foerderung Der Angewandten Forschung E.V. Semiconductor structure
JP2012231002A (ja) * 2011-04-26 2012-11-22 Advanced Power Device Research Association 半導体装置
JP2012248753A (ja) * 2011-05-30 2012-12-13 Panasonic Corp スイッチ装置
CN103367422A (zh) * 2012-03-30 2013-10-23 富士通株式会社 化合物半导体器件及其制造方法
US20140110722A1 (en) * 2012-10-24 2014-04-24 The Government Of The United States Of America, As Represented By The Secretary Of The Navy Semiconductor Structure or Device Integrated with Diamond
CN104051519A (zh) * 2013-03-15 2014-09-17 三菱电机株式会社 器件、高电子迁移率晶体管及控制其工作的方法

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108831922A (zh) * 2018-06-05 2018-11-16 大连芯冠科技有限公司 具有GaAs和GaN复合沟道的GaN HEMT器件及制备方法
CN108831922B (zh) * 2018-06-05 2021-05-18 大连芯冠科技有限公司 具有GaAs和GaN复合沟道的GaN HEMT器件及制备方法
JP2020027911A (ja) * 2018-08-16 2020-02-20 富士通株式会社 化合物半導体装置、化合物半導体装置の製造方法及び増幅器
JP7139774B2 (ja) 2018-08-16 2022-09-21 富士通株式会社 化合物半導体装置、化合物半導体装置の製造方法及び増幅器
CN113939918A (zh) * 2019-06-18 2022-01-14 三菱电机株式会社 半导体装置及其制造方法
CN112466944A (zh) * 2020-12-01 2021-03-09 西安电子科技大学 基于插指状p型掺杂金刚石的GaN HEMT及制备方法
CN113380877A (zh) * 2021-06-10 2021-09-10 四川美阔电子科技有限公司 一种双结型场板的功率器件

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