CN107731916B - 半导体器件及利用异质结形成金刚石n型导电沟道的方法 - Google Patents

半导体器件及利用异质结形成金刚石n型导电沟道的方法 Download PDF

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CN107731916B
CN107731916B CN201710948671.4A CN201710948671A CN107731916B CN 107731916 B CN107731916 B CN 107731916B CN 201710948671 A CN201710948671 A CN 201710948671A CN 107731916 B CN107731916 B CN 107731916B
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王晶晶
冯志红
蔚翠
周闯杰
刘庆彬
何泽召
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CETC 13 Research Institute
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Abstract

本发明公开了一种半导体器件及利用异质结形成金刚石n型导电沟道的方法，涉及半导体器件的制作方法技术领域。所述方法包括：在衬底上形成高阻金刚石层；在所述高阻金刚石层的上表面沉积具有施主特性且组分缓变的三元化合物形成第一施主层，在所述金刚石层与第一施主层的界面处形成一个缓变异质结，在金刚石一侧，近结处形成二维电子气，利用二维电子气作为n型导电沟道。所述方法可使n型金刚石材料沟道内的载流子浓度和迁移率分别达到1013cm‑2和2000cm2/Vs。

Description

半导体器件及利用异质结形成金刚石n型导电沟道的方法
技术领域
本发明涉及半导体器件的制作方法技术领域，尤其涉及一种半导体器件及利用异质结形成金刚石n型导电沟道的方法。
背景技术
金刚石作为一种宽禁带半导体材料具有高击穿场、耐辐照、高导热等诸多优良性能，以金刚石材料基础的器件统称为金刚石基器件，金刚石基器件具有工作温度高、击穿场强大、截止频率高、功率密度大等优点，是未来微波大功率器件、电力电子器件以及声表面波等器件的首选。金刚石禁带宽度大，原子结构紧密，目前尚不能进行有效的n型掺杂。现行的制作n型导电沟道的方法是元素掺杂方法，一般采用磷元素进行n型掺杂，这种掺杂的激活效率极低，在磷掺杂浓度为5×1017cm-3时，迁移率降为410cm2/Vs。
目前最好报道磷掺杂室温电子迁移率为780cm2/Vs（室温）。这远不能达到金刚石的理论值，发挥出材料本身的优异特性。在这种掺杂方式的基本物理机制为杂质电离释放多余载流子，而在低掺杂浓度下，杂质电离被强烈抑制，激活率极低，在高掺杂浓度下，引入掺杂还会导致较强的电离杂质散射，影响载流子迁移率，使载流子迁移率几乎降至0。这些使得金刚石材料的掺杂问题成为一个世界性的难题，n型掺杂问题不解决就不能形成有效的p-n结，这将极大的限制金刚石半导体器件的发展。因此，实现有效稳定的n沟道，是推进金刚石半导体材料走向应用的主要一步。
发明内容
本发明所要解决的技术问题是如何提供一种可使n型金刚石材料沟道内的载流子浓度和迁移率分别达到1013cm-2和2000cm2/Vs的方法。
为解决上述技术问题，本发明所采取的技术方案是：一种利用异质结形成金刚石n型导电沟道的方法，其特征在于包括如下步骤：
在衬底上形成高阻金刚石层；
在所述高阻金刚石层的上表面沉积具有施主特性且组分缓变的三元化合物形成第一施主层，在所述金刚石层与第一施主层的界面处形成一个缓变异质结，在金刚石一侧，近结处形成二维电子气，利用二维电子气作为n型导电沟道。
进一步的技术方案在于：所述方法还包括：在所述第一施主层的上表面沉积具有施主特性的二元化合物或者单质形成第二补偿施主层，为所述缓变异质结中的第一施主层提供补偿电子。
进一步的技术方案在于：所述方法还包括：在第一施主层与高阻金刚石层之间形成外延金刚石层的步骤。
进一步的技术方案在于：所述有施主特性且组分缓变的三元化合物包括：MgxGayNz、SixByNz、MgxAlyNz、FexAlyNz、MgxGayOz、FexAlyOz、ZnxAlyOz、ZnxMgyOz、MgxGayFz、FexAlyFz、ZnxAlyFz或ZnxMgyFz，其中上述三元化合物的化学式中，从左到右为第一至第三种元素，使用第一种元素替代部分第二种元素，使第一种元素的组分逐渐减少，而第二种元素的组分逐渐增加，上述三元化合物中x+y=a，a为一定值，a和z的值分别与三元化合物中第二种元素以及第三种元素的化合价有关。
进一步的技术方案在于：所述单质包括：锂Li、钠Na、钙Ga、镁Mg、钾K、硅Si、锗Ge、锌Zn或铁Fe；所述二元化合物包括：BxNy、GaxNy 、AlxNy、SixNy，BxNy、FexNy氮化物、GaxOy 、AlxOy、SixOy、ZnxOy或FexOy，其中上述二元化合物的化学式中，从左到右为第一至第二种元素，x和y的值分别与二元化合物中第一种元素以及第二种元素的化合价有关。
本发明还公开了一种半导体器件，其特征在于：包括衬底，所述衬底的上表面设有高阻金刚石层，所述金刚石层的上表面设有具有施主特性且组分缓变的三元化合物形成的第一施主层，在所述金刚石层与第一施主层的界面处形成一个缓变异质结，在金刚石一侧，近结处形成二维电子气，利用二维电子气作为n型导电沟道。
进一步的技术方案在于：所述第一施主层的上表面设有具有施主特性的二元化合物或者单质形成的第二补偿施主层，第二补偿施主层用于为所述缓变异质结中的第一施主层提供补偿电子。
进一步的技术方案在于：所述第一施主层和第二补偿施主层的厚度为1nm-100μm。
进一步的技术方案在于：所述具有施主特性且组分缓变的三元化合物包括：MgxGayNz、SixByNz、MgxAlyNz、FexAlyNz、MgxGayOz、FexAlyOz、ZnxAlyOz、ZnxMgyOz、MgxGayFz、FexAlyFz、ZnxAlyFz或ZnxMgyFz，其中上述三元化合物的化学式中，从左到右为第一至第三种元素，使用第一种元素替代部分第二种元素，使第一种元素的组分逐渐减少，而第二种元素的组分逐渐增加，上述三元化合物中x+y=a，a为一定值，a和z的值分别与三元化合物中第二种元素以及第三种元素的化合价有关。
进一步的技术方案在于：所述单质包括：锂Li、钠Na、钙Ga、镁Mg、钾K、硅Si、锗Ge、锌Zn或铁Fe；所述二元化合物包括：GaxNy、BxNy、AlxNy、SixNy，BxNy、FexNy氮化物、GaxOy 、AlxOy、SixOy、ZnxOy或FexOy，其中上述二元化合物的化学式中，从左到右为第一至第二种元素，x和y的值分别与二元化合物中第一种元素以及第二种元素的化合价有关。
采用上述技术方案所产生的有益效果在于：本发明所述方法利用金刚石材料表面极性键与第一施主层之间的极化作用，产生二维电子气，使载流子与施主原子相分离，不会受到散射的影响而降低迁移率，同时又利用第二补偿施主层来为第一施主层中的组分源源不断的补偿电子，来实现高迁移率和高载流子浓度的n型沟道。相较于传统的掺杂形式，这种由极化导致的掺杂形式具有较高的体迁移率和稳定的掺杂效率的先天优势，可使n型金刚石材料沟道内的载流子浓度和迁移率分别达到1013cm-2和2000cm2/Vs。
附图说明
图1是本发明实施例一所述方法的流程图；
图2是本发明实施例一所述半导体器件的结构示意图；
图3是本发明实施例一所述方法的流程图；
图4是本发明实施例一所述半导体器件的结构示意图；
图5是本发明实施例二所述方法的流程图；
图6是本发明实施例二所述半导体器件的结构示意图；
图7是本发明实施例所述半导体器件的能带原理图：
其中：1、衬底2、高阻金刚石层3、第一施主层4、二维电子气5、第二补偿施主层6、外延金刚石层7、金刚石层与第一施主层的界面。
具体实施方式
下面结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明的一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
在下面的描述中阐述了很多具体细节以便于充分理解本发明，但是本发明还可以采用其他不同于在此描述的其它方式来实施，本领域技术人员可以在不违背本发明内涵的情况下做类似推广，因此本发明不受下面公开的具体实施例的限制。
实施例一
总体的，如图1所示，本发明公开了一种利用异质结形成金刚石n型导电沟道的方法，包括如下步骤：
S101：在衬底1上形成高阻金刚石层2；
S102：在所述高阻金刚石层2的上表面形成外延金刚石层6；
S103：在所述外延金刚石层6的上表面沉积具有施主特性且组分缓变的三元化合物形成第一施主层3，在所述金刚石层与第一施主层3的界面处形成一个缓变异质结，在金刚石一侧，近结处形成二维电子气4，利用二维电子气4作为n型导电沟道；
S104：在所述第一施主层3的上表面沉积具有施主特性的二元化合物或者单质形成第二补偿施主层5，为所述缓变异质结中的第一施主层3提供补偿电子。
通过上述方法制作了一种半导体器件，如图2所示，包括衬底1，所述衬底1的上表面设有高阻金刚石层2，所述金刚石层的上表面设有外延金刚石层6，外延金刚石层6的上表面设有具有施主特性且组分缓变的三元化合物形成第一施主层3，在所述金刚石层与第一施主层3的界面处形成一个缓变异质结，在金刚石一侧，近结处形成二维电子气4，利用二维电子气4作为p型导电沟道；所述第一施主层3的上表面设有具有施主特性的二元化合物或者单质形成的第二补偿施主层5，第二补偿施主层5用于为所述缓变异质结中的第一施主层3提供补偿电子。
优选的，可利用现有技术中的任意一种方法获得高阻金刚石层2。优选的，所述第一施主层3包括：MgxGayNz、SixByNz、MgxAlyNz、FexAlyNz、MgxGayOz、FexAlyOz、ZnxAlyOz、ZnxMgyOz、MgxGayFz、FexAlyFz、ZnxAlyFz、ZnxMgyFz等任意与金刚石接触可以产生施主特性的氮化物、氧化物、氟化物的三元化合物。其中上述三元化合物的化学式中，从左到右为第一至第三种元素，使用第一种元素替代部分第二种元素，使第一种元素的组分逐渐减少，而第二种元素的组分逐渐增加，上述三元化合物中x+y=a，a为一定值，a和z的值分别与三元化合物中第二种元素以及第三种元素的化合价有关。
优选的，所述第二补偿施主层5中，单质包括：锂（Li）、钠（Na）钙（Ga）、镁(Mg)、钾(K)、硅（Si）、锗(Ge)锌（Zn）、铁(Fe) 等与金刚石接触可以产生施主特性的任意单质；化合物包括与金刚石接触可以产生施主特性的：BxNy、GaxNy 、AlxNy、SixNy，BxNy、FexNy等氮化物；或GaxOy 、AlxOy、SixOy、ZnxOy、FexOy等氧化物；或ZnxFy、GaxFy 、AlxFy、SixFy，BxFy等氟化物。其中上述二元化合物的化学式中，从左到右为第一至第二种元素，x和y的值分别与二元化合物中第一种元素以及第二种元素的化合价有关。优选的，所述第一施主层和第二补偿施主层的厚度为1nm-100μm。需要说明的是，所述第一施主层和第二补偿施主层的厚度比不局限于上述具体数值。
本发明所述方法利用金刚石材料表面极性键与第一施主层之间的极化作用，产生二维电子气，使载流子与施主原子相分离，不会受到散射的影响而降低迁移率，同时又利用第二补偿施主层来为第一施主层中的组分源源不断的补偿电子，来实现高迁移率和高载流子浓度的n型沟道。相较于传统的掺杂形式，这种由极化导致的掺杂形式具有较高的体迁移率和稳定的掺杂效率的先天优势，可使n型金刚石材料沟道内的载流子浓度和迁移率分别达到1013cm-2和2000cm2/Vs。图7是本发明实施例所述半导体器件的能带原理图。图7中所述界面的左侧为第一施主层，所述界面的右侧为金刚石，/>为导带底，/>为费米能级，/>为价带顶。
实施例二：
如图3所示，本发明公开了一种利用异质结形成金刚石n型导电沟道的方法，包括如下步骤：
S101：在钼衬底上利用MPCVD方法生长高阻金刚石层2，高阻金刚石层2的厚度为300μm；
S102：将步骤S101处理后的器件置于MPCVD设备中，抽真空至10-8mbar，然后通入CH4和H2的混合气，其中CH4流量为1000mL/min，H2流量为20L/min，反应室压力100mbar，生长时间5小时，沉积500nm高质量的外延金刚石层6；
S103：取出样品后，在原子层淀积设备中常温淀积20 nm的MgAlN第一施主层3，形成金刚石-MgAlN异质结。
S104：原位沉积1μm的AlN 第二补偿施主层5，为金刚石-MgAlN异质结补偿提供电子；
S105：取出样品后，制作电极，利用霍尔测试系统测试异质结结构的导电特性，样品为n型，载流子迁移率1500cm2/Vs。
如图4所示，本发明公开了一种半导体器件，包括钼衬底1，所述钼衬底1的上表面设有高阻金刚石层2，所述高阻金刚石层2的上表面设有外延金刚石层6，所述外延金刚石层6的上表面设有MgAlN第一施主层3，MgAlN第一施主层3的上表面设有AlN 第二补偿施主层5。
实施例三：
如图5所示，本发明公开了一种利用异质结形成金刚石n型导电沟道的方法，包括如下步骤：
S201：对衬底1的上表面进行抛光处理，抛至表面粗糙度0.5nm，所述衬底使用高阻金刚石；
S202：将步骤S201处理后得到的金刚石置于MPCVD设备中，利用氢等离子体将金刚石处理为氢终端金刚石，材料表面为C-H键；
S203：取出样品后，在CVD设备中，600℃温度下沉积50 nm的FeAlO第一施主层3，形成金刚石-FeAlO异质结；
S204：取出样品后，制作电极，利用霍尔测试系统测试异质结结构的导电特性，样品为n型，载流子迁移率2000cm2/Vs。
如图6所示，本发明公开了一种半导体器件，包括高阻金刚石衬底1，所述高阻金刚石衬底1的上表面为C-H键，所述衬底1的上表面设有FeAlO第一施主层3。
本发明所述方法利用缓变势垒的第一施主层与金刚石表面形成异质结，利用晶格畸变和极性分子的相互作用在界面处形成导带带阶的突变，电子被从缓变势垒施主层激发，在异质结界面处金刚石侧出现大量的呈准二维分布的自由电子，形成二维电子气。二维电子气被限制在界面处很薄的一层中，并且和电离杂质散射中心在物理位置上分离，从而能够获得非常高的迁移率。

Claims (6)

1.一种利用异质结形成金刚石n型导电沟道的方法，其特征在于包括如下步骤：
在衬底(1)上形成高阻金刚石层(2)；在所述高阻金刚石层(2)的上表面沉积具有施主特性且组分缓变的三元化合物形成第一施主层(3)，在所述金刚石层(2)与第一施主层(3)的界面处形成一个缓变异质结，在金刚石一侧，近结处形成二维电子气(4)，利用二维电子气作为n型导电沟道；
在所述第一施主层(3)的上表面沉积具有施主特性的二元化合物或者单质形成第二补偿施主层(5)，为所述缓变异质结中的第一施主层(3)提供补偿电子；
所述有施主特性且组分缓变的三元化合物包括：MgxGayNz、SixByNz、MgxAlyNz、FexAlyNz、MgxGayOz、FexAlyOz、ZnxAlyOz、ZnxMgyOz、MgxGayFz、FexAlyFz、ZnxAlyFz或ZnxMgyFz，其中上述三元化合物的化学式中，从左到右为第一至第三种元素，使用第一种元素替代部分第二种元素，使第一种元素的组分逐渐减少，而第二种元素的组分逐渐增加，上述三元化合物中x+y＝a，a为一定值，a和z的值分别与三元化合物中第二种元素以及第三种元素的化合价有关。
2.如权利要求1所述的利用异质结形成金刚石n型导电沟道的方法，其特征在于所述方法还包括：在第一施主层(3)与高阻金刚石层(2)之间形成外延金刚石层(6)的步骤。
3.如权利要求1所述的利用异质结形成金刚石n型导电沟道的方法，其特征在于：所述单质包括：锂Li、钠Na、钙Ga、镁Mg、钾K、硅Si、锗Ge、锌Zn或铁Fe；所述二元化合物包括：BxNy、GaxNy、AlxNy、SixNy，BxNy、FexNy氮化物、GaxOy、AlxOy、SixOy、ZnxOy或FexOy，其中上述二元化合物的化学式中，从左到右为第一至第二种元素，x和y的值分别与二元化合物中第一种元素以及第二种元素的化合价有关。
4.一种半导体器件，其特征在于：包括衬底(1)，所述衬底(1)的上表面设有高阻金刚石层(2)，所述金刚石层(2)的上表面设有具有施主特性且组分缓变的三元化合物形成的第一施主层(3)，在所述金刚石层与第一施主层(3)的界面处形成一个缓变异质结，在金刚石一侧，近结处形成二维电子气(4)，利用二维电子气(4)作为n型导电沟道；
所述第一施主层(3)的上表面设有具有施主特性的二元化合物或者单质形成的第二补偿施主层(5)，第二补偿施主层(5)用于为所述缓变异质结中的第一施主层(3)提供补偿电子；
所述具有施主特性且组分缓变的三元化合物包括：MgxGayNz、SixByNz、MgxAlyNz、FexAlyNz、MgxGayOz、FexAlyOz、ZnxAlyOz、ZnxMgyOz、MgxGayFz、FexAlyFz、ZnxAlyFz或ZnxMgyFz，其中上述三元化合物的化学式中，从左到右为第一至第三种元素，使用第一种元素替代部分第二种元素，使第一种元素的组分逐渐减少，而第二种元素的组分逐渐增加，上述三元化合物中x+y＝a，a为一定值，a和z的值分别与三元化合物中第二种元素以及第三种元素的化合价有关。
5.如权利要求4所述的半导体器件，其特征在于：所述第一施主层(3)和第二补偿施主层(5)的厚度为1nm-100μm。
6.如权利要求4所述的半导体器件，其特征在于：所述单质包括：锂Li、钠Na、钙Ga、镁Mg、钾K、硅Si、锗Ge、锌Zn或铁Fe；所述二元化合物包括：GaxNy、BxNy、AlxNy、SixNy，BxNy、FexNy氮化物、GaxOy、AlxOy、SixOy、ZnxOy或FexOy，其中上述二元化合物的化学式中，从左到右为第一至第二种元素，x和y的值分别与二元化合物中第一种元素以及第二种元素的化合价有关。
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008186936A (ja) * 2007-01-29 2008-08-14 Nec Corp 電界効果トランジスタ
CN102376817A (zh) * 2010-08-11 2012-03-14 王浩 一种半导体光电器件的制备方法
CN207217545U (zh) * 2017-10-12 2018-04-10 中国电子科技集团公司第十三研究所 一种具有n型导电沟道的半导体器件

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02202029A (ja) * 1989-01-31 1990-08-10 Sony Corp 化合物半導体装置
JP2786327B2 (ja) * 1990-10-25 1998-08-13 三菱電機株式会社 ヘテロ接合電界効果トランジスタ
US5274255A (en) * 1991-08-30 1993-12-28 Houssaye Paul De Structure for providing high resolution modulation of voltage potential in the vicinity of a surface
US7339205B2 (en) * 2004-06-28 2008-03-04 Nitronex Corporation Gallium nitride materials and methods associated with the same
GB0508889D0 (en) * 2005-04-29 2005-06-08 Element Six Ltd Diamond transistor and method of manufacture thereof
US7557378B2 (en) * 2006-11-08 2009-07-07 Raytheon Company Boron aluminum nitride diamond heterostructure
JP5672868B2 (ja) * 2010-08-31 2015-02-18 富士通株式会社 化合物半導体装置及びその製造方法
DE112014004277T5 (de) * 2013-09-18 2016-06-16 Suzhou Institute Of Nano-Tech And Nano-Bionics (Sinano), Chinese Academy Of Sciences Terahertz-Lichtquellenchip, Lichtquellenvorrichtung, Lichtquellenanordnung und ihr Herstellungsverfahren
WO2016085890A1 (en) * 2014-11-24 2016-06-02 Innosys, Inc. Gallium nitride growth on silicon
US9419121B1 (en) * 2015-07-17 2016-08-16 Mitsubishi Electric Research Laboratories, Inc. Semiconductor device with multiple carrier channels
US9583607B2 (en) * 2015-07-17 2017-02-28 Mitsubishi Electric Research Laboratories, Inc. Semiconductor device with multiple-functional barrier layer
US9806182B2 (en) * 2015-09-08 2017-10-31 Macom Technology Solutions Holdings, Inc. Parasitic channel mitigation using elemental diboride diffusion barrier regions
US9673281B2 (en) * 2015-09-08 2017-06-06 Macom Technology Solutions Holdings, Inc. Parasitic channel mitigation using rare-earth oxide and/or rare-earth nitride diffusion barrier regions
JP6623691B2 (ja) * 2015-10-30 2019-12-25 富士通株式会社 化合物半導体装置及びその製造方法
US10381310B2 (en) * 2017-03-13 2019-08-13 Intel Corporation Embedded multi-die interconnect bridge

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008186936A (ja) * 2007-01-29 2008-08-14 Nec Corp 電界効果トランジスタ
CN102376817A (zh) * 2010-08-11 2012-03-14 王浩 一种半导体光电器件的制备方法
CN207217545U (zh) * 2017-10-12 2018-04-10 中国电子科技集团公司第十三研究所 一种具有n型导电沟道的半导体器件

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