WO2017107295A1 - 适用于In Cell型触控显示面板的的GOA电路 - Google Patents

适用于In Cell型触控显示面板的的GOA电路 Download PDF

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Publication number
WO2017107295A1
WO2017107295A1 PCT/CN2016/072850 CN2016072850W WO2017107295A1 WO 2017107295 A1 WO2017107295 A1 WO 2017107295A1 CN 2016072850 W CN2016072850 W CN 2016072850W WO 2017107295 A1 WO2017107295 A1 WO 2017107295A1
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Prior art keywords
thin film
film transistor
type thin
gate
electrically connected
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Ceased
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PCT/CN2016/072850
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English (en)
French (fr)
Inventor
陈彩琴
赵莽
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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Priority to US14/917,568 priority Critical patent/US9934745B2/en
Publication of WO2017107295A1 publication Critical patent/WO2017107295A1/zh
Anticipated expiration legal-status Critical
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    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G06F3/04166—Details of scanning methods, e.g. sampling time, grouping of sub areas or time sharing with display driving
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3659—Control of matrices with row and column drivers using an active matrix the addressing of the pixel involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependant on signal of two data electrodes
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    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
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    • G11—INFORMATION STORAGE
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/13338—Input devices, e.g. touch panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0283—Arrangement of drivers for different directions of scanning
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
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    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
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    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
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    • G09G2310/0291—Details of output amplifiers or buffers arranged for use in a driving circuit
    • G—PHYSICS
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
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    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2354/00—Aspects of interface with display user

Definitions

  • the present invention relates to the field of touch display technologies, and in particular, to a GOA circuit suitable for an In Cell type touch display panel.
  • GOA Gate Driver on Array
  • TFT Thin Film Transistor
  • the driving method has the advantages of reducing production cost and realizing the narrow frame design of the panel, and is used for various displays.
  • the GOA circuit has two basic functions: the first is to output the scan drive signal, drive the gate line in the panel, open the TFT in the display area to charge the pixel; the second is the shift register function, when a scan drive signal After the output is completed, the output of the next scan drive signal is output by clock control, and is sequentially transmitted.
  • the embedded touch technology integrates the touch panel and the liquid crystal panel into one body, and embeds the touch panel function into the liquid crystal panel, so that the liquid crystal panel has the functions of displaying and sensing the touch input at the same time.
  • touch display panels have been widely accepted and used by people, such as smart phones, tablets, etc., using touch display panels.
  • the existing embedded touch technology is mainly divided into two types: one is that the touch circuit is on the cell type (On Cell), and the other is that the touch circuit is in the cell type (In Cell).
  • the In cell type touch display panel of the prior art realizes the function of the touch detection after the normal display period of each frame, that is, the touch scan signal is in each level of the GOA unit of the GOA circuit.
  • the touch detection is performed.
  • FIG. 1 shows a conventional GOA circuit suitable for an In Cell type touch display panel, comprising: a cascaded multi-level GOA unit, each level of the GOA unit includes: a forward and reverse scan control module 100, and control The input module 200, the reset module 300, the latch module 400, the NAND gate signal processing module 500, and the output buffer module 600.
  • the forward/reverse scan control module 100 is configured to select the level transmission signals of the upper and lower stages to implement forward or reverse scan driving.
  • the control input module 200 is used for input control of a level transmission signal to implement charging of the first node Q(N).
  • the reset module 300 is configured to perform a zeroing process on the first node Q(N).
  • the latch module 400 is configured to latch a level transfer signal.
  • the NAND gate signal The processing module 500 is configured to perform NAND processing on the latched level transfer signal and the clock signal to generate a gate scan driving signal of the current stage; the output buffer module 600 includes an odd number of series connected inverters for increasing the gate The drive capability of the pole scan drive signal reduces the RC loading.
  • N be a positive integer, in addition to the first-level GOA unit and the last-level GOA unit, in the N-th GOA unit:
  • the forward and reverse scan control module 100 includes: a first transmission gate TG1, a low potential control end of the first transmission gate TG1 is connected to the first DC control signal U2D, and a high potential control terminal is connected to the second DC control signal. D2U, the input end is electrically connected to the first node Q(N-1) of the upper N-1th GOA unit, the output end is electrically connected to the input end of the first clocked inverter TF1; and the second The transmission gate TG2, the high-potential control terminal of the second transmission gate TG2 is connected to the first DC control signal U2D, the low-potential control terminal is connected to the second DC control signal D2U, and the input terminal is electrically connected to the next-stage Nth a first node Q(N+1) of the +1 level GOA unit, the output end is electrically connected to the input end of the first clocked inverter TF1; the first node Q (N-1 of the N-1th GOA unit) a potential as a forward scan level
  • the control input module 200 includes: a first clocked inverter TF1, the high potential control terminal of the first clocked inverter TF1 is electrically connected to the Mth clock signal CK(M), and the low potential control terminal Electrically connected to the Mth inverted clock signal XCK (M), the output is electrically connected to the second node P (N);
  • the reset module 300 includes: a first P-type thin film transistor T1, a gate of the first P-type thin film transistor T1 is connected to a reset signal Reset, a source is connected to a constant voltage high potential VGH, and a drain is electrically connected to the first Two nodes P(N);
  • the latch module 400 includes a second clocked inverter TF2, and the low potential control terminal of the second clocked inverter TF2 is electrically connected to the Mth clock signal CK(M), and the high potential control terminal Electrically connected to the Mth inverted clock signal XCK(M), the input end is electrically connected to the first node Q(N), the output end is electrically connected to the second node P(N); and the first inverter IN1, the input end of the first inverter IN1 is electrically connected to the second node P (N), the output end is electrically connected to the first node Q (N);
  • the NAND gate signal processing module 500 includes: a NAND gate NAND, the first input terminal of the NAND gate NAND is electrically connected to the first node Q(N), and the second input terminal is connected to the M+2 gate. a clock signal, the output end is electrically connected to the input end of the second inverter IN2;
  • the output buffer module 600 includes: a second inverter IN2, an output end of the second inverter IN2 is electrically connected to an input end of the third inverter IN3; a third inverter IN3, the first The output of the three inverter IN3 is electrically connected to the input end of the fourth inverter IN4; and the fourth inversion The output terminal of the fourth inverter IN4 is electrically connected to the gate scan driving signal output terminal Gate(N).
  • the working process of the above-mentioned existing GOA circuit suitable for the In Cell type touch display panel in the normal display stage is as follows: taking the forward scan as an example, when the first node Q(N-1) of the N-1th GOA unit When the potential is high, the Mth clock signal CK(M) provides a high potential, the first node Q(N) is charged to a high level; when the Mth clock signal CK(M) is turned to a low potential, the first The potential of the node Q(N) is latched by the latch module 400; when the high potential of the M+2th clock signal CK(M+2) comes, the gate scan driving signal output terminal Gate(N) outputs a high potential; When the M+2 clock signal CK(M+2) transitions to a low potential, the gate scan driving signal output terminal Gate(N) stably outputs a low potential.
  • the touch scanning phase all signal lines are superimposed with a pulse that changes in accordance with the touch drive signal.
  • the touch scan is performed, and the gate scan drive signal output terminal Gate(N) is connected to the constant voltage low potential, and the constant voltage low potential changes with the jump of the touch drive signal.
  • the gate scan driving signal also changes as the touch drive signal changes.
  • the working mode of the touch scanning panel requires waveform processing of the gate scanning driving signal through an integrated circuit (IC) in the touch scanning stage, resulting in a large load of the IC.
  • IC integrated circuit
  • An object of the present invention is to provide a GOA circuit suitable for an In Cell type touch display panel, which can reduce the load on the signal processing of the IC during the touch scanning phase and improve the working efficiency of the GOA circuit.
  • the present invention provides a GOA circuit suitable for an In Cell type touch display panel, comprising: a cascaded multi-level GOA unit, each level of the GOA unit includes: a forward and reverse scanning control module, and a control An input module, a reset module, a latch module, a NAND gate signal processing module, and an output buffer module;
  • N be a positive integer, in addition to the first-level GOA unit and the last-level GOA unit, in the N-th GOA unit:
  • the forward/reverse scan control module includes: a first transmission gate, a low potential control end of the first transmission gate is connected to a first DC control signal, and a high potential control terminal is connected to a second DC control signal, and the input terminal is electrically Connected to the first node of the upper N-1th GOA unit, the output is electrically connected to the control input module; and the second transmission gate, the high potential control end of the second transmission gate is connected to the first DC a control signal, the low potential control end is connected to the second DC control signal, the input end is electrically connected to the first node of the next N+1th GOA unit, and the output end is electrically connected to the control input module;
  • the potential of the first node of the N-1th GOA unit is used as a forward scan level transmission signal
  • the potential of the first node of the (N+1)th GOA unit is used as a reverse scan level transmission signal
  • a reverse scan level transmission signal a reverse scan level transmission signal
  • the control input module includes: a first clock control inverter, the high potential control end of the first clock control inverter is connected to the Mth clock signal, and the low potential control end is connected to the Mth inverted clock signal
  • the input end is electrically connected to the output end of the first transmission gate and the output end of the second transmission gate, and the output end is electrically connected to the second node;
  • the reset module includes: an eleventh P-type thin film transistor, a gate of the eleventh P-type thin film transistor is connected to a reset signal, a source is connected to a constant voltage high potential, and a drain is electrically connected to the second node;
  • the latch module includes: a second clock control inverter, the low potential control end of the second clock control inverter is connected to the Mth clock signal, and the high potential control terminal is connected to the Mth inverted clock signal
  • the input end is electrically connected to the first node
  • the output end is electrically connected to the second node
  • the first inverter the input end of the first inverter is electrically connected to the second node, and the output end is electrically Connected to the first node;
  • the NAND gate signal processing module includes: a NAND gate, the first input end of the NAND gate is electrically connected to the first node, the second input end is connected to the M+2 clock signal, and the output end is electrically Connect the output buffer module;
  • the output buffer module includes:
  • a second inverter composed of a seventh P-type thin film transistor and an eighth N-type thin film transistor; a gate of the seventh P-type thin film transistor is electrically connected to a gate of the eighth N-type thin film transistor as a second reverse
  • the input end of the phase device is electrically connected to the output end of the NAND gate, and the drain of the seventh P-type thin film transistor is electrically connected to the drain of the eighth N-type thin film transistor as the output end of the second inverter
  • the source of the seventh P-type thin film transistor is electrically connected to a constant voltage high potential, and the source of the eighth N-type thin film transistor is connected to a constant voltage low potential;
  • a third transmission gate formed by the second P-type thin film transistor and the third N-type thin film transistor; the gate of the second P-type thin film transistor is used as a low-potential control terminal of the third transmission gate to access the touch control signal
  • the gate of the third N-type thin film transistor is used as a high potential control terminal of the third transmission gate to receive an inverted touch control signal, and the source of the second P-type thin film transistor and the source of the third N-type thin film transistor Electrically connected, the drain of the second P-type thin film transistor is electrically connected to the drain of the third N-type thin film transistor, respectively as an input end and an output end of the third transfer gate;
  • the gate of the sixth P-type thin film crystal is electrically connected to the output end of the second inverter, the source is connected to a constant voltage high potential, and the drain is electrically connected to the second P type a drain of the thin film transistor, a drain of the third N-type thin film transistor, and a gate of the ninth P-type thin film transistor;
  • the gate of the first P-type thin film transistor is connected to the reverse touch a control signal, the source is connected to the constant voltage high potential, and the drain is electrically connected to the drain of the second P-type thin film transistor, the drain of the third N-type thin film transistor, and the gate of the ninth P-type thin film transistor;
  • a fourth N-type thin film transistor the gate of the fourth N-type thin film transistor is connected to the touch control signal, the source is connected to the constant voltage low potential, and the drain is electrically connected to the source of the second P-type thin film transistor, a source of the third N-type thin film transistor and a gate of the tenth N-type thin film transistor;
  • the gate of the fifth N-type thin film transistor is electrically connected to the output end of the second inverter, the source is connected to the constant voltage low potential, and the drain is electrically connected to the second P type a source of the thin film transistor, a source of the third N-type thin film transistor, and a gate of the tenth N-type thin film transistor;
  • a ninth P-type thin film transistor a source of the ninth P-type thin film transistor is connected to a constant voltage high potential, and a drain is electrically connected to a gate scan driving signal output end;
  • the source of the tenth N-type thin film transistor is connected to a constant voltage low potential, and the drain is electrically connected to the gate scan driving signal output end;
  • the first DC control signal is opposite to the potential of the second DC control signal
  • the touch control signal In the normal display phase, the touch control signal is low, the reverse touch control signal is high, and the touch scan drive signal provides a low potential; during the touch scan phase, the touch control signal is high.
  • the reverse touch control signal is low, and the touch scan drive signal provides a periodic pulse signal.
  • the output of the gate scan drive signal is suspended, and the output gate scan drive signal is in a high impedance state, following the touch scan drive signal. The same high and low potential transitions occur when the high and low potentials jump.
  • the input of the first transmission gate is connected to the start signal of the circuit.
  • the input of the second transmission gate is connected to the start signal of the circuit.
  • the first inverter includes: an N-type thin film transistor and a P-type thin film transistor, wherein a gate of the N-type thin film transistor is electrically connected to a gate of the P-type thin film transistor as an input terminal, and an N-type thin film transistor The drain is electrically connected to the drain of the P-type thin film transistor as an output terminal, the source of the N-type thin film transistor is connected to a constant voltage low potential, and the source of the P-type thin film transistor is connected to a constant voltage high potential.
  • the first and second clocked inverters each include: two series-connected N-type thin film transistors and two series-connected P-type thin film transistors, wherein the gate of one P-type thin film transistor serves as a low potential control of the clocked inverter
  • the source is connected to a constant voltage high potential, and the drain is electrically connected to the source of another P-type thin film transistor; an N-type thin film transistor gate is used as a high potential control terminal of the clocked inverter, and the source is connected.
  • the drain is electrically connected to another N-type thin film crystal
  • the source of the tube the gate of the other N-type thin film transistor is electrically connected to the gate of the other P-type thin film transistor as the input terminal of the clocked inverter, and the drain of the other N-type thin film transistor is connected to the other P
  • the drain of the thin film transistor is electrically connected as the output of the clocked inverter.
  • the first and second transmission gates each include: an N-type thin film transistor and a P-type thin film transistor disposed oppositely, the gate of the N-type thin film transistor serves as a high potential control terminal of the transmission gate, and the P-type film
  • the gate of the transistor serves as a low potential control terminal of the transfer gate, and the source of the N-type thin film transistor is electrically connected to the source of the P-type thin film transistor as an input terminal of the transfer gate, and the drain of the N-type thin film transistor and the P-type thin film transistor The drain is electrically connected as the output of the transmission gate.
  • the NAND gate includes: two N-type thin film transistors connected in series and two P-type thin film transistors disposed opposite to each other, wherein a gate of the first P-type thin film transistor is electrically connected to a gate of the first N-type thin film transistor as a first input end of the NAND gate, a gate of the second P-type thin film transistor and a gate of the second N-type thin film transistor are electrically connected as a second input terminal of the NAND gate, and two P-type thin film transistors
  • the source is connected to a constant voltage high potential, and the drains of the two P-type thin film transistors are electrically connected to the drain of the first N-type thin film transistor as an output terminal of the NAND gate, the first N-type thin film transistor
  • the source is electrically connected to the drain of the second N-type thin film transistor, and the source of the second N-type thin film transistor is connected to the constant voltage low potential.
  • the invention also provides a GOA circuit suitable for an In Cell type touch display panel, comprising: a cascaded multi-level GOA unit, each stage GOA unit comprises: a forward and reverse scan control module, a control input module, a reset module , a latch module, a NAND gate signal processing module, and an output buffer module;
  • N be a positive integer, in addition to the first-level GOA unit and the last-level GOA unit, in the N-th GOA unit:
  • the forward/reverse scan control module includes: a first transmission gate, a low potential control end of the first transmission gate is connected to a first DC control signal, and a high potential control terminal is connected to a second DC control signal, and the input terminal is electrically Connected to the first node of the upper N-1th GOA unit, the output is electrically connected to the control input module; and the second transmission gate, the high potential control end of the second transmission gate is connected to the first DC
  • the control signal, the low potential control end is connected to the second DC control signal, the input end is electrically connected to the first node of the next N+1th GOA unit, and the output end is electrically connected to the control input module;
  • the N-1 level The potential of the first node of the GOA unit is used as a forward scan level transmission signal, and the potential of the first node of the N+1th GOA unit is used as a reverse scan level transmission signal;
  • the control input module includes: a first clock control inverter, the first clock control is reversed
  • the high potential control end of the phase device is connected to the Mth clock signal, and the low potential control end is connected to the Mth inverted clock signal, and the input end is electrically connected to the output end of the first transmission gate and the output end of the second transmission gate.
  • the output is electrically connected to the second node;
  • the reset module includes: an eleventh P-type thin film transistor, a gate of the eleventh P-type thin film transistor is connected to a reset signal, a source is connected to a constant voltage high potential, and a drain is electrically connected to the second node;
  • the latch module includes: a second clock control inverter, the low potential control end of the second clock control inverter is connected to the Mth clock signal, and the high potential control terminal is connected to the Mth inverted clock signal
  • the input end is electrically connected to the first node
  • the output end is electrically connected to the second node
  • the first inverter the input end of the first inverter is electrically connected to the second node, and the output end is electrically Connected to the first node;
  • the NAND gate signal processing module includes: a NAND gate, the first input end of the NAND gate is electrically connected to the first node, the second input end is connected to the M+2 clock signal, and the output end is electrically Connect the output buffer module;
  • the output buffer module includes:
  • a second inverter composed of a seventh P-type thin film transistor and an eighth N-type thin film transistor; a gate of the seventh P-type thin film transistor is electrically connected to a gate of the eighth N-type thin film transistor as a second reverse
  • the input end of the phase device is electrically connected to the output end of the NAND gate, and the drain of the seventh P-type thin film transistor is electrically connected to the drain of the eighth N-type thin film transistor as the output end of the second inverter a source of the seventh P-type thin film transistor is connected to a constant voltage high potential, and a source of the eighth N-type thin film transistor is connected to a constant voltage low potential;
  • a third transmission gate formed by the second P-type thin film transistor and the third N-type thin film transistor; the gate of the second P-type thin film transistor is used as a low-potential control terminal of the third transmission gate to access the touch control signal
  • the gate of the third N-type thin film transistor is used as a high potential control terminal of the third transmission gate to receive an inverted touch control signal, and the source of the second P-type thin film transistor and the source of the third N-type thin film transistor Electrically connected, the drain of the second P-type thin film transistor is electrically connected to the drain of the third N-type thin film transistor, respectively as an input end and an output end of the third transfer gate;
  • the gate of the sixth P-type thin film crystal is electrically connected to the output end of the second inverter, the source is connected to a constant voltage high potential, and the drain is electrically connected to the second P type a drain of the thin film transistor, a drain of the third N-type thin film transistor, and a gate of the ninth P-type thin film transistor;
  • a gate of the first P-type thin film transistor is connected to an inverted touch control signal, a source is connected to a constant voltage high potential, and a drain is electrically connected to a drain of the second P-type thin film transistor a drain of the pole, the third N-type thin film transistor, and a gate of the ninth P-type thin film transistor;
  • a fourth N-type thin film transistor the gate of which is connected to the touch control of the fourth N-type thin film transistor a signal, the source is connected to the constant voltage low potential, and the drain is electrically connected to the source of the second P-type thin film transistor, the source of the third N-type thin film transistor, and the gate of the tenth N-type thin film transistor;
  • the gate of the fifth N-type thin film transistor is electrically connected to the output end of the second inverter, the source is connected to the constant voltage low potential, and the drain is electrically connected to the second P type a source of the thin film transistor, a source of the third N-type thin film transistor, and a gate of the tenth N-type thin film transistor;
  • a ninth P-type thin film transistor a source of the ninth P-type thin film transistor is connected to a constant voltage high potential, and a drain is electrically connected to a gate scan driving signal output end;
  • the source of the tenth N-type thin film transistor is connected to a constant voltage low potential, and the drain is electrically connected to the gate scan driving signal output end;
  • the first DC control signal is opposite to the potential of the second DC control signal
  • the touch control signal In the normal display phase, the touch control signal (TCK) is low, the reverse touch control signal is high, and the touch scan drive signal provides a low potential; in the touch scan phase, the touch control signal is The high potential, the reverse touch control signal is low, the touch scan drive signal provides a periodic pulse signal, the gate scan drive signal output end is suspended, and the output gate scan drive signal is in a high impedance state, following the touch The scan drive signal jumps between high and low potentials and the same high and low potential jumps occur;
  • the input end of the first transmission gate is connected to the start signal of the circuit
  • the input end of the second transmission gate is connected to the start signal of the circuit
  • the first inverter includes: an N-type thin film transistor and a P-type thin film transistor, the gate of the N-type thin film transistor is electrically connected to the gate of the P-type thin film transistor as an input terminal, and the N-type film
  • the drain of the transistor is electrically connected to the drain of the P-type thin film transistor as an output terminal, the source of the N-type thin film transistor is connected to a constant voltage low potential, and the source of the P-type thin film transistor is connected to a constant voltage high potential.
  • the present invention provides a GOA circuit suitable for an In Cell type touch display panel.
  • a second P-type thin film transistor and a third are added to the output buffer module.
  • a third transmission gate composed of an N-type thin film transistor, a first P-type thin film transistor, and a fourth N-type thin film transistor, and introducing a touch control signal and a reverse touch control signal to control an operation state of the output buffer module, so that In the normal display phase, the third transmission gate is opened, the first and fourth thin film transistors are turned off, the output buffer module outputs the gate scan driving signal normally, and in the touch scanning phase, the third transmission gate is closed, the first and fourth films are closed.
  • the gate scan driving signal output terminal is suspended, and the output gate scan driving signal is high impedance.
  • the following high- and low-potential transition occurs when the touch scan driving signal jumps between high and low potentials, which can reduce the load on the signal processing of the IC during the touch scanning phase and improve the working efficiency of the GOA circuit.
  • FIG. 1 is a circuit diagram of a conventional GOA circuit suitable for an In Cell type touch display panel
  • FIG. 2 is a circuit diagram of a GOA circuit suitable for an In Cell type touch display panel according to the present invention
  • FIG. 3 is a circuit diagram of a first stage GOA unit of a GOA circuit suitable for an In Cell type touch display panel according to the present invention
  • FIG. 4 is a circuit diagram of a final stage GOA unit of a GOA circuit suitable for an In Cell type touch display panel according to the present invention
  • FIG. 5 is a forward scan timing diagram of a GOA circuit suitable for an In Cell type touch display panel according to the present invention.
  • FIG. 6 is a specific circuit structural diagram of a first inverter in a GOA circuit suitable for an In Cell type touch display panel according to the present invention
  • FIG. 7 is a specific circuit structural diagram of first and second clocked inverters in a GOA circuit suitable for an In Cell type touch display panel according to the present invention
  • FIG. 8 is a specific circuit structural diagram of first and second transmission gates in a GOA circuit suitable for an In Cell type touch display panel according to the present invention.
  • FIG. 9 is a structural diagram of a specific circuit of a NAND gate in a GOA circuit suitable for an In Cell type touch display panel according to the present invention.
  • the present invention provides a GOA circuit suitable for an In Cell type touch display panel, comprising: a cascaded multi-level GOA unit, each level of the GOA unit includes: forward and reverse scanning control The module 100, the control input module 200, the reset module 300, the latch module 400, the NAND gate signal processing module 500, and the output buffer module 600.
  • N be a positive integer, in addition to the first-level GOA unit and the last-level GOA unit, in the N-th GOA unit:
  • the forward and reverse scan control module 100 includes: a first transmission gate TG1, a low potential control end of the first transmission gate TG1 is connected to the first DC control signal U2D, and a high potential control terminal is connected to the second DC control signal.
  • D2U the input end is electrically connected to the first node Q (N-1) of the upper N-1th GOA unit, the output end is electrically connected to the control input module 200; and the second transmission gate TG2, the second The high potential control end of the transmission gate TG2 is connected to the first DC control signal U2D, the low potential control end is connected to the second DC control signal D2U, and the input end is electrically connected to the first stage of the next N+1th GOA unit.
  • Node Q(N+1) the output terminal is electrically connected to the control input module 200; the potential of the first node Q(N-1) of the N-1th GOA unit is used as a forward scan level transmission signal, and the N+1th level The potential of the first node Q(N-1) of the GOA unit is used as a reverse scan level transmission signal;
  • the control input module 200 includes: a first clocked inverter TF1, the high potential control terminal of the first clocked inverter TF1 is connected to the Mth clock signal CK(M), and the low potential control terminal is connected.
  • the M-phase inverted clock signal XCK (M) the input end is electrically connected to the output end of the first transmission gate TG1 and the output end of the second transmission gate TG2, the output end is electrically connected to the second node P (N);
  • the reset module 300 includes: an eleventh P-type thin film transistor T11, a gate of the eleventh P-type thin film transistor T11 is connected to a reset signal Reset, a source is connected to a constant voltage high potential VGH, and a drain is electrically connected. At the second node P(N);
  • the latch module 400 includes: a second clock control inverter TF2, the low potential control terminal of the second clock control inverter TF2 is connected to the Mth clock signal CK(M), and the high potential control terminal is connected.
  • the Mth inverted clock signal XCK(M) the input end is electrically connected to the first node Q(N), the output end is electrically connected to the second node P(N); and the first inverter IN1 is The input end of the first inverter IN1 is electrically connected to the second node P(N), and the output end is electrically connected to the first node Q(N);
  • the NAND gate signal processing module 500 includes: a NAND gate NAND, the first input terminal of the NAND gate NAND is electrically connected to the first node Q(N), and the second input terminal is connected to the M+2 gate.
  • Clock signal CK (M + 2), the output is electrically connected to the output buffer module 600;
  • the output buffer module 600 includes:
  • a second inverter IN2 composed of a seventh P-type thin film transistor T7 and an eighth N-type thin film transistor T8; a gate of the seventh P-type thin film transistor T7 is electrically connected to a gate of the eighth N-type thin film transistor T8 The pole is electrically connected to the output end of the NAND gate NAND, and the drain of the seventh P-type thin film transistor T7 is electrically connected to the drain of the eighth N-type thin film transistor T8.
  • the source of the seventh P-type thin film transistor T7 is connected to the constant voltage high potential VGH
  • the source of the eighth N-type thin film transistor T8 is connected to the constant voltage low potential VGL.
  • a third transfer gate TG3 composed of a second P-type thin film transistor T2 and a third N-type thin film transistor T3; a gate of the second P-type thin film transistor T2 serves as a low-potential control terminal of the third transfer gate TG3 Controlling the control signal TCK, the gate of the third N-type thin film transistor T3 as the high potential control end of the third transmission gate TG3 is connected to the inverted touch control signal XTCK, the source of the second P-type thin film transistor T2
  • the second P-type thin film transistor T2 is electrically connected to the drain of the third N-type thin film transistor T3, and the drain of the second P-type thin film transistor T2 is electrically connected to the drain of the third N-type thin film transistor T3 as the third transfer gate TG3.
  • a sixth P-type thin film transistor T6 the gate of the sixth P-type thin film crystal T6 is electrically connected to the output end of the second inverter IN2, the source is connected to the constant voltage high potential VGH, and the drain is electrically connected to the drain a drain of the second P-type thin film transistor T2, a drain of the third N-type thin film transistor T3, and a gate of the ninth P-type thin film transistor T9;
  • the first P-type thin film transistor T1 has a gate connected to the inverted touch control signal XTCK, a source connected to the constant voltage high potential VGH, and a drain electrically connected to the second P-type a drain of the thin film transistor T2, a drain of the third N-type thin film transistor T3, and a gate of the ninth P-type thin film transistor T9;
  • a fourth N-type thin film transistor T4 the gate of the fourth N-type thin film transistor T4 is connected to the touch control signal TCK, the source is connected to the constant voltage low potential VGL, and the drain is electrically connected to the second P-type thin film transistor.
  • a source of T2 a source of the third N-type thin film transistor T3, and a gate of the tenth N-type thin film transistor T10;
  • a fifth N-type thin film transistor T5 the gate of the fifth N-type thin film transistor T5 is electrically connected to the output end of the second inverter IN2, the source is connected to the constant voltage low potential VGL, and the drain is electrically connected to the drain a source of the second P-type thin film transistor T2, a source of the third N-type thin film transistor T3, and a gate of the tenth N-type thin film transistor T10;
  • a ninth P-type thin film transistor T9 the source of the ninth P-type thin film transistor T9 is connected to a constant voltage high potential VGH, and the drain is electrically connected to the gate scan driving signal output terminal Gate (N);
  • the tenth N-type thin film transistor T10 has a source connected to the constant voltage low potential VGL and a drain electrically connected to the gate scan driving signal output terminal Gate(N).
  • the input end of the first transmission gate TG1 is connected to the start signal STV of the circuit; referring to FIG. 4, in the last stage GOA unit, The input terminal of the second transmission gate TG2 is connected to the start signal STV of the circuit.
  • the first inverter IN1 includes: an N-type thin film transistor and a P-type thin film transistor, and the gate of the N-type thin film transistor is electrically connected to the gate of the P-type thin film transistor.
  • the drain of the N-type thin film transistor is electrically connected to the drain of the P-type thin film transistor as an output terminal, and the source of the N-type thin film transistor is connected to a constant voltage low potential VGL, P type The source of the thin film transistor is connected to a constant voltage high potential VGH.
  • the N-type thin film transistor When the input terminal is connected to the high potential signal, the N-type thin film transistor is turned on, and the output terminal outputs a low potential; when the input terminal is connected to the low potential signal, the P-type thin film transistor is turned on, and the output terminal outputs a high potential.
  • the first and second clocked inverters TF1, TF2 each include: two N-type thin film transistors connected in series and two P-type thin film transistors connected in series, wherein the gate of one P-type thin film transistor is used as a clock Control the low potential control terminal of the inverter, the source is connected to the constant voltage high potential VGH, the drain is electrically connected to the source of another P type thin film transistor; and the gate of an N type thin film transistor is used as the clock control inverter
  • the high potential control terminal, the source is connected to the constant voltage low potential VGL, the drain is electrically connected to the source of another N type thin film transistor; the gate of the other N type thin film transistor and the gate of the other P type thin film transistor
  • the electrical connection is used as the input of the clocked inverter, and the drain of the other N-type thin film transistor is electrically connected to the drain of the other P-type thin film transistor as the output of the clocked inverter.
  • the first and second transmission gates TG1, TG2 each include: an N-type thin film transistor and a P-type thin film transistor disposed opposite to each other, and the gate of the N-type thin film transistor serves as a high potential of the transmission gate.
  • a control terminal, a gate of the P-type thin film transistor is used as a low potential control terminal of the transfer gate, a source of the N-type thin film transistor and a source of the P-type thin film transistor are used as an input end of the transfer gate, and an N-type thin film transistor
  • the drain is electrically connected to the drain of the P-type thin film transistor as an output terminal of the transfer gate. Only when the low potential control terminal is connected to the low potential signal, and the high potential control terminal is connected to the high potential, the transmission gate is opened, and the input terminal and the output terminal are turned on.
  • the NAND gate NAND includes: two N-type thin film transistors connected in series and two P-type thin film transistors disposed opposite to each other, wherein a gate of the first P-type thin film transistor and a first N-type thin film transistor The gate is electrically connected as a first input end of the NAND gate, and the gate of the second P-type thin film transistor and the gate of the second N-type thin film transistor are electrically connected as a second input end of the NAND gate,
  • the sources of the P-type thin film transistors are all connected to the constant voltage high potential VGH, and the drains of the two P-type thin film transistors are electrically connected to the drain of the first N-type thin film transistor as the output of the NAND gate.
  • the source of one N-type thin film transistor is electrically connected to the drain of the second N-type thin film transistor, and the source of the second N-type thin film transistor is connected to the constant voltage low potential VGL. Only when the first input end and the second input end are connected to the high potential signal, the two N-type thin film transistors connected in series are turned on, and the output end outputs a low potential; as long as at least the first input end and the second input end are at least When a low potential signal is applied, a P-type thin film transistor is turned on and the output terminal outputs a high potential.
  • the clock signal is obtained by inputting an inverter to obtain an inverted clock signal, for example, the Mth strip The clock signal is input to the inverter to obtain the Mth inverted clock signal.
  • the GOA circuit of the present invention suitable for the In Cell type touch display panel can perform both forward scanning and reverse scanning: the first DC control signal U2D is opposite to the potential of the second DC control signal D2U.
  • the first DC control signal U2D provides a low potential and the second DC control signal D2U provides a high potential for forward scanning; when the first DC control signal U2D provides a high potential and the second DC control signal D2U provides At low potential, reverse scan is performed.
  • the working process of the GOA circuit applicable to the In Cell type touch display panel of the present invention includes two stages of normal display and touch scanning, as follows:
  • the normal display phase is entered.
  • the touch scan driving signal Tx always provides a low potential
  • the touch control signal TCK is a low potential
  • the reverse touch control signal XTCK is a high potential
  • the output buffer module is The third transfer gate TG3 in 600 is turned on, that is, both the second P-type thin film transistor T2 and the third N-type thin film transistor T3 are turned on, while the first P-type thin film transistor T1 and the fourth N-type thin film transistor T4 are both turned off.
  • the normal display phase is further divided into:
  • the first node Q(n-1) of the stage 1, the n-1th GOA unit (the first stage GOA unit is the start signal STV of the circuit) provides a high potential, that is, the level signal is high, due to the positive During scanning, the first DC control signal U2D provides a low potential, and the second DC control signal D2U provides a high potential.
  • the first transmission gate TG1 operates to transmit the high potential of the level transmission signal to the first clocked inverter TF1.
  • the Mth clock signal CK(M) provides a high potential
  • the first inverted clock XCK(M) provides a low potential
  • the first clocked control inverter TF1 is turned on
  • the second clocked controlled inverter TF2 is turned off
  • a clock control inverter TF1 output terminal output low potential that is, the second node P (N) is low potential
  • the low potential is converted to a high potential via the first inverter IN1 to the first node Q (N);
  • Phase 2 the Mth clock signal CK(M) transitions to a low potential, the first inverted clock XCK(M) transitions to a high potential, the second clocked control inverter TF2 turns on, and the first clocked inverter TF1 turns off.
  • the high potential of the first node Q(N) is latched by the second clocked inverter TF2 and the first inverter IN1, the NAND gate NAND outputs a high potential, and the output of the second inverter IN2 is low.
  • the potential, the sixth P-type thin film transistor T6 is turned on, the constant voltage high potential VGH is transmitted to the gate of the tenth N-type thin film transistor T10 via the opened third transfer gate TG3, and the tenth N-type thin film transistor T10 is turned on, and the gate scan is driven.
  • the output Gate (N) outputs a constant voltage low potential VGL;
  • Phase 3 the M+2 clock signal CK(M+2) provides a high potential, the first node Q(N) is still latched high, the NAND gate NAND output is low, and is output via the second inverter IN2.
  • the fifth N-type thin film transistor T5 is turned on, and the constant voltage low potential VGL is transmitted to the gate of the ninth P-type thin film transistor T9 via the opened third transfer gate TG3, and the ninth P-type thin film transistor T9 is turned on.
  • the pole scan drive output Gate (N) outputs a constant voltage high potential VGH;
  • Phase 4 subsequently, the M+2 clock signal CK(M+2) transitions to a low potential, and the gate scan drive output Gate(N) outputs a constant voltage low potential VGL;
  • the Mth clock signal CK(M) again provides a high potential, and the first node Q(n-1) of the n-1th stage GOA unit provides a low potential, via the first transmission gate TG1, and the first clock control
  • the inverter TF1 provides a high potential to the second node P(n), and then supplies a low potential to the first node Q(N) via the first inverter IN1, and then the first node Q(N) is latched to a low potential.
  • the gate scan drive output Gate (N) continuously outputs a constant voltage low potential VGL;
  • the touch scanning phase is entered.
  • the touch scan driving signal Tx provides a periodic pulse signal, and the touch control signal TCK changes to a high potential; the reverse touch control
  • the signal XTCK is turned to a low potential, and the third transfer gate TG3 is controlled to be turned off, and both the first P-type thin film transistor T1 and the fourth N-type thin film transistor T4 are controlled to be turned on, and the constant voltage high potential VGH is transmitted to the first P-type thin film transistor T1 to
  • the gate of the ninth P-type thin film transistor T9, the ninth P-type thin film transistor T9 is turned off, and the constant voltage low potential VGL is transmitted to the gate of the tenth N-type thin film transistor T10 via the fourth N-type thin film transistor T4, the tenth N-type
  • the thin film transistor T10 is also turned off, so that the gate scan driving signal output end (Gate(N)) is suspended, and the output gate scan driving signal is in a high impedance state, and follows the
  • the GOA circuit of the present invention for the In Cell type touch display panel is redesigned by the output buffer module, and the second P-type thin film transistor and the third N-type thin film transistor are added to the output buffer module.
  • the third transmission gate is opened, the first and fourth thin film transistors are turned off, the output buffer module outputs the gate scan driving signal normally, and in the touch scanning phase, the third transmission gate is closed, the first and fourth thin film transistors are turned on, and the gate is turned on.
  • the output of the scan driving signal is suspended, and the output of the gate scan driving signal is in a high impedance state, and the same high and low potential jump occurs when the touch scan driving signal jumps between high and low potentials, which can reduce the IC touch.
  • the control scanning stage improves the working efficiency of the GOA circuit for the signal processing load.

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Abstract

一种适用于In Cell型触控显示面板的GOA电路，在输出缓冲模块（600）中增加了由第二P型薄膜晶体管（T2）与第三N型薄膜晶体管（T3）构成的第三传输门（TG3）、第一P型薄膜晶体管（T1）、及第四N型薄膜晶体管（T4），并引入触控控制信号（TCK）与反相触控控制信号（XTCK）来控制输出缓冲模块（600）的工作状态，使得在触控扫描阶段，第三传输门（TG3)关闭，第一、第四薄膜晶体管（T1、T4）打开，栅极扫描驱动信号输出端（Gate（N））悬空，输出的栅极扫描驱动信号呈高阻态，跟随触控扫描驱动信号在高、低电位之间跳变而发生同样的高、低电位跳变，能够降低IC在触控扫描阶段对于信号处理的负载，提升GOA电路的工作效率。

Description

适用于In Cell型触控显示面板的的GOA电路 技术领域
本发明涉及触控显示技术领域，尤其涉及一种适用于In Cell型触控显示面板的GOA电路。
背景技术
GOA(Gate Driver on Array)技术即阵列基板行驱动技术，是利用薄膜晶体管(Thin Film Transistor，TFT)液晶显示器阵列制程将栅极扫描驱动电路制作在薄膜晶体管阵列基板上，以实现逐行扫描的驱动方式，具有降低生产成本和实现面板窄边框设计的优点，为多种显示器所使用。GOA电路具有两项基本功能：第一是输出扫描驱动信号，驱动面板内的栅极线，打开显示区内的TFT，以对像素进行充电；第二是移位寄存功能，当一个扫描驱动信号输出完成后，通过时钟控制进行下一个扫描驱动信号的输出，并依次传递下去。
嵌入式触控技术是将触控面板和液晶面板结合为一体，并将触控面板功能嵌入到液晶面板内，使得液晶面板同时具备显示和感知触控输入的功能。随着显示技术的飞速发展，触控显示面板已经广泛地被人们所接受及使用，如智能手机、平板电脑等均使用了触控显示面板。
现有的嵌入式触控技术主要分为两种：一种是触控电路在液晶盒上型(On Cell)，另一种是触控电路在液晶盒内型(In Cell)。
现有技术的In cell型触控显示面板会在每一帧画面的正常显示(Display)期间之后实现触控侦测(Sensing)的功能，即触控扫描信号在GOA电路的各级GOA单元均完成输出栅极扫描驱动信号的时刻开启，进入触控侦测。
图1所示为一种现有的适用于In Cell型触控显示面板的GOA电路，包括：级联的多级GOA单元，每一级GOA单元均包括：正反向扫描控制模块100、控制输入模块200、复位模块300、锁存模块400、与非门信号处理模块500、及输出缓冲模块600。
所述正反向扫描控制模块100用于对上、下级的级传信号进行选择，实现正向或反向扫描驱动。所述控制输入模块200用于级传信号的输入控制，实现对第一节点Q(N)的充电。所述复位模块300用于对第一节点Q(N)进行清零处理。所述锁存模块400用于锁存级传信号。所述与非门信号处 理模块500用于对锁存的级传信号与时钟信号进行与非处理，以产生本级的栅极扫描驱动信号；所述输出缓冲模块600包括奇数个串联的反相器，用于增加栅极扫描驱动信号的驱动能力，减小阻容延迟(RC Loading)。
具体地，设N为正整数，除第一级GOA单元与最后一级GOA单元外，在第N级GOA单元中：
所述正反向扫描控制模块100包括：第一传输门TG1，所述第一传输门TG1的低电位控制端接入第一直流控制信号U2D，高电位控制端接入第二直流控制信号D2U，输入端电性连接于上一级第N-1级GOA单元的第一节点Q(N-1)，输出端电性连接于第一时钟控制反相器TF1的输入端；以及第二传输门TG2，所述第二传输门TG2的高电位控制端接入第一直流控制信号U2D，低电位控制端接入第二直流控制信号D2U，输入端电性连接于下一级第N+1级GOA单元的第一节点Q(N+1)，输出端电性连接于第一时钟控制反相器TF1的输入端；第N-1级GOA单元的第一节点Q(N-1)的电位作为正向扫描级传信号，第N+1级GOA单元的第一节点Q(N-1)的电位作为反向扫描级传信号；
所述控制输入模块200包括：第一时钟控制反相器TF1，所述第一时钟控制反相器TF1的高电位控制端电性连接于第M条时钟信号CK(M)，低电位控制端电性连接于第M条反相时钟信号XCK(M)，输出端电性连接于第二节点P(N)；
所述复位模块300包括：第一P型薄膜晶体管T1，所述第一P型薄膜晶体管T1的栅极接入复位信号Reset，源极接入恒压高电位VGH，漏极电性连接于第二节点P(N)；
所述锁存模块400包括：第二时钟控制反相器TF2，所述第二时钟控制反相器TF2的低电位控制端电性连接于第M条时钟信号CK(M)，高电位控制端电性连接于第M条反相时钟信号XCK(M)，输入端电性连接于第一节点Q(N)，输出端电性连接于第二节点P(N)；以及第一反相器IN1，所述第一反相器IN1的输入端电性连接于第二节点P(N)，输出端电性连接于第一节点Q(N)；
所述与非门信号处理模块500包括：与非门NAND，所述与非门NAND的第一输入端电性连接于第一节点Q(N)，第二输入端接入第M+2条时钟信号，输出端电性连接于第二反相器IN2的输入端；
所述输出缓冲模块600包括：第二反相器IN2，所述第二反相器IN2的输出端电性连接于第三反相器IN3的输入端；第三反相器IN3，所述第三反相器IN3的输出端电性连接于第四反相器IN4的输入端；以及第四反相 器IN4，所述第四反相器IN4的输出端电性连接于栅极扫描驱动信号输出端Gate(N)。
上述现有的适用于In Cell型触控显示面板的GOA电路在正常显示阶段的工作过程为：以正向扫描为例，当第N-1级GOA单元的第一节点Q(N-1)的电位为高时，第M条时钟信号CK(M)提供高电位，第一节点Q(N)被充电至高电平；当第M条时钟信号CK(M)转变为低电位后，第一节点Q(N)的电位被锁存模块400锁存；当第M+2条时钟信号CK(M+2)的高电位来临时，栅极扫描驱动信号输出端Gate(N)输出高电位；当第M+2条时钟信号CK(M+2)转变为低电位后，栅极扫描驱动信号输出端Gate(N)稳定输出低电位。
但在触控扫描阶段，所有的信号线都要叠加一个跟随着触控驱动信号而变化的脉冲。触控显示面板正常显示完毕之后进行触控扫描，栅极扫描驱动信号输出端Gate(N)接入恒压低电位，此时恒压低电位会随着触控驱动信号的跳变而发生改变，栅极扫描驱动信号也会随着触控驱动信号的变化而变化。这种触控扫描面板的工作方式需要在触控扫描阶段通过集成电路板(Integrated Circuit，IC)对栅极扫描驱动信号进行波形处理，导致IC的负载较大。
发明内容
本发明的目的在于提供一种适用于In Cell型触控显示面板的GOA电路，能够降低IC在触控扫描阶段对于信号处理的负载，提升GOA电路的工作效率。
为实现上述目的，本发明提供了一种适用于In Cell型触控显示面板的GOA电路，包括：级联的多级GOA单元，每一级GOA单元均包括：正反向扫描控制模块、控制输入模块、复位模块、锁存模块、与非门信号处理模块、及输出缓冲模块；
设N为正整数，除第一级GOA单元与最后一级GOA单元外，在第N级GOA单元中：
所述正反向扫描控制模块包括：第一传输门，所述第一传输门的低电位控制端接入第一直流控制信号，高电位控制端接入第二直流控制信号，输入端电性连接于上一级第N-1级GOA单元的第一节点，输出端电性连接控制输入模块；以及第二传输门，所述第二传输门的高电位控制端接入第一直流控制信号，低电位控制端接入第二直流控制信号，输入端电性连接于下一级第N+1级GOA单元的第一节点，输出端电性连接控制输入模块； 第N-1级GOA单元的第一节点的电位作为正向扫描级传信号，第N+1级GOA单元的第一节点的电位作为反向扫描级传信号；
所述控制输入模块包括：第一时钟控制反相器，所述第一时钟控制反相器的高电位控制端接入第M条时钟信号，低电位控制端接入第M条反相时钟信号，输入端电性连接于第一传输门的输出端及第二传输门的输出端，输出端电性连接于第二节点；
所述复位模块包括：第十一P型薄膜晶体管，所述第十一P型薄膜晶体管的栅极接入复位信号，源极接入恒压高电位，漏极电性连接于第二节点；
所述锁存模块包括：第二时钟控制反相器，所述第二时钟控制反相器的低电位控制端接入第M条时钟信号，高电位控制端接入第M条反相时钟信号，输入端电性连接于第一节点，输出端电性连接于第二节点；以及第一反相器，所述第一反相器的输入端电性连接于第二节点，输出端电性连接于第一节点；
所述与非门信号处理模块包括：与非门，所述与非门的第一输入端电性连接于第一节点，第二输入端接入第M+2条时钟信号，输出端电性连接输出缓冲模块；
所述输出缓冲模块包括：
由第七P型薄膜晶体管与第八N型薄膜晶体管构成的第二反相器；所述第七P型薄膜晶体管的栅极电性连接于第八N型薄膜晶体管的栅极作为第二反相器的输入端并电性连接于与非门的输出端，所述第七P型薄膜晶体管的漏极电性连接于第八N型薄膜晶体管的漏极作为第二反相器的输出端，所述第七P型薄膜晶体管的源极电接入恒压高电位，所述第八N型薄膜晶体管的源极接入恒压低电位；
由第二P型薄膜晶体管与第三N型薄膜晶体管构成的第三传输门；所述第二P型薄膜晶体管的栅极作为第三传输门的低电位控制端接入触控控制信号，所述第三N型薄膜晶体管的栅极作为第三传输门的高电位控制端接入反相触控控制信号，所述第二P型薄膜晶体管的源极与第三N型薄膜晶体管的源极电性连接，所述第二P型薄膜晶体管的漏极与第三N型薄膜晶体管的漏极电性连接，分别作为第三传输门的输入端与输出端；
第六P型薄膜晶体管，所述第六P型薄膜晶体的栅极电性连接于第二反相器的输出端，源极接入恒压高电位，漏极电性连接于第二P型薄膜晶体管的漏极、第三N型薄膜晶体管的漏极、及第九P型薄膜晶体管的栅极；
第一P型薄膜晶体管，所述第一P型薄膜晶体管的栅极接入反相触控 控制信号，源极接入恒压高电位，漏极电性连接于第二P型薄膜晶体管的漏极、第三N型薄膜晶体管的漏极、及第九P型薄膜晶体管的栅极；
第四N型薄膜晶体管，所述第四N型薄膜晶体管的栅极接入触控控制信号，源极接入恒压低电位，漏极电性连接于第二P型薄膜晶体管的源极、第三N型薄膜晶体管的源极、及第十N型薄膜晶体管的栅极；
第五N型薄膜晶体管，所述第五N型薄膜晶体管的栅极电性连接于第二反相器的输出端，源极接入恒压低电位，漏极电性连接于第二P型薄膜晶体管的源极、第三N型薄膜晶体管的源极、及第十N型薄膜晶体管的栅极；
第九P型薄膜晶体管，所述第九P型薄膜晶体管的源极接入恒压高电位，漏极电性连接于栅极扫描驱动信号输出端；
第十N型薄膜晶体管，所述第十N型薄膜晶体管的源极接入恒压低电位，漏极电性连接于栅极扫描驱动信号输出端；
所述第一直流控制信号与第二直流控制信号的电位相反；
在正常显示阶段，所述触控控制信号为低电位，反相触控控制信号为高电位，触控扫描驱动信号提供低电位；在触控扫描阶段，所述触控控制信号为高电位，反相触控控制信号为低电位，触控扫描驱动信号提供周期性脉冲信号，所述栅极扫描驱动信号输出端悬空，输出的栅极扫描驱动信号呈高阻态，跟随触控扫描驱动信号在高、低电位之间跳变而发生同样的高、低电位跳变。
在第一级GOA单元中，所述第一传输门的输入端接入电路的起始信号。
在最后一级GOA单元中，所述第二传输门的输入端接入电路的起始信号。
所述第一反相器包括：一N型薄膜晶体管与一P型薄膜晶体管，所述N型薄膜晶体管的栅极与P型薄膜晶体管的栅极电性连接作为输入端，N型薄膜晶体管的漏极与P型薄膜晶体管的漏极电性连接作为输出端，N型薄膜晶体管的源极接入恒压低电位，P型薄膜晶体管的源极接入恒压高电位。
所述第一与第二时钟控制反相器均包括：两串联的N型薄膜晶体管与两串联的P型薄膜晶体管，其中一个P型薄膜晶体管的栅极作为时钟控制反相器的低电位控制端，源极接入恒压高电位，漏极电性连接于另一个P型薄膜晶体管的源极；一个N型薄膜晶体管栅极作为时钟控制反相器的高电位控制端，源极接入恒压低电位，漏极电性连接于另一个N型薄膜晶体 管的源极；另一个N型薄膜晶体管的栅极与另一个P型薄膜晶体管的栅极电性连接作为时钟控制反相器的输入端，另一个N型薄膜晶体管的漏极与另一个P型薄膜晶体管的漏极电性连接作为时钟控制反相器的输出端。
所述第一和第二传输门均包括：相对设置的一N型薄膜晶体管与一P型薄膜晶体管，所述N型薄膜晶体管的栅极作为传输门的高电位控制端，所述P型薄膜晶体管的栅极作为传输门的低电位控制端，N型薄膜晶体管的源极与P型薄膜晶体管的源极电性连接作为传输门的输入端，N型薄膜晶体管的漏极与P型薄膜晶体管的漏极电性连接作为传输门的输出端。
所述与非门包括：串联的两N型薄膜晶体管与相对设置的两P型薄膜晶体管，其中第一个P型薄膜晶体管的栅极与第一个N型薄膜晶体管的栅极电性连接作为与非门的第一输入端，第二个P型薄膜晶体管的栅极与第二个N型薄膜晶体管的栅极电性连接作为与非门的第二输入端，两个P型薄膜晶体管的源极均接入恒压高电位，两个P型薄膜晶体管的漏极均与第一个N型薄膜晶体管的漏极电性连接作为与非门的输出端，第一个N型薄膜晶体管的源极与第二个N型薄膜晶体管的漏极电性连接，第二个N型薄膜晶体管的源极接入恒压低电位。
当所述第一直流控制信号提供低电位且第二直流控制信号提供高电位时，进行正向扫描；当所述第一直流控制信号提供高电位且第二直流控制信号提供低电位时，进行反向扫描。
本发明还提供一种适用于In Cell型触控显示面板的GOA电路，包括：级联的多级GOA单元，每一级GOA单元均包括：正反向扫描控制模块、控制输入模块、复位模块、锁存模块、与非门信号处理模块、及输出缓冲模块；
设N为正整数，除第一级GOA单元与最后一级GOA单元外，在第N级GOA单元中：
所述正反向扫描控制模块包括：第一传输门，所述第一传输门的低电位控制端接入第一直流控制信号，高电位控制端接入第二直流控制信号，输入端电性连接于上一级第N-1级GOA单元的第一节点，输出端电性连接控制输入模块；以及第二传输门，所述第二传输门的高电位控制端接入第一直流控制信号，低电位控制端接入第二直流控制信号，输入端电性连接于下一级第N+1级GOA单元的第一节点，输出端电性连接控制输入模块；第N-1级GOA单元的第一节点的电位作为正向扫描级传信号，第N+1级GOA单元的第一节点的电位作为反向扫描级传信号；
所述控制输入模块包括：第一时钟控制反相器，所述第一时钟控制反 相器的高电位控制端接入第M条时钟信号，低电位控制端接入第M条反相时钟信号，输入端电性连接于第一传输门的输出端及第二传输门的输出端，输出端电性连接于第二节点；
所述复位模块包括：第十一P型薄膜晶体管，所述第十一P型薄膜晶体管的栅极接入复位信号，源极接入恒压高电位，漏极电性连接于第二节点；
所述锁存模块包括：第二时钟控制反相器，所述第二时钟控制反相器的低电位控制端接入第M条时钟信号，高电位控制端接入第M条反相时钟信号，输入端电性连接于第一节点，输出端电性连接于第二节点；以及第一反相器，所述第一反相器的输入端电性连接于第二节点，输出端电性连接于第一节点；
所述与非门信号处理模块包括：与非门，所述与非门的第一输入端电性连接于第一节点，第二输入端接入第M+2条时钟信号，输出端电性连接输出缓冲模块；
所述输出缓冲模块包括：
由第七P型薄膜晶体管与第八N型薄膜晶体管构成的第二反相器；所述第七P型薄膜晶体管的栅极电性连接于第八N型薄膜晶体管的栅极作为第二反相器的输入端并电性连接于与非门的输出端，所述第七P型薄膜晶体管的漏极电性连接于第八N型薄膜晶体管的漏极作为第二反相器的输出端，所述第七P型薄膜晶体管的源极接入恒压高电位，所述第八N型薄膜晶体管的源极接入恒压低电位；
由第二P型薄膜晶体管与第三N型薄膜晶体管构成的第三传输门；所述第二P型薄膜晶体管的栅极作为第三传输门的低电位控制端接入触控控制信号，所述第三N型薄膜晶体管的栅极作为第三传输门的高电位控制端接入反相触控控制信号，所述第二P型薄膜晶体管的源极与第三N型薄膜晶体管的源极电性连接，所述第二P型薄膜晶体管的漏极与第三N型薄膜晶体管的漏极电性连接，分别作为第三传输门的输入端与输出端；
第六P型薄膜晶体管，所述第六P型薄膜晶体的栅极电性连接于第二反相器的输出端，源极接入恒压高电位，漏极电性连接于第二P型薄膜晶体管的漏极、第三N型薄膜晶体管的漏极、及第九P型薄膜晶体管的栅极；
第一P型薄膜晶体管，所述第一P型薄膜晶体管的栅极接入反相触控控制信号，源极接入恒压高电位，漏极电性连接于第二P型薄膜晶体管的漏极、第三N型薄膜晶体管的漏极、及第九P型薄膜晶体管的栅极；
第四N型薄膜晶体管，所述第四N型薄膜晶体管的栅极接入触控控制 信号，源极接入恒压低电位，漏极电性连接于第二P型薄膜晶体管的源极、第三N型薄膜晶体管的源极、及第十N型薄膜晶体管的栅极；
第五N型薄膜晶体管，所述第五N型薄膜晶体管的栅极电性连接于第二反相器的输出端，源极接入恒压低电位，漏极电性连接于第二P型薄膜晶体管的源极、第三N型薄膜晶体管的源极、及第十N型薄膜晶体管的栅极；
第九P型薄膜晶体管，所述第九P型薄膜晶体管的源极接入恒压高电位，漏极电性连接于栅极扫描驱动信号输出端；
第十N型薄膜晶体管，所述第十N型薄膜晶体管的源极接入恒压低电位，漏极电性连接于栅极扫描驱动信号输出端；
所述第一直流控制信号与第二直流控制信号的电位相反；
在正常显示阶段，所述触控控制信号(TCK)为低电位，反相触控控制信号为高电位，触控扫描驱动信号提供低电位；在触控扫描阶段，所述触控控制信号为高电位，反相触控控制信号为低电位，触控扫描驱动信号提供周期性脉冲信号，所述栅极扫描驱动信号输出端悬空，输出的栅极扫描驱动信号呈高阻态，跟随触控扫描驱动信号在高、低电位之间跳变而发生同样的高、低电位跳变；
其中，在第一级GOA单元中，所述第一传输门的输入端接入电路的起始信号；
其中，在最后一级GOA单元中，所述第二传输门的输入端接入电路的起始信号；
其中，所述第一反相器包括：一N型薄膜晶体管与一P型薄膜晶体管，所述N型薄膜晶体管的栅极与P型薄膜晶体管的栅极电性连接作为输入端，N型薄膜晶体管的漏极与P型薄膜晶体管的漏极电性连接作为输出端，N型薄膜晶体管的源极接入恒压低电位，P型薄膜晶体管的源极接入恒压高电位。
本发明的有益效果：本发明提供的一种适用于In Cell型触控显示面板的GOA电路，通过对输出缓冲模块重新设计，在输出缓冲模块中增加了由第二P型薄膜晶体管与第三N型薄膜晶体管构成的第三传输门、第一P型薄膜晶体管、及第四N型薄膜晶体管，并引入触控控制信号与反相触控控制信号来控制输出缓冲模块的工作状态，使得在正常显示阶段，第三传输门打开，第一、第四薄膜晶体管关闭，输出缓冲模块正常输出栅极扫描驱动信号，而在进行触控扫描阶段，第三传输门关闭，第一、第四薄膜晶体管打开，栅极扫描驱动信号输出端悬空，输出的栅极扫描驱动信号呈高阻 态，跟随触控扫描驱动信号在高、低电位之间跳变而发生同样的高、低电位跳变，能够降低IC在触控扫描阶段对于信号处理的负载，提升GOA电路的工作效率。
附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1为一种现有的适用于In Cell型触控显示面板的GOA电路的电路图；
图2为本发明的适用于In Cell型触控显示面板的GOA电路的电路图；
图3为本发明的适用于In Cell型触控显示面板的GOA电路的第一级GOA单元的电路图；
图4为本发明的适用于In Cell型触控显示面板的GOA电路的最后一级GOA单元的电路图；
图5为本发明的适用于In Cell型触控显示面板的GOA电路的正向扫描时序图；
图6为本发明的适用于In Cell型触控显示面板的GOA电路中第一反相器的具体电路结构图；
图7为本发明的适用于In Cell型触控显示面板的GOA电路中第一和第二时钟控制反相器的具体电路结构图；
图8为本发明的适用于In Cell型触控显示面板的GOA电路中第一和第二传输门的具体电路结构图；
图9为本发明的适用于In Cell型触控显示面板的GOA电路中与非门的具体电路结构图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请同时参阅图2与图5，本发明提供一种适用于In Cell型触控显示面板的GOA电路，包括：级联的多级GOA单元，每一级GOA单元均包括：正反向扫描控制模块100、控制输入模块200、复位模块300、锁存模块400、与非门信号处理模块500、及输出缓冲模块600。
设N为正整数，除第一级GOA单元与最后一级GOA单元外，在第N级GOA单元中：
所述正反向扫描控制模块100包括：第一传输门TG1，所述第一传输门TG1的低电位控制端接入第一直流控制信号U2D，高电位控制端接入第二直流控制信号D2U，输入端电性连接于上一级第N-1级GOA单元的第一节点Q(N-1)，输出端电性连接控制输入模块200；以及第二传输门TG2，所述第二传输门TG2的高电位控制端接入第一直流控制信号U2D，低电位控制端接入第二直流控制信号D2U，输入端电性连接于下一级第N+1级GOA单元的第一节点Q(N+1)，输出端电性连接控制输入模块200；第N-1级GOA单元的第一节点Q(N-1)的电位作为正向扫描级传信号，第N+1级GOA单元的第一节点Q(N-1)的电位作为反向扫描级传信号；
所述控制输入模块200包括：第一时钟控制反相器TF1，所述第一时钟控制反相器TF1的高电位控制端接入第M条时钟信号CK(M)，低电位控制端接入第M条反相时钟信号XCK(M)，输入端电性连接于第一传输门TG1的输出端及第二传输门TG2的输出端，输出端电性连接于第二节点P(N)；
所述复位模块300包括：第十一P型薄膜晶体管T11，所述第十一P型薄膜晶体管T11的栅极接入复位信号Reset，源极接入恒压高电位VGH，漏极电性连接于第二节点P(N)；
所述锁存模块400包括：第二时钟控制反相器TF2，所述第二时钟控制反相器TF2的低电位控制端接入第M条时钟信号CK(M)，高电位控制端接入第M条反相时钟信号XCK(M)，输入端电性连接于第一节点Q(N)，输出端电性连接于第二节点P(N)；以及第一反相器IN1，所述第一反相器IN1的输入端电性连接于第二节点P(N)，输出端电性连接于第一节点Q(N)；
所述与非门信号处理模块500包括：与非门NAND，所述与非门NAND的第一输入端电性连接于第一节点Q(N)，第二输入端接入第M+2条时钟信号CK(M+2)，输出端电性连接输出缓冲模块600；
所述输出缓冲模块600包括：
由第七P型薄膜晶体管T7与第八N型薄膜晶体管T8构成的第二反相器IN2；所述第七P型薄膜晶体管T7的栅极电性连接于第八N型薄膜晶体管T8的栅极作为第二反相器IN2的输入端并电性连接于与非门NAND的输出端，所述第七P型薄膜晶体管T7的漏极电性连接于第八N型薄膜晶体管T8的漏极作为第二反相器IN2的输出端，所述第七P型薄膜晶体管T7的源极接入恒压高电位VGH，所述第八N型薄膜晶体管T8的源极接入恒压低电位VGL；
由第二P型薄膜晶体管T2与第三N型薄膜晶体管T3构成的第三传输门TG3；所述第二P型薄膜晶体管T2的栅极作为第三传输门TG3的低电位控制端接入触控控制信号TCK，所述第三N型薄膜晶体管T3的栅极作为第三传输门TG3的高电位控制端接入反相触控控制信号XTCK，所述第二P型薄膜晶体管T2的源极与第三N型薄膜晶体管T3的源极电性连接，所述第二P型薄膜晶体管T2的漏极与第三N型薄膜晶体管T3的漏极电性连接，分别作为第三传输门TG3的输入端与输出端；
第六P型薄膜晶体管T6，所述第六P型薄膜晶体T6的栅极电性连接于第二反相器IN2的输出端，源极接入恒压高电位VGH，漏极电性连接于第二P型薄膜晶体管T2的漏极、第三N型薄膜晶体管T3的漏极、及第九P型薄膜晶体管T9的栅极；
第一P型薄膜晶体管T1，所述第一P型薄膜晶体管T1的栅极接入反相触控控制信号XTCK，源极接入恒压高电位VGH，漏极电性连接于第二P型薄膜晶体管T2的漏极、第三N型薄膜晶体管T3的漏极、及第九P型薄膜晶体管T9的栅极；
第四N型薄膜晶体管T4，所述第四N型薄膜晶体管T4的栅极接入触控控制信号TCK，源极接入恒压低电位VGL，漏极电性连接于第二P型薄膜晶体管T2的源极、第三N型薄膜晶体管T3的源极、及第十N型薄膜晶体管T10的栅极；
第五N型薄膜晶体管T5，所述第五N型薄膜晶体管T5的栅极电性连接于第二反相器IN2的输出端，源极接入恒压低电位VGL，漏极电性连接于第二P型薄膜晶体管T2的源极、第三N型薄膜晶体管T3的源极、及第十N型薄膜晶体管T10的栅极；
第九P型薄膜晶体管T9，所述第九P型薄膜晶体管T9的源极接入恒压高电位VGH，漏极电性连接于栅极扫描驱动信号输出端Gate(N)；
第十N型薄膜晶体管T10，所述第十N型薄膜晶体管T10的源极接入恒压低电位VGL，漏极电性连接于栅极扫描驱动信号输出端Gate(N)。
特别地，请参阅图3，在第一级GOA单元中，所述第一传输门TG1的输入端接入电路的起始信号STV；请参阅图4，在最后一级GOA单元中，所述第二传输门TG2的输入端接入电路的起始信号STV。
具体地，请参阅图6，所述第一反相器IN1包括：一N型薄膜晶体管与一P型薄膜晶体管，所述N型薄膜晶体管的栅极与P型薄膜晶体管的栅极电性连接作为输入端，N型薄膜晶体管的漏极与P型薄膜晶体管的漏极电性连接作为输出端，N型薄膜晶体管的源极接入恒压低电位VGL，P型 薄膜晶体管的源极接入恒压高电位VGH。当输入端接入高电位信号时，N型薄膜晶体管打开，输出端输出低电位；当输入端接入低电位信号时，P型薄膜晶体管打开，输出端输出高电位。
请参阅图7，所述第一与第二时钟控制反相器TF1、TF2均包括：两串联的N型薄膜晶体管与两串联的P型薄膜晶体管，其中一个P型薄膜晶体管的栅极作为时钟控制反相器的低电位控制端，源极接入恒压高电位VGH，漏极电性连接于另一个P型薄膜晶体管的源极；一个N型薄膜晶体管栅极作为时钟控制反相器的高电位控制端，源极接入恒压低电位VGL，漏极电性连接于另一个N型薄膜晶体管的源极；另一个N型薄膜晶体管的栅极与另一个P型薄膜晶体管的栅极电性连接作为时钟控制反相器的输入端，另一个N型薄膜晶体管的漏极与另一个P型薄膜晶体管的漏极电性连接作为时钟控制反相器的输出端。仅在低电位控制端接入低电位信号，高电位控制端接入高电位的前提下：输入端接入高电位信号时，两串联的N型薄膜晶体管均打开，输出端输出低电位；输入端接入低电位信号时，两串联的P型薄膜晶体管均打开，输出端输出高电位。
请参阅图8，所述第一和第二传输门TG1、TG2均包括：相对设置的一N型薄膜晶体管与一P型薄膜晶体管，所述N型薄膜晶体管的栅极作为传输门的高电位控制端，所述P型薄膜晶体管的栅极作为传输门的低电位控制端，N型薄膜晶体管的源极与P型薄膜晶体管的源极电性作为传输门的输入端，N型薄膜晶体管的漏极与P型薄膜晶体管的漏极电性连接作为传送门的输出端。只有在低电位控制端接入低电位信号，高电位控制端接入高电位时，传输门才打开，输入端与输出端导通。
请参阅图9，所述与非门NAND包括：串联的两N型薄膜晶体管与相对设置的两P型薄膜晶体管，其中第一个P型薄膜晶体管的栅极与第一个N型薄膜晶体管的栅极电性连接作为与非门的第一输入端，第二个P型薄膜晶体管的栅极与第二个N型薄膜晶体管的栅极电性连接作为与非门的第二输入端，两个P型薄膜晶体管的源极均接入恒压高电位VGH，两个P型薄膜晶体管的漏极均与第一个N型薄膜晶体管的漏极电性连接作为与非门的输出端，第一个N型薄膜晶体管的源极与第二个N型薄膜晶体管的漏极电性连接，第二个N型薄膜晶体管的源极接入恒压低电位VGL。只有在第一输入端与第二输入端均接入高电位信号的情况下，串联的两N型薄膜晶体管均打开，输出端输出低电位；只要第一输入端、第二输入端的至少其中之一接入低电位信号，就会有P型薄膜晶体管打开，输出端输出高电位。进一步地，时钟信号通过输入一反相器得到反相时钟信号，例如将第M条 时钟信号输入反相器得到第M条反相时钟信号。
本发明的适用于In Cell型触控显示面板的GOA电路既能进行正向扫描，又能进行反向扫描：所述第一直流控制信号U2D与第二直流控制信号D2U的电位相反，当所述第一直流控制信号U2D提供低电位且第二直流控制信号D2U提供高电位时，进行正向扫描；当所述第一直流控制信号U2D提供高电位且第二直流控制信号D2U提供低电位时，进行反向扫描。请结合图2与图5，以正向扫描为例，本发明的适用于In Cell型触控显示面板的GOA电路的工作过程包括正常显示和触控扫描两个阶段，具体如下：
首先进入正常显示阶段，在该正常显示阶段，所述触控扫描驱动信号Tx始终提供低电位，所述触控控制信号TCK为低电位，反相触控控制信号XTCK为高电位，输出缓冲模块600中的第三传输门TG3打开，即第二P型薄膜晶体管T2与第三N型薄膜晶体管T3均打开，同时第一P型薄膜晶体管T1与第四N型薄膜晶体管T4均关闭。
进一步地，该正常显示阶段又分为：
阶段1、第n-1级GOA单元的第一节点Q(n-1)(第一级GOA单元则为电路的起始信号STV)提供高电位，即级传信号为高电位，由于正向扫描时，所述第一直流控制信号U2D提供低电位、第二直流控制信号D2U提供高电位，第一传输门TG1工作，将级传信号的高电位传输至第一时钟控制反相器TF1，此时第M条时钟信号CK(M)提供高电位，第一反相时钟XCK(M)提供低电位，第一时钟控制反相器TF1打开，第二时钟控制反相器TF2关闭，第一时钟控制反相器TF1输出端输出低电位即第二节点P(N)为低电位，该低电位经由第一反相器IN1后转变为高电位提供至第一节点Q(N)；
阶段2、第M条时钟信号CK(M)转变为低电位，第一反相时钟XCK(M)转变为高电位，第二时钟控制反相器TF2打开，第一时钟控制反相器TF1关闭，第一节点Q(N)的高电位在第二时钟控制反相器TF2与第一反相器IN1的作用下锁存，与非门NAND输出高电位，经由第二反相器IN2输出低电位，第六P型薄膜晶体管T6打开，恒压高电位VGH经由打开的第三传输门TG3传输至第十N型薄膜晶体管T10的栅极，第十N型薄膜晶体管T10打开，栅极扫描驱动输出端Gate(N)输出恒压低电位VGL；
阶段3、第M+2条时钟信号CK(M+2)提供高电位，第一节点Q(N)仍锁存为高电位，与非门NAND输出低电位，经由第二反相器IN2输出高电位，第五N型薄膜晶体管T5打开，恒压低电位VGL经由打开的第三传输门TG3传输至第九P型薄膜晶体管T9的栅极，第九P型薄膜晶体管T9打开，栅 极扫描驱动输出端Gate(N)输出恒压高电位VGH；
阶段4、随后，第M+2条时钟信号CK(M+2)转变为低电位，栅极扫描驱动输出端Gate(N)输出恒压低电位VGL；
阶段5、第M条时钟信号CK(M)再次提供高电位，第n-1级GOA单元的第一节点Q(n-1)提供低电位，经由第一传输门TG1、和第一时钟控制反相器TF1后提供高电位至第二节点P(n)，再经过第一反相器IN1提供低电位至第一节点Q(N)，然后第一节点Q(N)锁存至低电位，栅极扫描驱动输出端Gate(N)持续输出恒压低电位VGL；
正常显示阶段结束后，进入触控扫描阶段，在该触控扫描阶段，所述触控扫描驱动信号Tx提供周期性脉冲信号，所述触控控制信号TCK转变为高电位；反相触控控制信号XTCK转变为低电位，控制第三传输门TG3关闭，同时控制第一P型薄膜晶体管T1与第四N型薄膜晶体管T4均打开，恒压高电位VGH经由第一P型薄膜晶体管T1传输至第九P型薄膜晶体管T9的栅极，第九P型薄膜晶体管T9关闭，恒压低电位VGL经由第四N型薄膜晶体管T4传输至第十N型薄膜晶体管T10的栅极，第十N型薄膜晶体管T10亦关闭，使得所述栅极扫描驱动信号输出端(Gate(N))悬空，输出的栅极扫描驱动信号呈高阻态，并跟随触控扫描驱动信号Tx在高、低电位之间跳变而发生同样的高、低电位跳变。这样能够降低IC在触控扫描阶段对于信号处理的负载，提升GOA电路的工作效率。
综上所述，本发明的适用于In Cell型触控显示面板的GOA电路，通过对输出缓冲模块重新设计，在输出缓冲模块中增加了由第二P型薄膜晶体管与第三N型薄膜晶体管构成的第三传输门、第一P型薄膜晶体管、及第四N型薄膜晶体管，并引入触控控制信号与反相触控控制信号来控制输出缓冲模块的工作状态，使得在正常显示阶段，第三传输门打开，第一、第四薄膜晶体管关闭，输出缓冲模块正常输出栅极扫描驱动信号，而在触控扫描阶段，第三传输门关闭，第一、第四薄膜晶体管打开，栅极扫描驱动信号输出端悬空，输出的栅极扫描驱动信号呈高阻态，跟随触控扫描驱动信号在高、低电位之间跳变而发生同样的高、低电位跳变，能够降低IC在触控扫描阶段对于信号处理的负载，提升GOA电路的工作效率。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (13)

  1. 一种适用于In Cell型触控显示面板的GOA电路，包括：级联的多级GOA单元，每一级GOA单元均包括：正反向扫描控制模块、控制输入模块、复位模块、锁存模块、与非门信号处理模块、及输出缓冲模块；
    设N为正整数，除第一级GOA单元与最后一级GOA单元外，在第N级GOA单元中：
    所述正反向扫描控制模块包括：第一传输门，所述第一传输门的低电位控制端接入第一直流控制信号，高电位控制端接入第二直流控制信号，输入端电性连接于上一级第N-1级GOA单元的第一节点，输出端电性连接控制输入模块；以及第二传输门，所述第二传输门的高电位控制端接入第一直流控制信号，低电位控制端接入第二直流控制信号，输入端电性连接于下一级第N+1级GOA单元的第一节点，输出端电性连接控制输入模块；第N-1级GOA单元的第一节点的电位作为正向扫描级传信号，第N+1级GOA单元的第一节点的电位作为反向扫描级传信号；
    所述控制输入模块包括：第一时钟控制反相器，所述第一时钟控制反相器的高电位控制端接入第M条时钟信号，低电位控制端接入第M条反相时钟信号，输入端电性连接于第一传输门的输出端及第二传输门的输出端，输出端电性连接于第二节点；
    所述复位模块包括：第十一P型薄膜晶体管，所述第十一P型薄膜晶体管的栅极接入复位信号，源极接入恒压高电位，漏极电性连接于第二节点；
    所述锁存模块包括：第二时钟控制反相器，所述第二时钟控制反相器的低电位控制端接入第M条时钟信号，高电位控制端接入第M条反相时钟信号，输入端电性连接于第一节点，输出端电性连接于第二节点；以及第一反相器，所述第一反相器的输入端电性连接于第二节点，输出端电性连接于第一节点；
    所述与非门信号处理模块包括：与非门，所述与非门的第一输入端电性连接于第一节点，第二输入端接入第M+2条时钟信号，输出端电性连接输出缓冲模块；
    所述输出缓冲模块包括：
    由第七P型薄膜晶体管与第八N型薄膜晶体管构成的第二反相器；所述第七P型薄膜晶体管的栅极电性连接于第八N型薄膜晶体管的栅极作为 第二反相器的输入端并电性连接于与非门的输出端，所述第七P型薄膜晶体管的漏极电性连接于第八N型薄膜晶体管的漏极作为第二反相器的输出端，所述第七P型薄膜晶体管的源极接入恒压高电位，所述第八N型薄膜晶体管的源极接入恒压低电位；
    由第二P型薄膜晶体管与第三N型薄膜晶体管构成的第三传输门；所述第二P型薄膜晶体管的栅极作为第三传输门的低电位控制端接入触控控制信号，所述第三N型薄膜晶体管的栅极作为第三传输门的高电位控制端接入反相触控控制信号，所述第二P型薄膜晶体管的源极与第三N型薄膜晶体管的源极电性连接，所述第二P型薄膜晶体管的漏极与第三N型薄膜晶体管的漏极电性连接，分别作为第三传输门的输入端与输出端；
    第六P型薄膜晶体管，所述第六P型薄膜晶体的栅极电性连接于第二反相器的输出端，源极接入恒压高电位，漏极电性连接于第二P型薄膜晶体管的漏极、第三N型薄膜晶体管的漏极、及第九P型薄膜晶体管的栅极；
    第一P型薄膜晶体管，所述第一P型薄膜晶体管的栅极接入反相触控控制信号，源极接入恒压高电位，漏极电性连接于第二P型薄膜晶体管的漏极、第三N型薄膜晶体管的漏极、及第九P型薄膜晶体管的栅极；
    第四N型薄膜晶体管，所述第四N型薄膜晶体管的栅极接入触控控制信号，源极接入恒压低电位，漏极电性连接于第二P型薄膜晶体管的源极、第三N型薄膜晶体管的源极、及第十N型薄膜晶体管的栅极；
    第五N型薄膜晶体管，所述第五N型薄膜晶体管的栅极电性连接于第二反相器的输出端，源极接入恒压低电位，漏极电性连接于第二P型薄膜晶体管的源极、第三N型薄膜晶体管的源极、及第十N型薄膜晶体管的栅极；
    第九P型薄膜晶体管，所述第九P型薄膜晶体管的源极接入恒压高电位，漏极电性连接于栅极扫描驱动信号输出端；
    第十N型薄膜晶体管，所述第十N型薄膜晶体管的源极接入恒压低电位，漏极电性连接于栅极扫描驱动信号输出端；
    所述第一直流控制信号与第二直流控制信号的电位相反；
    在正常显示阶段，所述触控控制信号为低电位，反相触控控制信号为高电位，触控扫描驱动信号提供低电位；在触控扫描阶段，所述触控控制信号为高电位，反相触控控制信号为低电位，触控扫描驱动信号提供周期性脉冲信号，所述栅极扫描驱动信号输出端悬空，输出的栅极扫描驱动信号呈高阻态，跟随触控扫描驱动信号在高、低电位之间跳变而发生同样的高、低电位跳变。
  2. 如权利要求1所述的适用于In Cell型触控显示面板的GOA电路，其中，在第一级GOA单元中，所述第一传输门的输入端接入电路的起始信号。
  3. 如权利要求1所述的适用于In Cell型触控显示面板的GOA电路，其中，在最后一级GOA单元中，所述第二传输门的输入端接入电路的起始信号。
  4. 如权利要求1所述的适用于In Cell型触控显示面板的GOA电路，其中，所述第一反相器包括：一N型薄膜晶体管与一P型薄膜晶体管，所述N型薄膜晶体管的栅极与P型薄膜晶体管的栅极电性连接作为输入端，N型薄膜晶体管的漏极与P型薄膜晶体管的漏极电性连接作为输出端，N型薄膜晶体管的源极接入恒压低电位，P型薄膜晶体管的源极接入恒压高电位。
  5. 如权利要求1所述的适用于In Cell型触控显示面板的GOA电路，其中，所述第一与第二时钟控制反相器均包括：两串联的N型薄膜晶体管与两串联的P型薄膜晶体管，其中一个P型薄膜晶体管的栅极作为时钟控制反相器的低电位控制端，源极接入恒压高电位，漏极电性连接于另一个P型薄膜晶体管的源极；一个N型薄膜晶体管栅极作为时钟控制反相器的高电位控制端，源极接入恒压低电位，漏极电性连接于另一个N型薄膜晶体管的源极；另一个N型薄膜晶体管的栅极与另一个P型薄膜晶体管的栅极电性连接作为时钟控制反相器的输入端，另一个N型薄膜晶体管的漏极与另一个P型薄膜晶体管的漏极电性连接作为时钟控制反相器的输出端。
  6. 如权利要求1所述的适用于In Cell型触控显示面板的GOA电路，其中，所述第一和第二传输门均包括：相对设置的一N型薄膜晶体管与一P型薄膜晶体管，所述N型薄膜晶体管的栅极作为传输门的高电位控制端，所述P型薄膜晶体管的栅极作为传输门的低电位控制端，N型薄膜晶体管的源极与P型薄膜晶体管的源极电性连接作为传输门的输入端，N型薄膜晶体管的漏极与P型薄膜晶体管的漏极电性连接作为传输门的输出端。
  7. 如权利要求1所述的适用于In Cell型触控显示面板的GOA电路，其中，所述与非门包括：串联的两N型薄膜晶体管与相对设置的两P型薄膜晶体管，其中第一个P型薄膜晶体管的栅极与第一个N型薄膜晶体管的栅极电性连接作为与非门的第一输入端，第二个P型薄膜晶体管的栅极与第二个N型薄膜晶体管的栅极电性连接作为与非门的第二输入端，两个P型薄膜晶体管的源极均接入恒压高电位，两个P型薄膜晶体管的漏极均与第一个N型薄膜晶体管的漏极电性连接作为与非门的输出端，第一个N型 薄膜晶体管的源极与第二个N型薄膜晶体管的漏极电性连接，第二个N型薄膜晶体管的源极接入恒压低电位。
  8. 如权利要求1所述的适用于In Cell型触控显示面板的GOA电路，其中，当所述第一直流控制信号提供低电位且第二直流控制信号提供高电位时，进行正向扫描；当所述第一直流控制信号提供高电位且第二直流控制信号提供低电位时，进行反向扫描。
  9. 一种适用于In Cell型触控显示面板的GOA电路，包括：级联的多级GOA单元，每一级GOA单元均包括：正反向扫描控制模块、控制输入模块、复位模块、锁存模块、与非门信号处理模块、及输出缓冲模块；
    设N为正整数，除第一级GOA单元与最后一级GOA单元外，在第N级GOA单元中：
    所述正反向扫描控制模块包括：第一传输门，所述第一传输门的低电位控制端接入第一直流控制信号，高电位控制端接入第二直流控制信号，输入端电性连接于上一级第N-1级GOA单元的第一节点，输出端电性连接控制输入模块；以及第二传输门，所述第二传输门的高电位控制端接入第一直流控制信号，低电位控制端接入第二直流控制信号，输入端电性连接于下一级第N+1级GOA单元的第一节点，输出端电性连接控制输入模块；第N-1级GOA单元的第一节点的电位作为正向扫描级传信号，第N+1级GOA单元的第一节点的电位作为反向扫描级传信号；
    所述控制输入模块包括：第一时钟控制反相器，所述第一时钟控制反相器的高电位控制端接入第M条时钟信号，低电位控制端接入第M条反相时钟信号，输入端电性连接于第一传输门的输出端及第二传输门的输出端，输出端电性连接于第二节点；
    所述复位模块包括：第十一P型薄膜晶体管，所述第十一P型薄膜晶体管的栅极接入复位信号，源极接入恒压高电位，漏极电性连接于第二节点；
    所述锁存模块包括：第二时钟控制反相器，所述第二时钟控制反相器的低电位控制端接入第M条时钟信号，高电位控制端接入第M条反相时钟信号，输入端电性连接于第一节点，输出端电性连接于第二节点；以及第一反相器，所述第一反相器的输入端电性连接于第二节点，输出端电性连接于第一节点；
    所述与非门信号处理模块包括：与非门，所述与非门的第一输入端电性连接于第一节点，第二输入端接入第M+2条时钟信号，输出端电性连接输出缓冲模块；
    所述输出缓冲模块包括：
    由第七P型薄膜晶体管与第八N型薄膜晶体管构成的第二反相器；所述第七P型薄膜晶体管的栅极电性连接于第八N型薄膜晶体管的栅极作为第二反相器的输入端并电性连接于与非门的输出端，所述第七P型薄膜晶体管的漏极电性连接于第八N型薄膜晶体管的漏极作为第二反相器的输出端，所述第七P型薄膜晶体管的源极接入恒压高电位，所述第八N型薄膜晶体管的源极接入恒压低电位；
    由第二P型薄膜晶体管与第三N型薄膜晶体管构成的第三传输门；所述第二P型薄膜晶体管的栅极作为第三传输门的低电位控制端接入触控控制信号，所述第三N型薄膜晶体管的栅极作为第三传输门的高电位控制端接入反相触控控制信号，所述第二P型薄膜晶体管的源极与第三N型薄膜晶体管的源极电性连接，所述第二P型薄膜晶体管的漏极与第三N型薄膜晶体管的漏极电性连接，分别作为第三传输门的输入端与输出端；
    第六P型薄膜晶体管，所述第六P型薄膜晶体的栅极电性连接于第二反相器的输出端，源极接入恒压高电位，漏极电性连接于第二P型薄膜晶体管的漏极、第三N型薄膜晶体管的漏极、及第九P型薄膜晶体管的栅极；
    第一P型薄膜晶体管，所述第一P型薄膜晶体管的栅极接入反相触控控制信号，源极接入恒压高电位，漏极电性连接于第二P型薄膜晶体管的漏极、第三N型薄膜晶体管的漏极、及第九P型薄膜晶体管的栅极；
    第四N型薄膜晶体管，所述第四N型薄膜晶体管的栅极接入触控控制信号，源极接入恒压低电位，漏极电性连接于第二P型薄膜晶体管的源极、第三N型薄膜晶体管的源极、及第十N型薄膜晶体管的栅极；
    第五N型薄膜晶体管，所述第五N型薄膜晶体管的栅极电性连接于第二反相器的输出端，源极接入恒压低电位，漏极电性连接于第二P型薄膜晶体管的源极、第三N型薄膜晶体管的源极、及第十N型薄膜晶体管的栅极；
    第九P型薄膜晶体管，所述第九P型薄膜晶体管的源极接入恒压高电位，漏极电性连接于栅极扫描驱动信号输出端；
    第十N型薄膜晶体管，所述第十N型薄膜晶体管的源极接入恒压低电位，漏极电性连接于栅极扫描驱动信号输出端；
    所述第一直流控制信号与第二直流控制信号的电位相反；
    在正常显示阶段，所述触控控制信号(TCK)为低电位，反相触控控制信号为高电位，触控扫描驱动信号提供低电位；在触控扫描阶段，所述触控控制信号为高电位，反相触控控制信号为低电位，触控扫描驱动信号 提供周期性脉冲信号，所述栅极扫描驱动信号输出端悬空，输出的栅极扫描驱动信号呈高阻态，跟随触控扫描驱动信号在高、低电位之间跳变而发生同样的高、低电位跳变；
    其中，在第一级GOA单元中，所述第一传输门的输入端接入电路的起始信号；
    其中，在最后一级GOA单元中，所述第二传输门的输入端接入电路的起始信号；
    其中，所述第一反相器包括：一N型薄膜晶体管与一P型薄膜晶体管，所述N型薄膜晶体管的栅极与P型薄膜晶体管的栅极电性连接作为输入端，N型薄膜晶体管的漏极与P型薄膜晶体管的漏极电性连接作为输出端，N型薄膜晶体管的源极接入恒压低电位，P型薄膜晶体管的源极接入恒压高电位。
  10. 如权利要求9所述的适用于In Cell型触控显示面板的GOA电路，其中，所述第一与第二时钟控制反相器均包括：两串联的N型薄膜晶体管与两串联的P型薄膜晶体管，其中一个P型薄膜晶体管的栅极作为时钟控制反相器的低电位控制端，源极接入恒压高电位，漏极电性连接于另一个P型薄膜晶体管的源极；一个N型薄膜晶体管栅极作为时钟控制反相器的高电位控制端，源极接入恒压低电位，漏极电性连接于另一个N型薄膜晶体管的源极；另一个N型薄膜晶体管的栅极与另一个P型薄膜晶体管的栅极电性连接作为时钟控制反相器的输入端，另一个N型薄膜晶体管的漏极与另一个P型薄膜晶体管的漏极电性连接作为时钟控制反相器的输出端。
  11. 如权利要求9所述的适用于In Cell型触控显示面板的GOA电路，其中，所述第一和第二传输门均包括：相对设置的一N型薄膜晶体管与一P型薄膜晶体管，所述N型薄膜晶体管的栅极作为传输门的高电位控制端，所述P型薄膜晶体管的栅极作为传输门的低电位控制端，N型薄膜晶体管的源极与P型薄膜晶体管的源极电性连接作为传输门的输入端，N型薄膜晶体管的漏极与P型薄膜晶体管的漏极电性连接作为传输门的输出端。
  12. 如权利要求9所述的适用于In Cell型触控显示面板的GOA电路，其中，所述与非门包括：串联的两N型薄膜晶体管与相对设置的两P型薄膜晶体管，其中第一个P型薄膜晶体管的栅极与第一个N型薄膜晶体管的栅极电性连接作为与非门的第一输入端，第二个P型薄膜晶体管的栅极与第二个N型薄膜晶体管的栅极电性连接作为与非门的第二输入端，两个P型薄膜晶体管的源极均接入恒压高电位，两个P型薄膜晶体管的漏极均与第一个N型薄膜晶体管的漏极电性连接作为与非门的输出端，第一个N型 薄膜晶体管的源极与第二个N型薄膜晶体管的漏极电性连接，第二个N型薄膜晶体管的源极接入恒压低电位。
  13. 如权利要求9所述的适用于In Cell型触控显示面板的GOA电路，其中，当所述第一直流控制信号提供低电位且第二直流控制信号提供高电位时，进行正向扫描；当所述第一直流控制信号提供高电位且第二直流控制信号提供低电位时，进行反向扫描。
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