WO2017107236A1 - 像素单元以及阵列基板 - Google Patents

像素单元以及阵列基板 Download PDF

Info

Publication number
WO2017107236A1
WO2017107236A1 PCT/CN2015/099709 CN2015099709W WO2017107236A1 WO 2017107236 A1 WO2017107236 A1 WO 2017107236A1 CN 2015099709 W CN2015099709 W CN 2015099709W WO 2017107236 A1 WO2017107236 A1 WO 2017107236A1
Authority
WO
WIPO (PCT)
Prior art keywords
metal layer
pixel unit
storage capacitor
thin film
film transistor
Prior art date
Application number
PCT/CN2015/099709
Other languages
English (en)
French (fr)
Inventor
吕晓文
Original Assignee
深圳市华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市华星光电技术有限公司 filed Critical 深圳市华星光电技术有限公司
Priority to US14/913,999 priority Critical patent/US20180031930A1/en
Publication of WO2017107236A1 publication Critical patent/WO2017107236A1/zh

Links

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136213—Storage capacitors associated with the pixel electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3607—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals for displaying colours or for displaying grey scales with a specific pixel layout, e.g. using sub-pixels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/642—Capacitive arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H01L28/92—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by patterning layers, e.g. by etching conductive layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/40—Arrangements for improving the aperture ratio
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer

Definitions

  • the present invention relates to the field of liquid crystal display, and in particular to a pixel unit and an array substrate.
  • a flat panel display represented by a liquid crystal LCD and an organic light emitting diode (OLED) has been developed in the direction of large size and high resolution, and the thin film transistor TFT has been widely concerned as a core component of the flat panel display industry.
  • the thin film transistors commonly used in the prior art include amorphous silicon thin film transistors and oxide thin film transistors. Since the oxide thin film transistor has the advantage of high carrier mobility, it is not necessary to greatly change the advantages of the existing liquid crystal panel production line when introducing. And it has been widely used.
  • the resolution requirement of the liquid crystal display screen is also higher and higher.
  • the TFT is required to have sufficient potential during display, and therefore, the display is During the preparation process, a storage capacitor is set in the pixel unit to ensure the potential.
  • the storage capacitor is generally formed by sandwiching an insulating layer with a metal electrode, the metal is opaque, which causes a decrease in the aperture ratio of the display, which affects the display effect.
  • the technical problem to be solved by the present invention is to provide a pixel unit and an array substrate, which can effectively improve the aperture ratio of the liquid crystal display device while ensuring the resolution of the liquid crystal display device.
  • a technical solution adopted by the present invention is to provide a pixel unit including: a thin film transistor TFT and a storage capacitor electrically connected to the thin film transistor TFT, wherein the storage capacitor includes a relative setting a first metal layer and a second metal layer, the first metal layer being provided with a concave-convex pattern on one side of the second metal layer; the concave-convex pattern is formed by providing a groove on a surface of the first metal layer Form a grid structure.
  • the concave-convex pattern is formed by processing the first metal layer by at least one of imprinting, laser processing, and photolithography.
  • the insulating layer is filled between the first metal layer and the second metal layer.
  • the pixel unit further includes a pixel electrode, and the pixel electrode is connected in parallel with the storage capacitor.
  • the thin film transistor TFT is an oxide thin film transistor.
  • a pixel unit including: a thin film transistor TFT and a storage capacitor connected to the drain of the TFT, the storage capacitor including a relative setting And a first metal layer and a second metal layer, wherein the first metal layer is provided with a concave-convex pattern on one side of the second metal layer.
  • the concave-convex pattern is formed by providing a groove on a surface of the first metal layer.
  • the concave and convex pattern is formed by processing the first metal layer by at least one of imprinting, laser processing, and photolithography.
  • the type of the concave-convex pattern includes a mesh structure.
  • the insulating layer is filled between the first metal layer and the second metal layer.
  • the pixel unit further includes a pixel electrode, and the pixel electrode is connected in parallel with the storage capacitor.
  • the thin film transistor TFT is an oxide thin film transistor.
  • an array substrate comprising a pixel unit composed of a plurality of intersecting and non-intersecting scan lines and data lines
  • the pixel unit includes a thin film transistor TFT and a storage capacitor connected to the drain of the TFT, the storage capacitor includes a first metal layer and a second metal layer disposed opposite to each other, the first metal layer being opposite to the second metal layer
  • a concave and convex pattern is provided on one side.
  • the concave-convex pattern is formed by providing a groove on a surface of the first metal layer.
  • the concave and convex pattern is formed by processing the first metal layer by at least one of imprinting, laser processing, and photolithography.
  • the type of the concave-convex pattern includes a mesh structure.
  • the insulating layer is filled between the first metal layer and the second metal layer.
  • the pixel unit further includes a pixel electrode, and the pixel electrode is connected in parallel with the storage capacitor.
  • the thin film transistor TFT is an oxide thin film transistor.
  • the pixel unit of the present embodiment includes a thin film transistor TFT and a storage capacitor electrically connected to the thin film transistor TFT, and the storage capacitor includes a first metal layer and a second oppositely disposed.
  • the first metal layer is provided with a concave-convex pattern on one surface of the second metal layer.
  • FIG. 1 is a cross-sectional structural view showing an embodiment of a pixel unit of the present invention
  • FIG. 2 is a schematic structural view of an embodiment of a storage capacitor of the present invention.
  • FIG. 3 is a top plan view showing an embodiment of a first metal layer of a storage capacitor of the present invention
  • FIG. 4 is a schematic structural view of an embodiment of an array substrate of the present invention.
  • FIG. 1 is a cross-sectional structural diagram of an embodiment of a pixel unit of the present invention.
  • the pixel unit of the present embodiment includes a thin film transistor TFT 101 and a storage capacitor 102 electrically connected to the thin film transistor TFT, wherein the storage capacitor 102 includes a first metal layer 1021 and a second metal layer disposed opposite to each other. 1022, the thin film transistor TFT101 includes an oxide thin film transistor, and may be other types of transistors, as long as it can function as a switch, which is not limited herein.
  • the thin film transistor TFT 101 includes a gate electrode 1012 disposed on the glass substrate 1011, an insulating layer 1013 formed on the gate electrode 1012, and an active layer 1014 disposed over the insulating layer 1013, further including two ends of the active layer 1014.
  • a source 1015 and a drain 1016 of a portion of the active layer 1014 are separated and exposed by a channel.
  • a passivation layer 1017 and a flat layer 1018 are further disposed on the surface of the pixel electrode, and a touch electrode 1019 is further disposed to electrically connect the storage capacitor 102.
  • the pixel unit further includes a pixel electrode (not shown), and the pixel electrode and the storage capacitor are electrically connected to the thin film transistor TFT through the touch electrode
  • the gate 1012 of the thin film transistor TFT 101 is electrically connected to the scan line, and the scan line is used for the TFT 101 to provide a control signal for the thin film transistor, and the thin film transistor TFT
  • the source 1015 of 101 is electrically coupled to a data line that provides a data drive signal for the pixel unit.
  • an operating voltage is supplied to the pixel electrode, and a charging voltage is also supplied to the storage capacitor 102.
  • the storage capacitor stores the charge to complement the TFT of the thin film transistor. The potential required for the pixel electrode when 101 is turned off.
  • the first metal layer 1021 is provided with a concavo-convex pattern with respect to one surface of the second metal layer 1022.
  • FIG. 2 is a schematic diagram of the refinement structure of the storage capacitor 102 of FIG. 1.
  • the first metal layer 201 is provided with a concave-convex pattern 2011 opposite to the surface of the second metal layer 202.
  • an insulating layer 203 is further interposed between the first metal layer 201 and the second metal layer 202, and the insulating layer 203 includes an inorganic oxide such as silicon dioxide, and may also be other insulating materials, and is not used here. limited.
  • the surface of the first metal layer 201 is provided with a undulating concave-convex pattern.
  • the position of the storage capacitor can be reduced, and the aperture ratio of the liquid crystal display device can be increased.
  • the concave-convex pattern may be processed by at least one of imprinting, laser processing or photolithography to form undulating grooves on the surface of the first metal layer 201, thereby forming irregularities of different shapes.
  • the pattern increases the surface area of the first metal layer 201.
  • the embossing process is to place the sheet material between the upper and lower molds, and the thickness of the material is changed under the action of pressure, and the material outside the extrusion is filled in the mold cavity convex and concave with the undulating fine lines.
  • a forming method for forming the undulating bulge and the typeface or pattern is obtained on the surface of the workpiece.
  • Laser processing is to engrave various concave and convex patterns on the surface of the first metal layer by laser.
  • the photolithography process refers to a process of removing a specific portion on the surface of the first metal layer to leave a uneven pattern on the first metal layer. In the present embodiment, as long as the uneven pattern of the high and low undulations can be formed on the surface of the first metal layer 201, it is not limited herein.
  • the specific presentation form of the concave-convex pattern is not limited, such as a grid structure, as shown in FIG. 3, in other embodiments, any animal shape, a specific Chinese character structure, etc., as long as the relative position of the first metal layer can be increased.
  • the surface area can be.
  • the first metal layer 201 may directly form a storage capacitor with the pixel electrode of the thin film transistor TFT, which is not limited herein.
  • the pixel unit of the present embodiment includes a thin film transistor TFT and a storage capacitor electrically connected to the TFT, the storage capacitor includes a first metal layer and a second metal layer disposed opposite to each other, the first metal layer is opposite to the first metal layer One side of the second metal layer is provided with a concavo-convex pattern.
  • the concave-convex pattern By forming a concave-convex pattern on the first metal layer, the facing area of the first metal layer and the second metal layer at both ends of the storage capacitor is increased, and the capacity of the storage capacitor is further increased, so that it can be changed or even increased.
  • the physical size of the storage capacitor is reduced, the aperture ratio of the liquid crystal display is improved, and the display screen of the liquid crystal display is further improved.
  • FIG. 4 is a schematic structural diagram of an embodiment of an array substrate according to an embodiment of the present invention.
  • the array substrate of the present embodiment includes a plurality of scan lines 401, a plurality of data lines 402, and a plurality of scan surfaces 401 and a plurality of data lines 402. a plurality of pixel units 403 formed by two or two but not intersecting, each of the pixel units 403 including a thin film transistor TFT 4031.
  • the storage capacitor 4032 electrically connected to the TFT further includes a pixel electrode 4033 connected in parallel with the storage capacitor 4032.
  • the thin film transistor TFT 4031 includes an oxide thin film transistor having a gate connected to the scan line 401 for receiving a scan control signal transmitted by the scan line 401, a source connected to the data line 402, receiving a data signal transmitted by the data line 402, and a drain thereof.
  • the storage capacitor 4032 and the pixel electrode 4033 are electrically connected.
  • the storage capacitor 4032 When the thin film transistor TFT4031 turns on the electrical signal, while supplying the operating voltage to the pixel electrode 4033, the storage capacitor 4032 is also supplied with a charging voltage, and the storage capacitor stores the electric charge to supplement the TFT of the thin film transistor. The potential required for the pixel electrode 4033 when 4031 is turned off.
  • the storage capacitor 4032 includes a first metal layer and a second metal layer disposed opposite to each other.
  • the first metal layer is provided with a concavo-convex pattern with respect to one surface of the second metal layer.
  • the specific appearance of the concave-convex pattern is not limited, such as a mesh structure.
  • any animal shape, a specific Chinese character structure, or the like may be used as long as the relative surface area of the first metal layer can be increased.
  • an insulating layer is disposed between the first metal layer and the second metal layer.
  • the insulating layer includes an inorganic oxide, such as silicon dioxide, and may be other insulating materials, which is not limited herein.
  • C the capacitance capacity formula
  • the surface of the first metal layer is provided with a undulating concave-convex pattern, and by increasing the facing area of the first metal layer and the second metal layer, the storage is increased without changing the storage capacitor volume of the original thin film transistor.
  • the capacity of the capacitor is increased.
  • the position of the storage capacitor can be reduced, and the aperture ratio of the liquid crystal display device can be increased.
  • the concave-convex pattern may be processed by at least one of imprinting, laser processing or photolithography to form undulating grooves on the surface of the first metal layer, thereby forming concave and convex patterns of different shapes. , increasing the surface area of the first metal layer.
  • the embossing process is to place the sheet material between the upper and lower molds, and the thickness of the material is changed under the action of pressure, and the material outside the extrusion is filled in the mold cavity convex and concave with the undulating fine lines.
  • a forming method for forming the undulating bulge and the typeface or pattern is obtained on the surface of the workpiece.
  • Laser processing is to engrave various concave and convex patterns on the surface of the first metal layer by laser.
  • the photolithography process refers to a process of removing a specific portion on the surface of the first metal layer to leave a uneven pattern on the first metal layer. In the present embodiment, as long as a concave and convex pattern of high and low undulations can be formed on the surface of the first metal layer, it is not limited herein.
  • the first metal layer may directly form a storage capacitor with the pixel electrode of the thin film transistor TFT, which is not limited herein.
  • the array substrate of the embodiment includes a pixel unit composed of a plurality of intersecting and non-intersecting scan lines and data lines, and the pixel unit includes a thin film transistor TFT and a storage capacitor electrically connected to the TFT.
  • the storage capacitor includes a first metal layer and a second metal layer disposed opposite to each other, and the first metal layer is provided with a concave-convex pattern on one side of the second metal layer.
  • the present invention further provides a liquid crystal display device comprising the array substrate of any of the above embodiments, further comprising a color filter substrate and liquid crystal molecules sandwiched between the array substrate and the color filter substrate. Let me repeat.

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Nonlinear Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Mathematical Physics (AREA)
  • Optics & Photonics (AREA)
  • Liquid Crystal (AREA)
  • Theoretical Computer Science (AREA)
  • Thin Film Transistor (AREA)

Abstract

一种像素单元以及阵列基板，所述像素单元包括：薄膜晶体管TFT（101）以及与所述TFT（101）电连接的存储电容（102），所述存储电容（102）包括相对设置的第一金属层（1021）和第二金属层（1022），所述第一金属层（1021）相对所述第二金属层（1022）的一面设置有凹凸图案（2011）。能够保证液晶显示装置解析度的前提下，有效提高液晶显示装置的开口率。

Description

像素单元以及阵列基板
【技术领域】
本发明涉及液晶显示领域，特别是涉及一种像素单元以及阵列基板。
【背景技术】
伴随着液晶LCD以及有机发光二极管OLED为代表的平板显示器向着大尺寸、高分辨率的方向发展，薄膜晶体管TFT作为平板显示行业的核心部件，也得到广泛的关注。现有技术中常用的薄膜晶体管包括非晶硅薄膜晶体管以及氧化物薄膜晶体管，由于氧化物薄膜晶体管具有载流子迁移率高的优势，在导入时无需大幅改变现有的液晶面板生产线等优势，而得到了广泛应用。
在液晶显示器得到广泛应用的同时，用户对液晶显示画面的解析度要求也越来越高，为了保证显示过程中高要求的解析度，要求液晶显示器在显示时TFT具有充足的电位，因此，在显示器的制备过程中，会在像素单元中设置存储电容，来保证电位。
然而，由于存储电容一般是由金属电极夹置绝缘层而制成，由于金属不透光，会造成显示器开口率的降低，影响了显示效果。
【发明内容】
本发明主要解决的技术问题是提供一种像素单元以及阵列基板，能够在保证液晶显示装置解析度的前提下，有效提高液晶显示装置的开口率。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种像素单元，所述像素单元包括：薄膜晶体管TFT以及与所述薄膜晶体管TFT电连接的存储电容，所述存储电容包括相对设置的第一金属层和第二金属层，所述第一金属层相对所述第二金属层的一面设置有凹凸图案；所述凹凸图案是通过在所述第一金属层的表面设置凹槽而形成网格结构。
其中，所述凹凸图案是通过压印、激光加工以及光刻中的至少一种工艺对所述第一金属层处理而形成。
其中，所述第一金属层与所述第二金属层之间填充有绝缘层。
其中，所述像素单元还包括像素电极，所述像素电极与所述存储电容并联。
其中，所述薄膜晶体管TFT为氧化物薄膜晶体管。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种像素单元，所述像素单元包括：薄膜晶体管TFT以及与所述TFT漏极连接的存储电容，所述存储电容包括相对设置的第一金属层和第二金属层，所述第一金属层相对所述第二金属层的一面设置有凹凸图案。
其中，所述凹凸图案是通过在所述第一金属层的表面设置凹槽而形成。
其中，所述凹凸图案是通过压印、激光加工以及光刻中的至少一种方式对所述第一金属层进行处理而形成。
其中，所述凹凸图案的类型包括网格结构。
其中，所述第一金属层与所述第二金属层之间填充有绝缘层。
其中，所述像素单元还包括像素电极，所述像素电极与所述存储电容并联。
其中，所述薄膜晶体管TFT为氧化物薄膜晶体管。
为解决上述技术问题，本发明采用的再一个技术方案是：提供一种阵列基板，所述阵列基板包括由多条两两交叉且不相交的扫描线和数据线所组成的像素单元，所述像素单元包括薄膜晶体管TFT以及与所述TFT漏极连接的存储电容，所述存储电容包括相对设置的第一金属层和第二金属层，所述第一金属层相对所述第二金属层的一面设置有凹凸图案。
其中，所述凹凸图案是通过在所述第一金属层的表面设置凹槽而形成。
其中，所述凹凸图案是通过压印、激光加工以及光刻中的至少一种方式对所述第一金属层进行处理而形成。
其中，所述凹凸图案的类型包括网格结构。
其中，所述第一金属层与所述第二金属层之间填充有绝缘层。
其中，所述像素单元还包括像素电极，所述像素电极与所述存储电容并联。
其中，所述薄膜晶体管TFT为氧化物薄膜晶体管。
本发明的有益效果是：区别于现有技术的情况，本实施方式的像素单元包括薄膜晶体管TFT以及与薄膜晶体管TFT电连接的存储电容，该存储电容包括相对设置的第一金属层和第二金属层，所述第一金属层相对所述第二金属层的一面设置有凹凸图案。通过在第一金属层的表现形成凹凸图案，增大了存储电容两端的第一金属层与第二金属层的正对面积，进一步增大了存储电容的容量，因此，能够在不改变甚至增大存储电容容量的前提下，减小存储电容的物理大小，提高了液晶显示器的开口率，进一步改善了液晶显示器的显示画面。
【附图说明】
图1是本发明像素单元一实施方式的剖面结构示意图；
图2是本发明存储电容一实施方式的结构示意图；
图3是本发明存储电容的第一金属层一实施方式的俯视示意图；
图4是本发明阵列基板一实施方式的结构示意图。
【具体实施方式】
参阅图1，图1是本发明像素单元一实施方式的剖面结构示意图。如图1所示，本实施方式的像素单元包括薄膜晶体管TFT101以及与所述薄膜晶体管TFT电连接的存储电容102，其中，该存储电容102包括相对设置的第一金属层1021以及第二金属层1022，该薄膜晶体管TFT101包括氧化物薄膜晶体管，还可以为其他类型的晶体管，只要能起到开关作用即可，在此不做限定。
如图1所示，薄膜晶体管TFT 101包括设置在玻璃基板上1011上的栅极1012，栅极1012上形成的有绝缘层1013、设置在绝缘层1013上方的有源层1014、还包括分隔在该有源层1014的两端，以一沟道分开并暴露部分有源层1014的源极1015以及漏极1016。在像素电极的表面还设置有钝化层1017以及平坦层1018，还设置有触控电极1019以电连接该存储电容102。
进一步地，所述像素单元还包括像素电极（图中未示出），像素电极与存储电容通过触控电极电连接在薄膜晶体管TFT 101的漏极1016上，该薄膜晶体管TFT 101的栅极1012电连接在扫描线上，该扫描线为TFT 101提薄膜晶体管供控制信号，薄膜晶体管TFT 101的源极1015电连接在数据线上，该数据线为该像素单元提供数据驱动信号。具体地，在该薄膜晶体管TFT101接通电信号时，在为像素电极提供工作电压的同时，也为该存储电容102提供充电电压，该存储电容将该电荷进行存储，以补充在该薄膜晶体管TFT 101断开时像素电极所需要的电位。
为了给像素电极提供足够的电压，进一步地，第一金属层1021相对于第二金属层1022的一面设置有凹凸图案。具体地，如图2所示，图2为图1中存储电容102的细化结构示意图，第一金属层201相对第二金属层202的表面设置有凹凸图案2011。
另外，在第一金属层201与第二金属层202之间还夹置有绝缘层203，，该绝缘层203包括无机氧化物，如二氧化硅，也可以为其他绝缘物质，在此不做限定。
具体地，当在第一金属层201的表面设置了起伏不平的凹凸图案，能够有效增大形成存储电容电极的相对正对面积，根据电容容量公式C=εS/(4κπd)，其中，ε、κ、π均为常数，S为第一金属层401和第二金属层402的正对面积，d为第一金属层201和第二金属层202的相对距离，在相对距离d保持不变的条件下，正对面积S越大，存储电容的容量就越大。
因此，第一金属层201的表面设置起伏不平的凹凸图案，通过增大第一金属层201和第二金属层202的正对面积，在不改变原有薄膜晶体管的存储电容体积的前提下，增大存储电容的容量。
另外，还可以通过在以上述方式增加存储电容容量的基础上，减小存储电容的所占位置，增大液晶显示装置的开口率。
其中，该凹凸图案可通过压印、激光加工或者光刻中的至少一种工艺对第一金属层进行处理，以在第一金属层201的表面形成起伏的凹槽，从而形成不同形状的凹凸图案，增加第一金属层201的表面积。
其中，压印工艺是将板料放在上、下模之间，在压力作用下使其材料厚度发生变化，并将挤压外的材料，充塞在有起伏细纹的模具形腔凸、凹处，而在工件表面得到形成起伏鼓凸及字样或花纹的一种成形方法。激光加工是通过激光在第一金属层表面雕刻各种凹凸图案。光刻工艺是指在第一金属层的表面将特定部分除去，以在第一金属层上留下凸凹不平的图案的工艺。应用到本实施方式中，只要能在第一金属层201的表面形成高低起伏的凹凸图案，在此不做限定。
所述凹凸图案的具体呈现形式不做限定，如网格结构，如图3所示，在其他实施方式中，还可以是任意动物形状，具体汉字结构等，只要能增加第一金属层的相对表面积即可。
在另一个实施方式中，第一金属层201也可以直接与薄膜晶体管TFT的像素电极构成存储电容，在此不做限定。
区别于现有技术，本实施方式的像素单元包括薄膜晶体管TFT以及与TFT电连接的存储电容，该存储电容包括相对设置的第一金属层和第二金属层，所述第一金属层相对所述第二金属层的一面设置有凹凸图案。通过在第一金属层的表现形成凹凸图案，增大了存储电容两端的第一金属层与第二金属层的正对面积，进一步增大了存储电容的容量，因此，能够在不改变甚至增大存储电容容量的前提下，减小存储电容的物理大小，提高了液晶显示器的开口率，进一步改善了液晶显示器的显示画面。
参阅图4，图4是本发明阵列基板一实施方式的结构示意图，本实施方式的阵列基板包括多条扫描线401，多条数据线402以及该多条扫面先401与多条数据线402两两交叉却不相交所组成的多个像素单元403，每个像素单元403包括一薄膜晶体管TFT 4031，与该TFT电连接的存储电容4032，还包括与该存储电容4032并联的像素电极4033。其中，该薄膜晶体管TFT 4031包括氧化物薄膜晶体管，其栅极与该扫描线401连接，以接收扫描线401传输的扫描控制信号，其源极与数据线402连接，接收数据线402传输的数据信号，其漏极与存储电容4032以及像素电极4033电连接。
在该薄膜晶体管TFT4031接通电信号时，在为像素电极4033提供工作电压的同时，也为该存储电容4032提供充电电压，该存储电容将该电荷进行存储，以补充在该薄膜晶体管TFT 4031断开时像素电极4033所需要的电位。
进一步地，存储电容4032包括相对设置的第一金属层以及第二金属层。为了给像素电极4033提供足够的电压，进一步地，第一金属层相对于第二金属层的一面设置有凹凸图案。
具体地，该凹凸图案具体呈现形式不做限定，如网格结构，在其他实施方式中，还可以是任意动物形状，具体汉字结构等，只要能增加第一金属层的相对表面积即可。
另外，在第一金属层与第二金属层之间还夹置有绝缘层，该绝缘层包括无机氧化物，如二氧化硅，也可以为其他绝缘物质，在此不做限定。
具体地，当在第一金属层的表面设置了起伏不平的凹凸图案，能够有效增大形成存储电容电极的相对正对面积，根据电容容量公式C=εS/(4κπd)，其中，ε、κ、π均为常数，S为第一金属层401和第二金属层402的正对面积，d为第一金属层和第二金属层的相对距离，在相对距离d保持不变的条件下，正对面积S越大，存储电容的容量就越大。
因此，第一金属层的表面设置起伏不平的凹凸图案，通过增大第一金属层和第二金属层的正对面积，在不改变原有薄膜晶体管的存储电容体积的前提下，增大存储电容的容量。
另外，还可以通过在以上述方式增加存储电容容量的基础上，减小存储电容的所占位置，增大液晶显示装置的开口率。
其中，该凹凸图案可通过压印、激光加工或者光刻中的至少一种工艺对第一金属层进行处理，以在第一金属层的表面形成起伏的凹槽，从而形成不同形状的凹凸图案，增加第一金属层的表面积。
其中，压印工艺是将板料放在上、下模之间，在压力作用下使其材料厚度发生变化，并将挤压外的材料，充塞在有起伏细纹的模具形腔凸、凹处，而在工件表面得到形成起伏鼓凸及字样或花纹的一种成形方法。激光加工是通过激光在第一金属层表面雕刻各种凹凸图案。光刻工艺是指在第一金属层的表面将特定部分除去，以在第一金属层上留下凸凹不平的图案的工艺。应用到本实施方式中，只要能在第一金属层的表面形成高低起伏的凹凸图案，在此不做限定。
在另一个实施方式中，第一金属层也可以直接与薄膜晶体管TFT的像素电极构成存储电容，在此不做限定。
区别于现有技术，本实施方式的阵列基板包括由多条两两交叉且不相交的扫描线和数据线所组成的像素单元，像素单元包括薄膜晶体管TFT以及与TFT电连接的存储电容，该存储电容包括相对设置的第一金属层和第二金属层，所述第一金属层相对所述第二金属层的一面设置有凹凸图案。通过在第一金属层的表现形成凹凸图案，增大了存储电容两端的第一金属层与第二金属层的正对面积，进一步增大了存储电容的容量，因此，能够在不改变甚至增大存储电容容量的前提下，减小存储电容的物理大小，提高了液晶显示器的开口率，进一步改善了液晶显示器的显示画面。
另外，本发明还提供一种液晶显示装置，该液晶显示装置包括上述任意实施方式的阵列基板，还包括彩膜基板以及夹持在该阵列基板与彩膜基板之间的液晶分子，在此不再赘述。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (19)

  1. 一种像素单元，其中，所述像素单元包括：薄膜晶体管TFT以及与所述薄膜晶体管TFT电连接的存储电容，所述存储电容包括相对设置的第一金属层和第二金属层，所述第一金属层相对所述第二金属层的一面设置有凹凸图案；所述凹凸图案是通过在所述第一金属层的表面设置凹槽而形成网格结构。
  2. 根据权利要求1所述的像素单元，其中，所述凹凸图案是通过压印、激光加工以及光刻中的至少一种工艺对所述第一金属层处理而形成。
  3. 根据权利要求1所述的像素单元，其中，所述第一金属层与所述第二金属层之间填充有绝缘层。
  4. 根据权利要求1所述的像素单元，其中，所述像素单元还包括像素电极，所述像素电极与所述存储电容并联。
  5. 根据权利要求1所述的像素电极，其中，所述薄膜晶体管TFT为氧化物薄膜晶体管。
  6. 一种像素单元，其中，所述像素单元包括：薄膜晶体管TFT以及与所述薄膜晶体管TFT电连接的存储电容，所述存储电容包括相对设置的第一金属层和第二金属层，所述第一金属层相对所述第二金属层的一面设置有凹凸图案。
  7. 根据权利要求6所述的像素单元，其中，所述凹凸图案是通过在所述第一金属层的表面设置凹槽而形成。
  8. 根据权利要求6所述的像素单元，其中，所述凹凸图案是通过压印、激光加工以及光刻中的至少一种工艺对所述第一金属层处理而形成。
  9. 根据权利要求6所述的像素单元，其中，所述凹凸图案的类型包括网格结构。
  10. 根据权利要求6所述的像素单元，其中，所述第一金属层与所述第二金属层之间填充有绝缘层。
  11. 根据权利要求6所述的像素单元，其中，所述像素单元还包括像素电极，所述像素电极与所述存储电容并联。
  12. 根据权利要求6所述的像素电极，其中，所述薄膜晶体管TFT为氧化物薄膜晶体管。
  13. 一种阵列基板，所述阵列基板包括由多条两两交叉且不相交的扫描线和数据线所组成的像素单元，其中，所述像素单元包括薄膜晶体管TFT以及与所述TFT漏极连接的存储电容，所述存储电容包括相对设置的第一金属层和第二金属层，所述第一金属层相对所述第二金属层的一面设置有凹凸图案。
  14. 根据权利要求13所述的阵列基板，其中，所述凹凸图案是通过在所述第一金属层的表面设置凹槽而形成。
  15. 根据权利要求13所述的阵列基板，其中，所述凹凸图案是通过压印、激光加工以及光刻中的至少一种方式对所述第一金属层进行处理而形成。
  16. 根据权利要求13所述的阵列基板，其中，所述凹凸图案的类型包括网格结构。
  17. 根据权利要求13所述的阵列基板，其中，所述第一金属层与所述第二金属层之间填充有绝缘层。
  18. 根据权利要求13所述的阵列基板，其中，所述像素单元还包括像素电极，所述像素电极与所述存储电容并联。
  19. 根据权利要求13所述的阵列基板，其中，所述薄膜晶体管TFT为氧化物薄膜晶体管。
PCT/CN2015/099709 2015-12-21 2015-12-30 像素单元以及阵列基板 WO2017107236A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US14/913,999 US20180031930A1 (en) 2015-12-21 2015-12-30 Pixel unit and array substrate

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201510966877.0A CN105575976A (zh) 2015-12-21 2015-12-21 像素单元以及阵列基板
CN201510966877.0 2015-12-21

Publications (1)

Publication Number Publication Date
WO2017107236A1 true WO2017107236A1 (zh) 2017-06-29

Family

ID=55885927

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2015/099709 WO2017107236A1 (zh) 2015-12-21 2015-12-30 像素单元以及阵列基板

Country Status (3)

Country Link
US (1) US20180031930A1 (zh)
CN (1) CN105575976A (zh)
WO (1) WO2017107236A1 (zh)

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1403853A (zh) * 2002-09-05 2003-03-19 统宝光电股份有限公司 应用于平面显示器上的储存电容结构及其形成方法
CN1651985A (zh) * 2005-03-11 2005-08-10 广辉电子股份有限公司 一种液晶显示装置及其下基板的制造方法
US20070153149A1 (en) * 2006-01-02 2007-07-05 Wintek Tft substrate, liquid crystal display panel, and methods for manufacturing the same
KR20070111029A (ko) * 2006-05-16 2007-11-21 삼성전자주식회사 박막 트랜지스터 기판 및 그의 제조 방법
CN102023428A (zh) * 2009-09-23 2011-04-20 北京京东方光电科技有限公司 Tft-lcd阵列基板及其制造方法
CN103824865A (zh) * 2014-02-14 2014-05-28 京东方科技集团股份有限公司 一种阵列基板及其制备方法和显示装置
CN105116642A (zh) * 2015-09-24 2015-12-02 京东方科技集团股份有限公司 阵列基板及其制作方法、显示装置

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100754126B1 (ko) * 2005-11-23 2007-08-30 삼성에스디아이 주식회사 액정표시장치 어레이 기판 및 그 제조방법
KR101084273B1 (ko) * 2010-03-03 2011-11-16 삼성모바일디스플레이주식회사 유기 발광 표시 장치 및 그 제조 방법

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1403853A (zh) * 2002-09-05 2003-03-19 统宝光电股份有限公司 应用于平面显示器上的储存电容结构及其形成方法
CN1651985A (zh) * 2005-03-11 2005-08-10 广辉电子股份有限公司 一种液晶显示装置及其下基板的制造方法
US20070153149A1 (en) * 2006-01-02 2007-07-05 Wintek Tft substrate, liquid crystal display panel, and methods for manufacturing the same
KR20070111029A (ko) * 2006-05-16 2007-11-21 삼성전자주식회사 박막 트랜지스터 기판 및 그의 제조 방법
CN102023428A (zh) * 2009-09-23 2011-04-20 北京京东方光电科技有限公司 Tft-lcd阵列基板及其制造方法
CN103824865A (zh) * 2014-02-14 2014-05-28 京东方科技集团股份有限公司 一种阵列基板及其制备方法和显示装置
CN105116642A (zh) * 2015-09-24 2015-12-02 京东方科技集团股份有限公司 阵列基板及其制作方法、显示装置

Also Published As

Publication number Publication date
US20180031930A1 (en) 2018-02-01
CN105575976A (zh) 2016-05-11

Similar Documents

Publication Publication Date Title
WO2014036730A1 (zh) 一种显示面板及液晶显示装置
WO2017024599A1 (zh) 一种具有触控功能的阵列基板及显示装置
WO2019041476A1 (zh) 一种阵列基板及其制作方法、显示面板
WO2017197693A1 (zh) 3t像素结构及液晶显示装置
WO2018006479A1 (zh) 阵列基板及其制作方法、以及液晶显示面板
WO2016149957A1 (zh) 液晶显示装置、液晶显示器及其制作方法和暗点作业方法
WO2017219421A1 (zh) 一种tft阵列基板及其制作方法、液晶显示装置
WO2016078204A1 (zh) 一种液晶显示面板及阵列基板
WO2013149467A1 (zh) 阵列基板及其制作方法和显示装置
WO2018032551A1 (zh) 液晶显示面板及液晶显示装置
WO2019019427A1 (zh) 金属网板及蒸镀掩膜装置
WO2016078133A1 (zh) 液晶显示面板及其彩膜阵列基板
WO2017015993A1 (zh) 液晶显示器及其液晶面板
WO2017124596A1 (zh) 液晶显示面板及液晶显示装置
WO2018040468A1 (zh) 显示器及其显示面板
WO2019015077A1 (zh) 一种阵列基板及其制造方法、液晶显示装置
WO2016106784A1 (zh) 一种像素结构及液晶显示面板
WO2019000651A1 (zh) 一种柔性背板的制作方法、液晶显示面板以及oled显示面板
WO2016078101A1 (zh) 显示面板及其制造方法
WO2019041553A1 (zh) 像素结构垂直沟道有机薄膜晶体管及其制作方法
WO2017101161A1 (zh) 基于hsd结构的显示面板和显示装置
WO2015006959A1 (zh) 显示面板及显示装置
WO2014121525A1 (zh) 阵列基板、显示装置及阵列基板的制造方法
WO2016173021A1 (zh) 显示面板及显示装置
WO2017181463A1 (zh) 阵列基板及其制造方法、液晶显示器

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 15911233

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 15911233

Country of ref document: EP

Kind code of ref document: A1