WO2014121525A1 - 阵列基板、显示装置及阵列基板的制造方法 - Google Patents

阵列基板、显示装置及阵列基板的制造方法 Download PDF

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Publication number
WO2014121525A1
WO2014121525A1 PCT/CN2013/071662 CN2013071662W WO2014121525A1 WO 2014121525 A1 WO2014121525 A1 WO 2014121525A1 CN 2013071662 W CN2013071662 W CN 2013071662W WO 2014121525 A1 WO2014121525 A1 WO 2014121525A1
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Prior art keywords
dielectric layer
electrode
capacitor
region
capacitor electrode
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PCT/CN2013/071662
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English (en)
French (fr)
Inventor
许宗义
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深圳市华星光电技术有限公司
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Priority to GB1513062.8A priority Critical patent/GB2524212A/en
Priority to JP2015555535A priority patent/JP6063587B2/ja
Priority to DE112013006398.0T priority patent/DE112013006398T5/de
Priority to US13/818,988 priority patent/US20140217410A1/en
Publication of WO2014121525A1 publication Critical patent/WO2014121525A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1339—Gaskets; Spacers; Sealing of cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors

Definitions

  • the present invention relates to the field of liquid crystal displays, and in particular to an array substrate, a display device, and a method of fabricating an array substrate.
  • Liquid crystal panels typically include a color film substrate and an array substrate.
  • the production process of the liquid crystal panel usually includes an array process, a group process, and a module process.
  • the array process mainly includes the production process of the array substrate.
  • the assembly process mainly includes a process of bonding the array substrate and the color filter substrate together.
  • the module process includes FPC (Flexible) Printed Circuit, flexible circuit board, etc. The process of assembling the circuit.
  • the step of bonding the array substrate and the color filter substrate together includes a step of sealing at the frame of the array substrate and the color filter substrate. Specifically, the sealing step includes two steps of potting and curing.
  • OLED Organic Electroluminesence
  • the packaging process of the OLED panel is to cure the sealant by laser baking after the glue is applied.
  • Laser curing temperatures of up to 1000 ° C or even higher.
  • the coating position of the sealant is partially overlapped with the position of the drive electrode. If the sealant is in direct contact with the drive electrode, the peeling of the sealant from the position of the drive electrode is likely to occur during the curing process.
  • the technical problem to be solved by the present invention is to provide an array substrate, a display device, and a method of manufacturing the array substrate, which have an improved sealing effect.
  • a technical solution adopted by the present invention is to provide a method for fabricating an array substrate, the method comprising: providing a substrate; forming a source, a drain, a driving electrode, and a first capacitor electrode on the substrate Forming a first dielectric layer, the first dielectric layer covering the source, the drain, the driving electrode and the first capacitor electrode, the first dielectric layer comprising a first region covering the first capacitor electrode and a second covering the driving electrode a region, a thickness of the second region is greater than a thickness of the first region, a second region is used to form a glass melt thereon; a second capacitor electrode is formed on the first region of the first dielectric layer, and a second capacitor electrode A capacitor electrode and a first dielectric layer therebetween form a first capacitor.
  • the thickness of the first region is 200 to 1000 angstroms, and the thickness of the second region is 1000 to 8000 angstroms.
  • the step of forming the first dielectric layer further includes: forming a pixel electrode on the first dielectric layer, the pixel electrode is connected to the source; forming an organic material layer on the first dielectric layer, and covering the second electrode with the organic material layer The plate, the pixel electrode exposes the organic material layer; and a plurality of protruding spacers are formed on the organic material layer.
  • the step of forming a source, a drain, a driving electrode and a first capacitor electrode on the substrate includes: forming a second dielectric layer on the substrate; forming a semiconductor layer and a third capacitor electrode on the second dielectric layer; forming a third dielectric layer, a third dielectric layer is formed on the second dielectric layer and covers the semiconductor layer and the third capacitor electrode; a gate electrode and a fourth capacitor electrode are formed on the third dielectric layer, the gate electrode and the semiconductor layer Positively, the fourth capacitor electrode, the third capacitor electrode and the third dielectric layer therebetween form a second capacitor; forming a fourth dielectric layer, the fourth dielectric layer being formed on the third dielectric layer and covering the gate and a fourth capacitor electrode; a source, a drain, a first capacitor electrode and a driving electrode are formed on the fourth dielectric layer, and the source and the drain are both connected to the semiconductor layer.
  • an array substrate including a substrate, a driving electrode, a first capacitor, a source, a drain, and a first dielectric layer
  • the first capacitor includes the first The capacitor electrode and the second capacitor electrode, the source, the drain, the driving electrode and the first capacitor electrode are formed on the substrate, and the first dielectric layer covers the source, the drain, the driving electrode and the first capacitor electrode, and the first dielectric
  • the layer includes a first region covering the first capacitor electrode and a second region covering the driving electrode, the thickness of the second region being greater than the thickness of the first region, the second region for forming a glass melt thereon, and the second capacitor electrode forming On the first area.
  • the thickness of the first region is 200 to 1000 angstroms, and the thickness of the second region is 1000 to 8000 angstroms.
  • the array substrate further includes a pixel electrode, an organic material layer and a spacer device.
  • the pixel electrode is formed on the first dielectric layer and connected to the source.
  • the organic material layer is located on the first dielectric layer and covers the second electrode plate, and the pixel electrode is exposed.
  • An organic material layer is formed, and the spacer is convexly disposed on the organic material layer.
  • the second capacitor electrode is a metal material or a transparent conductive material.
  • the array substrate further includes a second dielectric layer, a semiconductor layer, a third dielectric layer, a gate, a fourth dielectric layer, and a second capacitor, the second capacitor includes a third capacitor electrode and a fourth capacitor electrode, and a second The dielectric layer is formed on the substrate, the semiconductor layer and the third capacitor electrode are located between the second dielectric layer and the third dielectric layer, and the gate electrode and the fourth capacitor electrode are located between the third dielectric layer and the fourth dielectric layer The source and the gate are both connected to the semiconductor layer.
  • a display device including an array substrate, a color filter substrate, and a plastic frame surrounded by a glass melt adhesive; the plastic frame is located on the array substrate and the color frame Between the film substrates; the array substrate includes a substrate, a driving electrode, a first capacitor, a source, a drain and a first dielectric layer, the first capacitor includes a first capacitor electrode and a second capacitor electrode, a source, a drain, and a driving The electrode and the first capacitor electrode are formed on the substrate, the first dielectric layer covers the source, the drain, the driving electrode and the first capacitor electrode, and the first dielectric layer comprises a first region covering the first capacitor electrode and a cover driving electrode The second region has a thickness greater than a thickness of the first region, a second region for forming a glass melt thereon, and a second capacitor electrode formed on the first region.
  • the thickness of the first region is 200 to 1000 angstroms, and the thickness of the second region is 1000 to 8000 angstroms.
  • the array substrate further includes a pixel electrode, an organic material layer and a spacer device.
  • the pixel electrode is formed on the first dielectric layer and connected to the source.
  • the organic material layer is located on the first dielectric layer and covers the second electrode plate, and the pixel electrode is exposed.
  • An organic material layer is formed, and the spacer is convexly disposed on the organic material layer.
  • the second capacitor electrode is a metal material or a transparent conductive material.
  • the array substrate further includes a second dielectric layer, a semiconductor layer, a third dielectric layer, a gate, a fourth dielectric layer, and a second capacitor, the second capacitor includes a third capacitor electrode and a fourth capacitor electrode, and a second The dielectric layer is formed on the substrate, the semiconductor layer and the third capacitor electrode are located between the second dielectric layer and the third dielectric layer, and the gate electrode and the fourth capacitor electrode are located between the third dielectric layer and the fourth dielectric layer The source and the gate are both connected to the semiconductor layer.
  • the first dielectric layer of the array substrate of the present invention comprises a first region between the first capacitor electrode and the second capacitor electrode and a second region covering the driving electrode
  • the thickness of the second region is greater than the thickness of the first region; thus, on the basis of ensuring the charge storage amount of the first capacitor, the glass melt is peeled off due to the direct contact of the driving electrode with the glass melt in the sealing process. Phenomenon, further, the thickness of the second region corresponding to the driving electrode is thicker, so the sealing effect in the sealing process is better.
  • FIG. 1 is a partial front elevational view of an array substrate of the present invention
  • FIG. 2 is a top plan view showing the array substrate shown in FIG. 1 applied to a display device;
  • Figure 3 is a front elevational view corresponding to the area A of the display device shown in Figure 2;
  • FIG. 4 is a flow chart showing a method of manufacturing the array substrate of the present invention.
  • the array substrate of the present invention comprises a substrate 1, a driving electrode 2, a first capacitor 3, a TFT layer (not labeled), a first dielectric layer 51, a pixel electrode 6, an organic material layer 7, and a spacer device 8.
  • the first capacitor 3 includes a first capacitor electrode 31 and a second capacitor electrode 32.
  • the TFT layer includes a second dielectric layer 52, a semiconductor layer 43, a third dielectric layer 53, a gate 44, a fourth dielectric layer 54, a source 41, a drain 42, and a second capacitor 9.
  • the second capacitor 9 includes a third capacitor electrode 91 and a fourth capacitor electrode 92.
  • the second dielectric layer 52 is formed on the substrate 1.
  • the semiconductor layer 43 and the third capacitor electrode 91 are formed on a side of the second dielectric layer 52 away from the substrate 1.
  • the third capacitor electrode 91 and the semiconductor layer 43 may be sequentially formed by different processes or simultaneously generated in the same process.
  • the two materials are the same material, that is, the third capacitor electrode 91 is also a semiconductor material.
  • the third dielectric layer 53 is formed on the second dielectric layer 52.
  • the third dielectric layer 53 covers the semiconductor layer 43 and the third capacitor electrode 91 such that the third capacitor electrode 91 and the semiconductor layer 43 are located between the second dielectric layer 52 and the third dielectric layer 53.
  • the gate electrode 44 and the fourth capacitor electrode 92 are formed on the third dielectric layer 53.
  • the gate electrode 44 and the fourth capacitor electrode 92 are formed simultaneously by the same process or sequentially by different processes.
  • a fourth dielectric layer is formed on the third dielectric layer 53.
  • the fourth dielectric layer 54 covers the gate electrode 44 and the fourth capacitor electrode 92 such that the gate electrode 44 and the fourth capacitor electrode 92 are located between the third dielectric layer 53 and the fourth dielectric layer 54.
  • the source 41, the drain 42, the first capacitor electrode 31 and the driving electrode 2 are formed on the fourth dielectric layer 54; the four are formed simultaneously by the same process or different processes are successively formed.
  • the drive electrode 2 is formed on the array substrate 100 at a position close to one side edge.
  • a first dielectric layer 51 is formed on the fourth dielectric layer 54.
  • the first dielectric layer 51 covers the source 41, the drain 42, the first capacitor electrode 31, and the drive electrode 2.
  • the first dielectric layer 51 includes a first region 511 covering the first capacitor electrode 31 and a second region 512 covering the driving electrode 2.
  • the thickness of the second region 512 is greater than the thickness of the first region 511.
  • the thickness of the first region 511 is between 200 and 1000 angstroms
  • the thickness of the second region 512 is between 1000 and 8000 angstroms.
  • a second capacitor electrode 32 is formed on the first region 511 of the first dielectric layer 51.
  • the first capacitor electrode 31, the second capacitor electrode 32, and the first dielectric layer 51 therebetween form a first capacitor 3. Since the thickness of the first dielectric layer 51 between the first capacitor electrode 31 and the second capacitor electrode 32 is small, the first capacitor 3 can obtain a higher charge storage amount to meet the use requirement.
  • the first region 511 of the first dielectric layer 51 covers the driving electrode 2, and the first region 511 is used to form a glass frit 22 thereon to cover the array substrate 100 and the color filter substrate. 21 for packaging.
  • the glass melt is poured on the sealing area (not labeled) on the periphery of the array substrate 100, and the sealing area partially overlaps the second area 512; then, laser baking is used.
  • the method of curing the glass melt since the thick first dielectric layer 51 is disposed between the driving electrode 2 and the glass frit 22, the first dielectric layer 51 forms a good transition between the two, so that the glass frit 22 is good. Curing the package effect.
  • the pixel electrode 6 is formed on the first dielectric layer 51.
  • the pixel electrode 6 is connected to the source 41.
  • the pixel electrode 6 and the second capacitor electrode 32 are formed simultaneously by the same process or sequentially by different processes.
  • the pixel electrode 6 and the second capacitor electrode 32 are simultaneously formed by the same process, and both are made of a transparent conductive material or a silver process.
  • the second capacitor electrode 32 can also adopt other conductive materials.
  • the organic material layer 7 is formed on the first dielectric layer 51.
  • the organic material layer 7 covers the second electrode plate and exposes the pixel electrode 6.
  • the spacers 8 are spaced apart from the organic material layer 7 to support the color filter substrate 21 assembled with the array substrate 100.
  • the arrangement area of the organic material layer 7 is smaller than that of the first dielectric layer 51. At least the organic material layer 7 is not disposed on the sealant region of the array substrate 100, so that the glass frit 22 is poured onto the first dielectric layer 51 disposed on the surface layer of the sealant region.
  • the first dielectric layer 51, the second dielectric layer 52, the third dielectric layer 53, and the fourth dielectric layer 54 are both silicon nitride or silicon oxide materials.
  • the material of the above dielectric layer is not limited by the above materials. Moreover, the same material may be used between adjacent dielectric layers, and different materials may also be used.
  • the first dielectric layer 51 of the array substrate 100 of the present invention includes a first region 511 between the first capacitor electrode 31 and the second capacitor electrode 32 and a second region 512 covering the driving electrode 2,
  • the thickness of the two regions 512 is larger than the thickness of the first region 511; thus, on the basis of ensuring the charge storage amount of the first capacitor 3, the glass melting is prevented from being caused by the direct contact of the driving electrode 2 with the glass frit 22 in the sealing process.
  • the phenomenon that the glue 22 is peeled off further, the thickness of the second region 512 corresponding to the driving electrode 2 is thicker, and therefore, the sealing effect in the frame sealing process is better.
  • the present invention further provides a display device including the array frame 100, the color filter substrate 21, the FPC 20, and the glass frit 22 surrounded by the foregoing embodiments.
  • the plastic frame is located between the array substrate 100 and the color filter substrate 21.
  • the FPC 20 is connected to the drive electrode 2.
  • the present invention further provides a method of fabricating an array substrate.
  • the manufacturing method includes:
  • the substrate 1 may be a light transmissive plate of a glass substrate or other material.
  • the first dielectric layer 51 covers the source 41, the drain 42, the drive electrode 2, and the first capacitor electrode 31.
  • the first dielectric layer 51 includes a first region 511 covering the first capacitor electrode 31 and a second region 512 covering the driving electrode 2.
  • the thickness of the second region 512 is greater than the thickness of the first region 511.
  • the second region 512 is used to form a glass frit 22 thereon.
  • step S20 further includes forming a second dielectric layer 52 on the substrate 1.
  • a semiconductor layer 43 and a third capacitor electrode 91 are formed on the second dielectric layer 52.
  • a third dielectric layer 53 is formed, and a third dielectric layer 53 is formed on the second dielectric layer 52 and covers the semiconductor layer 43 and the third capacitor electrode 91.
  • a gate electrode 44 and a fourth capacitor electrode 92 are formed on the third dielectric layer 53, the gate electrode 44 and the semiconductor layer 43 face each other, and the fourth capacitor electrode 92, the third capacitor electrode 91, and the third dielectric layer therebetween form a first Two capacitors 9.
  • a fourth dielectric layer 54 is formed, and a fourth dielectric layer 54 is formed on the third dielectric layer 53 and covers the gate electrode 44 and the fourth capacitor electrode 92.
  • a source 41, a drain 42, a first capacitor electrode 31 and a drive electrode 2 are formed on the fourth dielectric layer 92, and the source 41 and the drain 42 are both connected to the semiconductor layer 43.
  • the first region 511 has a thickness of 200 to 1000 angstroms
  • the second region 512 has a thickness of 1000 to 8000 angstroms.
  • the manufacturing method further includes, after the step S30, forming a pixel electrode 6 on the first dielectric layer 51, and the pixel electrode 6 is connected to the source electrode 41.
  • the step of forming the pixel electrode 6 may be completed in synchronization with step S40 or sequentially.
  • the materials of the two are the same, that is, the transparent electrode material or silver is selected.
  • the organic material layer 7 is formed on the first dielectric layer 51.
  • the organic material layer 7 covers the second capacitor electrode 32.
  • the pixel electrode 6 exposes the organic material layer 7.
  • a plurality of spacers 8 are protruded from the organic material layer 7. The spacers 8 are used to support the color filter substrate 21 of the display device that is assembled and assembled with the array substrate 100.

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Abstract

一种阵列基板的制造方法，包括：于基板（1）上形成源极（41）、漏极（42）、驱动电极（2）和第一电容电极（31）；形成第一介电层（51），覆盖源极（41）、漏极（42）、驱动电极（2）和第一电容电极（31），第一介电层（51）包括第一区域（511）和覆盖驱动电极（2）、厚度大于第一区域（511）的第二区域（512）；于第一介电层（51）的第一区域（511）上形成第二电容电极（32），第二电容电极（32）、第一电容电极（31）以及其间的第一介电层（51）形成第一电容（3）。通过上述方式，采用该阵列基板的显示装置能够取得良好的封胶效果。

Description

阵列基板、显示装置及阵列基板的制造方法
【技术领域】
本发明涉及液晶显示器领域，特别是涉及一种阵列基板、显示装置及阵列基板的制造方法。
【背景技术】
液晶面板通常包括彩膜基板和阵列基板。液晶面板的生产工序通常包括阵列制程、组立制程以及模组制程。阵列制程主要包括阵列基板的生产过程。组立制程主要包括将阵列基板和彩膜基板贴合在一起的过程。模组制程则包括将FPC(Flexible Printed Circuit，柔性电路板)等电路进行组装的过程。
阵列基板上形成呈阵列排布的TFT(Thin-Film Transistor,薄膜晶体管)、电容和像素电极，以及形成于外围的驱动电极。驱动电极控制TFT的通断电，因此驱动电极连接TFT和FPC。组立制程中，将阵列基板和彩膜基板贴合在一起的步骤之前还包括在阵列基板和彩膜基板的边框处封胶的步骤。具体来说，封胶步骤包括灌胶和固化两个步骤。
OLED（Organic Electroluminesence Display，有机电激光显示）面板作为液晶面板的未来发展新趋势，其对水汽和氧气等物质非常敏感，因此其封装条件较苛刻。
现有技术中，OLED面板的封装工艺为灌胶后采用激光烘烤的方法使封框胶固化。激光固化的温度达1000℃甚至更高。然而，封框胶的涂覆位置与驱动电极的排布位置部分重合，若封框胶与驱动电极直接接触则固化过程中极易发生封框胶自驱动电极的位置处发生剥离的现象。
【发明内容】
本发明主要解决的技术问题是提供一种改善封框效果的阵列基板、显示装置及阵列基板的制造方法。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种阵列基板的制造方法，该制造方法包括：提供一基板；于基板上形成源极、漏极、驱动电极和第一电容电极；形成第一介电层，第一介电层覆盖源极、漏极、驱动电极和第一电容电极，第一介电层包括覆盖第一电容电极的第一区域和覆盖驱动电极的第二区域，第二区域的厚度大于第一区域的厚度，第二区域用于在其上形成玻璃熔胶；于第一介电层的第一区域上形成第二电容电极，第二电容电极、第一电容电极以及其间的第一介电层形成第一电容。
其中，第一区域的厚度为200~1000埃，第二区域的厚度为1000~8000埃。
其中，形成第一介电层的步骤之后进一步包括：于第一介电层上形成像素电极，像素电极连接源极；于第一介电层上形成有机材料层，有机材料层覆盖第二电极板，像素电极裸露出有机材料层；于有机材料层上形成若干凸出的间隔装置。
其中，于基板上形成源极、漏极、驱动电极和第一电容电极的步骤包括：于基板上形成第二介电层；于第二介电层上形成半导体层和第三电容电极；形成第三介电层，第三介电层形成于第二介电层上且覆盖半导体层和第三电容电极；于第三介电层上形成栅极和第四电容电极，栅极和半导体层正对，第四电容电极、第三电容电极以及其间的第三介电层形成第二电容；形成第四介电层，第四介电层形成于第三介电层上且覆盖栅极和第四电容电极；于第四介电层上形成源极、漏极、第一电容电极和驱动电极，源极和漏极均连接至半导体层。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种阵列基板，包括基板、驱动电极、第一电容、源极、漏极和第一介电层，第一电容包括第一电容电极和第二电容电极，源极、漏极、驱动电极和第一电容电极形成于基板上，第一介电层覆盖源极、漏极、驱动电极和第一电容电极，第一介电层包括覆盖第一电容电极的第一区域和覆盖驱动电极的第二区域，第二区域的厚度大于第一区域的厚度，第二区域用于在其上形成玻璃熔胶，第二电容电极形成于第一区域上。
其中，第一区域的厚度为200~1000埃，第二区域的厚度为1000~8000埃。
其中，阵列基板进一步包括像素电极、有机材料层和间隔装置，像素电极形成于第一介质层上且连接源极，有机材料层位于第一介电层上且覆盖第二电极板，像素电极裸露出有机材料层，间隔装置于有机材料层上凸出设置。
其中，第二电容电极是金属材料或透明导电材料。
其中，阵列基板进一步包括第二介电层、半导体层、第三介电层、栅极、第四介电层和第二电容，第二电容包括第三电容电极和第四电容电极，第二介电层形成于基板上，半导体层和第三电容电极位于第二介电层和第三介电层之间，栅极和第四电容电极位于第三介电层和第四介电层之间，源极和栅极均与半导体层连接。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种显示装置，该显示装置包括阵列基板、彩膜基板和由玻璃熔胶围设的胶框；胶框位于阵列基板和彩膜基板之间；阵列基板包括基板、驱动电极、第一电容、源极、漏极和第一介电层，第一电容包括第一电容电极和第二电容电极，源极、漏极、驱动电极和第一电容电极形成于基板上，第一介电层覆盖源极、漏极、驱动电极和第一电容电极，第一介电层包括覆盖第一电容电极的第一区域和覆盖驱动电极的第二区域，第二区域的厚度大于第一区域的厚度，第二区域用于在其上形成玻璃熔胶，第二电容电极形成于第一区域上。
其中，第一区域的厚度为200~1000埃，第二区域的厚度为1000~8000埃。
其中，阵列基板进一步包括像素电极、有机材料层和间隔装置，像素电极形成于第一介质层上且连接源极，有机材料层位于第一介电层上且覆盖第二电极板，像素电极裸露出有机材料层，间隔装置于有机材料层上凸出设置。
其中，第二电容电极是金属材料或透明导电材料。
其中，阵列基板进一步包括第二介电层、半导体层、第三介电层、栅极、第四介电层和第二电容，第二电容包括第三电容电极和第四电容电极，第二介电层形成于基板上，半导体层和第三电容电极位于第二介电层和第三介电层之间，栅极和第四电容电极位于第三介电层和第四介电层之间，源极和栅极均与半导体层连接。
本发明的有益效果是：区别于现有技术的情况，本发明阵列基板的第一介电层包括位于第一电容电极、第二电容电极之间的第一区域和覆盖驱动电极的第二区域，第二区域的厚度大于第一区域的厚度设计；从而在保障第一电容的电荷存储量的基础上，避免发生因驱动电极直接接触封框工艺中的玻璃熔胶而使玻璃熔胶剥离的现象，进一步地，驱动电极对应的第二区域的厚度较厚，因此封框工艺中的封框效果更好。
【附图说明】
图1是本发明阵列基板的局部主视示意图；
图2是本图1所示阵列基板应用于显示装置中的俯视示意图；
图3是图2所示显示装置的区域A对应的主视示意图；
图4是本发明阵列基板的制造方法的流程图。
【具体实施方式】
参阅图1和图2，本发明阵列基板包括基板1、驱动电极2、第一电容3、TFT层（未标示）、第一介电层51、像素电极6、有机材料层7和间隔装置8。第一电容3包括第一电容电极31和第二电容电极32。
TFT层包括第二介电层52、半导体层43、第三介电层53、栅极44、第四介电层54、源极41、漏极42和第二电容9。第二电容9包括第三电容电极91和第四电容电极92。
第二介电层52形成于基板1上。半导体层43和第三电容电极91形成于第二介电层52的远离基板1的一侧上。第三电容电极91和半导体层43可以由不同的制程依次制成，或者在同一制程中同时生成。当第三电容电极91和半导体层43由同一制程形成时，二者为同样的材质，即，第三电容电极91亦为半导体材料。
第三介电层53形成于第二介电层52上。第三介电层53覆盖半导体层43和第三电容电极91，使第三电容电极91和半导体层43位于第二介电层52和第三介电层53之间。
栅极44和第四电容电极92形成于第三介电层53上。栅极44和第四电容电极92由同一制程同时形成，或者由不同制程依次形成。第四介电层形成于第三介电层53上。第四介电层54覆盖栅极44和第四电容电极92，使栅极44和第四电容电极92位于第三介电层53和第四介电层54之间。
源极41、漏极42、第一电容电极31和驱动电极2形成于第四介电层54上；四者由相同的制程同时形成或者不同的制程先后形成。驱动电极2形成于阵列基板100上靠近一侧边缘的位置处。第一介电层51形成于所述第四介电层54上。第一介电层51覆盖源极41、漏极42、第一电容电极31和驱动电极2。第一介电层51包括覆盖第一电容电极31的第一区域511和覆盖驱动电极2的第二区域512。第二区域512的厚度大于第一区域511的厚度。优选地，第一区域511的厚度为200~1000埃之间，第二区域512的厚度为1000~8000埃之间。
第一介电层51的第一区域511上形成第二电容电极32。第一电容电极31、第二电容电极32和二者之间的第一介电层51形成第一电容3。因第一电容电极31和第二电容电极32之间的第一介电层51的厚度较小，使第一电容3能够得到较高的电荷存储量，以满足使用需求。
请一并参照图2和图3，第一介电层51的第一区域511覆盖驱动电极2，第一区域511用于在其上形成玻璃熔胶22，以将阵列基板100和彩膜基板21进行封装。
玻璃熔胶22的封装工艺中，首先，将玻璃熔胶灌注在阵列基板100外围的封胶区（未标示）上，该封胶区与第二区域512部分重叠；接着，将采用激光烘烤的方法使玻璃熔胶固化。本发明中，因驱动电极2与玻璃熔胶22之间设置较厚的第一介电层51，第一介电层51在二者之间形成良好的过渡，使玻璃熔胶22取得良好的固化封装效果。
进一步地，像素电极6形成于第一介电层51上。像素电极6连接至源极41。像素电极6与第二电容电极32由相同的制程同时形成或者由不同的制程先后形成。优选地，像素电极6和第二电容电极32采用相同的制程同时形成，二者均采用透明导电材料或者银制程。当二者采用不同制程时，第二电容电极32亦可采用其他的导电材料。
有机材料层7形成于第一介电层51上。有机材料层7覆盖第二电极板并将像素电极6裸露出来。间隔装置8自有机材料层7上凸出间隔设置，以支撑与阵列基板100相互组装的彩膜基板21。
有机材料层7的设置面积小于第一介电层51。至少阵列基板100的框胶区上没有铺设有机材料层7，使得玻璃熔胶22灌注至设置于框胶区的表层的第一介质层51上。
本发明中，第一介质层51、第二介质层52、第三介质层53和第四介质层54均为氮化硅或氧化硅材料。实际应用中，上述介质层的材料不受上述材料限制。并且，相邻的介质层之间可以采用相同的材料，亦可以选用不同的材料。
区别于现有技术，本发明阵列基板100的第一介电层51包括位于第一电容电极31、第二电容电极32之间的第一区域511和覆盖驱动电极2的第二区域512，第二区域512的厚度大于第一区域511的厚度设计；从而在保障第一电容3的电荷存储量的基础上，避免发生因驱动电极2直接接触封框工艺中的玻璃熔胶22而使玻璃熔胶22剥离的现象，进一步地，驱动电极2对应的第二区域512的厚度较厚，因此，封框工艺中的封框效果更好。
请参照图2，本发明进一步提供一种显示装置，显示装置包括前述实施例中描述的阵列基板100、彩膜基板21、FPC20和玻璃熔胶22围设的胶框。胶框位于阵列基板100和彩膜基板21之间。FPC20连接至驱动电极2。
请参照图4，本发明进一步提供一种阵列基板的制造方法。该制造方法包括：
S10，提供一基板1。
基板1可以是玻璃基板或其他材料的透光板。
S20，于基板1上形成源极41、漏极42、驱动电极2和第一电容电极31。
S30，形成第一介电层51。第一介电层51覆盖源极41、漏极42、驱动电极2和第一电容电极31。第一介电层51包括覆盖第一电容电极31的第一区域511和覆盖驱动电极2的第二区域512。第二区域512的厚度大于第一区域511的厚度。第二区域512用于在其上形成玻璃熔胶22。
S40，于第一介电层51的第一区域511上形成第二电容电极32。第二电容电极32、第一电容电极31以及其间的第一介电层51形成第一电容3。
具体来说，步骤S20进一步包括：于基板1上形成第二介电层52。于第二介电层52上形成半导体层43和第三电容电极91。形成第三介电层53，第三介电层53形成于第二介电层52上且覆盖半导体层43和第三电容电极91。于第三介电层53上形成栅极44和第四电容电极92，栅极44和半导体层43正对，第四电容电极92、第三电容电极91以及其间的第三介电层形成第二电容9。形成第四介电层54，第四介电层54形成于第三介电层53上且覆盖栅极44和第四电容电极92。于第四介电层92上形成源极41、漏极42、第一电容电极31和驱动电极2，源极41和漏极42均连接至半导体层43。
步骤S30中，优选地，第一区域511的厚度为200~1000埃，第二区域512的厚度为1000~8000埃。
该制造方法于步骤S30之后进一步包括：于第一介电层51上形成像素电极6，像素电极6连接至源极41。形成像素电极6的步骤可与步骤S40同步完成或先后完成。像素电极6和第二电容电极32选择同一制程同步形成时，二者的材料相同，即均选择透明电极材料或银。
像素电极6制成后，于第一介电层51上形成有机材料层7。有机材料层7覆盖第二电容电极32。像素电极6裸露出有机材料层7。最后，于有机材料层7上凸出设置若干间隔装置8，间隔装置8用以支撑显示装置的与阵列基板100贴合组装的彩膜基板21。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (14)

  1. 一种阵列基板的制造方法，其中，所述制造方法包括：
    提供一基板；
    于所述基板上形成源极、漏极、驱动电极和第一电容电极；
    形成第一介电层，所述第一介电层覆盖所述源极、所述漏极、所述驱动电极和所述第一电容电极，所述第一介电层包括覆盖所述第一电容电极的第一区域和覆盖所述驱动电极的第二区域，所述第二区域的厚度大于所述第一区域的厚度，所述第二区域用于在其上形成玻璃熔胶；
    于所述第一介电层的所述第一区域上形成第二电容电极，所述第二电容电极、所述第一电容电极以及其间的所述第一介电层形成第一电容。
  2. 根据权利要求1所述的阵列基板的制造方法，其中，所述第一区域的厚度为200~1000埃，所述第二区域的厚度为1000~8000埃。
  3. 根据权利要求1所述的阵列基板的制造方法，其中，所述形成第一介电层的步骤之后进一步包括：
    于所述第一介电层上形成像素电极，所述像素电极连接所述源极；
    于所述第一介电层上形成有机材料层，所述有机材料层覆盖所述第二电极板，所述像素电极裸露出所述有机材料层；
    于所述有机材料层上形成若干凸出的间隔装置。
  4. 根据权利要求1所述的阵列基板的制造方法，其中，所述于所述基板上形成源极、漏极、驱动电极和第一电容电极的步骤包括：
    于所述基板上形成第二介电层；
    于所述第二介电层上形成半导体层和第三电容电极；
    形成第三介电层，所述第三介电层形成于所述第二介电层上且覆盖所述半导体层和所述第三电容电极；
    于所述第三介电层上形成栅极和第四电容电极，所述栅极和所述半导体层正对，所述第四电容电极、所述第三电容电极以及其间的所述第三介电层形成第二电容；
    形成第四介电层，所述第四介电层形成于所述第三介电层上且覆盖所述栅极和所述第四电容电极；
    于所述第四介电层上形成所述源极、所述漏极、所述第一电容电极和所述驱动电极，所述源极和所述漏极均连接至所述半导体层。
  5. 一种阵列基板，其中，所述阵列基板包括基板、驱动电极、第一电容、源极、漏极和第一介电层，所述第一电容包括第一电容电极和第二电容电极，所述源极、所述漏极、所述驱动电极和所述第一电容电极形成于所述基板上，所述第一介电层覆盖所述源极、所述漏极、所述驱动电极和所述第一电容电极，所述第一介电层包括覆盖所述第一电容电极的第一区域和覆盖所述驱动电极的第二区域，所述第二区域的厚度大于所述第一区域的厚度，所述第二区域用于在其上形成玻璃熔胶，所述第二电容电极形成于所述第一区域上。
  6. 根据权利要求5所述的阵列基板，其中，所述第一区域的厚度为200~1000埃，所述第二区域的厚度为1000~8000埃。
  7. 根据权利要求5所述的阵列基板，其中，所述阵列基板进一步包括像素电极、有机材料层和间隔装置，所述像素电极形成于所述第一介质层上且连接所述源极，所述有机材料层位于所述第一介电层上且覆盖所述第二电极板，所述像素电极裸露出所述有机材料层，所述间隔装置于所述有机材料层上凸出设置。
  8. 根据权利要求5所述的阵列基板，其中，所述第二电容电极是金属材料或透明导电材料。
  9. 根据权利要求8所述的阵列基板，其中，所述阵列基板进一步包括第二介电层、半导体层、第三介电层、栅极、第四介电层和第二电容，所述第二电容包括第三电容电极和第四电容电极，所述第二介电层形成于所述基板上，所述半导体层和所述第三电容电极位于所述第二介电层和所述第三介电层之间，所述栅极和所述第四电容电极位于所述第三介电层和所述第四介电层之间，所述源极和所述栅极均与所述半导体层连接。
  10. 一种显示装置，其中，所述显示装置包括阵列基板、彩膜基板和由玻璃熔胶围设的胶框；胶框位于阵列基板和彩膜基板之间；所述阵列基板包括基板、驱动电极、第一电容、源极、漏极和第一介电层，所述第一电容包括第一电容电极和第二电容电极，所述源极、所述漏极、所述驱动电极和所述第一电容电极形成于所述基板上，所述第一介电层覆盖所述源极、所述漏极、所述驱动电极和所述第一电容电极，所述第一介电层包括覆盖所述第一电容电极的第一区域和覆盖所述驱动电极的第二区域，所述第二区域的厚度大于所述第一区域的厚度，所述第二区域用于在其上形成所述玻璃熔胶，所述第二电容电极形成于所述第一区域上。
  11. 根据权利要求10所述的显示装置，其中，所述第一区域的厚度为200~1000埃，所述第二区域的厚度为1000~8000埃。
  12. 根据权利要求10所述的显示装置，其中，所述阵列基板进一步包括像素电极、有机材料层和间隔装置，所述像素电极形成于所述第一介质层上且连接所述源极，所述有机材料层位于所述第一介电层上且覆盖所述第二电极板，所述像素电极裸露出所述有机材料层，所述间隔装置于所述有机材料层上凸出设置。
  13. 根据权利要求10所述的显示装置，其中，所述第二电容电极是金属材料或透明导电材料。
  14. 根据权利要求13所述的显示装置，其中，所述阵列基板进一步包括第二介电层、半导体层、第三介电层、栅极、第四介电层和第二电容，所述第二电容包括第三电容电极和第四电容电极，所述第二介电层形成于所述基板上，所述半导体层和所述第三电容电极位于所述第二介电层和所述第三介电层之间，所述栅极和所述第四电容电极位于所述第三介电层和所述第四介电层之间，所述源极和所述栅极均与所述半导体层连接。
PCT/CN2013/071662 2013-02-05 2013-02-19 阵列基板、显示装置及阵列基板的制造方法 WO2014121525A1 (zh)

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