WO2016078101A1 - 显示面板及其制造方法 - Google Patents

显示面板及其制造方法 Download PDF

Info

Publication number
WO2016078101A1
WO2016078101A1 PCT/CN2014/092125 CN2014092125W WO2016078101A1 WO 2016078101 A1 WO2016078101 A1 WO 2016078101A1 CN 2014092125 W CN2014092125 W CN 2014092125W WO 2016078101 A1 WO2016078101 A1 WO 2016078101A1
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
electrode
display panel
passivation layer
hole
Prior art date
Application number
PCT/CN2014/092125
Other languages
English (en)
French (fr)
Inventor
聂诚磊
Original Assignee
深圳市华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市华星光电技术有限公司 filed Critical 深圳市华星光电技术有限公司
Priority to US14/407,938 priority Critical patent/US9780118B2/en
Publication of WO2016078101A1 publication Critical patent/WO2016078101A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0274—Optical details, e.g. printed circuits comprising integral optical means
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/183—Components mounted in and supported by recessed areas of the printed circuit board
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K5/00—Casings, cabinets or drawers for electric apparatus
    • H05K5/0017—Casings, cabinets or drawers for electric apparatus with operator interface units
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0104—Properties and characteristics in general
    • H05K2201/0108—Transparent
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10128—Display

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a display panel and a method of fabricating the same.
  • the surface of existing mobile phones, tablets and the like has a plurality of functional components, such as buttons, speakers, cameras, and the like, in addition to the main body portion being a display panel.
  • These functional components are indispensable for the normal operation of the device, but they require additional space for the device. Since mobile phones, tablets and other devices are now pursuing thin and light, narrow frames, and the installation space on the device is limited. Therefore, the screen ratio of the device is reduced.
  • the technical problem to be solved by the present invention is to provide a display panel and a manufacturing method thereof, which can save installation space and increase the screen ratio of the display panel, thereby improving the user experience.
  • one technical solution adopted by the present invention is to provide a display panel including a first substrate and a second substrate disposed opposite to each other, a pixel array disposed between the first substrate and the second substrate, and An electrode disposed on a surface of the first substrate adjacent to the second substrate, the second substrate being provided with a through hole corresponding to the electrode such that the electrode is exposed through the through hole portion.
  • the display panel further comprises a passivation layer, the passivation layer covers the electrode, and the electrode is exposed in a corresponding area of the through hole.
  • the first substrate is an array substrate
  • the second substrate is a transparent cover
  • the passivation layer is disposed on the array substrate
  • the pixel array is disposed on the passivation layer.
  • the first substrate is a transparent cover
  • the second substrate is an array substrate
  • the pixel array is disposed on the array substrate
  • the passivation layer is disposed on the pixel array.
  • the display panel further comprises a support layer supported between the passivation layer and the transparent cover.
  • the display panel further includes a functional component that is received in the through hole and electrically connected to the electrode.
  • the functional components are speakers, cameras or buttons.
  • the display panel further includes a first plastic frame disposed along an edge of the through hole and a second plastic frame disposed along an edge of the first substrate and the second substrate, wherein the first plastic frame and the second plastic frame are used for sealing the first substrate And a second substrate, thereby forming a sealed structure sealing the pixel array.
  • another technical solution adopted by the present invention is to provide a manufacturing method of a display panel, comprising: forming an electrode; forming a passivation layer on one side of the electrode; the passivation layer partially covering the electrode, so that the electrode Partially exposed; forming an array substrate on the other side of the electrode, forming a pixel array on the passivation layer; forming a transparent cover over the pixel array; the transparent cover is provided with a through hole corresponding to the electrode, and the passivation layer is in the through hole The electrode is exposed in the corresponding area so that the electrode is exposed through the through hole portion.
  • another technical solution adopted by the present invention is to provide a method for manufacturing a display panel, comprising: forming an array substrate, wherein the array substrate is provided with a through hole; and forming a pixel array on the array substrate; Forming a passivation layer on the pixel array; forming a support layer on the passivation layer; forming a transparent cover plate and forming an electrode on the transparent cover; placing the transparent cover on the support layer, partially covering the electrode, and passivating The layer exposes the electrode in a corresponding area of the through hole such that the electrode is exposed through the through hole.
  • the invention has the beneficial effects that the electrode is disposed on the surface of the first substrate of the display panel adjacent to the second substrate, and the second substrate is provided with a through hole corresponding to the electrode, so that the electrode is The through hole portion is exposed, so that the functional component can be installed in the through hole and electrically connected to the electrode, so that the functional component can be embedded on the display panel, thereby saving installation space and increasing the screen ratio of the display panel, thereby Can enhance the user experience.
  • FIG. 1 is a plan view of a display panel according to a first embodiment of the present invention
  • Figure 2 is a cross-sectional view taken along line A-A of Figure 1;
  • Figure 3 is a cross-sectional view taken along line B-B of Figure 1;
  • FIG. 4 is a plan view of a display panel according to a second embodiment of the present invention.
  • Figure 5 is a cross-sectional view taken along line C-C of Figure 4.
  • Figure 6 is a cross-sectional view taken along line D-D of Figure 4.
  • Figure 7 is a flow chart showing a first embodiment of a method of manufacturing a display panel of the present invention.
  • Figure 8 is a flow chart showing a second embodiment of the manufacturing method of the display panel of the present invention.
  • FIG. 1 is a plan view of a display panel according to a first embodiment of the present invention
  • FIG. 2 is a cross-sectional view taken along line AA of FIG. 1
  • FIG. 3 is a cross section of the first embodiment of FIG. Figure.
  • the maximum surface of the display panel in Figure 1 is parallel to the paper surface.
  • the display panel includes a first substrate 11 and a second substrate 12 disposed opposite to each other, a pixel array 13 disposed between the first substrate 11 and the second substrate 12, and a first substrate 11 disposed adjacent to the second substrate
  • the electrode 14 on the surface of the second substrate 12 is provided with a through hole 120 corresponding to the electrode 14 such that the electrode 14 is partially exposed through the through hole 120.
  • the display panel further includes a passivation layer 15 covering the electrode 14 and exposing the electrode 14 in a corresponding region of the via 120. That is, the passivation layer 15 does not completely cover the electrode 14, but exposes the electrode 14 in a corresponding region of the via 120 such that the electrode 14 is partially exposed through the via 120.
  • the first substrate 11 is the array substrate 11
  • the second substrate 12 is the transparent cover 12
  • the passivation layer 15 is disposed on the array substrate 11
  • the pixel array 13 is disposed on the passivation layer 15.
  • the array substrate 11 and the transparent cover 12 are rectangular panels. In other embodiments, the array substrate 11 and the transparent cover 12 may have other shapes.
  • the array substrate 11 and the transparent cover 12 are disposed in parallel with each other, that is, the largest faces are disposed in parallel with each other.
  • the display panel further includes a functional component 16 that is received in the through hole 120 and electrically connected to the electrode.
  • functional component 16 is a horn, a camera or a button. In other embodiments, functional component 16 can also be other components.
  • the display panel further includes a first plastic frame 17 disposed along an edge of the through hole 120 and a second plastic frame 18 disposed along an edge of the first substrate 11 and the second substrate 12, the first glue
  • the frame 17 and the second bezel 18 are used to seal the first substrate 11 and the second substrate 12, thereby forming a sealing structure for sealing the pixel array 13.
  • the dimension of the through hole 120 in any one direction along the plane of the second substrate 12 is smaller than a quarter of the dimension of the second substrate 12 in the direction.
  • the size of the through hole 120 is set to be a small proportion of the display panel, so that the space on the display panel can be reasonably utilized.
  • the through holes 120 are circular, the electrodes 14 are strip-shaped and the number is two, the two electrodes 14 are parallel to each other, and the edges of the two electrodes 14 away from each other are tangent to the inner edge of the through hole 120.
  • the closest distance of the edge of the through hole 120 to the edge of the second substrate 12 is less than a quarter of the width of the second substrate 12.
  • the through hole 120 is disposed at the edge of the display panel to further properly allocate the space on the display panel.
  • the thickness of the passivation layer 15 is greater than the thickness of the pixel array 13.
  • the thickness of the passivation layer 15 is set larger than the thickness of the pixel array 13, so that the capacitive coupling effect can be reduced.
  • FIG. 4 is a plan view of a display panel according to a second embodiment of the present invention
  • FIG. 5 is a cross-sectional view in the CC direction of FIG. 4
  • FIG. 6 is a cross-section in the DD direction of FIG. Figure.
  • the maximum surface of the display panel in Figure 4 is parallel to the paper surface.
  • the display panel includes a first substrate 21 and a second substrate 22 disposed opposite to each other, a pixel array 23 disposed between the first substrate 21 and the second substrate 22, and a first substrate 21 disposed adjacent to the second substrate
  • the electrode 24 on the surface of the second substrate 22 is provided with a through hole 220 corresponding to the electrode 24 such that the electrode 24 is partially exposed through the through hole 220.
  • the display panel further includes a passivation layer 25 covering the electrode 24 and exposing the electrode 24 in a corresponding area of the via 220. That is, the passivation layer 25 does not completely cover the electrode 24, but exposes the electrode 24 in a corresponding region of the via 220 so that the electrode 24 is partially exposed through the via 220.
  • the first substrate 21 is a transparent cover 21, the second substrate 22 is an array substrate 22, the pixel array 23 is disposed on the array substrate 22, and the passivation layer 25 is disposed on the pixel array 22.
  • the array substrate 22 and the transparent cover 21 are rectangular panels. In other embodiments, the array substrate 22 and the transparent cover 21 may have other shapes.
  • the array substrate 22 and the transparent cover 21 are disposed in parallel with each other, that is, the largest faces are disposed in parallel with each other.
  • the display panel further includes a functional component 26 that is received in the through hole 220 and electrically connected to the electrode.
  • the functional component is a horn, a camera or a button.
  • functional component 26 can also be other components.
  • the display panel further includes a first plastic frame 27 disposed along an edge of the through hole 220 and a second plastic frame 28 disposed along an edge of the first substrate 21 and the second substrate 22, the first glue
  • the frame 27 and the second bezel 28 are used to seal the first substrate 21 and the second substrate 22, thereby forming a sealing structure for sealing the pixel array 23.
  • the display panel further includes a support layer 29 supported between the passivation layer 23 and the transparent cover 21.
  • the size of the through hole 220 in any one of the directions along the plane of the second substrate 22 is smaller than a quarter of the dimension of the second substrate 22 in the direction.
  • the size of the through hole 220 is set to be a small proportion of the display panel, so that the space on the display panel can be reasonably utilized.
  • the through holes 220 are circular, the electrodes 24 are strip-shaped and the number is two, the two electrodes 24 are parallel to each other, and the edges of the two electrodes 24 away from each other are tangent to the inner edge of the through hole 220.
  • the closest distance of the edge of the through hole 220 to the edge of the second substrate 22 is less than a quarter of the width of the second substrate 22.
  • the through hole 220 is disposed at the edge of the display panel to further properly allocate the space on the display panel.
  • the thickness of the passivation layer 25 is greater than the thickness of the pixel array 23.
  • the thickness of the passivation layer 25 is set larger than the thickness of the pixel array 23, so that the capacitive coupling effect can be reduced.
  • FIG. 7 is a flow chart of the first embodiment of the manufacturing method of the display panel of the present invention.
  • the manufacturing method of the display panel includes the following steps:
  • Step S11 forming an electrode
  • Step S12 forming a passivation layer on one side of the electrode, and partially covering the electrode with the passivation layer to expose the electrode portion;
  • Step S13 forming an array substrate on the other side of the electrode, and forming a pixel array on the passivation layer;
  • Step S14 forming a transparent cover over the pixel array.
  • the transparent cover is provided with a through hole corresponding to the electrode, and the passivation layer exposes the electrode in a corresponding area of the through hole, so that the electrode is exposed through the through hole.
  • the array substrate 11 and the transparent cover 12 are rectangular panels. In other embodiments, the array substrate 11 and the transparent cover 12 may have other shapes. Preferably, the array substrate 11 and the transparent cover 12 are disposed in parallel with each other, that is, the largest faces are disposed in parallel with each other.
  • the method further includes: a first plastic frame disposed along an edge of the through hole and a second plastic frame disposed along edges of the first substrate and the second substrate, wherein the first plastic frame and the second plastic frame are used to seal the first The substrate and the second substrate, in turn, form a sealed structure that seals the pixel array.
  • the method further includes: providing a functional component in the through hole, the functional component being electrically connected to the electrode.
  • the functional component is a horn, a camera or a button.
  • the functional components can also be other components.
  • the size of the through hole 120 in any one direction along the plane of the transparent cover 12 is smaller than a quarter of the size of the transparent cover 12 in the direction.
  • the size of the through hole 120 is set to be a small proportion of the display panel, so that the space on the display panel can be reasonably utilized.
  • the through holes 120 are circular, the electrodes 14 are strip-shaped and the number is two, the two electrodes 14 are parallel to each other, and the edges of the two electrodes 14 away from each other are tangent to the inner edge of the through hole 120.
  • the edge of the through hole 120 has a closest distance to the edge of the transparent cover 12 of less than a quarter of the width of the transparent cover 12.
  • the through hole 120 is disposed at the edge of the display panel to further properly allocate the space on the display panel.
  • the thickness of the passivation layer 15 is greater than the thickness of the pixel array 13.
  • the thickness of the passivation layer 15 is set larger than the thickness of the pixel array 13, so that the capacitive coupling effect can be reduced.
  • FIG. 8 is a flow chart of a second embodiment of a method for manufacturing a display panel of the present invention.
  • the manufacturing method of the display panel includes the following steps:
  • Step S21 forming an array substrate, wherein the array substrate is provided with a through hole;
  • Step S22 forming a pixel array on the array substrate
  • Step S23 forming a passivation layer on the pixel array; forming a support layer on the passivation layer;
  • Step S24 forming a transparent cover plate and forming an electrode on the transparent cover plate
  • Step S25 The transparent cover is disposed on the support layer, the passivation layer partially covers the electrode, and the passivation layer exposes the electrode in a corresponding area of the through hole, so that the electrode is exposed through the through hole.
  • the array substrate 22 and the transparent cover 21 are rectangular panels. In other embodiments, the array substrate 22 and the transparent cover 21 may have other shapes. Preferably, the array substrate 22 and the transparent cover 21 are disposed in parallel with each other, that is, the largest faces are disposed in parallel with each other.
  • the method further includes: a first plastic frame disposed along an edge of the through hole and a second plastic frame disposed along edges of the first substrate and the second substrate, wherein the first plastic frame and the second plastic frame are used to seal the first The substrate and the second substrate, in turn, form a sealed structure that seals the pixel array.
  • the method further includes: providing a functional component in the through hole, the functional component being electrically connected to the electrode.
  • the functional component is a horn, a camera or a button.
  • the functional components can also be other components.
  • the size of the via 220 in any one of the planes on the plane of the array substrate 22 is less than one quarter of the size of the array substrate 22 in the direction.
  • the size of the through hole 120 is set to be a small proportion of the display panel, so that the space on the display panel can be reasonably utilized.
  • the through holes 220 are circular, the electrodes 24 are strip-shaped and the number is two, the two electrodes 24 are parallel to each other, and the edges of the two electrodes 24 away from each other are tangent to the inner edge of the through hole 220.
  • the closest distance of the edge of the via 220 to the edge of the array substrate 22 is less than a quarter of the width of the array substrate 22.
  • the through hole 220 is disposed at the edge of the display panel to further properly allocate the space on the display panel.
  • the thickness of the passivation layer 25 is greater than the thickness of the pixel array 23.
  • the thickness of the passivation layer 25 is set larger than the thickness of the pixel array 23, so that the capacitive coupling effect can be reduced.
  • the present invention provides an electrode on a surface of the first substrate adjacent to the second substrate on the first substrate, and the second substrate is provided with a through hole corresponding to the electrode, so that the electrode is exposed through the through hole portion, thereby making the function
  • the component can be installed in the through hole and electrically connected to the electrode, so that the functional component can be embedded on the display panel, thereby saving installation space and increasing the screen ratio of the display panel, thereby improving the user experience.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Theoretical Computer Science (AREA)
  • Electrochromic Elements, Electrophoresis, Or Variable Reflection Or Absorption Elements (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种显示面板及其制造方法，该显示面板包括相对设置的第一基板（11）和第二基板（12）、设置在第一基板（11）和第二基板（12）之间的像素阵列（13）以及设置在第一基板（11）靠近第二基板（12）的表面上的电极（14），第二基板（12）与电极（14）对应地设置有通孔（120），以使得电极（14）经通孔（120）部分外露。通过上述方式，能够实现在显示面板上内嵌功能性组件，进而能够节省安装空间，提高显示面板的屏占比，从而可以提升用户的体验。

Description

显示面板及其制造方法
【技术领域】
本发明涉及显示技术领域，特别是涉及一种显示面板及其制造方法。
【背景技术】
目前已有的手机、平板等设备的表面除了主体部分为显示面板之外，还存在许多功能组件，如按键、喇叭、摄像头等等。这些功能组件对于设备的正常运行来说不可或缺，但是却需要设备为之提供额外的放置空间，由于现在手机、平板电脑等设备都追求轻薄化、窄边框，而设备上的安装空间有限，因此会降低了设备的屏占比。
因此，需要提供一种显示面板及其制造方法，以解决上述技术问题。
【发明内容】
本发明主要解决的技术问题是提供一种显示面板及其制造方法，能够节省安装空间，提高显示面板的屏占比，从而可以提升用户的体验。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种显示面板，显示面板包括相对设置的第一基板和第二基板、设置在第一基板和第二基板之间的像素阵列以及设置在第一基板靠近第二基板的表面上的电极，第二基板与电极对应地设置有通孔，以使得电极经通孔部分外露。
其中，显示面板进一步包括钝化层，钝化层覆盖电极，且在通孔的对应区域外露电极。
其中，第一基板为阵列基板，第二基板为透明盖板，钝化层设置于阵列基板上，像素阵列设置在钝化层上。
其中，第一基板为透明盖板，第二基板为阵列基板，像素阵列设置于阵列基板上，钝化层设置于像素阵列上。
其中，显示面板进一步包括支撑于钝化层与透明盖板之间的支撑层。
其中，显示面板进一步包括功能组件，功能组件容置于通孔内，且与电极电连接。
其中，功能组件为喇叭、摄像头或按键。
其中，显示面板进一步包括沿通孔的边缘设置的第一胶框和沿第一基板和第二基板的边缘设置的第二胶框，第一胶框和第二胶框用于密封第一基板和第二基板，进而形成密封像素阵列的密封结构。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种显示面板的制造方法，制造方法包括：形成电极；在电极一面形成钝化层，钝化层部分覆盖电极，以使得电极部分外露；在电极另一面形成阵列基板，在钝化层上形成像素阵列；在像素阵列上方形成透明盖板，透明盖板上与电极对应地设有通孔，且钝化层在通孔的对应区域外露电极，以使得电极通过通孔部分外露。
为解决上述技术问题，本发明采用的又一个技术方案是：提供一种显示面板的制造方法，制造方法包括：形成阵列基板，阵列基板上设有通孔；在阵列基板上形成像素阵列；在像素阵列上形成钝化层；在钝化层上形成支撑层；形成透明盖板并在透明盖板上形成电极；将透明盖板设置在支撑层上，钝化层部分覆盖电极，且钝化层在通孔的对应区域外露电极，使得电极通过通孔外露。
本发明的有益效果是：区别于现有技术的情况，本发明通过在显示面板的第一基板上靠近第二基板的表面上设置电极，且第二基板与电极对应设置通孔，使得电极经通孔部分外露，从而使得功能性组件可以安装在通孔中且与电极电连接，从而可以实现在显示面板上内嵌功能性组件，进而能够节省安装空间，提高显示面板的屏占比，从而可以提升用户的体验。
【附图说明】
图1是本发明第一实施例的显示面板的俯视图；
图2是图1中A-A方向的截面图；
图3是图1中B-B方向的截面图；
图4是本发明第二实施例的显示面板的俯视图；
图5是图4中C-C方向的截面图；
图6是图4中D-D方向的截面图；
图7是本发明显示面板的制造方法第一实施例的流程图；
图8是本发明显示面板的制造方法第二实施例的流程图。
【具体实施方式】
下面结合附图和实施例对本发明进行详细的说明。
请一并参阅图1、图2以及图3，图1是本发明第一实施例的显示面板的俯视图，图2是图1中A-A方向的截面图，图3是图1中B-B方向的截面图。图1中显示面板最大表面与纸面平行。
在本实施例中，显示面板包括相对设置的第一基板11和第二基板12、设置在第一基板11和第二基板12之间的像素阵列13以及设置在第一基板11靠近第二基板12的表面上的电极14，第二基板12与电极14对应地设置有通孔120，以使得电极14经通孔120部分外露。
优选地，在本实施例中，显示面板还包括钝化层15，钝化层15覆盖电极14，且在通孔120的对应区域外露电极14。即钝化层15未完全覆盖电极14，而是在通孔120的对应区域外露电极14，以使得电极14经通孔120部分外露。
优选地，在本实施例中，第一基板11为阵列基板11，第二基板12为透明盖板12，钝化层15设置于阵列基板11上，像素阵列13设置在钝化层15上。优选地，阵列基板11与透明盖板12为矩形面板，在其他实施例中，阵列基板11与透明盖板12也可以为其他形状。优选地，阵列基板11与透明盖板12相互平行设置，即最大面相互平行设置。
优选地，在本实施例中，显示面板还包括功能组件16，功能组件16容置于通孔120内，且与电极电连接。优选地，功能组件16为喇叭、摄像头或按键。在其他实施例中，功能组件16也可以为其他零件。
优选地，在本实施例中，显示面板还包括沿通孔120的边缘设置的第一胶框17和沿第一基板11和第二基板12的边缘设置的第二胶框18，第一胶框17和第二胶框18用于密封第一基板11和第二基板12，进而形成密封像素阵列13的密封结构。
优选地，通孔120沿第二基板12所在平面上的任意一方向的尺寸均小于第二基板12沿该方向的尺寸的四分之一。将通孔120的尺寸设置为占显示面板较小的比例，从而可以合理的利用显示面板上的空间。
优选地，通孔120为圆形，电极14为条状且数量为两个，两个电极14彼此平行，两个电极14彼此远离的边缘与通孔120的内边缘相切。
优选地，通孔120的边缘与第二基板12的边缘的最近距离小于四分之一的第二基板12的宽度。将通孔120设置在显示面板的边缘，进一步合理分配显示面板上的空间。
优选地，钝化层15的厚度大于像素阵列13的厚度。将钝化层15的厚度设置为大于像素阵列13的厚度，从而可以减小电容耦合影响。
请参阅一并图4、图5以及图6，图4是本发明第二实施例的显示面板的俯视图，图5是图4中C-C方向的截面图，图6是图4中D-D方向的截面图。图4中显示面板最大表面与纸面平行。
在本实施例中，显示面板包括相对设置的第一基板21和第二基板22、设置在第一基板21和第二基板22之间的像素阵列23以及设置在第一基板21靠近第二基板22的表面上的电极24，第二基板22与电极24对应地设置有通孔220，以使得电极24经通孔220部分外露。
优选地，在本实施例中，显示面板还包括钝化层25，钝化层25覆盖电极24，且在通孔220的对应区域外露电极24。即钝化层25未完全覆盖电极24，而是在通孔220的对应区域外露电极24，以使得电极24经通孔220部分外露。
优选地，第一基板21为透明盖板21，第二基板22为阵列基板22，像素阵列23设置于阵列基板22上，钝化层25设置于像素阵列22上。优选地，阵列基板22与透明盖板21为矩形面板，在其他实施例中，阵列基板22与透明盖板21也可以为其他形状。优选地，阵列基板22与透明盖板21相互平行设置，即最大面相互平行设置。
优选地，在本实施例中，显示面板还包括功能组件26，功能组件26容置于通孔220内，且与电极电连接。优选地，功能组件为喇叭、摄像头或按键。在其他实施例中，功能组件26也可以为其他零件。
优选地，在本实施例中，显示面板还包括沿通孔220的边缘设置的第一胶框27和沿第一基板21和第二基板22的边缘设置的第二胶框28，第一胶框27和第二胶框28用于密封第一基板21和第二基板22，进而形成密封像素阵列23的密封结构。
优选地，显示面板还包括支撑于钝化层23与透明盖板21之间的支撑层29。
优选地，通孔220沿第二基板22所在平面上的任意一方向的尺寸均小于第二基板22沿该方向的尺寸的四分之一。将通孔220的尺寸设置为占显示面板较小的比例，从而可以合理的利用显示面板上的空间。
优选地，通孔220为圆形，电极24为条状且数量为两个，两个电极24彼此平行，两个电极24彼此远离的边缘与通孔220的内边缘相切。
优选地，通孔220的边缘与第二基板22的边缘的最近距离小于四分之一的第二基板22的宽度。将通孔220设置在显示面板的边缘，进一步合理分配显示面板上的空间。
优选地，钝化层25的厚度大于像素阵列23的厚度。将钝化层25的厚度设置为大于像素阵列23的厚度，从而可以减小电容耦合影响。
请参阅图7，图7是本发明显示面板的制造方法第一实施例的流程图。在本实施例中，显示面板的制造方法包括以下步骤：
步骤S11：形成电极；
步骤S12：在电极一面形成钝化层，钝化层部分覆盖电极，以使得电极部分外露；
步骤S13：在电极另一面形成阵列基板，在钝化层上形成像素阵列；
步骤S14：在像素阵列上方形成透明盖板，透明盖板上与电极对应地设有通孔，且钝化层在通孔的对应区域外露电极，以使得电极通过通孔部分外露。
在步骤S11~S14中，阵列基板11与透明盖板12为矩形面板，在其他实施例中，阵列基板11与透明盖板12也可以为其他形状。优选地，阵列基板11与透明盖板12相互平行设置，即最大面相互平行设置。在步骤S14之后还可以包括：沿通孔的边缘设置的第一胶框和沿第一基板和第二基板的边缘设置第二胶框，第一胶框和第二胶框用于密封第一基板和第二基板，进而形成密封像素阵列的密封结构。在步骤S14之后还可以包括：在通孔内设置功能组件，功能组件与电极电连接。优选地，功能组件为喇叭、摄像头或按键。在其他实施例中，功能组件也可以为其他零件。优选地，通孔120沿透明盖板12所在平面上的任意一方向的尺寸均小于透明盖板12沿该方向的尺寸的四分之一。将通孔120的尺寸设置为占显示面板较小的比例，从而可以合理的利用显示面板上的空间。优选地，通孔120为圆形，电极14为条状且数量为两个，两个电极14彼此平行，两个电极14彼此远离的边缘与通孔120的内边缘相切。优选地，通孔120的边缘与透明盖板12的边缘的最近距离小于四分之一的透明盖板12的宽度。将通孔120设置在显示面板的边缘，进一步合理分配显示面板上的空间。优选地，钝化层15的厚度大于像素阵列13的厚度。将钝化层15的厚度设置为大于像素阵列13的厚度，从而可以减小电容耦合影响。
请参阅图8，图8是本发明显示面板的制造方法第二实施例的流程图。在本实施例中，显示面板的制造方法包括以下步骤：
步骤S21：形成阵列基板，阵列基板上设有通孔；
步骤S22：在阵列基板上形成像素阵列；
步骤S23：在像素阵列上形成钝化层；在钝化层上形成支撑层；
步骤S24：形成透明盖板并在透明盖板上形成电极；
步骤S25：将透明盖板设置在支撑层上，钝化层部分覆盖电极，且钝化层在通孔的对应区域外露电极，使得电极通过通孔外露。
在步骤S21~S25中，阵列基板22与透明盖板21为矩形面板，在其他实施例中，阵列基板22与透明盖板21也可以为其他形状。优选地，阵列基板22与透明盖板21相互平行设置，即最大面相互平行设置。在步骤S25之后还可以包括：沿通孔的边缘设置的第一胶框和沿第一基板和第二基板的边缘设置第二胶框，第一胶框和第二胶框用于密封第一基板和第二基板，进而形成密封像素阵列的密封结构。在步骤S25之后还可以包括：在通孔内设置功能组件，功能组件与电极电连接。优选地，功能组件为喇叭、摄像头或按键。在其他实施例中，功能组件也可以为其他零件。优选地，通孔220沿阵列基板22所在平面上的任意一方向的尺寸均小于阵列基板22沿该方向的尺寸的四分之一。将通孔120的尺寸设置为占显示面板较小的比例，从而可以合理的利用显示面板上的空间。优选地，通孔220为圆形，电极24为条状且数量为两个，两个电极24彼此平行，两个电极24彼此远离的边缘与通孔220的内边缘相切。优选地，通孔220的边缘与阵列基板22的边缘的最近距离小于四分之一的阵列基板22的宽度。将通孔220设置在显示面板的边缘，进一步合理分配显示面板上的空间。优选地，钝化层25的厚度大于像素阵列23的厚度。将钝化层25的厚度设置为大于像素阵列23的厚度，从而可以减小电容耦合影响。
区别于现有技术，本发明通过在显示面板的第一基板上靠近第二基板的表面上设置电极，且第二基板与电极对应设置通孔，使得电极经通孔部分外露，从而使得功能性组件可以安装在通孔中且与电极电连接，从而可以实现在显示面板上内嵌功能性组件，进而能够节省安装空间，提高显示面板的屏占比，从而可以提升用户的体验。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (10)

  1. 一种显示面板，其中，所述显示面板包括相对设置的第一基板和第二基板、设置在所述第一基板和所述第二基板之间的像素阵列以及设置在所述第一基板靠近所述第二基板的表面上的电极，所述第二基板与所述电极对应地设置有通孔，以使得所述电极经所述通孔部分外露。
  2. 根据权利要求1所述的显示面板，其中，所述显示面板进一步包括钝化层，所述钝化层部分覆盖所述电极，且在所述通孔的对应区域外露所述电极。
  3. 根据权利要求2所述的显示面板，其中，所述第一基板为阵列基板，所述第二基板为透明盖板，所述钝化层设置于所述阵列基板上，所述像素阵列设置在所述钝化层上。
  4. 根据权利要求2所述的显示面板，其中，所述第一基板为透明盖板，所述第二基板为阵列基板，所述像素阵列设置于所述阵列基板上，所述钝化层设置于所述像素阵列上。
  5. 根据权利要求4所述的显示面板，其中，所述显示面板进一步包括支撑于所述钝化层与所述透明盖板之间的支撑层。
  6. 根据权利要求1所述的显示面板，其中，所述显示面板进一步包括功能组件，所述功能组件容置于所述通孔内，且与所述电极电连接。
  7. 根据权利要求6所述的显示面板，其中，所述功能组件为喇叭、摄像头或按键。
  8. 根据权利要求1所述的显示面板，其中，所述显示面板进一步包括沿所述通孔的边缘设置的第一胶框和沿所述第一基板和所述第二基板的边缘设置的第二胶框，所述第一胶框和所述第二胶框用于密封所述第一基板和第二基板，进而形成密封所述像素阵列的密封结构。
  9. 一种显示面板的制造方法，其中，所述制造方法包括：
    形成电极；
    在所述电极一面形成钝化层，所述钝化层部分覆盖所述电极，以使得所述电极部分外露；
    在所述电极另一面形成阵列基板，在所述钝化层上形成像素阵列；
    在所述像素阵列上方形成透明盖板，所述透明盖板上与所述电极对应地设有通孔，且所述钝化层在所述通孔的对应区域外露所述电极，以使得所述电极通过所述通孔部分外露。
  10. 一种显示面板的制造方法，其中，所述制造方法包括：
    形成阵列基板，所述阵列基板上设有通孔；
    在所述阵列基板上形成像素阵列；
    在所述像素阵列上形成钝化层；
    在所述钝化层上形成支撑层；
    形成透明盖板并在所述透明盖板上形成电极；
    将所述透明盖板设置在所述支撑层上，所述钝化层部分覆盖所述电极，且所述钝化层在所述通孔的对应区域外露所述电极，使得所述电极通过所述通孔外露。
PCT/CN2014/092125 2014-11-18 2014-11-25 显示面板及其制造方法 WO2016078101A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US14/407,938 US9780118B2 (en) 2014-11-18 2014-11-25 Display panel and a manufacturing method thereof

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201410660210.3A CN104361832B (zh) 2014-11-18 2014-11-18 显示面板及其制造方法
CN201410660210.3 2014-11-18

Publications (1)

Publication Number Publication Date
WO2016078101A1 true WO2016078101A1 (zh) 2016-05-26

Family

ID=52529089

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2014/092125 WO2016078101A1 (zh) 2014-11-18 2014-11-25 显示面板及其制造方法

Country Status (3)

Country Link
US (1) US9780118B2 (zh)
CN (1) CN104361832B (zh)
WO (1) WO2016078101A1 (zh)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106921767A (zh) * 2017-03-07 2017-07-04 捷开通讯(深圳)有限公司 一种高屏占比的移动终端
CN107249053A (zh) * 2017-05-09 2017-10-13 广东欧珀移动通信有限公司 显示器及移动终端
CN107144995A (zh) * 2017-05-17 2017-09-08 广东欧珀移动通信有限公司 显示屏、显示装置及移动终端
CN113281930B (zh) * 2017-06-30 2022-08-12 厦门天马微电子有限公司 显示屏及显示装置
CN107247356A (zh) * 2017-07-31 2017-10-13 广东欧珀移动通信有限公司 显示面板和电子设备
US20190037063A1 (en) * 2017-07-31 2019-01-31 Guangdong Oppo Mobile Telecommunications Corp., Ltd. Display panel and electronic device
CN109727539B (zh) * 2018-12-17 2020-10-30 维沃移动通信有限公司 一种显示模组和电子设备
KR20210103037A (ko) * 2020-02-12 2021-08-23 삼성디스플레이 주식회사 표시 장치 및 전자 기기

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070195238A1 (en) * 2006-02-22 2007-08-23 Seong-Ho Kim Transflective liquid crystal display and panel therefor
CN101359678A (zh) * 2007-07-30 2009-02-04 统宝光电股份有限公司 图像显示系统及其制作方法
CN101763186A (zh) * 2008-12-23 2010-06-30 胜华科技股份有限公司 触控面板
CN103137891A (zh) * 2011-12-01 2013-06-05 群康科技(深圳)有限公司 有机发光二极管与其所组成的有机发光二极管显示器
CN103257489A (zh) * 2013-04-27 2013-08-21 友达光电股份有限公司 主动元件基板与应用其的显示面板
CN103984147A (zh) * 2014-05-04 2014-08-13 深圳市华星光电技术有限公司 阵列面板及其制作方法
CN104133307A (zh) * 2013-05-03 2014-11-05 启耀光电股份有限公司 显示面板及显示装置

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050264689A1 (en) * 2004-05-26 2005-12-01 Yang Shou A Display panel having a video camera
JP2009175230A (ja) * 2008-01-22 2009-08-06 Sharp Corp 表示装置
TWI431568B (zh) * 2010-09-17 2014-03-21 Au Optronics Corp 顯示器
US9143668B2 (en) * 2010-10-29 2015-09-22 Apple Inc. Camera lens structures and display structures for electronic devices
CN102650763B (zh) * 2011-08-26 2015-01-07 北京京东方光电科技有限公司 一种液晶显示屏及其制造方法与显示器
CN103021278B (zh) 2012-12-07 2015-08-19 京东方科技集团股份有限公司 一种显示面板及显示装置
US9806219B2 (en) * 2013-02-14 2017-10-31 Apple Inc. Displays with camera window openings

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070195238A1 (en) * 2006-02-22 2007-08-23 Seong-Ho Kim Transflective liquid crystal display and panel therefor
CN101359678A (zh) * 2007-07-30 2009-02-04 统宝光电股份有限公司 图像显示系统及其制作方法
CN101763186A (zh) * 2008-12-23 2010-06-30 胜华科技股份有限公司 触控面板
CN103137891A (zh) * 2011-12-01 2013-06-05 群康科技(深圳)有限公司 有机发光二极管与其所组成的有机发光二极管显示器
CN103257489A (zh) * 2013-04-27 2013-08-21 友达光电股份有限公司 主动元件基板与应用其的显示面板
CN104133307A (zh) * 2013-05-03 2014-11-05 启耀光电股份有限公司 显示面板及显示装置
CN103984147A (zh) * 2014-05-04 2014-08-13 深圳市华星光电技术有限公司 阵列面板及其制作方法

Also Published As

Publication number Publication date
US20160351593A1 (en) 2016-12-01
US9780118B2 (en) 2017-10-03
CN104361832A (zh) 2015-02-18
CN104361832B (zh) 2016-11-30

Similar Documents

Publication Publication Date Title
WO2016078101A1 (zh) 显示面板及其制造方法
WO2014032324A1 (zh) 一种显示面板以及液晶显示器
WO2014036730A1 (zh) 一种显示面板及液晶显示装置
WO2019100524A1 (zh) 一种全屏指纹识别触控显示屏
WO2019006826A1 (zh) 一种柔性显示面板及其制备方法、柔性显示装置
WO2018196112A1 (zh) Ltps阵列基板及其制作方法
WO2018006479A1 (zh) 阵列基板及其制作方法、以及液晶显示面板
WO2013143197A1 (zh) 液晶显示面板及其制造方法以及液晶显示装置
WO2016155100A1 (zh) 液晶显示装置及其液晶显示面板
WO2018032551A1 (zh) 液晶显示面板及液晶显示装置
WO2016078133A1 (zh) 液晶显示面板及其彩膜阵列基板
WO2017024599A1 (zh) 一种具有触控功能的阵列基板及显示装置
WO2018188162A1 (zh) 一种有机发光显示面板
WO2013159417A1 (zh) 液晶显示模组及液晶显示装置
WO2019144483A1 (zh) 显示模组及电子设备
WO2019052008A1 (zh) 一种阵列基板及其制备方法、显示装置
WO2019072204A1 (zh) 触控基板及其制作方法、显示装置
WO2015006959A1 (zh) 显示面板及显示装置
WO2019041476A1 (zh) 一种阵列基板及其制作方法、显示面板
WO2016173021A1 (zh) 显示面板及显示装置
WO2019095500A1 (zh) 一种显示面板以及显示器
WO2019015077A1 (zh) 一种阵列基板及其制造方法、液晶显示装置
WO2014121525A1 (zh) 阵列基板、显示装置及阵列基板的制造方法
WO2019000521A1 (zh) 一种有机发光显示屏的制备方法及显示装置
WO2018232925A1 (zh) 一种阵列基板、液晶面板及液晶显示器

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 14407938

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 14906380

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 14906380

Country of ref document: EP

Kind code of ref document: A1