WO2017092514A1 - 移位寄存器单元及其驱动方法与显示装置 - Google Patents

移位寄存器单元及其驱动方法与显示装置 Download PDF

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Publication number
WO2017092514A1
WO2017092514A1 PCT/CN2016/102999 CN2016102999W WO2017092514A1 WO 2017092514 A1 WO2017092514 A1 WO 2017092514A1 CN 2016102999 W CN2016102999 W CN 2016102999W WO 2017092514 A1 WO2017092514 A1 WO 2017092514A1
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Prior art keywords
pull
transistor
signal
control node
source
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PCT/CN2016/102999
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English (en)
French (fr)
Inventor
周依芳
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京东方科技集团股份有限公司
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Priority to US15/749,571 priority Critical patent/US10706758B2/en
Publication of WO2017092514A1 publication Critical patent/WO2017092514A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only

Definitions

  • the present disclosure relates to a shift register unit, a driving method thereof, and a display device.
  • the shift register includes a multi-stage shift register unit, and each stage shift register unit corresponds to one row of pixel units.
  • the progressive scan driving of the pixel unit of the display device is implemented by a multi-stage shift register unit to display an image.
  • each stage of the shift register unit is composed of a plurality of thin film transistors, and signals in the shift register unit are transmitted through the respective thin film transistors.
  • the threshold voltage of a thin film transistor is susceptible to the stability of the manufacturing process as well as the temperature. Under the condition that the manufacturing process is unstable, high temperature or low temperature, the threshold voltage of the thin film transistor will change greatly, so that the signal of the pull-up control node in the shift register unit and the signal of the pull-down control node are distorted, thereby causing shifting.
  • the signal distortion output by the bit register unit is severe, and sometimes the shift register unit cannot output a signal, thereby reducing the display effect of the display device.
  • the present disclosure provides a shift register unit, a driving method thereof and a display device for reducing the influence of instability of a manufacturing process and high temperature, low temperature, etc. on a signal transmitted in a shift register unit, thereby improving display performance of the display device.
  • a shift register unit comprising:
  • An input module which is connected to the trigger signal end, the pull-down signal end, the first clock signal end, the low-level end, and the pull-up control node, for the signal at the trigger signal end, the signal of the first clock signal end, and the pull-down signal end Under the control of the signal, transmitting the signal of the trigger signal end or the signal of the low level end to the pull-up control node;
  • a pull-down compensation module which is connected to the control signal end, the pull-up control node, the pull-down control node, and the low-level end, and is configured to perform a signal to the pull-down control node when the signal of the pull-up control node is a high level state At least two pull-downs, pulling the signal of the pull-down control node to a low state;
  • a pull-up module connecting the second clock signal end, the pull-up control node, and an output end of the shift register unit, for the signal of the pull-up control node and the signal of the second clock signal end Controlling, pulling up the signal of the output end of the shift register unit to a high level state, and pulling up the signal of the pull-up control node to a high level state by using its own bootstrap phenomenon;
  • a pull-down module connecting the input module, the pull-up module, the pull-up control node, the pull-down control node, the low-level end, and an output of the shift register unit, for Pulling down the signal of the output of the shift register to a low state under the control of the signal of the pull-down control node,
  • the pull-up control node is a connection point of the input module, a pull-down compensation module, the pull-up module, and the pull-down module, and the pull-down control node is a connection between the pull-down compensation module and the pull-down module. point.
  • a driving method of a shift register unit including:
  • the signal of the trigger signal end, the signal of the first clock signal end, and the signal of the pull-down signal end are received by the input module, and the signal at the trigger signal end, the signal of the first clock signal end, and the pull-down signal end Under the control of the signal, the signal of the trigger signal end or the signal of the low level end is transmitted to the pull-up control node; when the pull-up control node is in the high level state, the signal of the pull-down control node is pulled down by the pull-down compensation module Pulling down the signal of the pull-down control node to a low state; under the control of the signal of the pull-down control node, the signal of the output end of the shift register is pulled down to a low state by a pull-down module;
  • the pull-up module pulls up the signal of the pull-up control node to a high state by using its own bootstrap action; the signal of the pull-up control node and the second clock signal Under the control of the signal of the terminal, the signal of the output terminal of the shift register unit is pulled up to a high state by the pull-up module.
  • a display apparatus comprising a plurality of shift register units described in the above technical solutions.
  • the shift register unit includes an input module, a pull-down compensation module, a pull-up module, and a pull-down module, which are unstable and high in the manufacturing process in the prior art.
  • the pull-down compensation module in the embodiment of the present disclosure can pull down the control node when the pull-up control node is in a high state, or the low-temperature condition, the shift register unit outputs a signal that is more severely distorted than the shift register unit. The signal is pulled down at least twice to ensure that the pull down The control node is pulled down to a low state.
  • FIG. 1 is a schematic structural diagram of a shift register unit in Embodiment 1 of the present disclosure
  • FIG. 2 is a schematic structural diagram of a shift register unit in Embodiment 2 of the present disclosure
  • FIG. 3 is a timing diagram of signals corresponding to the shift register units of FIGS. 2, 4, 7, and 8;
  • FIG. 4 is another schematic structural diagram of a shift register unit in Embodiment 2 of the present disclosure.
  • FIG. 5 is a comparison diagram of allowable voltages of a shift register unit in the present disclosure and a pull-up control node in a shift register unit in the prior art;
  • FIG. 6 is a comparison diagram of allowable voltages of a shift register unit in the present disclosure and a pull-down control node in a shift register unit in the prior art;
  • FIG. 7 is a schematic structural diagram of a shift register unit in Embodiment 3 of the present disclosure.
  • FIG. 8 is another schematic structural diagram of a shift register unit in Embodiment 3 of the present disclosure.
  • FIG. 1 is a schematic structural diagram of a shift register unit in Embodiment 1 of the present disclosure.
  • a shift register unit provided by an embodiment of the present disclosure includes an input module P1 , a pull-down compensation module P2 , a pull-up module P3 , and a pull-down module P4 .
  • the input module P1 is connected to the trigger signal terminal STU, the pull-down signal terminal STD, the first clock signal terminal CLK1, the low-level terminal VGL, the pull-down module P4, the pull-up module P3, and the pull-up control node Q.
  • the pull-up control node Q is a connection point of the input module P1, the pull-down compensation module P2, the pull-up module P3, and the pull-down module P4.
  • the signal of the trigger signal terminal STU or the signal of the low-level terminal VGL is transmitted to the pull-up control node Q under the control of the signal of the signal transmitting terminal STU, the signal of the first clock signal terminal CLK1, and the signal of the pull-down signal terminal STD.
  • the pull-down compensation module P2 is connected to the control signal terminal CON, the pull-up control node Q, the pull-down control node QB, and the low-level terminal VGL.
  • the pull-down control node QB is a connection point of the pull-down compensation module P2 and the pull-down module P4.
  • the pull-down compensation module P2 is configured to pull down the signal of the pull-down control node QB at least twice when the signal of the pull-up control node Q is in a high state, and pull down the signal of the pull-down control node QB to a low state.
  • the pull-up module P3 is connected to the second clock signal terminal CLK2, the pull-down module P4, the pull-up control node Q, and the output terminal OUT of the shift register unit.
  • the pull-up module P3 is configured to pull up the signal of the output terminal OUT of the shift register unit to a high state under the control of the signal of the pull-up control node Q and the signal of the second clock signal terminal CLK2, and utilize the self The bootstrap action pulls up the signal of the pull-up control node Q to a high state.
  • the pull-down module P4 is connected to the input module P1, the pull-up module P3, the pull-up control node Q, the pull-down control node QB, the low-level terminal VGL, and the output terminal OUT of the shift register unit.
  • the pull-down module P4 is used to pull down the signal at the output of the shift register to a low state under the control of the signal of the pull-down control node QB.
  • the driving method of the above shift register unit will be described below in conjunction with the above shift register unit.
  • the driving method of the above shift register unit includes the following work process:
  • the signal of the trigger signal terminal STU, the signal of the first clock signal terminal CLK1 and the signal of the pull-down signal terminal STD are received by the input module P1, and the signal of the trigger signal terminal STU, the first clock signal terminal CLK1 Under the control of the signal and the signal of the pull-down signal terminal STD, the signal of the trigger signal terminal STU or the signal of the low-level terminal VGL is transmitted to the pull-up control node Q; when the pull-up compensation module P2 is in the high state of the pull-up control node Q, The signal of the pull-down control node QB is pulled down.
  • At least two pull-downs can be performed to pull down the signal of the pull-down control node QB to a low state; the pull-down module P4 is shifted under the control of the signal of the pull-down control node QB. The signal at the output of the register is pulled low.
  • the pull-up module P3 uses its own bootstrap action to pull up the signal of the pull-up control node Q to a high state; the pull-up module P3 pulls up the signal of the control node Q and the second clock signal. Under the control of the signal of the terminal CLK2, the signal of the output terminal OUT of the shift register unit is pulled up to a high state.
  • first phase and the second phase of the foregoing driving method are mainly related to each signal terminal (such as a trigger signal terminal STU, a pull-down signal terminal STD, a first clock signal terminal CLK1, and a second clock).
  • the signal timing of the signal terminal CLK2 is related and there is no chronological order.
  • the shift register unit includes an input module P1, a pull-down compensation module P2, a pull-up module P3, and a pull-down module P4, which are unstable in the manufacturing process in the prior art.
  • the pull-down compensation module P2 in the embodiment of the present disclosure can be in the high state of the pull-up control node Q when the pull-up compensation module P2 is in the high-level state.
  • the signal of the pull-down control node QB is pulled down at least twice to ensure that the pull-down control node QB is pulled down to a low state.
  • the accuracy of the signal of the pull-down control node QB can be ensured, and the influence of the instability of the manufacturing process and the high temperature and low temperature on the signal transmitted in the shift register unit can be reduced, thereby Improve the display effect of the display device.
  • FIG. 2 is a schematic structural diagram of a shift register unit in Embodiment 2 of the present disclosure.
  • control signal terminal CON is at the high level terminal VGH.
  • the input module P1 includes a first transistor T1, a second transistor T2, a third transistor T3, and a fourth transistor T4.
  • the gate of the first transistor T1 is connected to the trigger signal terminal STU
  • the source of the first transistor T1 is connected to the drain of the second transistor T2
  • the first transistor T1 The drain connection triggers the signal terminal STU.
  • the gate of the second transistor T2 is connected to the first clock signal terminal CLK1
  • the source of the second transistor T2 is connected to the drain of the third transistor T3 and the pull-up control node Q
  • the drain of the second transistor T2 is connected to the drain of the third transistor T3.
  • the gate of the third transistor T3 is connected to the pull-down signal terminal STD
  • the source of the third transistor T3 is connected to the drain of the fourth transistor T4, the pull-up module P3 and the pull-down module P4, and the drain of the third transistor T3 is connected to the pull-up control node.
  • the gate of the fourth transistor T4 is connected to the pull-down signal terminal STD
  • the source of the fourth transistor T4 is connected to the low-level terminal VGL
  • the drain of the fourth transistor T4 is connected to the pull-up module P3 and the pull-down module P4.
  • the pull-down compensation module P2 includes a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and an eighth transistor T8.
  • the gate of the fifth transistor T5 is connected to the high-level terminal VGH
  • the source of the fifth transistor T5 is connected to the drain of the sixth transistor T6 and the gate of the seventh transistor T7
  • the drain of the fifth transistor T5 is connected to the high-level terminal VGH.
  • the gate of the sixth transistor T6 is connected to the pull-up control node Q
  • the source of the sixth transistor T6 is connected to the low-level terminal VGL
  • the drain of the sixth transistor T6 is connected to the seventh transistor T7. The gate.
  • the source of the seventh transistor T7 is connected to the pull-down control node QB, and the drain of the seventh transistor T7 is connected to the high-level terminal VGH.
  • the gate of the eighth transistor T8 is connected to the pull-up control node Q, the source of the eighth transistor T8 is connected to the low-level terminal VGL, and the drain of the eighth transistor T8 is connected to the pull-down control node QB. It should be noted that, when the signal of the pull-up control node Q is in a high state, the fifth transistor T5 and the sixth transistor T6 pull down the signal of the pull-down control node QB for the first time, and the seventh transistor T7 and the eighth transistor T8 performs a second pulldown on the signal of the pull-down control node QB.
  • the pull-down compensation module P2 may further include a larger number of transistors, thereby performing more pull-down on the signal of the pull-down control node QB, but in the embodiment, the pull-down compensation module includes four transistors, and this The four transistors pull down the signal of the pull-down control node QB twice.
  • the pull-up module P3 includes a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, and a twelfth transistor T12.
  • the gate of the ninth transistor T9 is connected to the pull-up control node Q
  • the source of the ninth transistor T9 is connected to the gate of the eleventh transistor T11 and the pull-down module P4
  • the drain of the ninth transistor T9 is connected to the second clock signal terminal CLK2.
  • the gate of the tenth transistor T10 is connected to the pull-up control node Q
  • the source of the tenth transistor T10 is connected to the drain of the eleventh transistor T11 and the pull-down module P4, and the drain of the tenth transistor T10 is connected to the second clock signal terminal CLK2.
  • the gate of the eleventh transistor T11 is connected to the pull-down module P4, the source of the eleventh transistor T11 is connected to the source of the first transistor T1 and the pull-down module P4, and the drain of the eleventh transistor T11 is connected to the pull-down module P4.
  • the gate of the twelfth transistor T12 is connected to the pull-up control node Q, the source of the twelfth transistor T12 is connected to the output terminal OUT of the shift register unit, and the drain of the twelfth transistor T12 is connected to the second clock signal terminal CLK2.
  • the pull-down module P4 includes a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15, a sixteenth transistor T16, and a seventeenth transistor T17.
  • the gate of the thirteenth transistor T13 is connected to the pull-down control node QB, and the source of the thirteenth transistor T13 is connected to the drain of the fourteenth transistor T14, the source of the eleventh transistor T11, and the source of the first transistor T1,
  • the drain of the thirteen transistor T13 is connected to the pull-up control node Q.
  • the gate of the fourteenth transistor T14 is connected to the pull-down control node QB, the source of the fourteenth transistor T14 is connected to the low-level terminal VGL, and the drain of the fourteenth transistor T14 is connected to the source of the eleventh transistor T11 and the first transistor T1.
  • the gate of the fifteenth transistor T15 is connected to the pull-down control node QB, the source of the fifteenth transistor T15 is connected to the low-level terminal VGL, and the drain of the fifteenth transistor T15 is connected to the source of the ninth transistor T9 and the eleventh transistor T11. The gate.
  • the gate of the sixteenth transistor T16 is connected to the pull-down control node QB, the source of the sixteenth transistor T16 is connected to the low-level terminal VGL, and the drain of the sixteenth transistor T16 is connected to the source of the tenth transistor T10 and the eleventh crystal.
  • the gate of the seventeenth transistor T17 is connected to the pull-down control node QB, the source of the seventeenth transistor T17 is connected to the low-level terminal VGL, and the drain of the seventeenth transistor T17 is connected to the output terminal OUT of the shift register unit.
  • the pull-up control node Q is the source of the second transistor T2, the drain of the third transistor T3, the gate of the sixth transistor T6, the gate of the eighth transistor T8, and the gate of the ninth transistor T9.
  • the pull-down control node QB is a source of the seventh transistor T7 and a drain of the eighth transistor T8
  • FIG. 3 shows a signal timing diagram corresponding to the shift register unit of FIG. 2.
  • each of the above transistors is an N-type transistor.
  • the signal of the trigger signal terminal STU and the signal of the first clock signal terminal CLK1 are both in a high state, and the signal of the pull-down signal terminal STD and the signal of the second clock signal terminal CLK2 are both In a low state, the gate of the first transistor T1 receives the signal of the trigger signal terminal STU, the first transistor T1 is turned on; the gate of the second transistor T2 receives the signal of the first clock signal terminal CLK1, and the second transistor T2 leads The gate of the third transistor T3 and the gate of the fourth transistor T4 receive the signal of the pull-down signal terminal STD, the third transistor T3 and the fourth transistor T4 are both turned off, and the pull-up control node Q receives the first transistor T1 and the The signal of the trigger signal terminal STU transmitted by the second transistor T2; the gate of the fifth transistor T5 receives the high level signal of the high level terminal VGH, the fifth transistor T5 is turned on; the gate of the seventh transistor T7 receives the fifth transistor
  • the signal of the trigger signal terminal STU and the signal of the first clock signal terminal CLK1 are both in a low state, and the signal of the pull-down signal terminal STD and the signal of the second clock signal terminal CLK2 are both in a high state
  • the gate of one transistor T1 receives the signal of the trigger signal terminal STU, the first transistor T1 is turned off; the gate of the second transistor T2 receives the signal of the first clock signal terminal CLK1, the second transistor T2 is turned off; the gate of the third transistor T3 Receiving a signal of the pull-down signal terminal STD with the gate of the fourth transistor T4, the third transistor T3 and the fourth transistor T4 are turned on; the capacitances of the ninth transistor T9, the tenth transistor T10 and the twelfth transistor T12 generate a bootstrap phenomenon, Pulling up the signal of the pull-up control node Q to a high state; the gate of the fifth transistor T5 receives a high level signal of the high level terminal VGH, the fifth transistor T5 is
  • the signal of the trigger signal terminal STU and the signal of the second clock signal terminal CLK2 are in a low state, and the signal of the pull-down signal terminal STD and the signal of the first clock signal terminal CLK1 are in a high state, the first transistor
  • the gate of T1 receives the signal of the trigger signal terminal STU, the first transistor T1 is turned off; the gate of the second transistor T2 receives the signal of the first clock signal terminal CLK1, the second transistor T2 is turned on; the gate of the third transistor T3 is The gate of the fourth transistor T4 receives the signal of the pull-down signal terminal STD, and the third transistor T3 and the fourth transistor T4 are both turned on; the pull-up control node Q receives the low-level end transmitted through the third transistor T3 and the fourth transistor T4.
  • the gate of the fifth transistor T5 receives the high level signal of the high level terminal VGH, and the fifth transistor T5 is turned on; the gate of the seventh transistor T7 receives the high level signal of the high level terminal VGH transmitted through the fifth transistor T5.
  • the seventh transistor T7 is turned on; the gate of the sixth transistor T6 and the gate of the eighth transistor T8 receive the signal of the pull-up control node Q, the sixth transistor T6 and the eighth transistor T8 are turned off; the pull-down control node QB receives the pass a high-level signal of the high-level terminal VGH transmitted by the seven-transistor T7; a gate of the ninth transistor T9, a gate of the tenth transistor T10, and a gate of the twelfth transistor T12 receive a signal of the pull-up control node Q,
  • the nine-transistor T9, the tenth transistor T10 and the twelfth transistor T12 are both turned off; the gate of the thirteenth transistor T13, the gate of the fourteenth transistor T14, the gate of the fifteenth transistor T15, and the sixteenth transistor T16
  • the gate and the gate of the seventeenth transistor T17 receive the signal of the pull-down control node QB, and the thirteenth transistor T13, the fourteenth transistor T14
  • FIG. 4 is a schematic diagram showing another structure of a shift register unit in Embodiment 2 of the present disclosure.
  • the low level terminal VGL may include a first low level terminal VGL1 and a second low level terminal VGL2.
  • the source of the fourth transistor T4, the source of the sixth transistor T6, the source of the eighth transistor T8, the source of the fourteenth transistor T14, and the source of the fifteenth transistor T15 are both connected to the second low-level terminal VGL2,
  • the source of the sixteenth transistor T16 and the source of the seventeenth transistor T17 are both connected to the first low-level terminal VGL1.
  • the voltage of the signal of the first low-level terminal VGL1 is higher than the voltage of the signal of the second low-level terminal VGL2, for example, the voltage of the signal of the first low-level terminal VGL1 is -5V, and the voltage of the signal of the second low-level terminal VGL2 It is -10V.
  • the sixth transistor T6 and the eighth transistor T8 are turned off, so that the signal of the pull-down control node QB is in a high state, the thirteenth transistor T13, the fourteenth The transistor T14, the fifteenth transistor T15, the sixteenth transistor T16 and the seventeenth transistor T17 are all turned on, and the pull-up control node Q is discharged to the same low level state as the signal of the second low-level terminal VGL2, and the tenth transistor
  • the source of T10 and the source of the twelfth transistor T12 are both pulled down to the same low level state as the signal of the first low-level terminal VGL1, thereby ensuring the gate-source of the tenth transistor T10 and the twelfth transistor T12.
  • the voltage between the two is less than zero, further ensuring that the tenth transistor T10 and the twelfth transistor T12 are turned off, thereby improving the accuracy of signal transmission in the shift register unit, and further improving the display effect of the display device.
  • the driving method of the shift register unit shown in FIG. 4 and the driving method of the shift register shown in FIG. Therefore, it will not be repeated here.
  • 5 and 6 respectively show a comparison of allowable voltages of a shift register unit and a pull-up control node and a pull-down control node in a shift register unit provided by an embodiment of the present disclosure.
  • FIG. 5 and FIG. 6 Please refer to FIG. 5 and FIG. 6 below. It can be seen from the allowable voltage comparison diagram of the pull-up control node in FIG. 5 that with the shift register unit of the prior art, when the voltage of the pull-up control node Q exceeds 30.5 V, the signal output from the shift register unit is distorted. Severe, even unable to output a signal; and with the shift register unit in the embodiment of the present disclosure, when the voltage of the pull-up control node Q exceeds 37.9V, the signal outputted by the shift register unit may be severely distorted or unable to output a signal. happening. Similarly, it can be seen from the allowable voltage comparison diagram of the pull-down control node in FIG.
  • the shift register unit when the voltage of the pull-down control node QB is lower than -3.87V, the shift register unit outputs The signal distortion is severe, and the signal cannot be outputted.
  • the signal outputted by the shift register unit may be seriously distorted or The case where the signal cannot be output.
  • the shift register unit in the embodiment of the present disclosure expands the range of the threshold voltage variation of the thin film transistor, thereby reducing the instability of the manufacturing process and the influence of high temperature, low temperature, etc. on the signal transmitted in the shift register unit, thereby improving the display device. The display effect.
  • FIG. 7 is a block diagram showing a structure of a shift register unit in Embodiment 3 of the present disclosure.
  • control signal terminal CON may include a first clock signal terminal CLK1 and a second clock signal terminal CLK2, and the pull-down compensation module P2 may also be implemented by another circuit structure.
  • CLK1 a first clock signal terminal CLK1
  • CLK2 a second clock signal terminal CLK2
  • P2 may also be implemented by another circuit structure.
  • the pull-down compensation module P2 may include a first pull-down compensation sub-module P21 and a second pull-down compensation sub-module P22.
  • the first pull-down compensation sub-module P21 and the second pull-down compensation sub-module P22 are configured to alternately pull down the signal of the pull-down control node QB at least twice when the pull-up control node Q is in a high state, and pull down the control node The QB signal is pulled down to a low state.
  • the first pull-down compensation sub-module P21 includes an eighteenth transistor T18, a nineteenth transistor T19, a twentieth transistor T20, and a twenty-first transistor T21.
  • the gate of the eighteenth transistor T18 is connected to the first clock signal terminal CLK1
  • the source of the eighteenth transistor T18 is connected to the drain of the nineteenth transistor T19 and the gate of the twentieth transistor T20
  • the eighteenth transistor T18 The drain is connected to the first clock signal terminal CLK1.
  • the gate of the nineteenth transistor T19 is connected to the pull-up control node Q
  • the source of the nineteenth transistor T19 is connected to the low-level terminal VGL
  • the drain of the nineteenth transistor T19 is connected to the gate of the twentieth transistor T20.
  • the source of the twentieth transistor T20 is connected to the pull-down control node QB
  • the drain of the twentieth transistor T20 is connected to the first clock signal terminal CLK1.
  • the gate of the twenty-first transistor T21 is connected to the pull-up control node Q, the source of the twenty-first transistor T21 is connected to the low-level terminal VGL, and the drain of the twenty-first transistor T21 is connected to the pull-down control node QB.
  • the second pull-down compensation sub-module P22 includes a twenty-second transistor T22, a twenty-third transistor T23, a twenty-fourth transistor T24, and a twenty-fifth transistor T25.
  • the gate of the twenty-second transistor T22 is connected to the second clock signal terminal CLK2, and the source of the twenty-second transistor T22 is connected to the drain of the twenty-third transistor T23 and the gate of the twenty-fourth transistor T24.
  • the drain of the twenty-two transistor T22 is connected to the second clock signal terminal CLK2.
  • the gate of the twenty-third transistor T23 is connected to the pull-up control node Q
  • the source of the twenty-third transistor T23 is connected to the low-level terminal VGL
  • the drain of the twenty-third transistor T23 is connected to the gate of the twenty-fourth transistor T24.
  • the source of the twenty-fourth transistor T24 is connected to the pull-down control node QB
  • the drain of the twenty-fourth transistor T24 is connected to the second clock signal terminal CLK2.
  • the gate of the twenty-fifth transistor T25 is connected to the pull-up control node Q
  • the source of the twenty-fifth transistor T25 is connected to the low-level terminal VGL
  • the drain of the twenty-fifth transistor T25 is connected to the pull-down control node QB.
  • the signal of the first clock signal terminal CLK1 and the signal of the second clock signal terminal CLK2 may be inverted signals. Therefore, the first pull-down compensation sub-module P21 controlled by the signal of the first clock signal terminal CLK1 and the second pull-down compensation sub-module P22 controlled by the signal of the second clock signal terminal CLK2 alternately perform the signal of the pull-down control node QB. Pull down at least twice.
  • first pull-down compensation sub-module P21 and the second pull-down compensation sub-module P22 may each include a larger number of transistors, thereby alternately pulling down the pull-down control node QB at least twice, but in the embodiment.
  • the first pull-down compensation sub-module P21 and the second pull-down compensation sub-module P22 each include four transistors, and the first four pull-down compensation sub-modules P21 and the second pull-down compensation sub-module P22 alternately pull down the control node QB performs two pulldowns.
  • each of the above transistors is an N-type transistor.
  • the signal timing shown in FIG. 3 is also applicable to the shift register unit shown in FIG.
  • the signal of the trigger signal terminal STU and the signal of the first clock signal terminal CLK1 are both in a high state, and the signal of the pull-down signal terminal STD and the signal of the second clock signal terminal CLK2 are both low state, first The gate of the transistor T1 receives the signal of the trigger signal terminal STU, the first transistor T1 is turned on; the gate of the second transistor T2 receives the signal of the first clock signal terminal CLK1, the second transistor T2 is turned on; the gate of the third transistor T3 The gate of the pole and the fourth transistor T4 receives the pull-down signal end The signal of the STD, the third transistor T3 and the fourth transistor T4 are both turned off, the pull-up control node Q receives the signal of the trigger signal terminal STU transmitted through the first transistor T1 and the second transistor T2; the gate of the eighteenth transistor T18 Receiving the signal of the first clock signal terminal CLK1, the eighteenth transistor T18 is turned on; the gate of the twentieth transistor T20 receives the signal
  • the signal is pulled down to a low state; the gate of the twenty-second transistor T22 receives the signal of the second clock signal terminal CLK2, and the twenty-second transistor T22 is turned off. At this time, the second pull-down compensation sub-module P22 is in a standby state; The gate of the thirteenth transistor T13, the gate of the fourteenth transistor T14, the gate of the fifteenth transistor T15, the gate of the sixteenth transistor T16, and the gate of the seventeenth transistor T17 receive the pull-down control node QB.
  • the thirteenth transistor T13, the fourteenth transistor T14, the fifteenth transistor T15, the sixteenth transistor T16 and the seventeenth transistor T17 are all turned off; the gate of the ninth transistor T9, the gate of the tenth transistor T10 and The gate of the twelfth transistor T12 receives the signal of the pull-up control node Q, the ninth transistor T9, the tenth transistor T10 and the twelfth transistor T12 are turned on; the twelfth transistor T12 transmits the signal of the second clock signal terminal CLK2 To the output terminal OUT of the shift register unit, the signal of the output terminal OUT of the shift register unit is pulled down to a low state.
  • the signal of the trigger signal terminal STU and the signal of the first clock signal terminal CLK1 are both in a low state, and the signal of the pull-down signal terminal STD and the signal of the second clock signal terminal CLK2 are both in a high state
  • the gate of one transistor T1 receives the signal of the trigger signal terminal STU, the first transistor T1 is turned off; the gate of the second transistor T2 receives the signal of the first clock signal terminal CLK1, the second transistor T2 is turned off; the gate of the third transistor T3 Receiving a signal of the pull-down signal terminal STD with the gate of the fourth transistor T4, the third transistor T3 and the fourth transistor T4 are turned on; the capacitances of the ninth transistor T9, the tenth transistor T10 and the twelfth transistor T12 generate a bootstrap phenomenon, Pulling up the signal of the pull-up control node Q to a high state; the gate of the twenty-second transistor T22 receives the signal of the second clock signal terminal CLK2, and the twenty-second transistor
  • the signal of the trigger signal terminal STU and the signal of the second clock signal terminal CLK2 are in a low state, and the signal of the pull-down signal terminal STD and the signal of the first clock signal terminal CLK1 are in a high state, the first transistor
  • the gate of T1 receives the signal of the trigger signal terminal STU, the first transistor T1 is turned off; the gate of the second transistor T2 receives the signal of the first clock signal terminal CLK1, the second transistor T2 is turned on; the gate of the third transistor T3 is The gate of the fourth transistor T4 receives the signal of the pull-down signal terminal STD, and the third transistor T3 and the fourth transistor T4 are both turned on; the pull-up control node Q receives the low-level end transmitted through the third transistor T3 and the fourth transistor T4.
  • the signal of the first clock signal terminal CLK1, the twentieth transistor T20 is turned on; the gate of the nineteenth transistor T19 and the gate of the twenty-first transistor T21 receive the signal of the pull-up control node Q, and the nineteenth transistor T19 versus The twenty-one transistor T21 is turned off; the pull-down control node QB receives the signal of the first clock signal terminal CLK1 transmitted through the twentieth transistor T20; the gate of the twenty-second transistor T22 receives the signal of the second clock signal terminal CLK2, The twenty-two transistor T22 is turned off, and the second pull-down compensation sub-module P22 is in a standby state; the gate of the ninth transistor T9, the gate of the tenth transistor T10, and the gate of the twelfth transistor T12 receive the signal of the pull-up control node Q.
  • the ninth transistor T9, the tenth transistor T10 and the twelfth transistor T12 are both turned off; the gate of the thirteenth transistor T13, the gate of the fourteenth transistor T14, the gate of the fifteenth transistor T15, and the sixteenth transistor
  • the gate of T16 and the gate of the seventeenth transistor T17 receive the signal of the pull-down control node QB, and the thirteenth transistor T13, the fourteenth transistor T14, the fifteenth transistor T15, the sixteenth transistor T16 and the seventeenth transistor T17 Turn on, the seventeenth transistor T17 transmits the low level signal of the low level terminal VGL to the shift register
  • the output terminal OUT of the element pulls the signal of the output terminal OUT of the shift register unit to a low state.
  • FIG. 8 is a schematic diagram showing another structure of a shift register unit in Embodiment 3 of the present disclosure.
  • the low level terminal VGL may include a first low level terminal VGL1 and a second low level terminal VGL2.
  • a source of the nineteenth transistor T19, a source of the twenty-first transistor T21, a source of the twenty-third transistor T23, and a source of the twenty-fifth transistor T25 are all connected to the second low-level terminal VGL2,
  • the source of the sixteen transistor T16 and the source of the seventeenth transistor T17 are both connected to the first low level terminal VGL1.
  • the voltage of the signal of the first low-level terminal VGL1 is higher than the voltage of the signal of the second low-level terminal VGL2, for example, the voltage of the signal of the first low-level terminal VGL1 is -5V, and the voltage of the signal of the second low-level terminal VGL2 It is -10V.
  • the nineteenth transistor T19, the twenty-first transistor T21, the twenty-third transistor T23 and the twenty-fifth transistor T25 are turned off, so that the pull-down control node QB
  • the signal is in a high state, and the thirteenth transistor T13, the fourteenth transistor T14, the fifteenth transistor T15, the sixteenth transistor T16 and the seventeenth transistor T17 are both turned off, and the pull-up control node Q is discharged to the second
  • the signal of the low-level terminal VGL2 has the same low-level state, and the source of the tenth transistor T10 and the source of the twelfth transistor T12 are both pulled down to the same low level state as the signal of the first low-level terminal VGL1, thereby ensuring
  • the voltage between the gate-source of the tenth transistor T10 and the twelfth transistor T12 is less than zero, further ensuring that the tenth transistor T10 and the twelfth transistor T12 are turned off,
  • Embodiments of the present disclosure provide a display device including a plurality of shift register units in the above embodiments, and shift register units of each stage are sequentially cascaded, and a shift register unit in the display device is
  • the shift register unit in the above embodiment has the same advantages and will not be described herein.
  • the display device may be any product or component having a display function, such as a liquid crystal display panel, an electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.

Abstract

一种移位寄存器单元机器驱动方法与显示装置。所述移位寄存器单元包括输入单元（P1）、下拉补偿模块（P2）、下拉模块（P4）和上拉模块（P3），其中，下拉补偿模块（P2）用于在上拉控制节点（Q）的信号为高电平状态时，对下拉控制节点（QB）的信号进行至少两次下拉，确保将下拉控制节点（QB）的信号下拉至低电平状态。在制造过程不稳定、高温或低温的条件下，也能够保证下拉控制节点的信号的准确度，降低制造过程不稳定以及高温、低温等情况对移位寄存器单元中传输的信号的影响，从而提高显示装置的显示效果。

Description

移位寄存器单元及其驱动方法与显示装置 技术领域
本公开涉及一种移位寄存器单元及其驱动方法与显示装置。
背景技术
显示装置在进行显示时，需要利用移位寄存器实现对像素单元的扫描。移位寄存器包括多级移位寄存器单元，每一级移位寄存器单元对应一行像素单元。由多级移位寄存器单元实现对显示装置的像素单元的逐行扫描驱动，以显示图像。
在移位寄存器中，每一级移位寄存器单元都由多个薄膜晶体管构成，移位寄存器单元中的信号是通过各个薄膜晶体管进行传输的。然而，薄膜晶体管的阈值电压容易受到制造过程的稳定程度以及温度的影响。在制造过程不稳定、高温或低温的条件下，薄膜晶体管的阈值电压会发生较大幅度的变化，使得移位寄存器单元中的上拉控制节点的信号以及下拉控制节点的信号失真，从而导致移位寄存器单元输出的信号失真较为严重，有时甚至会导致移位寄存器单元无法输出信号，进而降低了显示装置的显示效果。
发明内容
本公开提供一种移位寄存器单元及其驱动方法与显示装置，用于降低制造过程不稳定以及高温、低温等情况对移位寄存器单元中传输的信号的影响，从而提高显示装置的显示效果。
按照本公开的第一方面，提供了一种移位寄存器单元，包括：
输入模块，其连接触发信号端、下拉信号端、第一时钟信号端、低电平端和上拉控制节点，用于在所述触发信号端的信号、所述第一时钟信号端的信号以及下拉信号端的信号的控制下，将所述触发信号端的信号或低电平端的信号传输至上拉控制节点；
下拉补偿模块，其连接控制信号端、所述上拉控制节点、下拉控制节点和低电平端，用于在所述上拉控制节点的信号为高电平状态时，对下拉控制节点的信号进行至少两次下拉，将所述下拉控制节点的信号下拉至低电平状态；
上拉模块，其连接第二时钟信号端、所述上拉控制节点和所述移位寄存器单元的输出端，用于在所述上拉控制节点的信号与所述第二时钟信号端的信号的控制下，将所述移位寄存器单元的输出端的信号上拉为高电平状态，以及利用自身的自举现象将所述上拉控制节点的信号上拉为高电平状态；
下拉模块，其连接所述输入模块、所述上拉模块、所述上拉控制节点、所述下拉控制节点、所述低电平端和所述移位寄存器单元的输出端，用于在所述下拉控制节点的信号的控制下，将所述移位寄存器的输出端的信号下拉为低电平状态，
其中，所述上拉控制节点为所述输入模块、下拉补偿模块、所述上拉模块和所述下拉模块的连接点，所述下拉控制节点为所述下拉补偿模块与所述下拉模块的连接点。
按照本公开的第二方面，提供了一种移位寄存器单元的驱动方法，包括：
在第一阶段中，通过输入模块接收触发信号端的信号、第一时钟信号端的信号和下拉信号端的信号，并在所述触发信号端的信号、所述第一时钟信号端的信号和所述下拉信号端的信号的控制下，将所述触发信号端的信号或低电平端的信号传输至上拉控制节点；在所述上拉控制节点为高电平状态时，通过下拉补偿模块对下拉控制节点的信号进行下拉，将下拉控制节点的信号下拉至低电平状态；在下拉控制节点的信号的控制下，通过下拉模块将所述移位寄存器的输出端的信号下拉为低电平状态；
在第二阶段中，由所述上拉模块利用自身的自举作用，将所述上拉控制节点的信号上拉为高电平状态；在所述上拉控制节点的信号与第二时钟信号端的信号的控制下，通过所述上拉模块将所述移位寄存器单元的输出端的信号上拉为高电平状态。
按照本公开的第三方面，提供一种显示装置，包括多级上述技术方案中所述的移位寄存器单元。
在本公开实施例提供的移位寄存器单元及其驱动方法与显示装置中，移位寄存器单元包括输入模块、下拉补偿模块、上拉模块和下拉模块，与现有技术中制造过程不稳定、高温或低温的条件下，移位寄存器单元输出的信号失真较为严重的移位寄存器单元相比，本公开实施例中的下拉补偿模块能够在上拉控制节点为高电平状态时，对下拉控制节点的信号进行至少两次下拉，确保下拉 控制节点被下拉为低电平状态。在制造过程不稳定、高温或低温的条件下，也能够保证下拉控制节点的信号的准确度，降低制造过程不稳定以及高温、低温等情况对移位寄存器单元中传输的信号的影响，从而提高显示装置的显示效果。
附图说明
此处所说明的附图用来提供对本公开的进一步理解，构成本公开的一部分。在附图中：
图1为本公开实施例一中的移位寄存器单元的结构示意图；
图2为本公开实施例二中的移位寄存器单元的一种结构示意图；
图3为与图2、图4、图7、图8中的移位寄存器单元均对应的信号时序图；
图4为本公开实施例二中的移位寄存器单元的另一种结构示意图；
图5为本公开中移位寄存器单元与现有技术中移位寄存器单元中上拉控制节点的允许电压对比图；
图6为本公开中移位寄存器单元与现有技术中移位寄存器单元中下拉控制节点的允许电压对比图；
图7为本公开实施例三中的移位寄存器单元的一种结构示意图；
图8为本公开实施例三中的移位寄存器单元的另一种结构示意图。
具体实施方式
为了进一步说明本公开实施例提供的移位寄存器单元及其驱动方法与显示装置，下面结合说明书附图进行详细描述。本公开的示意性实施例及其说明用于解释本公开，并不构成对本公开的限定。
图1示出本公开实施例一中的移位寄存器单元的结构示意图。
请参阅图1，本公开实施例提供的移位寄存器单元包括输入模块P1、下拉补偿模块P2、上拉模块P3和下拉模块P4。其中，输入模块P1连接触发信号端STU、下拉信号端STD、第一时钟信号端CLK1、低电平端VGL、下拉模块P4、上拉模块P3和上拉控制节点Q。上拉控制节点Q为输入模块P1、下拉补偿模块P2、上拉模块P3和下拉模块P4的连接点。输入模块P1用于在触 发信号端STU的信号、第一时钟信号端CLK1的信号以及下拉信号端STD的信号的控制下，将触发信号端STU的信号或低电平端VGL的信号传输至上拉控制节点Q。下拉补偿模块P2连接控制信号端CON、上拉控制节点Q、下拉控制节点QB和低电平端VGL。下拉控制节点QB为下拉补偿模块P2与下拉模块P4的连接点。下拉补偿模块P2用于在上拉控制节点Q的信号为高电平状态时，对下拉控制节点QB的信号进行至少两次下拉，将下拉控制节点QB的信号下拉至低电平状态。上拉模块P3连接第二时钟信号端CLK2、下拉模块P4、上拉控制节点Q和移位寄存器单元的输出端OUT。上拉模块P3用于在上拉控制节点Q的信号与第二时钟信号端CLK2的信号的控制下，将移位寄存器单元的输出端OUT的信号上拉为高电平状态，以及利用自身的自举作用，将上拉控制节点Q的信号上拉为高电平状态。下拉模块P4连接输入模块P1、上拉模块P3、上拉控制节点Q、下拉控制节点QB、低电平端VGL和移位寄存器单元的输出端OUT。下拉模块P4用于在下拉控制节点QB的信号的控制下，将移位寄存器的输出端的信号下拉为低电平状态。
下面将结合上述移位寄存器单元，对上述移位寄存器单元的驱动方法进行相关说明。上述移位寄存器单元的驱动方法包括以下工作过程：
在第一阶段中，由输入模块P1接收触发信号端STU的信号、第一时钟信号端CLK1的信号和下拉信号端STD的信号，并在触发信号端STU的信号、第一时钟信号端CLK1的信号和下拉信号端STD的信号的控制下，将触发信号端STU的信号或低电平端VGL的信号传输至上拉控制节点Q；下拉补偿模块P2在上拉控制节点Q为高电平状态时，对下拉控制节点QB的信号进行下拉，例如，可进行至少两次下拉，将下拉控制节点QB的信号下拉至低电平状态；下拉模块P4在下拉控制节点QB的信号的控制下，将移位寄存器的输出端的信号下拉为低电平状态。
在第二阶段中，上拉模块P3利用自身的自举作用，将上拉控制节点Q的信号上拉为高电平状态；上拉模块P3在上拉控制节点Q的信号与第二时钟信号端CLK2的信号的控制下，将移位寄存器单元的输出端OUT的信号上拉为高电平状态。
需要说明的是，上述驱动方法的第一阶段和第二阶段主要与各个信号端(比如触发信号端STU、下拉信号端STD、第一时钟信号端CLK1、第二时钟 信号端CLK2)的信号时序相关，并没有一定的时间先后顺序。
本公开实施例提供的移位寄存器单元及其驱动方法中，移位寄存器单元包括输入模块P1、下拉补偿模块P2、上拉模块P3和下拉模块P4，与现有技术中在制造过程不稳定、高温或低温的条件下，移位寄存器单元输出的信号失真较为严重的移位寄存器单元相比，本公开实施例中的下拉补偿模块P2能够在上拉控制节点Q为高电平状态时，对下拉控制节点QB的信号进行至少两次下拉，确保下拉控制节点QB被下拉为低电平状态。在制造过程不稳定、高温或低温的条件下，也能够保证下拉控制节点QB的信号的准确度，降低制造过程不稳定以及高温、低温等情况对移位寄存器单元中传输的信号的影响，从而提高显示装置的显示效果。
图2示出本公开实施例二中的移位寄存器单元的一种结构示意图。
请参阅图2，下面将通过举例详细说明实施例一中的输入模块P1、下拉补偿模块P2、上拉模块P3和下拉模块P4的具体结构。在该实例中，控制信号端CON为高电平端VGH。
如图2所示，输入模块P1包括第一晶体管T1、第二晶体管T2、第三晶体管T3和第四晶体管T4。第一晶体管T1的栅极连接触发信号端STU，第一晶体管T1的源极连接第二晶体管T2的漏极、第三晶体管T3的源极和第四晶体管T4的漏极，第一晶体管T1的漏极连接触发信号端STU。第二晶体管T2的栅极连接第一时钟信号端CLK1，第二晶体管T2的源极连接第三晶体管T3的漏极和上拉控制节点Q，第二晶体管T2的漏极连接第三晶体管T3的源极、第四晶体管T4的漏极、上拉模块P3和下拉模块P4。第三晶体管T3的栅极连接下拉信号端STD，第三晶体管T3的源极连接第四晶体管T4的漏极、上拉模块P3和下拉模块P4，第三晶体管T3的漏极连接上拉控制节点Q。第四晶体管T4的栅极连接下拉信号端STD，第四晶体管T4的源极连接低电平端VGL，第四晶体管T4的漏极连接上拉模块P3和下拉模块P4。
下拉补偿模块P2包括第五晶体管T5、第六晶体管T6、第七晶体管T7和第八晶体管T8。第五晶体管T5的栅极连接高电平端VGH，第五晶体管T5的源极连接第六晶体管T6的漏极和第七晶体管T7的栅极，第五晶体管T5的漏极连接高电平端VGH。第六晶体管T6的栅极连接上拉控制节点Q，第六晶体管T6的源极连接低电平端VGL，第六晶体管T6的漏极连接第七晶体管T7 的栅极。第七晶体管T7的源极连接下拉控制节点QB，第七晶体管T7的漏极连接高电平端VGH。第八晶体管T8的栅极连接上拉控制节点Q，第八晶体管T8的源极连接低电平端VGL，第八晶体管T8的漏极连接下拉控制节点QB。需要说明的是，在上拉控制节点Q的信号为高电平状态时，第五晶体管T5与第六晶体管T6对下拉控制节点QB的信号进行第一次下拉，第七晶体管T7与第八晶体管T8对下拉控制节点QB的信号进行第二次下拉。可替换地，下拉补偿模块P2还可以包括更多数目的晶体管，从而对下拉控制节点QB的信号进行更多次的下拉，但本实施例中的情况为下拉补偿模块包括四个晶体管，且这四个晶体管对下拉控制节点QB的信号进行两次下拉。
上拉模块P3包括第九晶体管T9、第十晶体管T10、第十一晶体管T11与第十二晶体管T12。第九晶体管T9的栅极连接上拉控制节点Q，第九晶体管T9的源极连接第十一晶体管T11的栅极和下拉模块P4，第九晶体管T9的漏极连接第二时钟信号端CLK2。第十晶体管T10的栅极连接上拉控制节点Q，第十晶体管T10的源极连接第十一晶体管T11的漏极和下拉模块P4，第十晶体管T10的漏极连接第二时钟信号端CLK2。第十一晶体管T11的栅极连接下拉模块P4，第十一晶体管T11的源极连接第一晶体管T1的源极和下拉模块P4，第十一晶体管T11的漏极连接下拉模块P4。第十二晶体管T12的栅极连接上拉控制节点Q，第十二晶体管T12的源极连接移位寄存器单元的输出端OUT，第十二晶体管T12的漏极连接第二时钟信号端CLK2。
下拉模块P4包括第十三晶体管T13、第十四晶体管T14、第十五晶体管T15、第十六晶体管T16与第十七晶体管T17。第十三晶体管T13的栅极连接下拉控制节点QB，第十三晶体管T13的源极连接第十四晶体管T14的漏极、第十一晶体管T11的源极和第一晶体管T1的源极，第十三晶体管T13的漏极连接上拉控制节点Q。第十四晶体管T14的栅极连接下拉控制节点QB，第十四晶体管T14的源极连接低电平端VGL，第十四晶体管T14的漏极连接第十一晶体管T11的源极和第一晶体管T1的源极。第十五晶体管T15的栅极连接下拉控制节点QB，第十五晶体管T15的源极连接低电平端VGL，第十五晶体管T15的漏极连接第九晶体管T9的源极和第十一晶体管T11的栅极。第十六晶体管T16的栅极连接下拉控制节点QB，第十六晶体管T16的源极连接低电平端VGL，第十六晶体管T16的漏极连接第十晶体管T10的源极和第十一晶 体管T11的漏极。第十七晶体管T17的栅极连接下拉控制节点QB，第十七晶体管T17的源极连接低电平端VGL，第十七晶体管T17的漏极连接移位寄存器单元的输出端OUT。
需要说明的是，上拉控制节点Q为第二晶体管T2的源极、第三晶体管T3的漏极、第六晶体管T6的栅极、第八晶体管T8的栅极、第九晶体管T9的栅极、第十晶体管T10的栅极、第十二晶体管T12的栅极与第十三晶体管T13的漏极的连接节点；下拉控制节点QB为第七晶体管T7的源极、第八晶体管T8的漏极、第十三晶体管T13的栅极、第十四晶体管T14的栅极、第十五晶体管T15的栅极、第十六晶体管T16的栅极与第十七晶体管T17的栅极的连接节点。
图3示出与图2中的移位寄存器单元对应的信号时序图。
下面将以上述各个晶体管均为N型晶体管为例，参照图3对图2所示的移位寄存器单元的驱动方法进行说明。
如图3所示，在A-B时间段中，触发信号端STU的信号与第一时钟信号端CLK1的信号均为高电平状态，下拉信号端STD的信号与第二时钟信号端CLK2的信号均为低电平状态，第一晶体管T1的栅极接收触发信号端STU的信号，第一晶体管T1导通；第二晶体管T2的栅极接收第一时钟信号端CLK1的信号，第二晶体管T2导通；第三晶体管T3的栅极与第四晶体管T4的栅极接收下拉信号端STD的信号，第三晶体管T3和第四晶体管T4均截止，上拉控制节点Q接收通过第一晶体管T1与第二晶体管T2传输来的触发信号端STU的信号；第五晶体管T5的栅极接收高电平端VGH的高电平信号，第五晶体管T5导通；第七晶体管T7的栅极接收通过第五晶体管T5传输来的高电平端VGH的高电平信号，第七晶体管T7导通；第六晶体管T6的栅极与第八晶体管T8的栅极接收上拉控制节点Q的信号，第六晶体管T6与第八晶体管T8导通，将下拉控制节点QB的信号下拉至低电平状态；第十三晶体管T13的栅极、第十四晶体管T14的栅极、第十五晶体管T15的栅极、第十六晶体管T16的栅极与第十七晶体管T17的栅极接收下拉控制节点QB的信号，第十三晶体管T13、第十四晶体管T14、第十五晶体管T15、第十六晶体管T16与第十七晶体管T17均截止；第九晶体管T9的栅极、第十晶体管T10的栅极与第十二晶体管T12的栅极接收上拉控制节点Q的信号，第九晶体管T9、第 十晶体管T10与第十二晶体管T12导通；第十二晶体管T12将第二时钟信号端CLK2的信号传输至移位寄存器的输出端，将移位寄存器的输出端的信号下拉为低电平状态。
B-C时间段中，触发信号端STU的信号与第一时钟信号端CLK1的信号均为低电平状态，下拉信号端STD的信号与第二时钟信号端CLK2的信号均为高电平状态，第一晶体管T1的栅极接收触发信号端STU的信号，第一晶体管T1截止；第二晶体管T2的栅极接收第一时钟信号端CLK1的信号，第二晶体管T2截止；第三晶体管T3的栅极与第四晶体管T4的栅极接收下拉信号端STD的信号，第三晶体管T3与第四晶体管T4导通；第九晶体管T9、第十晶体管T10与第十二晶体管T12的电容产生自举现象，将上拉控制节点Q的信号上拉为高电平状态；第五晶体管T5的栅极接收高电平端VGH的高电平信号，第五晶体管T5导通；第七晶体管T7的栅极接收通过第五晶体管T5传输来的高电平端VGH的高电平信号，第七晶体管T7导通；第六晶体管T6的栅极与第八晶体管T8的栅极接收上拉控制节点Q的信号，第六晶体管T6与第八晶体管T8导通，将下拉控制节点QB的信号下拉至低电平状态；第十三晶体管T13的栅极、第十四晶体管T14的栅极、第十五晶体管T15的栅极、第十六晶体管T16的栅极与第十七晶体管T17的栅极接收下拉控制节点QB的信号，第十三晶体管T13、第十四晶体管T14、第十五晶体管T15、第十六晶体管T16与第十七晶体管T17均截止；第九晶体管T9的栅极、第十晶体管T10的栅极与第十二晶体管T12的栅极接收上拉控制节点Q的信号，第九晶体管T9、第十晶体管T10与第十二晶体管T12均导通，第十二晶体管T12将第二时钟信号端CLK2的信号传输至移位寄存器单元的输出端OUT，将移位寄存器单元的输出端OUT的信号上拉为高电平状态。
C-D时间段中，触发信号端STU的信号与第二时钟信号端CLK2的信号为低电平状态，下拉信号端STD的信号与第一时钟信号端CLK1的信号为高电平状态，第一晶体管T1的栅极接收触发信号端STU的信号，第一晶体管T1截止；第二晶体管T2的栅极接收第一时钟信号端CLK1的信号，第二晶体管T2导通；第三晶体管T3的栅极与第四晶体管T4的栅极接收下拉信号端STD的信号，第三晶体管T3和第四晶体管T4均导通；上拉控制节点Q接收通过第三晶体管T3与第四晶体管T4传输来的低电平端VGL的低电平信号； 第五晶体管T5的栅极接收高电平端VGH的高电平信号，第五晶体管T5导通；第七晶体管T7的栅极接收通过第五晶体管T5传输来的高电平端VGH的高电平信号，第七晶体管T7导通；第六晶体管T6的栅极与第八晶体管T8的栅极接收上拉控制节点Q的信号，第六晶体管T6与第八晶体管T8截止；下拉控制节点QB接收通过第七晶体管T7传输来的高电平端VGH的高电平信号；第九晶体管T9的栅极、第十晶体管T10的栅极与第十二晶体管T12的栅极接收上拉控制节点Q的信号，第九晶体管T9、第十晶体管T10与第十二晶体管T12均截止；第十三晶体管T13的栅极、第十四晶体管T14的栅极、第十五晶体管T15的栅极、第十六晶体管T16的栅极与第十七晶体管T17的栅极接收下拉控制节点QB的信号，第十三晶体管T13、第十四晶体管T14、第十五晶体管T15、第十六晶体管T16与第十七晶体管T17导通，第十七晶体管T17将低电平端VGL的低电平信号传输至移位寄存器单元的输出端OUT，将移位寄存器单元的输出端OUT的信号下拉为低电平状态。
图4示出本公开实施例二中的移位寄存器单元的另一种结构示意图。
请参阅图4，可替换地，低电平端VGL可以包括第一低电平端VGL1和第二低电平端VGL2。第四晶体管T4的源极、第六晶体管T6的源极、第八晶体管T8的源极、第十四晶体管T14的源极与第十五晶体管T15的源极均连接第二低电平端VGL2，第十六晶体管T16的源极与第十七晶体管T17的源极均连接第一低电平端VGL1。其中第一低电平端VGL1的信号的电压高于第二低电平端VGL2的信号的电压，比如：第一低电平端VGL1的信号的电压为-5V，第二低电平端VGL2的信号的电压为-10V。由于在上拉控制节点Q的信号为低电平状态时，使得第六晶体管T6、第八晶体管T8截止，使得下拉控制节点QB的信号为高电平状态，第十三晶体管T13、第十四晶体管T14、第十五晶体管T15、第十六晶体管T16与第十七晶体管T17均导通，上拉控制节点Q放电至与第二低电平端VGL2的信号相同的低电平状态，第十晶体管T10的源极与第十二晶体管T12的源极均下拉至与第一低电平端VGL1的信号相同的低电平状态，从而保证第十晶体管T10、第十二晶体管T12的栅极-源极之间的电压小于零，进一步保证第十晶体管T10、第十二晶体管T12截止，提高了移位寄存器单元中信号传输的准确性，进一步提高了显示装置的显示效果。图4所示移位寄存器单元的驱动方法与图3所示的移位寄存器的驱动方法一 致，在此不再重复。
图5和图6分别示出本公开实施例提供的移位寄存器单元与现有技术的移位寄存器单元中的上拉控制节点和下拉控制节点的允许电压对比图。
下面请参阅图5与图6。从图5中的上拉控制节点的允许电压对比图可以看出，利用现有技术中的移位寄存器单元，当上拉控制节点Q的电压超过30.5V时，移位寄存器单元输出的信号失真严重，甚至无法输出信号；而利用本公开实施例中的移位寄存器单元，当上拉控制节点Q的电压超过37.9V时，移位寄存器单元输出的信号才可能发生失真严重或无法输出信号的情况。同理，从图6中的下拉控制节点的允许电压对比图可以看出，利用现有技术中的移位寄存器单元，当下拉控制节点QB的电压低于-3.87V时，移位寄存器单元输出的信号失真严重，甚至无法输出信号；而利用本公开实施例中的移位寄存器单元，当下拉控制节点QB的电压低于-7.2V时，移位寄存器单元输出的信号才可能发生失真严重或无法输出信号的情况。本公开实施例中的移位寄存器单元扩大了允许薄膜晶体管的阈值电压变化的范围，从而降低制造过程不稳定以及高温、低温等情况对移位寄存器单元中传输的信号的影响，从而提高显示装置的显示效果。
图7示出本公开的实施例三中的移位寄存器单元的一种结构示意图。
请参阅图7，可替换地，在本实施例中，控制信号端CON可以包括第一时钟信号端CLK1与第二时钟信号端CLK2，下拉补偿模块P2还可以采用另一种电路结构来实现，下面将进行详细说明。
如图7所示，下拉补偿模块P2可以包括第一下拉补偿子模块P21和第二下拉补偿子模块P22。第一下拉补偿子模块P21与第二下拉补偿子模块P22用于在上拉控制节点Q为高电平状态时，交替地对下拉控制节点QB的信号进行至少两次下拉，将下拉控制节点QB的信号下拉至低电平状态。例如，第一下拉补偿子模块P21包括第十八晶体管T18、第十九晶体管T19、第二十晶体管T20与第二十一晶体管T21。其中，第十八晶体管T18的栅极连接第一时钟信号端CLK1，第十八晶体管T18的源极连接第十九晶体管T19的漏极和第二十晶体管T20的栅极，第十八晶体管T18的漏极连接第一时钟信号端CLK1。第十九晶体管T19的栅极连接上拉控制节点Q，第十九晶体管T19的源极连接低电平端VGL，第十九晶体管T19的漏极连接第二十晶体管T20的栅极。 第二十晶体管T20的源极连接下拉控制节点QB，第二十晶体管T20的漏极连接第一时钟信号端CLK1。第二十一晶体管T21的栅极连接上拉控制节点Q，第二十一晶体管T21的源极连接低电平端VGL，第二十一晶体管T21的漏极连接下拉控制节点QB。第二下拉补偿子模块P22包括第二十二晶体管T22、第二十三晶体管T23、第二十四晶体管T24与第二十五晶体管T25。其中，第二十二晶体管T22的栅极连接第二时钟信号端CLK2，第二十二晶体管T22的源极连接第二十三晶体管T23的漏极和第二十四晶体管T24的栅极，第二十二晶体管T22的漏极连接第二时钟信号端CLK2。第二十三晶体管T23的栅极连接上拉控制节点Q，第二十三晶体管T23的源极连接低电平端VGL，第二十三晶体管T23的漏极连接第二十四晶体管T24的栅极。第二十四晶体管T24的源极连接下拉控制节点QB，第二十四晶体管T24的漏极连接第二时钟信号端CLK2。第二十五晶体管T25的栅极连接上拉控制节点Q，第二十五晶体管T25的源极连接低电平端VGL，第二十五晶体管T25的漏极连接下拉控制节点QB。在图7所示电路中，可选择地，第一时钟信号端CLK1的信号与第二时钟信号端CLK2的信号可以为反相信号。因此，受第一时钟信号端CLK1的信号控制的第一下拉补偿子模块P21和受第二时钟信号端CLK2的信号控制的第二下拉补偿子模块P22，交替对下拉控制节点QB的信号进行至少两次下拉。需要说明的是，第一下拉补偿子模块P21与第二下拉补偿子模块P22均可以包括更多数目的晶体管，从而交替对下拉控制节点QB进行至少两次下拉，但本实施例中的情况为第一下拉补偿子模块P21与第二下拉补偿子模块P22均包括四个晶体管，且第一下拉补偿子模块P21与第二下拉补偿子模块P22各自的四个晶体管交替对下拉控制节点QB进行两次下拉。
下面将以上述各个晶体管均为N型晶体管为例，对图7所示的移位寄存器单元的驱动方法进行说明。图3所示的信号时序同样适用于图7所示的移位寄存器单元。
A-B时间段，触发信号端STU的信号与第一时钟信号端CLK1的信号均为高电平状态，下拉信号端STD的信号与第二时钟信号端CLK2的信号均为低电平状态，第一晶体管T1的栅极接收触发信号端STU的信号，第一晶体管T1导通；第二晶体管T2的栅极接收第一时钟信号端CLK1的信号，第二晶体管T2导通；第三晶体管T3的栅极与第四晶体管T4的栅极接收下拉信号端 STD的信号，第三晶体管T3和第四晶体管T4均截止，上拉控制节点Q接收通过第一晶体管T1与第二晶体管T2传输来的触发信号端STU的信号；第十八晶体管T18的栅极接收第一时钟信号端CLK1的信号，第十八晶体管T18导通；第二十晶体管T20的栅极接收通过第十八晶体管T18传输来的第一时钟信号端CLK1的信号，第二十晶体管T20导通；第十九晶体管T19的栅极与第二十一晶体管T21的栅极接收上拉控制节点Q的信号，第十九晶体管T19与第二十一晶体管T21导通，将下拉控制节点QB的信号下拉至低电平状态；第二十二晶体管T22的栅极接收第二时钟信号端CLK2的信号，第二十二晶体管T22截止，此时，第二下拉补偿子模块P22处于备用状态；第十三晶体管T13的栅极、第十四晶体管T14的栅极、第十五晶体管T15的栅极、第十六晶体管T16的栅极与第十七晶体管T17的栅极接收下拉控制节点QB的信号，第十三晶体管T13、第十四晶体管T14、第十五晶体管T15、第十六晶体管T16与第十七晶体管T17均截止；第九晶体管T9的栅极、第十晶体管T10的栅极与第十二晶体管T12的栅极接收上拉控制节点Q的信号，第九晶体管T9、第十晶体管T10与第十二晶体管T12导通；第十二晶体管T12将第二时钟信号端CLK2的信号传输至移位寄存器单元的输出端OUT，将移位寄存器单元的输出端OUT的信号下拉为低电平状态。
B-C时间段中，触发信号端STU的信号与第一时钟信号端CLK1的信号均为低电平状态，下拉信号端STD的信号与第二时钟信号端CLK2的信号均为高电平状态，第一晶体管T1的栅极接收触发信号端STU的信号，第一晶体管T1截止；第二晶体管T2的栅极接收第一时钟信号端CLK1的信号，第二晶体管T2截止；第三晶体管T3的栅极与第四晶体管T4的栅极接收下拉信号端STD的信号，第三晶体管T3与第四晶体管T4导通；第九晶体管T9、第十晶体管T10与第十二晶体管T12的电容产生自举现象，将上拉控制节点Q的信号上拉为高电平状态；第二十二晶体管T22的栅极接收第二时钟信号端CLK2的信号，第二十二晶体管T22导通；第二十四晶体管T24的栅极接收通过第二十二晶体管T22传输来的第二时钟信号端CLK2的信号，第二十四晶体管T24导通；第二十三晶体管T23的栅极与第二十五晶体管T25的栅极接收上拉控制节点Q的信号，第二十三晶体管T23与第二十五晶体管T25导通，将下拉控制节点QB的信号下拉至低电平状态；第十八晶体管T18的栅极接收 第一时钟信号端CLK1的信号，第十八晶体管T18截止，第一下拉补偿子模块P21处于备用状态；第十三晶体管T13的栅极、第十四晶体管T14的栅极、第十五晶体管T15的栅极、第十六晶体管T16的栅极与第十七晶体管T17的栅极接收下拉控制节点QB的信号，第十三晶体管T13、第十四晶体管T14、第十五晶体管T15、第十六晶体管T16与第十七晶体管T17均截止；第九晶体管T9的栅极、第十晶体管T10的栅极和第十二晶体管T12的栅极接收上拉控制节点Q的信号，第九晶体管T9、第十晶体管T10与第十二晶体管T12均导通；第十二晶体管T12将第二时钟信号端CLK2的信号传输至移位寄存器单元的输出端OUT，将移位寄存器单元的输出端OUT的信号上拉为高电平状态。
C-D时间段中，触发信号端STU的信号与第二时钟信号端CLK2的信号为低电平状态，下拉信号端STD的信号与第一时钟信号端CLK1的信号为高电平状态，第一晶体管T1的栅极接收触发信号端STU的信号，第一晶体管T1截止；第二晶体管T2的栅极接收第一时钟信号端CLK1的信号，第二晶体管T2导通；第三晶体管T3的栅极与第四晶体管T4的栅极接收下拉信号端STD的信号，第三晶体管T3和第四晶体管T4均导通；上拉控制节点Q接收通过第三晶体管T3与第四晶体管T4传输来的低电平端VGL的低电平信号；第十八晶体管T18的栅极接收第一时钟信号端CLK1的信号，第十八晶体管T18导通；第二十晶体管T20的栅极接收通过第十八晶体管T18传输来的第一时钟信号端CLK1的信号，第二十晶体管T20导通；第十九晶体管T19的栅极与第二十一晶体管T21的栅极接收上拉控制节点Q的信号，第十九晶体管T19与第二十一晶体管T21截止；下拉控制节点QB接收通过第二十晶体管T20传输来的第一时钟信号端CLK1的信号；第二十二晶体管T22的栅极接收第二时钟信号端CLK2的信号，第二十二晶体管T22截止，第二下拉补偿子模块P22处于备用状态；第九晶体管T9的栅极、第十晶体管T10的栅极与第十二晶体管T12的栅极接收上拉控制节点Q的信号，第九晶体管T9、第十晶体管T10与第十二晶体管T12均截止；第十三晶体管T13的栅极、第十四晶体管T14的栅极、第十五晶体管T15的栅极、第十六晶体管T16的栅极与第十七晶体管T17的栅极接收下拉控制节点QB的信号，第十三晶体管T13、第十四晶体管T14、第十五晶体管T15、第十六晶体管T16与第十七晶体管T17导通，第十七晶体管T17将低电平端VGL的低电平信号传输至移位寄存器单 元的输出端OUT，将移位寄存器单元的输出端OUT的信号下拉为低电平状态。
图8示出本公开实施例三中的移位寄存器单元的另一种结构示意图。
请参阅图8，可替换地，低电平端VGL可以包括第一低电平端VGL1和第二低电平端VGL2。第十九晶体管T19的源极、第二十一晶体管T21的源极、第二十三晶体管T23的源极与第二十五晶体管T25的源极均连接所述第二低电平端VGL2，第十六晶体管T16的源极与第十七晶体管T17的源极均连接第一低电平端VGL1。其中第一低电平端VGL1的信号的电压高于第二低电平端VGL2的信号的电压，比如：第一低电平端VGL1的信号的电压为-5V，第二低电平端VGL2的信号的电压为-10V。由于在上拉控制节点Q的信号为低电平状态时，使得第十九晶体管T19、第二十一晶体管T21、第二十三晶体管T23与第二十五晶体管T25截止，使得下拉控制节点QB的信号为高电平状态，第十三晶体管T13、第十四晶体管T14、第十五晶体管T15、第十六晶体管T16与第十七晶体管T17均截止，上拉控制节点Q放电至与第二低电平端VGL2的信号相同的低电平状态，第十晶体管T10的源极与第十二晶体管T12的源极均下拉至与第一低电平端VGL1的信号相同的低电平状态，从而保证第十晶体管T10、第十二晶体管T12的栅极-源极之间的电压小于零，进一步保证第十晶体管T10、第十二晶体管T12截止，提高了移位寄存器单元中信号传输的准确性，进一步提高了显示装置的显示效果。图8所示移位寄存器单元的驱动方法与图3所示的移位寄存器的驱动方法一致，故在此不做赘述。
本公开实施例提供了一种显示装置，所述显示装置包括多级上述实施例中的移位寄存器单元，且各级移位寄存器单元依次级联，所述显示装置中的移位寄存器单元与上述实施例中的移位寄存器单元具有的优势相同，此处不再赘述。具体的，显示装置可以为液晶显示面板、电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。
本申请要求于2015年12月4日递交的中国专利申请第201510886307.0 号的优先权，在此全文引用该中国专利申请公开的内容作为本申请的一部分。

Claims (12)

  1. 一种移位寄存器单元，包括：
    输入模块，其连接触发信号端、下拉信号端、第一时钟信号端、低电平端和上拉控制节点，用于在所述触发信号端的信号、所述第一时钟信号端的信号以及下拉信号端的信号的控制下，将所述触发信号端的信号或低电平端的信号传输至所述上拉控制节点；
    下拉补偿模块，其连接控制信号端、所述上拉控制节点、下拉控制节点和低电平端，用于在所述上拉控制节点的信号为高电平状态时，对下拉控制节点的信号进行至少两次下拉，将所述下拉控制节点的信号下拉至低电平状态；
    上拉模块，其连接第二时钟信号端、所述上拉控制节点和所述移位寄存器单元的输出端，用于在所述上拉控制节点的信号与所述第二时钟信号端的信号的控制下，将所述移位寄存器单元的输出端的信号上拉为高电平状态，以及利用自身的自举现象将所述上拉控制节点的信号上拉为高电平状态；
    下拉模块，其连接所述输入模块、所述上拉模块、所述上拉控制节点、所述下拉控制节点、所述低电平端和所述移位寄存器单元的输出端，用于在所述下拉控制节点的信号的控制下，将所述移位寄存器的输出端的信号下拉为低电平状态，
    其中，所述上拉控制节点为所述输入模块、下拉补偿模块、所述上拉模块和所述下拉模块的连接点，所述下拉控制节点为所述下拉补偿模块与所述下拉模块的连接点。
  2. 根据权利要求1所述的移位寄存器单元，其中，所述输入模块包括：
    第一晶体管，其栅极连接触发信号端，其源极连接第二晶体管的漏极、第三晶体管的源极和第四晶体管的漏极，其漏极连接所述触发信号端；
    所述第二晶体管，其栅极连接第一时钟信号端，其源极连接第三晶体管的漏极和所述上拉控制节点，其漏极连接第三晶体管的源极、第四晶体管的漏极、所述上拉模块和所述下拉模块；
    所述第三晶体管，其栅极连接所述下拉信号端，其源极连接所述第四晶体管的漏极、所述上拉模块和所述下拉模块，其漏极连接所述上拉控制节点；
    所述第四晶体管，其栅极连接所述下拉信号端，其源极连接所述低电平端， 其漏极连接所述上拉模块和所述下拉模块。
  3. 根据权利要求2所述的移位寄存器单元，其中，所述下拉补偿模块包括：
    第五晶体管，其栅极连接所述控制信号端，其源极连接第六晶体管的漏极和第七晶体管的栅极，其漏极连接所述控制信号端；
    所述第六晶体管，其栅极连接所述上拉控制节点，其源极连接所述低电平端，其漏极连接所述第七晶体管的栅极；
    所述第七晶体管，其源极连接下拉控制节点，其漏极连接所述控制信号端；
    所述第八晶体管，其栅极连接所述上拉控制节点，其源极连接所述低电平端，其漏极连接所述下拉控制节点。
  4. 根据权利要求2所述的移位寄存器单元，其中，所述上拉模块包括：
    第九晶体管，其栅极连接所述上拉控制节点，其源极连接第十一晶体管的栅极和下拉模块，其漏极连接所述第二时钟信号端；
    所述第十晶体管，其栅极连接所述上拉控制节点，其源极连接所述第十一晶体管的漏极和所述下拉模块，其漏极连接所述第二时钟信号端；
    所述第十一晶体管，其栅极连接所述下拉模块，其源极连接所述第一晶体管的源极和所述下拉模块，其漏极连接所述下拉模块；
    所述第十二晶体管，其栅极连接所述上拉控制节点，其源极连接所述移位寄存器单元的输出端，其漏极连接所述第二时钟信号端。
  5. 根据权利要求4所述的移位寄存器单元，其中，所述下拉模块包括：
    第十三晶体管，其栅极连接所述下拉控制节点，其源极连接第十四晶体管的漏极、所述第十一晶体管的源极和所述第一晶体管的源极，其漏极连接所述上拉控制节点；
    第十四晶体管，其栅极连接所述下拉控制节点，其源极连接低电平端，其漏极连接所述第十一晶体管的源极和所述第一晶体管的源极；
    第十五晶体管，其栅极连接所述下拉控制节点，其源极连接所述低电平端，其漏极连接所述第九晶体管的源极和所述第十一晶体管的栅极；
    第十六晶体管，其栅极连接所述下拉控制节点，其源极连接所述低电平端，其漏极连接所述第十晶体管的源极和所述第十一晶体管的漏极；
    第十七晶体管，其栅极连接所述下拉控制节点，其源极连接所述低电平端， 其漏极连接所述移位寄存器单元的输出端。
  6. 根据权利要求1所述的移位寄存器单元，其中，所述控制信号端包括所述第一时钟信号端和第二时钟信号端；所述下拉补偿模块包括第一下拉补偿子模块和第二下拉补偿子模块，所述第一下拉补偿子模块与所述第二下拉补偿子模块用于在所述上拉控制节点为高电平状态时，交替对所述下拉控制节点的信号进行至少两次下拉，将所述下拉控制节点的信号下拉至低电平状态。
  7. 根据权利要求6所述的移位寄存器单元，其中，所述第一下拉补偿子模块包括：
    第十八晶体管，其栅极连接所述第一时钟信号端，其源极连接第十九晶体管的漏极和第二十晶体管的栅极，其漏极连接所述第一时钟信号端；
    所述第十九晶体管，其栅极连接所述上拉控制节点，其源极连接所述低电平端，其漏极连接所述第二十晶体管的栅极；
    所述第二十晶体管，其源极连接下拉控制节点，其漏极连接所述第一时钟信号端；
    所述第二十一晶体管，其栅极连接所述上拉控制节点，其源极连接所述低电平端，其漏极连接所述下拉控制节点。
  8. 根据权利要求6所述的移位寄存器单元，其中，所述第二下拉补偿子模块包括：
    第二十二晶体管，其栅极连接所述第二时钟信号端，其源极连接第二十三晶体管的漏极和第二十四晶体管的栅极，其漏极连接所述第二时钟信号端；
    所述第二十三晶体管，其栅极连接所述上拉控制节点，其源极连接所述低电平端，其漏极连接所述第二十四晶体管的栅极；
    所述第二十四晶体管，其源极连接下拉控制节点，其漏极连接所述第二时钟信号端；
    所述第二十五晶体管，其栅极连接所述上拉控制节点，其源极连接所述低电平端，其漏极连接所述下拉控制节点。
  9. 根据权利要求2、3或5中任意一项所述的移位寄存器单元，其中，所述低电平端包括第一低电平端和第二低电平端，所述第一低电平端的信号的电压高于所述第二低电平端的信号的电压；
    第四晶体管的源极、第六晶体管的源极、第八晶体管的源极、第十四晶体 管的源极与第十五晶体管的源极均连接所述第二低电平端，第十六晶体管的源极与第十七晶体管的源极均连接所述第一低电平端。
  10. 根据权利要求9所述的移位寄存器单元，其中，第十九晶体管的源极、第二十一晶体管的源极、第二十三晶体管的源极与第二十五晶体管的源极均连接所述第二低电平端。
  11. 一种如权利要求1-10中任意一项所述的移位寄存器单元的驱动方法，包括：
    在第一阶段中，通过输入模块接收触发信号端的信号、第一时钟信号端的信号和下拉信号端的信号，并在所述触发信号端的信号、所述第一时钟信号端的信号和所述下拉信号端的信号的控制下，将所述触发信号端的信号或低电平端的信号传输至上拉控制节点；在所述上拉控制节点为高电平状态时，通过下拉补偿模块对下拉控制节点的信号进行下拉，将下拉控制节点的信号下拉至低电平状态；在下拉控制节点的信号的控制下，通过下拉模块将所述移位寄存器的输出端的信号下拉为低电平状态；
    在第二阶段中，由所述上拉模块利用自身的自举作用，将所述上拉控制节点的信号上拉为高电平状态；在所述上拉控制节点的信号与第二时钟信号端的信号的控制下，通过所述上拉模块将所述移位寄存器单元的输出端的信号上拉为高电平状态。
  12. 一种显示装置，其中，包括多级如权利要求1-10中任意一项所述的移位寄存器单元。
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