WO2017056389A1 - 半導体基体、半導体装置、半導体基体の製造方法、並びに、半導体装置の製造方法 - Google Patents

半導体基体、半導体装置、半導体基体の製造方法、並びに、半導体装置の製造方法 Download PDF

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WO2017056389A1
WO2017056389A1 PCT/JP2016/003915 JP2016003915W WO2017056389A1 WO 2017056389 A1 WO2017056389 A1 WO 2017056389A1 JP 2016003915 W JP2016003915 W JP 2016003915W WO 2017056389 A1 WO2017056389 A1 WO 2017056389A1
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Prior art keywords
buffer layer
layer
substrate
boron
region
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English (en)
French (fr)
Japanese (ja)
Inventor
洋志 鹿内
憲 佐藤
勝 篠宮
慶太郎 土屋
和徳 萩本
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Sanken Electric Co Ltd
Shin Etsu Handotai Co Ltd
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Sanken Electric Co Ltd
Shin Etsu Handotai Co Ltd
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Priority to US15/760,579 priority Critical patent/US10529842B2/en
Priority to KR1020187008630A priority patent/KR102658784B1/ko
Priority to CN201680058423.6A priority patent/CN108140582B/zh
Publication of WO2017056389A1 publication Critical patent/WO2017056389A1/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6326—Deposition processes
    • H10P14/6328—Deposition from the gas or vapour phase
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H10D30/475—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs
    • H10D30/4755—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs having wide bandgap charge-carrier supplying layers, e.g. modulation doped HEMTs such as n-AlGaAs/GaAs HEMTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/015—Manufacture or treatment of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H10D30/475—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/60—Impurity distributions or concentrations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3414—Deposited materials, e.g. layers characterised by the chemical composition being group IIIA-VIA materials
    • H10P14/3416—Nitrides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/65—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials
    • H10P14/6516—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials
    • H10P14/6518—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials by introduction of substances into an already-existing insulating layer
    • H10P14/6524—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials by introduction of substances into an already-existing insulating layer the substance being nitrogen
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/90—Thermal treatments, e.g. annealing or sintering
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
    • H10D62/8503—Nitride Group III-V materials, e.g. AlN or GaN

Definitions

  • the present invention relates to a semiconductor substrate, a semiconductor device, a method for manufacturing a semiconductor substrate, and a method for manufacturing a semiconductor device.
  • the nitride semiconductor layer is generally formed on an inexpensive silicon substrate or sapphire substrate.
  • the lattice constants of these substrates and the nitride semiconductor layers are greatly different, and the thermal expansion coefficients are also different. Therefore, large strain energy is generated in the nitride semiconductor layer formed by epitaxial growth on the substrate. As a result, the nitride semiconductor layer is likely to generate cracks and crystal quality.
  • Patent Document 1 discloses that the buffer layer contains boron in order to reduce the pit density (that is, the defect density).
  • the longitudinal breakdown voltage is improved by doping the buffer layer with iron.
  • the vertical breakdown voltage of the buffer layer is increased by doping iron.
  • the inventors have found that the above prior art has the following problems. That is, even if boron is contained in the buffer layer to reduce the pit density, if the buffer layer is doped with an acceptor element such as a transition metal in order to improve the vertical breakdown voltage of the device, the pits caused by boron As a result, the suppression effect is lowered, resulting in deterioration of device characteristics.
  • the present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor substrate capable of obtaining a high pit suppression effect while maintaining a high vertical breakdown voltage, and a semiconductor device using the same.
  • the present invention comprises a substrate, a buffer layer made of a nitride semiconductor and provided on the substrate, and a channel layer made of a nitride semiconductor and provided on the buffer layer,
  • the buffer layer is provided on the substrate side, is provided on the first region with a boron concentration higher than the acceptor element concentration, and has a boron concentration lower than that of the first region.
  • a second region having a higher acceptor element concentration than the first region.
  • the buffer layer has the first region provided on the substrate side and having a boron concentration higher than the acceptor element concentration, and is provided on the first region and has a lower boron concentration than the first region.
  • the buffer layer includes a decrease region in which the boron concentration decreases from the substrate side toward the channel layer side, and the buffer layer is closer to the channel layer side than the boron concentration decrease start position of the decrease region.
  • the acceptor element includes an increasing region in which the acceptor element increases from the substrate side toward the channel layer side.
  • the buffer layer may include an initial layer made of AlN on the substrate side, and the initial layer may not include an acceptor element.
  • the buffer layer includes an initial layer made of AlN on the substrate side, and the acceptor element concentration of the initial layer can be made lower than the boron concentration of the initial layer.
  • the acceptor element is any one of a transition metal, carbon, and magnesium.
  • Such an element can be suitably used as an acceptor element to be introduced into the buffer layer.
  • the present invention also provides a semiconductor device comprising the semiconductor substrate described above and an electrode provided on the channel layer.
  • Such a semiconductor device can be a semiconductor device capable of obtaining a high pit suppression effect while maintaining a high vertical breakdown voltage.
  • the present invention is a method for manufacturing a semiconductor substrate, comprising: a step of forming a buffer layer made of a nitride semiconductor on a substrate; and a step of forming a channel layer made of a nitride semiconductor on the buffer layer,
  • the buffer layer includes an initial layer made of AlN on the substrate side, and the step of forming the buffer layer is such that the boron concentration of the buffer layer gradually decreases from the substrate side toward the channel layer side.
  • a step of introducing boron into the buffer layer wherein in the step of forming the buffer layer, doping of the acceptor element is started after the initial layer is formed. .
  • the step of introducing boron into the buffer layer includes a step of diffusing boron from the substrate doped with boron by thermal diffusion into the buffer layer. Can do.
  • boron is diffused from the substrate doped with boron by thermal diffusion into the buffer layer and boron is introduced into the buffer layer, so that the boron concentration of the buffer layer is more efficiently directed from the substrate side to the channel layer side. Can be gradually reduced.
  • the step of introducing boron into the buffer layer may include a step of doping boron from the vapor phase by introducing a boron-containing dopant gas when the buffer layer is formed by vapor deposition.
  • the buffer layer has sufficient boron to obtain a pit suppression effect. Can be contained.
  • transition metal any of transition metal, carbon, and magnesium as the acceptor element.
  • Such an element can be suitably used as an acceptor element to be introduced into the buffer layer.
  • the present invention also provides a method for manufacturing a semiconductor device, comprising the steps of preparing a semiconductor substrate manufactured by the above-described method of manufacturing a semiconductor substrate, and forming an electrode on the channel layer. To do.
  • Such a method for manufacturing a semiconductor device can manufacture a semiconductor device capable of obtaining a high pit suppression effect while maintaining a high vertical breakdown voltage.
  • the semiconductor substrate of the present invention can be a semiconductor substrate capable of obtaining a high pit suppression effect while maintaining a high vertical breakdown voltage.
  • the semiconductor device of the present invention can be a semiconductor device in which the generation of pits is suppressed while maintaining a high vertical breakdown voltage.
  • a semiconductor substrate capable of obtaining a high pit suppression effect while maintaining a high vertical breakdown voltage can be manufactured.
  • FIG. 6 is a diagram showing impurity profiles of semiconductor substrates in Examples 1 to 3 and Comparative Examples 1 to 3. It is a figure which shows the pit density evaluation result by the microscope dark field image analysis of the semiconductor substrate of Example 1 and Comparative Examples 1 to 3.
  • FIG. 3 is a diagram showing a boron concentration profile of a semiconductor substrate of Example 1. It is a figure which shows the impurity profile of a semiconductor substrate at the time of changing iron concentration by the AlN layer and GaN layer in the laminated body of a buffer layer.
  • the buffer layer may be formed to improve the vertical breakdown voltage of the device.
  • an acceptor element such as a transition metal is doped, there is a problem that the pit suppression effect due to boron is lowered and the device characteristics are deteriorated.
  • the present inventors have made extensive studies on a semiconductor substrate capable of obtaining a high pit suppressing effect while maintaining a high vertical breakdown voltage.
  • a first region provided on the substrate side and having a boron concentration higher than the acceptor element concentration and the first region provided on the first region and having a lower boron concentration than the first region.
  • the second region having a higher acceptor element concentration it is found that a high pit suppression effect can be obtained by the first region, and a high vertical breakdown voltage can be maintained by the second region, It came to make this invention.
  • the semiconductor substrate 10 includes a substrate 12, a buffer layer 25 made of a nitride semiconductor provided on the substrate 12, and a buffer layer 25.
  • a channel layer 26 made of a nitride semiconductor is provided.
  • the substrate 12 can be a silicon-based substrate such as a silicon substrate or a SiC substrate, and the channel layer 26 can be a GaN layer, for example.
  • the buffer layer 25 is provided on the substrate 12, has a boron concentration higher than the acceptor element concentration, and is provided on the first region 23 on the opposite side of the substrate 12, and has a boron concentration higher than that of the first region 23.
  • a second region 24 that is lower and has a higher acceptor element concentration than the first region 23 is included.
  • the boron concentration in the first region 23 is preferably 1 ⁇ 10 17 to 1 ⁇ 10 21 atoms / cm 3
  • the acceptor element concentration in the first region 23 is 1 ⁇ 10 15 to 1 ⁇ 10 15 atoms / cm 3. It is preferably 5 ⁇ 10 17 atoms / cm 3 .
  • the boron concentration in the second region 24 is preferably 1 ⁇ 10 13 to 1 ⁇ 10 15 atoms / cm 3
  • the acceptor concentration in the second region 24 is 5 ⁇ 10 17 to 1 ⁇ 10 20. It is desirable to be atoms / cm 3 .
  • the semiconductor substrate 10 can further include a barrier layer 27 on the channel layer 26, and the operation layer 29 can be formed by the channel layer 26 and the barrier layer 27.
  • the barrier layer 27 can be an AlGaN layer, for example.
  • the buffer layer 25 is provided on the substrate 12 side and has the first region 23 whose boron concentration is higher than the acceptor element concentration, a high pit suppressing effect can be obtained, and the nitride semiconductor layer on the first region 23 can be obtained. Pit can be suppressed satisfactorily. Further, the buffer layer 25 has a second region 24 provided on the first region 23 and having a boron concentration lower than that of the first region 23 and higher than that of the first region 23. High vertical pressure resistance can be maintained.
  • the semiconductor substrate 10 includes a decreasing region in which the boron concentration of the buffer layer 25 decreases from the substrate 12 side toward the channel layer 26 side, and the buffer layer 25 accepts closer to the channel layer 26 than the boron concentration decrease start position in the decreasing region. It is preferable to include an increasing region where the element increases from the substrate 12 side toward the channel layer 26 side. By adopting such a configuration, the acceptor element concentration on the substrate 12 side of the buffer layer 25 can be lowered more reliably, so that a higher pit suppressing effect can be achieved more effectively for the reduced region and the nitride semiconductor layer thereon. Obtainable.
  • the increasing rate of the acceptor element concentration in the increasing region in the buffer layer is larger than the decreasing rate in the decreasing region for lowering the acceptor element concentration above the channel region above the increasing region (that is, the slope is steep). Preferably).
  • the buffer layer 25 is provided on the substrate 12 side with an initial layer 13 made of AlN and on the initial layer 13. It can be set as the structure containing the laminated body 14 provided.
  • the stacked body 14 can be a stacked body in which a first layer 15 made of a nitride semiconductor and a second layer 16 having a composition different from that of the first layer 15 are repeatedly stacked.
  • the first layer 15 is made of, for example, AlyGa1-yN
  • the second layer 16 is made of, for example, AlxGa1-xN (0 ⁇ x ⁇ y ⁇ 1).
  • the first layer 15 can be an AlN layer
  • the second layer 16 can be a GaN layer.
  • the initial layer 13 can be made not to contain an acceptor element.
  • an initial layer in the buffer layer 25 By providing such an initial layer in the buffer layer 25, a higher pit suppressing effect can be obtained more effectively for the nitride semiconductor layer on the initial layer, and the elements in the buffer layer 25 and the substrate 12 can be obtained. Can be prevented from reacting.
  • the acceptor element concentration in the initial layer 13 can be made lower than the boron concentration in the initial layer 13.
  • the acceptor element introduced into the buffer layer 25 is any of transition metal, carbon, and magnesium. Such an element can be suitably used as the acceptor element, but iron is particularly preferable.
  • FIG. 3 is a schematic cross-sectional view showing an example of an embodiment of a semiconductor device of the present invention.
  • electrodes for example, the first electrode 30, the second electrode 31, and the control electrode 32
  • the concentration be lower than the channel layer 26 side concentration.
  • the first electrode 30 and the second electrode 31 are configured such that current flows from the first electrode 30 to the second electrode 31 via the two-dimensional electron gas 28 formed in the channel layer 26. Can be arranged. The current flowing between the first electrode 30 and the second electrode 31 can be controlled by the potential applied to the control electrode 32.
  • Such a semiconductor device can be a high-quality semiconductor device in which generation of pits is suppressed while maintaining a high vertical breakdown voltage.
  • the substrate 12 is prepared (see FIG. 4A).
  • the substrate 12 can be, for example, a silicon substrate or a SiC substrate.
  • an initial layer 13 made of AlN provided on the substrate 12 side of the buffer layer 25 is formed on the substrate 12 (see FIG. 4B).
  • the initial layer 13 can be grown to a thickness of 10 to 300 nm, for example, at a temperature of 800 ° C. to 1200 ° C., for example, by MOVPE (metal organic chemical vapor deposition).
  • a stacked body 14 made of a nitride semiconductor provided on the channel layer 26 side of the buffer layer 25 is formed on the initial layer 13 (see FIG. 4C).
  • the first layer 15 made of AlN (see FIG. 2) and the second layer 16 made of GaN (see FIG. 2) are heated to a temperature of, for example, 800 ° C. to 1200 ° C. by the MOVPE method. Can be grown alternately.
  • the film thickness of the first layer 15 is, for example, 3 to 30 nm
  • the film thickness of the second layer 16 is, for example, 2 to 7 nm.
  • the step of forming the buffer layer 25 is a step of introducing boron into the buffer layer so that the boron concentration of the buffer layer 25 gradually decreases from the substrate 12 side toward the channel layer 26 side. Is included.
  • boron as the substrate 12 is 1 ⁇ 10 18 atoms / cm 3 to 1 ⁇ 10 21 atoms / cm 3 , preferably 5 ⁇ 10 18 atoms / cm 3 to 5 ⁇ 10.
  • boron can be diffused from the substrate 12 doped with boron into the buffer layer 25 by thermal diffusion.
  • boron is diffused from the substrate doped with boron by thermal diffusion into the buffer layer 25, and boron is introduced into the buffer layer 25, so that the boron concentration of the buffer layer 25 can be more efficiently increased from the substrate 12 side. It can be gradually decreased toward the channel layer 26 side.
  • the step of introducing boron into the buffer layer 25 may be a step of doping boron from the vapor phase by introducing a boron-containing dopant gas when the buffer layer 25 is formed by vapor phase growth.
  • boron is doped from the vapor phase by introducing boron-containing dopant gas during the vapor phase growth, and boron is introduced into the buffer layer 25, so that sufficient pit suppression effect can be obtained. Can be contained in the buffer layer 25.
  • the acceptor element has a maximum value of 5 ⁇ 10 17 to 5 ⁇ 10 20 atoms / cm 3 after the initial layer 13 is formed.
  • Start doping Specifically, when the formation of the stacked body 14 by the MOCVD method is started, the addition of a doping gas of an acceptor element such as Cp 2 Fe (bisclopentadienyl iron) can be started. As described above, by starting the doping of the acceptor element after the initial layer is formed in the step of forming the buffer layer 25, a high pit suppression effect can be obtained while maintaining a high vertical breakdown voltage.
  • a channel layer 26 made of a nitride semiconductor is formed on the buffer layer 25 (see FIG. 4D).
  • the channel layer 26 made of GaN can be formed on the buffer layer 25 by MOVPE, for example, at a temperature of 800 ° C. to 1200 ° C. to 500 to 4000 nm.
  • a barrier layer 27 made of a nitride semiconductor can be formed on the channel layer 26 (see FIG. 4E).
  • the barrier layer 27 made of AlGaN can be formed on the channel layer 26 by MOVPE, for example, at a temperature of 800 ° C. to 1200 ° C. for 10 to 50 nm.
  • the channel layer 26 and the barrier layer 27 can form the operation layer 29.
  • acceptor element introduced into the buffer layer 25 it is preferable to use any of transition metals, carbon, and magnesium. Such an element can be suitably used as the acceptor element, and iron is particularly preferable.
  • the semiconductor substrate 10 can be manufactured as described above. If it is the manufacturing method of the semiconductor base demonstrated above, the semiconductor base
  • a semiconductor substrate 10 manufactured using the manufacturing method described above with reference to FIG. 4 is prepared (see FIG. 5A).
  • electrodes for example, the first electrode 30, the second electrode 31, and the control electrode 32
  • the first electrode 30 and the second electrode 31 can be formed of, for example, a laminated film of Ti / Al
  • the control electrode 32 is a lower layer film made of a metal oxide or metal nitride such as SiO or SiN.
  • an upper film made of a metal such as Ni, Au, Mo, and Pt.
  • the semiconductor device 11 can be manufactured as described above. With the above-described semiconductor device manufacturing method, it is possible to manufacture a high-quality semiconductor device in which generation of pits is suppressed while maintaining a high vertical breakdown voltage.
  • Example 1 A semiconductor substrate 10 as shown in FIG. 1 having a buffer layer having an iron concentration profile and a boron concentration profile shown in FIG. 6B was produced. That is, in the buffer layer of Example 1 including an initial layer made of AlN on a substrate 12 made of silicon, and a buffer layer made of a laminated body in which GaN layers and AlN layers are alternately laminated, A decreasing region where the boron concentration gradually decreases from 3 ⁇ 10 19 atoms / cm 3 from the substrate 12 side toward the channel layer 26 side, and an iron concentration provided on the decreasing region increases from the substrate 12 side toward the channel layer 26 side.
  • An electrode was formed on the channel layer 26 of the manufactured semiconductor substrate 10 through the barrier layer 27, and the semiconductor device 11 as shown in FIG. 3 was manufactured.
  • the device breakdown voltage (longitudinal breakdown voltage) when the semiconductor device 11 was turned off was measured using a measurement method as shown in FIG. 9. The measurement results are shown in FIG.
  • Example 2 A semiconductor substrate 10 as shown in FIG. 1 having a buffer layer having an iron concentration profile and a boron concentration profile shown in FIG. That is, in the buffer layer of Example 2 including an initial layer made of AlN on a substrate 12 made of silicon and a buffer layer made of a laminate in which GaN layers and AlN layers are alternately laminated, A decreasing region where the boron concentration gradually decreases from 3 ⁇ 10 19 atoms / cm 3 from the substrate 12 side toward the channel layer 26 side, and an iron concentration provided on the channel layer 26 side from the boron concentration decreasing start position There is an increasing region that increases from the side toward the channel layer 26 toward 5 ⁇ 10 19 atoms / cm 3 , and the boron concentration decreasing region partially overlaps the iron concentration increasing region, and the boron concentration decreases, The iron concentration is gradually increasing.
  • the increasing rate of the acceptor element concentration in the increasing region in the buffer layer is larger than the decreasing rate in the decreasing region for lowering the acceptor element concentration above the channel region above the increasing region (that is, the slope is steep). is there).
  • the produced semiconductor substrate 10 was subjected to light spot density evaluation (that is, pit density evaluation) in the same manner as in Example 1. The evaluation results were almost the same as those in Example 1. Moreover, about the produced semiconductor base
  • An electrode was formed on the channel layer 26 of the manufactured semiconductor substrate 10 through the barrier layer 27, and the semiconductor device 11 as shown in FIG. 3 was manufactured.
  • the device breakdown voltage longitudinal breakdown voltage
  • the total number of iron atoms in the buffer layer is larger than that in Example 1, and thus the measurement result is better than that in Example 1. It became a result.
  • Example 3 A semiconductor substrate 10 as shown in FIG. 1 provided with a buffer layer having an iron concentration profile and a boron concentration profile shown in FIG. That is, in the buffer layer of Example 3 including an initial layer made of AlN on a substrate 12 made of silicon and a buffer layer made of a laminate in which GaN layers and AlN layers are alternately laminated, A decreasing region where the boron concentration gradually decreases from 3 ⁇ 10 19 atoms / cm 3 from the substrate 12 side toward the channel layer 26 side, and an iron concentration provided on the channel layer 26 side from the boron concentration decreasing start position There is an increasing region that increases from the side toward the channel layer 26 toward 5 ⁇ 10 19 atoms / cm 3 , and the boron concentration decreasing region does not overlap with the iron concentration increasing region (that is, after the boron concentration decreases) , The iron concentration is increasing).
  • the increasing rate of the acceptor element concentration in the increasing region in the buffer layer is larger than the decreasing rate in the decreasing region for lowering the acceptor element concentration above the channel region above the increasing region (that is, the slope is steep). is there).
  • the produced semiconductor substrate 10 was subjected to light spot density evaluation (that is, pit density evaluation) in the same manner as in Example 1. The evaluation result was better than that of Example 1. Moreover, about the produced semiconductor base
  • An electrode was formed on the channel layer 26 of the manufactured semiconductor substrate 10 through the barrier layer 27, and the semiconductor device 11 as shown in FIG. 3 was manufactured.
  • the device breakdown voltage longitudinal breakdown voltage
  • the total number of iron atoms in the buffer layer was smaller than in Example 1, and thus the measurement result was slightly more than in Example 1. The result was inferior.
  • Comparative Example 1 A semiconductor substrate provided with a buffer layer having an iron concentration profile and a boron concentration profile shown in FIG. That is, the buffer layer of Comparative Example 1 was not subjected to iron doping or boron doping.
  • the produced semiconductor substrate was subjected to light spot density evaluation (that is, pit density evaluation) in the same manner as in Example 1. The evaluation results are shown in FIG. Moreover, the length of the crack from a board
  • Comparative Example 2 A semiconductor substrate provided with a buffer layer having an iron concentration profile and a boron concentration profile shown in FIG. That is, in the buffer layer of Comparative Example 2, boron doping was performed as in Example 1, but iron doping was not performed.
  • the produced semiconductor substrate was subjected to light spot density evaluation (that is, pit density evaluation) in the same manner as in Example 1. The evaluation results are shown in FIG. Moreover, the length of the crack from a board
  • An electrode was formed on the channel layer of the manufactured semiconductor substrate via a barrier layer to manufacture a semiconductor device.
  • the produced semiconductor device it carried out similarly to Example 1, and measured device breakdown voltage (longitudinal breakdown voltage). The measurement results are shown in FIG.
  • Example 3 A semiconductor substrate provided with a buffer layer having an iron concentration profile and a boron concentration profile shown in FIG. That is, in the buffer layer of Comparative Example 3, boron doping was performed in the same manner as in Example 1, but iron doping was performed on the entire buffer layer (ie, from the initial layer of the buffer layer).
  • the produced semiconductor substrate was subjected to light spot density evaluation (that is, pit density evaluation) in the same manner as in Example 1. The evaluation results are shown in FIG. Moreover, the length of the crack from a board
  • An electrode was formed on the channel layer of the manufactured semiconductor substrate via a barrier layer to manufacture a semiconductor device.
  • the device breakdown voltage (longitudinal breakdown voltage) was measured in the same manner as in Example 1 in the region where the pits of the manufactured semiconductor device were not observed. The measurement results are shown in FIG.
  • Example 1 which performed iron doping from the laminated body, there was no influence of iron doping and the pit suppression effect equivalent to the comparative example 2 which did not perform iron doping was acquired.
  • Example 2 where the boron concentration decreased on the substrate side of the buffer layer and the iron concentration increased, the same pit suppression effect as in Example 1 was obtained.
  • Example 3 in which the iron concentration increased after the boron concentration decreased on the substrate side of the buffer layer, a better pit suppression effect than in Example 1 was obtained.
  • Example 1 in Comparative Example 3 in which iron doping is performed from the AlN initial layer (that is, iron doping is performed on the entire buffer layer), the crack extends longer while AlN doped with boron.
  • Example 1 in which the initial layer was not doped with iron but was doped with iron from a laminate with a reduced boron concentration, the crack length was the same as in Comparative Example 2 where no iron was doped. This is considered to be an effect by not doping the boron-doped layer with iron.
  • Example 2 where the boron concentration decreased on the substrate side of the buffer layer and the iron concentration increased, the crack length was the same as in Example 1.
  • Example 3 in which the iron concentration increased after the boron concentration decreased on the substrate side of the buffer layer, the crack length was the same as that in Example 1.
  • Example 1 which performed iron doping from the laminated body also has the effect (namely, improvement of a vertical direction pressure
  • the longitudinal breakdown voltage equivalent to that of Comparative Example 3 was obtained because the layer of the buffer layer doped with boron (that is, the layer not doped with iron) is shown in FIG.
  • Example 2 in which the boron concentration decreased on the substrate side of the buffer layer and the iron concentration increased, a better vertical breakdown voltage than in Example 1 was obtained. Further, in Example 3 in which the iron concentration increased after the boron concentration decreased on the substrate side of the buffer layer, a longitudinal breakdown voltage better than that in Comparative Example 2 was obtained although it was slightly inferior to Example 1.
  • the present invention is not limited to the above embodiment.
  • the above-described embodiment is an exemplification, and the present invention has substantially the same configuration as the technical idea described in the claims of the present invention, and any device that exhibits the same function and effect is the present invention. It is included in the technical scope of the invention.
  • the semiconductor substrate 10 ′ of FIG. 2 only the first layer 15 (for example, AlN layer) of the stacked body 14 includes the acceptor element, and the second layer 16 (for example, GaN layer) does not include the acceptor element. Or you may make it reduce. In this case, as shown in FIG.
  • the impurity profile in Example 1 is such that the iron concentration increases at the location of the AlN layer of the stack, and the iron concentration decreases at the location of the GaN layer of the stack. It will be a thing.
  • the impurity profile in Example 2 shows that the iron concentration increases in the initial layer and the AlN layer of the stack, and the iron concentration decreases in the GaN layer of the stack. It will be like that. Even in the above case, the same effect can be obtained. Further, the expression “above” includes a case where there are different layers between them.

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PCT/JP2016/003915 2015-09-30 2016-08-29 半導体基体、半導体装置、半導体基体の製造方法、並びに、半導体装置の製造方法 Ceased WO2017056389A1 (ja)

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KR1020187008630A KR102658784B1 (ko) 2015-09-30 2016-08-29 반도체 기체, 반도체 장치, 반도체 기체의 제조 방법, 및, 반도체 장치의 제조 방법
CN201680058423.6A CN108140582B (zh) 2015-09-30 2016-08-29 半导体衬底、半导体装置、半导体衬底的制造方法、以及半导体装置的制造方法

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