WO2017049844A1 - 预充电电路、扫描驱动电路、阵列基板和显示装置 - Google Patents

预充电电路、扫描驱动电路、阵列基板和显示装置 Download PDF

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Publication number
WO2017049844A1
WO2017049844A1 PCT/CN2016/073633 CN2016073633W WO2017049844A1 WO 2017049844 A1 WO2017049844 A1 WO 2017049844A1 CN 2016073633 W CN2016073633 W CN 2016073633W WO 2017049844 A1 WO2017049844 A1 WO 2017049844A1
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Prior art keywords
node
unit
transistor
output
potential
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PCT/CN2016/073633
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English (en)
French (fr)
Inventor
王俊伟
封宾
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京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Priority to US15/538,007 priority Critical patent/US10157684B2/en
Publication of WO2017049844A1 publication Critical patent/WO2017049844A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/18—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages
    • G11C19/182—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes
    • G11C19/184—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes with field-effect transistors, e.g. MOS-FET
    • G11C19/186—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes with field-effect transistors, e.g. MOS-FET using only one transistor per capacitor, e.g. bucket brigade shift register
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/18—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages
    • G11C19/182—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes
    • G11C19/188—Organisation of a multiplicity of shift registers, e.g. regeneration, timing or input-output circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0248—Precharge or discharge of column electrodes before or after applying exact column voltages

Definitions

  • the present disclosure relates to a precharge circuit, a scan drive circuit, an array substrate, and a display device.
  • a precharge circuit, a scan drive circuit, an array substrate, and a display device are provided in an embodiment of the present disclosure.
  • a precharge circuit comprising an input end and an output end, further comprising a switch unit, a first pull up unit and a second pull up unit, wherein:
  • the first end of the switch unit is connected to the first node, the second end is connected to the input end, and the third end is connected to the second node, for conducting the second end and the third end when the first end is at a high level ;
  • the first end of the first pull-up unit is connected to the output end, and the second end is connected to the first node, for pulling up the potential at the second end when the first end is at a high level;
  • the switching unit includes a first transistor, a gate of the first transistor is connected to the first node, one of a source and a drain is connected to the input end, and the other is connected to the second node.
  • the first pull-up unit includes a second transistor, a gate of the second transistor is connected to the output end, one of a source and a drain is connected to the output end, and the other is connected to the first One node.
  • the second pull-up unit includes a third transistor, a gate of the third transistor is connected to the second node, and one of a source and a drain is connected to the second node, and another connection is Said output.
  • the pre-charging circuit further includes a reset module; the reset module is connected to the first node, and is configured to be at the first node after being turned from a high level to a low level at the input end The electrical position is low.
  • the reset module includes a fourth transistor, a gate of the fourth transistor is connected to the first node, one of a source and a drain is connected to the first node, and the other is connected to the input end. .
  • the reset module includes a fifth transistor, a gate of the fifth transistor is connected to the initial input signal, one of the source and the drain is connected to the first node, and the other is connected to the low voltage line. .
  • the potential at the input terminal is pulled up to a high level to maintain a low level at the output end;
  • the first pull-up unit pulls up the potential at the first node
  • the switching unit turns on the input end and the second node, and the second pull-up unit pulls up a potential at the output end;
  • the electrical position at the input is at a low level, and the high level of the output is maintained, such that: the first pull-up unit pulls up the potential at the first node
  • the switch unit turns on the input end and the second node;
  • the low level of the input is maintained and the electrical position at the output is low.
  • a scan driving circuit comprising a multi-stage shift register unit; wherein any one of the precharge circuits of any one of the above two stages of the shift register unit is provided .
  • the scan driving circuit specifically includes: a multi-stage first shift register unit driven by the first clock signal and the third clock signal, and a multi-stage driven by the second clock signal and the fourth clock signal a second shift register unit; the input end and the output end of the multi-stage first shift register unit are sequentially connected in series; the input end and the output end of the multi-stage second shift register unit are sequentially connected in series; Between the output of the first shift register unit and the output of the second shift register unit of the i-th stage, and the output of the second shift register unit of the i-th stage and the first of the i+1th stage A precharge circuit of any of the above is provided between the output terminals of the shift register unit; the i is a positive integer.
  • the first clock signal, the second clock signal, the third clock signal, and the fourth clock cycle in a clock cycle beginning with the first clock signal being converted to an active level
  • the time period during which the clock signal is at the active level is sequentially delayed by a predetermined time; the length of the predetermined time is less than one-half of the clock period.
  • an array substrate comprising the scan driving circuit of any of the above.
  • a display area is disposed on the array substrate, the scan driving circuit is disposed on at least one side of the display area, and the pre-charge circuit is disposed within the display area.
  • a display device comprising the array substrate of any of the above.
  • the pre-charging circuit of the embodiment of the present disclosure can pre-charge the next-stage scan driving signal by using the one-stage scan driving signal, so that the output capability of the scan driving signal can be improved based on the principle of charge sharing.
  • the power consumption of the scan driving circuit can be reduced while ensuring the output capability of the scan driving signal, which is advantageous for improving product performance and solving The problem of insufficient scanning signal output capability in large-size GOA products.
  • FIG. 2 is a schematic diagram showing the circuit structure of a precharge circuit in an embodiment of the present disclosure
  • FIG. 3 is a schematic diagram showing the circuit structure of a precharge circuit in still another embodiment of the present disclosure.
  • FIG. 4 is a schematic circuit diagram of a precharge circuit according to another embodiment of the present disclosure.
  • FIG. 5 is a schematic flow chart showing the steps of a driving method of a precharge circuit in an embodiment of the present disclosure
  • FIG. 6 is a circuit timing diagram of a precharge circuit in an embodiment of the present disclosure.
  • FIG. 7 is a schematic structural diagram of a scan driving circuit in an embodiment of the present disclosure.
  • the precharge circuit 1 includes an input terminal IN and an output terminal OUT, and further includes a switch unit 11, a first pull-up unit 12, and a second pull-up unit 13.
  • the first end of the switch unit 11 is connected to the first node P1, the second end is connected to the input terminal IN, and the third end is connected to the second node P2.
  • the switch unit 11 is configured to turn on the second end and the third end when the first end is at a high level;
  • the first end of the first pull-up unit 12 is connected to the output end OUT, and the second end is connected to the first node P1.
  • the first pull-up unit 12 is configured to pull up a potential at the second end when the first end is at a high level;
  • the first end of the second pull-up unit 13 is connected to the second node P2, and the second end is connected to the output terminal OUT.
  • the second pull-up unit 13 is for pulling up the potential at the second end when it is at a high level at the first end.
  • pulse-up in this context refers to raising the level at the corresponding circuit node to a high level.
  • pulse-down refers to lowering the level at the corresponding circuit node to a low level. Level. It can be understood that the above-mentioned “pull-up” and “pull-down” can be realized by the directional movement of the electric charge, and thus can be realized by the electronic component having the corresponding function or a combination thereof, which is not limited by the disclosure.
  • the input terminal IN and the output terminal OUT are both connected to a low level, pre-charging
  • the first node P1 and the second node P2 inside the circuit 1 are both at a low level, so that the above-mentioned switching unit 11, the first pull-up unit 13, and the second pull-up unit 13 do not work, and the potential at each node remains unchanged. change.
  • the switching unit 11 and the first pull-up unit 13 are in the process of starting from the low level to the high level at the input terminal IN.
  • the two pull-up units 13 remain in the previous operating state, so the potentials at the first node P1, the second node P2, and the output terminal OUT remain unchanged.
  • the first pull-up unit 12 can be at the output terminal OUT.
  • the potential at the first node P1 is pulled up by the high level, so that the potential at the first node P1 quickly reaches a high level (the high level at the first node P1 is lower than the high level at the output terminal OUT) .
  • the switching unit 11 turns on the input terminal IN and the second node P2 under the high level of the first node P1, so that the high level at the input terminal IN pulls up the potential at the second node P2.
  • the second pull-up unit 13 can reversely pull up the potential at the output terminal OUT, forming a positive feedback of the potential rise at the output terminal OUT, and accelerating the output terminal OUT.
  • the rise in potential is the first level at the second node P2
  • the scan drive signal can be used to preprocess another scan drive signal. Charging, so that the output capability of the scan driving signal can be improved based on the principle of charge sharing.
  • the embodiment of the present disclosure can reduce the power consumption of the scan driving circuit while ensuring the output capability of the scan driving signal, thereby contributing to product performance, because the requirement of the maximum amplitude voltage of the scan driving signal can be reduced. Improvement.
  • FIG. 2 is a schematic diagram of a circuit structure of a precharge circuit in an embodiment of the present disclosure.
  • the switching unit 11 may include a first transistor T1.
  • the gate of the first transistor T1 is connected to the first node P1, one of the source and the drain is connected to the input terminal IN, and the other is connected to the second node P2.
  • the first transistor T1 in FIG. 1 is an N-type transistor, so that one end connected to the second node P2 is a source, and one end connected to the input terminal IN is a drain. It can be seen that when the first node P1 is at a high level, a current can be conducted between the source and the drain of the first transistor T1, so that the function of the above-mentioned switching unit 11 can be realized, and can be combined with the existing GOA. The process is integrated to reduce manufacturing costs.
  • the first pull up unit 12 includes a second transistor T2.
  • the gate of the second transistor T2 is connected to the output terminal OUT, one of the source and the drain is connected to the output terminal OUT, and the other is connected to the first node P1.
  • the second transistor T2 in FIG. 1 is an N-type transistor, so that one end connected to the first node P1 is a source, and one end connected to the output terminal OUT is a drain. It can be seen that when the output terminal OUT is at a high level, the current between the source and the drain of the second transistor T2 can be turned on and the pull-up of the potential at the first node P1 can be realized, so that the above first can be realized.
  • the function of the unit 12 is pulled and integrated with existing GOA processes to reduce manufacturing costs.
  • the second pull-up unit 13 includes a third transistor T3.
  • the gate of the third transistor T3 is connected to the second node P2, one of the source and the drain is connected to the second node P2, and the other is connected to the output terminal OUT.
  • the third transistor T3 in FIG. 1 is an N-type transistor, so that one end connected to the output terminal OUT is a source, and one end connected to the second node P2 is a drain. It can be seen that when the second node P2 is at a high level, the current between the source and the drain of the third transistor T3 can be turned on and the pull-up of the potential at the output terminal OUT can be realized, so that the above second can be realized.
  • the function of the unit 13 is pulled and integrated with the existing GOA process to reduce the manufacturing cost.
  • the pre-charge circuit if the coupling capacitance at the first node is too large, then the potential at the output terminal changes from a low level to a high level, and then from a high level to a low level at the first node. The potential will be held high for a period of time, so that the pre-charge circuit will not return to the normal state, and thus may affect the workflow of the next time (such as in the next display frame after a display frame).
  • a reset module connected to the first node P1 may be added on the basis of any of the precharge circuits described above, and the reset module is used to switch from a high level to a low level at the input end OUT.
  • the electrical position at the first node P1 is at a low level.
  • FIG. 3 is a schematic diagram of a circuit structure of a precharge circuit in still another embodiment of the present disclosure.
  • the precharge circuit shown in FIG. 3 adds a reset module 14 including a fourth transistor T4 to the circuit structure shown in FIG.
  • the gate of the fourth transistor T4 is connected to the first node P1, and one of the source and the drain is also connected to the first node P1, and the other is connected to the input terminal IN.
  • a current can be conducted between the source and the drain of the fourth transistor T4 so that the electrical position at the first node P1 can be set to a low level at the input terminal IN.
  • Low level so the function of the above-described reset unit 14 can be realized, and can be integrated with the existing GOA process to reduce the manufacturing cost.
  • FIG. 4 is a schematic diagram of a circuit structure of a precharge circuit in another embodiment of the present disclosure. It can be seen that the precharge circuit shown in FIG. 4 adds a reset module 14 including a fifth transistor T5 and a sixth transistor T6 to the circuit structure shown in FIG. 2 (the reset module 14 is illustrated by 14a and 14b). Two parts).
  • the precharge circuit shown in FIG. 4 adds a reset module 14 including a fifth transistor T5 and a sixth transistor T6 to the circuit structure shown in FIG. 2 (the reset module 14 is illustrated by 14a and 14b). Two parts).
  • the reset module 14 is illustrated by 14a and 14b. Two parts).
  • the gate of the fifth transistor T5 is connected to the start input signal STV (specifically, a control signal that is an active level for at least part of the time between returning from the normal state to the rise of the potential at the input terminal, applied to
  • the scan driving circuit may be specifically an input signal of the first stage shift register unit, one of the source and the drain is connected to the first node P1, and the other is connected to the low level voltage line Vss. Therefore, when the initial input signal STV is at an active level, a current can be conducted between the source and the drain of the fifth transistor T5, and thus the first node P1 can be set to a low level by the low-level voltage line Vss.
  • the function of the reset unit 14 described above is implemented.
  • the gate of the sixth transistor T6 is connected to the above-described initial input signal STV, one of the source and the drain is connected to the second node P2, and the other is connected to the low-voltage voltage line Vss. Therefore, the electrical position at the second node P2 can be set to a low level by a similar process, thereby realizing the reset of the potential at the second node P2, and improving the stability of the precharge circuit operation. It can be understood that when any one of the transistors in the embodiments of the present disclosure has a structure in which the source and the drain are symmetric, the source and the drain thereof can be regarded as two electrodes which are not particularly distinguished. In the specific implementation, the type of transistor can be selected according to the application requirements.
  • FIG. 5 is a flow chart showing the steps of a driving method of a precharge circuit in an embodiment of the present disclosure. Referring to Figure 5, the method includes the following steps:
  • Step 301 In the first phase, pull the potential at the input terminal to a high level to maintain a low level at the output end;
  • Step 302 In the second phase, the high potential of the input terminal is maintained, and the potential at the output terminal is pulled up to a high level, so that: the first pull-up unit pulls up the potential at the first node, and the switch unit inputs The terminal is electrically connected to the second node, and the second pull-up unit pulls up the potential at the output end;
  • Step 303 In the third stage, the electric position at the input end is a low level, and the high level of the output end is maintained, so that: the first pull-up unit pulls up the potential at the first node, and the switch unit inputs The terminal is electrically connected to the second node;
  • Step 304 In the fourth phase, keep the input low level and the electrical position at the output end Is low.
  • FIG. 6 is a circuit timing diagram of a precharge circuit in one embodiment of the present disclosure. Taking the precharge circuit shown in FIG. 2 as an example, the step flow shown in FIG. 5 and the circuit timing shown in FIG. 6 will be described in detail below:
  • the potential at the input terminal IN is pulled up to a high level in step 301 while maintaining a low level at the output terminal OUT, so that the first transistor T1, the second transistor T2, and the third transistor T3 is in a closed state, and the potentials at the first node P1 and the second node P2 are both kept at a low level.
  • the high potential of the input terminal IN is maintained in step 302, and the potential at the output terminal OUT is pulled up to a high level, so that the potential of the second transistor T2 starts to rise after the output terminal OUT starts to rise.
  • the third transistor T3 turns on and pulls up the potential at the output terminal OUT, forming a positive feedback and accelerating the rise of the potential at the output terminal OUT.
  • step 303 the electrical position at the input terminal IN is at a low level, and the high level of the output terminal OUT is maintained, so that the second transistor T2 remains open under the high potential at the output terminal OUT.
  • the potential at the first node P1 is maintained at a high level; the potential at the second node P2 is pulled down by the first transistor T1 that is turned on, so that the third transistor T3 is turned off.
  • the low level of the input terminal IN is maintained in step 304 and the electrical position at the output terminal OUT is low.
  • the second transistor T2 and the third transistor T3 remain off, and the high level at the first node P1 is gradually lowered to a low level by the coupling capacitor.
  • the first transistor T1 is caused to transition from on to off (or in a floating state).
  • the pre-charging circuit includes the reset module 14 of any of the above, the potential at the first node P1 can be returned to the low level in the normal state, so that the pre-charging is performed when the above steps 301 to 304 are continued thereafter.
  • the circuit can repeat the workflow of the first to fourth stages described above.
  • an embodiment of the present disclosure provides a scan driving circuit including a multi-stage shift register unit; and any one of the precharge circuits of any one of the above two stages of the shift register unit is provided .
  • the pre-charging circuit of the embodiment of the present disclosure can pre-charge the next-stage scan driving signal by using the one-stage scan driving signal, so that the output capability of the scan driving signal can be improved based on the principle of charge sharing.
  • the embodiment of the present disclosure can reduce the requirement of the maximum amplitude voltage of the scan driving signal, the output of the scan driving signal can be guaranteed.
  • the power consumption of the scan driving circuit is reduced, which is beneficial to the improvement of product performance.
  • the multi-stage shift register unit in which the input terminal and the output terminal are serially connected in series and each includes a reset terminal may be cascaded in the following manner: except for the first-stage shift register unit, any one-stage shift register The input terminals of the unit are connected to the output terminal of the shift register unit of the previous stage; except for the shift register unit of the first stage, the output of the shift register unit of any stage is reset with the shift register unit of the previous stage. Connected to the end.
  • FIG. 7 is a schematic structural diagram of a scan driving circuit in an embodiment of the present disclosure.
  • the scan driving circuit in this embodiment is a first shift register unit GOA of an odd-numbered order of, for example, 2n+1, 2n+3, 2n+5, 2n+7, and the number of stages is, for example, a second shift register unit GOA of even stages of 2(n+1), 2(n+2), 2(n+3), 2(n+4), where n is a non-negative integer, such as 0, 1 , 2...etc.
  • all odd-numbered first shift register units are sequentially cascaded in the manner described above, and are connected to and driven by the first clock signal CLKL and the third clock signal CLKLB; all even-numbered second shifts
  • the registering units are sequentially cascaded in the above manner, and both the second clock signal CLKR and the fourth clock signal CLKRB are connected and driven by the two clock signals.
  • the input terminal of the first shift register unit of the first odd-numbered stage is connected to the odd-numbered start signal STV-L
  • the input terminal of the second shift register unit of the first even-numbered stage is connected to the even-numbered start signal STV- R
  • all of the first shift register units and all of the second shift register units are connected to the same low-level bias voltage Vss.
  • the output of the first shift register unit of the i-th stage and the output of the second shift register unit of the i-th stage, and the output of the second shift register unit of the i-th stage A precharge unit PCU is provided between the terminal and the output terminal of the first shift register unit of the i+1th stage, and the precharge unit PCU may have the structure of any one of the precharge circuits described above.
  • the precharge unit PCU may have the structure of any one of the precharge circuits described above.
  • the first clock signal CLKL, the second clock signal CLKR, and the third clock are in a clock cycle starting from a time when the first clock signal CLKL is changed from an inactive level to an active level.
  • the period in which the signal CLKLB and the fourth clock signal CLKRB are at an active level is sequentially delayed by a predetermined time; the length of the predetermined time is less than one-half of a clock period. Based on this, the input end and the output end of any pre-charging unit PCU can satisfy the condition that the high-level maintenance time at least partially overlaps.
  • an embodiment of the present disclosure provides an array substrate including the scan driving circuit of any of the above, and thus has the advantages of any of the above-described scan driving circuits.
  • the display substrate may be provided on the array substrate, and the scan driving circuit is disposed on at least one side of the display area to form an array substrate under the GOA structure.
  • the pre-charging circuit may be disposed within the display area and formed by the same process as the transistors of the display area.
  • an embodiment of the present disclosure provides a display device including the array substrate of any of the above, and thus has the advantages of any of the above array substrates.
  • the display device in this embodiment may be any product or component having a display function, such as an electronic paper, a mobile phone, a tablet computer, a television, a notebook computer, a digital photo frame, a navigator, and the like.
  • the orientation or positional relationship of the terms “upper”, “lower” and the like is based on the orientation or positional relationship shown in the drawings, and is merely for convenience of description of the present disclosure and simplified description. It is not intended or implied that the device or the component of the invention may have a particular orientation, and is constructed and operated in a particular orientation, and thus is not to be construed as limiting the disclosure.
  • the terms “mounted,” “connected,” and “connected” are used in a broad sense, and may be, for example, a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection, It can also be an electrical connection; it can be directly connected, or it can be connected indirectly through an intermediate medium, which can be the internal connection of two components.
  • the specific meanings of the above terms in the present disclosure can be understood by those skilled in the art on a case-by-case basis.

Abstract

一种预充电电路（1）、扫描驱动电路、阵列基板和显示装置；该预充电电路（1）包括输入端（IN）和输出端（OUT），还包括开关单元（11）、第一上拉单元（12）和第二上拉单元（13），其中：所述开关单元（11）的第一端连接第一节点（P1），第二端连接所述输入端（IN），第三端连接第二节点（P2），用于在第一端处为高电平时导通第二端与第三端；所述第一上拉单元（12）的第一端连接所述输出端（OUT），第二端连接所述第一节点（P1），用于在第一端处为高电平时上拉第二端处的电位；所述第二上拉单元（13）的第一端连接所述第二节点（P2），第二端连接所述输出端（OUT），用于在第一端处为高电平时上拉第二端处的电位。该预充电电路（1）可以在保障扫描驱动信号的输出能力的同时降低扫描驱动电路的功耗，有利于产品性能的提升。

Description

预充电电路、扫描驱动电路、阵列基板和显示装置 技术领域
本公开涉及一种预充电电路、扫描驱动电路、阵列基板和显示装置。
背景技术
阵列基板行驱动(Gate driver On Array，GOA)技术作为一种新型显示技术，通过将扫描驱动电路集成在阵列基板上，可以去掉扫描驱动集成电路的部分，从而节省材料并减少工艺步骤，达到降低产品成本的目的。然而，目前的GOA产品大多应用于中小尺寸产品上，当产品尺寸较大时，会导致扫描驱动信号输出能力不足的问题。比如远端位置处由于电阻过大而使得扫描驱动信号的幅值过小，或者由于延迟过大而导致无法实现高频显示。为了改善该问题，现有技术通常会增大扫描驱动信号的最大幅值电压，从而整体上提高每一位置处扫描驱动信号的幅值。但是这种方式会增大扫描驱动电路的整体功耗，不利于产品性能的提升。
发明内容
在本公开的实施例中提供一种预充电电路、扫描驱动电路、阵列基板和显示装置。
按照本公开的第一方面，提供了一种预充电电路，包括输入端和输出端，还包括开关单元、第一上拉单元和第二上拉单元，其中：
所述开关单元的第一端连接第一节点，第二端连接所述输入端，第三端连接第二节点，用于在第一端处为高电平时导通第二端与第三端；
所述第一上拉单元的第一端连接所述输出端，第二端连接所述第一节点，用于在第一端处为高电平时上拉第二端处的电位；
所述第二上拉单元的第一端连接所述第二节点，第二端连接所述输出端，用于在第一端处为高电平时上拉第二端处的电位。
可选地，所述开关单元包括第一晶体管，所述第一晶体管的栅极连接所述第一节点，源极与漏极中的一个连接所述输入端，另一个连接所述第二节点。
可选地，所述第一上拉单元包括第二晶体管，所述第二晶体管的栅极连接所述输出端，源极与漏极中的一个连接所述输出端，另一个连接所述第一节点。
可选地，所述第二上拉单元包括第三晶体管，所述第三晶体管的栅极连接所述第二节点，源极与漏极中的一个连接所述第二节点，另一个连接所述输出端。
可选地，所述预充电电路还包括复位模块；所述复位模块连接所述第一节点，用于在所述输入端处由高电平转为低电平之后将所述第一节点处的电位置为低电平。
可选地，所述复位模块包括第四晶体管，所述第四晶体管的栅极连接所述第一节点，源极与漏极中的一个连接所述第一节点，另一个连接所述输入端。
可选地，所述复位模块包括第五晶体管，所述第五晶体管的栅极连接起始输入信号，源极与漏极中的一个连接所述第一节点，另一个连接低电平电压线。
可选地，所述复位模块还包括第六晶体管，所述第六晶体管的栅极连接所述起始输入信号，源极与漏极中的一个连接所述第二节点，另一个连接低电平电压线。
按照本公开的第二方面，还提供了一种上述任意一种预充电电路的驱动方法，包括：
在第一阶段内，将所述输入端处的电位向高电平上拉，保持所述输出端处的低电平；
在第二阶段内，保持所述输入端的高电位，并将所述输出端处的电位向高电平上拉，以使：所述第一上拉单元上拉所述第一节点处的电位，所述开关单元将所述输入端与所述第二节点导通，所述第二上拉单元上拉所述输出端处的电位；
在第三阶段内，将所述输入端处的电位置为低电平，并保持所述输出端的高电平，以使：所述第一上拉单元上拉所述第一节点处的电位，所述开关单元将所述输入端与所述第二节点导通；
在第四阶段内，保持所述输入端的低电平，并将所述输出端处的电位置为低电平。
按照本公开的第三方面，还提供了一种扫描驱动电路，包括多级移位寄存单元；相邻两级所述移位寄存单元的输出端之间设有上述任意一种的预充电电路。
可选地，所述扫描驱动电路具体包括：由第一时钟信号与第三时钟信号驱动的多级第一移位寄存单元，和，由第二时钟信号与第四时钟信号驱动的多级 第二移位寄存单元；所述多级第一移位寄存单元的输入端与输出端依次串接；所述多级第二移位寄存单元的输入端与输出端依次串接；第i级的第一移位寄存器单元的输出端与第i级的第二移位寄存器单元的输出端之间，以及第i级的第二移位寄存器单元的输出端与第i+1级的第一移位寄存器单元的输出端之间，均设有上述任意一种的预充电电路；所述i为正整数。
可选地，在以所述第一时钟信号转为有效电平为始的一个时钟周期内，所述第一时钟信号、所述第二时钟信号、所述第三时钟信号和所述第四时钟信号处于有效电平的时间段依次滞后预定时间；所述预定时间的长度小于二分之一的时钟周期。
按照本公开的第四方面，还提供了一种阵列基板，包括上述任意一种的扫描驱动电路。
可选地，所述阵列基板上设有显示区，所述扫描驱动电路设置在所述显示区之外的至少一侧，所述预充电电路设置在所述显示区之内。
按照本公开的第五方面，还提供了一种显示装置，包括上述任意一种的阵列基板。
由上述技术方案可知，本公开实施例的预充电电路可以利用一级扫描驱动信号来对下一级扫描驱动信号进行预充电，从而可以基于电荷分享的原理提升扫描驱动信号的输出能力。与现有技术相比，由于可以降低对扫描驱动信号的最大幅值电压的需求，因此可以在保障扫描驱动信号的输出能力的同时降低扫描驱动电路的功耗，有利于产品性能的提升，解决了大尺寸GOA产品中扫描驱动信号输出能力不足的问题。
附图说明
图1是本公开一个实施例中一种预充电电路的示意性结构框图；
图2是本公开一个实施例中一种预充电电路的电路结构示意图；
图3是本公开又一实施例中一种预充电电路的电路结构示意图；
图4是本公开另一实施例中一种预充电电路的电路结构示意图；
图5是本公开一个实施例中一种预充电电路的驱动方法的步骤流程示意图；
图6是本公开一个实施例中一种预充电电路的电路时序图；
图7是本公开一个实施例中一种扫描驱动电路的结构示意图。
具体实施方式
为使本公开实施例的原理、技术方案和优点更加清楚，下面将结合附图进行更清楚、更完整地描述。显然，所描述的实施例只是本发明的一部分实施例，而不是全部的实施例。
图1是本公开一个实施例中一种预充电电路的示意性结构框图。参见图1，该预充电电路1包括输入端IN和输出端OUT，还包括开关单元11、第一上拉单元12和第二上拉单元13。
在图1中，开关单元11的第一端连接第一节点P1，第二端连接输入端IN，第三端连接第二节点P2。该开关单元11用于在第一端处为高电平时导通第二端与第三端；
第一上拉单元12的第一端连接输出端OUT，第二端连接第一节点P1。该第一上拉单元12用于在第一端处为高电平时上拉第二端处的电位；
第二上拉单元13的第一端连接第二节点P2，第二端连接上述输出端OUT。该第二上拉单元13用于在第一端处为高电平时上拉第二端处的电位。
需要说明的是，本文中的“高电平”和“低电平”分别指的是某一电路节点位置处由电位高度范围代表的两种逻辑状态。举例来说，第一节点P1和第二节点P2处的高电平可以具体指代高于公共端电压的电位，第一节点P1和第二节点P2处的低电平可以具体指代低于公共端电压的电位。时输入端IN和输出端OUT处的高电平可以具体指代高于公共端电压6V以上的电位，输出端输入端IN和OUT处的低电平可以具体指代低于公共端电压6V以上的电位。可以理解的是，具体的电位高度范围可以在具体应用场景下根据需要进行设置，本公开对此不做限制。
与之对应的，本文中的“上拉”指的是使相应的电路节点处的电平上升至高电平，本文中的“下拉”指的是使相应的电路节点处的电平下降至低电平。可以理解的是，上述“上拉”与“下拉”均可以通过电荷的定向移动实现，因此可以具体藉由具有相应功能的电子元器件或其组合实现，本公开对此不做限制。
为了更清楚地说明上述各单元的结构与功能，下面对上述预充电电路1的工作原理进行简述。
参见图1，一般状态下，输入端IN与输出端OUT均连接低电平，预充电 电路1内部的第一节点P1和第二节点P2处均为低电平，从而上述开关单元11、第一上拉单元13、第二上拉单元13均不工作，各个节点处的电位保持不变。
此时，若输入端IN处的电位开始由低电平上升，那么在输入端IN处开始由低电平上升至高电平的过程中，由于上述开关单元11、第一上拉单元13、第二上拉单元13仍保持之前的工作状态，因此第一节点P1、第二节点P2以及输出端OUT处的电位仍保持不变。
而在输入端IN处的电位已上升到高电平并保持为高电平、输出端开始由低电平上升到高电平的过程中，第一上拉单元12可以在输出端OUT处的高电平作用下上拉第一节点P1处的电位，使得第一节点P1处的电位很快达到高电平(第一节点P1处的高电平低于输出端OUT处的高电平)。此时，开关单元11在第一节点P1的高电平作用下导通输入端IN与第二节点P2，使得输入端IN处的高电平对第二节点P2处的电位进行上拉。由此，在第二节点P2处的高电平作用下，第二上拉单元13可以反过来上拉输出端OUT处的电位，形成输出端OUT处电位上升的正反馈，加速输出端OUT处电位的上升。
此后，在输出端OUT处已上升并保持为高电平的期间内，第一节点P1会在第一上拉单元12的作用下保持为高电平，从而开关单元11保持输入端IN与第二节点P2之间的导通。此时若输入端IN处的电位由高电平转为低电平，那么第二节点P2处的电位会随着输入端IN处电位的下降而下降，最终降至低电平。此后，若输出端OUT处的电位也由高电平转为低电平，则在输入端IN处的电位再次上升并保持为高电平时可以重复上述加速输出端OUT处电位的上升的流程。
可以看出，在将预充电电路1的输入端IN与输出端OUT分别连接高电平阶段有交叉的两个扫描驱动信号时，就可以利用一个扫描驱动信号来对另一个扫描驱动信号进行预充电，从而可以基于电荷分享的原理提升扫描驱动信号的输出能力。与现有技术相比，本公开实施例由于可以降低对扫描驱动信号的最大幅值电压的需求，因此可以在保障扫描驱动信号的输出能力的同时降低扫描驱动电路的功耗，有利于产品性能的提升。
作为一种更具体的示例，图2是本公开一个实施例中一种预充电电路的电路结构示意图。
参见图2，本公开的一个实施例中，开关单元11可以包括第一晶体管T1。 第一晶体管T1的栅极连接第一节点P1，源极与漏极中的一个连接输入端IN，另一个连接第二节点P2。可替换地，图1中的第一晶体管T1为N型晶体管，因此与第二节点P2相连的一端为源极，与输入端IN相连的一端为漏极。可以看出，在第一节点P1处为高电平时，第一晶体管T1内部的源极与漏极之间可以导通电流，因此可以实现上述开关单元11的功能，并可以与现有的GOA工艺相集成从而减小制作成本。
在图2所示实施例中，第一上拉单元12包括第二晶体管T2。第二晶体管T2的栅极连接输出端OUT，源极与漏极中的一个连接输出端OUT，另一个连接第一节点P1。可替换地，图1中的第二晶体管T2为N型晶体管，因此与第一节点P1相连的一端为源极，与输出端OUT相连的一端为漏极。可以看出，在输出端OUT处为高电平时，第二晶体管T2内部的源极与漏极之间可以导通电流并实现第一节点P1处电位的上拉，因此可以实现上述第一上拉单元12的功能，并可以与现有的GOA工艺相集成从而减小制作成本。
在图2所示实施例中，第二上拉单元13包括第三晶体管T3。第三晶体管T3的栅极连接第二节点P2，源极与漏极中的一个连接第二节点P2，另一个连接输出端OUT。可替换地，图1中的第三晶体管T3为N型晶体管，因此与输出端OUT相连的一端为源极，与第二节点P2相连的一端为漏极。可以看出，在第二节点P2处为高电平时，第三晶体管T3内部的源极与漏极之间可以导通电流并实现输出端OUT处电位的上拉，因此可以实现上述第二上拉单元13的功能，并可以与现有的GOA工艺相集成从而减小制作成本。
然而在上述预充电电路中若第一节点处的耦合电容过大，那么在输出端处电位由低电平转为高电平，再由高电平转为低电平之后第一节点处的电位会在一段时间内被保持为高电平，使得预充电电路不能回复到一般状态，因而有可能会影响下一次(比如在一个显示帧之后的下一个显示帧内)的工作流程。
为解决这一问题，在上述任意一种预充电电路的基础上可以增设一与第一节点P1相连的复位模块，该复位模块用于在输入端OUT处由高电平转为低电平之后将第一节点P1处的电位置为低电平。
举例来说，图3是本公开又一实施例中一种预充电电路的电路结构示意图。可以看出，图3所示的预充电电路在图2所示的电路结构的基础上增加了包括一第四晶体管T4的复位模块14。该第四晶体管T4的栅极连接第一节点P1，源极与漏极中的一个也连接第一节点P1，另一个连接输入端IN。从而， 在第一节点P1处为高电平时，第四晶体管T4内部的源极与漏极之间可以导通电流，因而可以在输入端IN处为低电平时将第一节点P1处的电位置为低电平，因此可以实现上述复位单元14的功能，并可以与现有的GOA工艺相集成从而减小制作成本。
作为另一种示例，图4是本公开另一实施例中一种预充电电路的电路结构示意图。可以看出，图4所示的预充电电路在图2所示的电路结构的基础上增加了包括第五晶体管T5和第六晶体管T6的复位模块14(图示的复位模块14由14a与14b两部分组成)。图4中，第五晶体管T5的栅极连接起始输入信号STV(具体为在回到一般状态到输入端处电位开始上升之间的至少部分时间内为有效电平的控制信号，在应用至扫描驱动电路中时可以具体为第一级移位寄存器单元的输入信号)，源极与漏极中的一个连接所述第一节点P1，另一个连接低电平电压线Vss。从而，在起始输入信号STV为有效电平时，第五晶体管T5内部的源极与漏极之间可以导通电流，因而第一节点P1可以被低电平电压线Vss置为低电平，实现上述复位单元14的功能。
此外，第六晶体管T6的栅极连接上述起始输入信号STV，源极与漏极中的一个连接第二节点P2，另一个连接低电平电压线Vss。因而可以通过类似的过程将第二节点P2处的电位置为低电平，实现第二节点P2处电位的复位，提高预充电电路工作的稳定性。可以理解的是，本公开实施例中的任意一个晶体管在具有源极与漏极对称的结构时，其源极与漏极可以视为不作特别区分的两个电极。在具体实施时，晶体管的类型可以根据应用需求选取。
基于同样的发明构思，图5是本公开一个实施例中一种预充电电路的驱动方法的步骤流程示意图。参见图5，该方法包括下列步骤：
步骤301：在第一阶段内，将输入端处的电位向高电平上拉，保持输出端处的低电平；
步骤302：在第二阶段内，保持输入端的高电位，并将输出端处的电位向高电平上拉，以使：第一上拉单元上拉第一节点处的电位，开关单元将输入端与第二节点导通，第二上拉单元上拉输出端处的电位；
步骤303：在第三阶段内，将输入端处的电位置为低电平，并保持输出端的高电平，以使：第一上拉单元上拉第一节点处的电位，开关单元将输入端与第二节点导通；
步骤304：在第四阶段内，保持输入端的低电平，并将输出端处的电位置 为低电平。
与图5所示的步骤流程以及上文所述的预充电电路1的工作原理一致，图6是本公开一个实施例中一种预充电电路的电路时序图。以图2所示的预充电电路为例，下面对图5所示的步骤流程和图6所示的电路时序进行详细说明：
在第一阶段I内，在步骤301中将输入端IN处的电位向高电平上拉，同时保持输出端OUT处的低电平，从而第一晶体管T1、第二晶体管T2、第三晶体管T3均处于关闭状态，第一节点P1与第二节点P2处的电位均保持为低电平。
在第二阶段II内，在步骤302中保持输入端IN的高电位，并将输出端OUT处的电位向高电平上拉，从而第二晶体管T2在输出端OUT处的电位开始上升后打开，上拉第一节点P1处的电位；第一节点P1处的电位上升后，第一晶体管T1打开而输入端IN上拉第二节点P2处的电位；第二节点P2处的电位上升后，第三晶体管T3打开并上拉输出端OUT处的电位，形成正反馈并加速输出端OUT处的电位的上升。
在第三阶段III内，在步骤303中将输入端IN处的电位置为低电平，并保持输出端OUT的高电平，从而输出端OUT处的高电位作用下第二晶体管T2保持开启，第一节点P1处的电位保持为高电平；第二节点P2处的电位被开启的第一晶体管T1下拉，使得第三晶体管T3关闭。
在第四阶段IV内，在步骤304中保持输入端IN的低电平并将输出端OUT处的电位置为低电平。在包括第四阶段IV在内的之后的时间内，第二晶体管T2与第三晶体管T3保持关闭，而第一节点P1处的高电平会在耦合电容的作用下逐渐降为低电平，使得第一晶体管T1由开启转变为关闭(或者处于浮接状态)。然而在预充电电路包括上述任意一种的复位模块14时，第一节点P1处的电位可以回到一般状态下的低电平，从而在此后继续执行上述步骤301至步骤304时，该预充电电路又可以重复上述第一至第四阶段的工作流程。
基于同样的发明构思，本公开实施例提供一种扫描驱动电路，包括多级移位寄存单元；相邻两级所述移位寄存单元的输出端之间设有上述任意一种的预充电电路。可以看出，本公开实施例的预充电电路可以利用一级扫描驱动信号来对下一级扫描驱动信号进行预充电，从而可以基于电荷分享的原理提升扫描驱动信号的输出能力。与现有技术相比，由于本公开实施例可以降低对扫描驱动信号的最大幅值电压的需求，因此可以在保障扫描驱动信号的输出能 力的同时降低扫描驱动电路的功耗，有利于产品性能的提升。
举例来说，上述输入端与输出端依次串接、并均包括复位端的多级移位寄存单元可以按照下述方式级联：除第一级移位寄存器单元之外，任一级移位寄存器单元的输入端均与上一级移位寄存器单元的输出端相连；除第一级移位寄存器单元之外，任一级移位寄存器单元的输出端均与上一级移位寄存器单元的复位端相连。
作为另一种示例，图7是本公开一个实施例中一种扫描驱动电路的结构示意图。参见图7，本实施例中的扫描驱动电路分别为级数例如是2n+1、2n+3、2n+5、2n+7的奇数级的第一移位寄存单元GOA，以及级数例如是2(n+1)、2(n+2)、2(n+3)、2(n+4)的偶数级的第二移位寄存单元GOA，其中n为非负整数，例如0、1、2……等。从而，所有奇数级的第一移位寄存单元按照上述方式依次级联，都连接第一时钟信号CLKL与第三时钟信号CLKLB，并由这两个时钟信号驱动；所有偶数级的第二移位寄存单元按照上述方式依次级联，都连接第二时钟信号CLKR与第四时钟信号CLKRB，并由这两个时钟信号驱动。此外，第一个奇数级的第一移位寄存单元的输入端连接奇数级起始信号STV-L，第一个偶数级的第二移位寄存单元的输入端连接偶数级起始信号STV-R，而且所有的第一移位寄存单元与所有的第二移位寄存单元均连接相同的低电平偏置电压Vss。
对于任意的正整数i，第i级的第一移位寄存器单元的输出端与第i级的第二移位寄存器单元的输出端之间，以及第i级的第二移位寄存器单元的输出端与第i+1级的第一移位寄存器单元的输出端之间，均设有一个预充电单元PCU，而预充电单元PCU可以具有上述任意一种的预充电电路的结构。由此，在预充电单元PCU的作用下，除第一级之外的任一级移位寄存器单元的输出端都可以在电位逐渐上升的阶段内被上一级移位寄存器单元的输出端的高电平进行预充电，从而基于电荷分享的原理提升扫描驱动信号的输出能力。
可选地，在以所述第一时钟信号CLKL由无效电平转为有效电平的时刻为开始的一个时钟周期内，上述第一时钟信号CLKL、上述第二时钟信号CLKR、上述第三时钟信号CLKLB和上述第四时钟信号CLKRB处于有效电平的时间段依次滞后预定时间；所述预定时间的长度小于二分之一的时钟周期。基于此，任一预充电单元PCU的输入端与输出端均可以满足高电平的维持时间有至少部分重合的条件。
基于同样的发明构思，本公开实施例提供一种阵列基板，该阵列基板包括上述任意一种的扫描驱动电路，因而具有上述任意一种扫描驱动电路所具有的优点。其中，阵列基板上可以设有显示区，而且所述扫描驱动电路设置在所述显示区之外的至少一侧，以形成GOA结构下的阵列基板。进一步地，所述预充电电路可以设置在所述显示区之内，并与显示区的晶体管采用相同工艺制作形成。
基于同样的发明构思，本公开实施例提供了一种显示装置，该显示装置包括上述任意一种的阵列基板，因而具有上述任意一种阵列基板所具有的优点。需要说明的是，本实施例中的显示装置可以为：电子纸、手机、平板电脑、电视机、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
在本公开的描述中需要说明的是，术语“上”、“下”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本公开中的具体含义。
本公开的说明书中，说明了大量具体细节。然而，能够理解，本公开的实施例可以在没有这些具体细节的情况下实践。在一些实例中，并未详细示出公知的方法、结构和技术，以便不模糊对本说明书的理解。
类似地，应当理解，为了精简本公开并帮助理解各个发明方面中的一个或多个，在上面对本公开的示例性实施例的描述中，本公开的各个特征有时被一起分组到单个实施例、图、或者对其的描述中。然而，并不应将该公开的方法解释成反映如下意图：即所要求保护的本公开技术方案要求比在每个权利要求中所明确记载的特征更多的特征。更确切地说，如权利要求书所反映的那样，发明方面在于少于前面公开的单个实施例的所有特征。因此，遵循具体实施方式的权利要求书由此明确地并入该具体实施方式，其中每个权利要求本身都作为本公开的单独实施例。
应该注意的是上述实施例对本公开进行说明而不是对本公开进行限制，并 且本领域技术人员在不脱离所附权利要求的范围的情况下可设计出替换实施例。单词“包含”不排除存在未列在权利要求中的元件或步骤。位于元件之前的单词“一”或“一个”不排除存在多个这样的元件。本公开可以借助于包括有若干不同元件的硬件以及借助于适当编程的计算机来实现。在列举了若干装置的单元权利要求中，这些装置中的若干个可以是通过同一个硬件项来具体体现。单词第一、第二、以及第三等的使用不表示任何顺序。可将这些单词解释为名称。
最后应当说明的是：以上各实施例仅用以说明本公开的技术方案，而非对其进行限制。尽管参照前述各实施例对本公开的实施例进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本公开各实施例技术方案的范围，其均应涵盖在本公开的说明书和所附权利要求书的范围当中。
本申请要求于2015年9月24日递交的中国专利申请第201510616050.7号的优先权，在此全文引用该中国专利申请公开的内容作为本申请的一部分。

Claims (15)

  1. 一种预充电电路，包括输入端和输出端，还包括开关单元、第一上拉单元和第二上拉单元，其中：
    所述开关单元的第一端连接第一节点，第二端连接所述输入端，第三端连接第二节点，用于在第一端处为高电平时导通第二端与第三端；
    所述第一上拉单元的第一端连接所述输出端，第二端连接所述第一节点，用于在第一端处为高电平时上拉第二端处的电位；
    所述第二上拉单元的第一端连接所述第二节点，第二端连接所述输出端，用于在第一端处为高电平时上拉第二端处的电位。
  2. 根据权利要求1所述的预充电电路，其中，所述开关单元包括第一晶体管，所述第一晶体管的栅极连接所述第一节点，源极与漏极中的一个连接所述输入端，另一个连接所述第二节点。
  3. 根据权利要求1所述的预充电电路，其中，所述第一上拉单元包括第二晶体管，所述第二晶体管的栅极连接所述输出端，源极与漏极中的一个连接所述输出端，另一个连接所述第一节点。
  4. 根据权利要求1所述的预充电电路，其中，所述第二上拉单元包括第三晶体管，所述第三晶体管的栅极连接所述第二节点，源极与漏极中的一个连接所述第二节点，另一个连接所述输出端。
  5. 根据权利要求1至4中任意一项所述的预充电电路，其中，还包括复位模块；所述复位模块连接所述第一节点，用于在所述输入端处由高电平转为低电平之后将所述第一节点处的电位置为低电平。
  6. 根据权利要求5所述的预充电电路，其中，所述复位模块包括第四晶体管，所述第四晶体管的栅极连接所述第一节点，源极与漏极中的一个连接所述第一节点，另一个连接所述输入端。
  7. 根据权利要求5所述的预充电电路，其中，所述复位模块包括第五晶体管，所述第五晶体管的栅极连接起始输入信号，源极与漏极中的一个连接所述第一节点，另一个连接低电平电压线。
  8. 根据权利要求7所述的预充电电路，其中，所述复位模块还包括第六晶体管，所述第六晶体管的栅极连接所述起始输入信号，源极与漏极中的一个连接所述第二节点，另一个连接低电平电压线。
  9. 一种如权利要求1至8中任意一项中所述的预充电电路的驱动方法，包括：
    在第一阶段内，将所述输入端处的电位向高电平上拉，保持所述输出端处的低电平；
    在第二阶段内，保持所述输入端的高电位，并将所述输出端处的电位向高电平上拉，以使所述第一上拉单元上拉所述第一节点处的电位，所述开关单元将所述输入端与所述第二节点导通，所述第二上拉单元上拉所述输出端处的电位；
    在第三阶段内，将所述输入端处的电位置为低电平，并保持所述输出端的高电平，以使所述第一上拉单元上拉所述第一节点处的电位，所述开关单元将所述输入端与所述第二节点导通；
    在第四阶段内，保持所述输入端的低电平，并将所述输出端处的电位置为低电平。
  10. 一种扫描驱动电路，包括多级移位寄存单元；相邻两级所述移位寄存单元的输出端之间设有如权利要求1至8中任一项所述的预充电电路。
  11. 根据权利要求10所述的扫描驱动电路，其中，所述扫描驱动电路包括：由第一时钟信号与第三时钟信号驱动的多级第一移位寄存单元，和，由第二时钟信号与第四时钟信号驱动的多级第二移位寄存单元；所述多级第一移位寄存单元的输入端与输出端依次串接；所述多级第二移位寄存单元的输入端与输出端依次串接；第i级的第一移位寄存器单元的输出端与第i级的第二移位寄存器单元的输出端之间，以及第i级的第二移位寄存器单元的输出端与第i+1级的第一移位寄存器单元的输出端之间，均设有如权利要求1至8中任一项所述的预充电电路；所述i为正整数。
  12. 根据权利要求11所述的扫描驱动电路，其中，在以所述第一时钟信号转为有效电平为始的一个时钟周期内，所述第一时钟信号、所述第二时钟信号、所述第三时钟信号和所述第四时钟信号处于有效电平的时间段依次滞后预定时间；所述预定时间的长度小于二分之一的时钟周期。
  13. 一种阵列基板，包括如权利要求10至12中任一项所述的扫描驱动电路。
  14. 根据权利要求13所述的阵列基板，其中，所述阵列基板上设有显示区，所述扫描驱动电路设置在所述显示区之外的至少一侧，所述预充电电路设 置在所述显示区之内。
  15. 一种显示装置，包括如权利要求13或14所述的阵列基板。
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