WO2017045215A1 - 一种液晶显示装置及其栅极驱动电路 - Google Patents

一种液晶显示装置及其栅极驱动电路 Download PDF

Info

Publication number
WO2017045215A1
WO2017045215A1 PCT/CN2015/090140 CN2015090140W WO2017045215A1 WO 2017045215 A1 WO2017045215 A1 WO 2017045215A1 CN 2015090140 W CN2015090140 W CN 2015090140W WO 2017045215 A1 WO2017045215 A1 WO 2017045215A1
Authority
WO
WIPO (PCT)
Prior art keywords
thin film
film transistor
signal
level
node
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2015/090140
Other languages
English (en)
French (fr)
Inventor
肖军城
曹尚操
颜尧
戴荣磊
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wuhan China Star Optoelectronics Technology Co Ltd
TCL China Star Optoelectronics Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Technology Co Ltd
Wuhan China Star Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen China Star Optoelectronics Technology Co Ltd, Wuhan China Star Optoelectronics Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Technology Co Ltd
Priority to US14/786,071 priority Critical patent/US9799293B2/en
Publication of WO2017045215A1 publication Critical patent/WO2017045215A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0871—Several active elements per pixel in active matrix panels with level shifting
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0245—Clearing or presetting the whole screen independently of waveforms, e.g. on power-on
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present invention relates to the field of liquid crystal display technology, and in particular, to a liquid crystal display device and a gate driving circuit thereof.
  • Array substrate row driver (GOA, Gate Driver On Array or Gate On The Array) circuit is formed by using a conventional thin film transistor display device (TFT-LCD) array (Array) process to form a gate line scan driving signal circuit on the array substrate to realize a progressive scanning operation on the gate line.
  • TFT-LCD thin film transistor display device
  • Array gate line scan driving signal circuit on the array substrate to realize a progressive scanning operation on the gate line.
  • COF flexible circuit board
  • COG glass circuit board
  • the GOA circuit needs to implement the function of stopping the signal to match the touch screen, such as scanning with the touch screen.
  • the display device Normally, after the GOA circuit stops in the implementation signal, the display device needs to be black-awakeed.
  • the GOA circuit needs to set all the gate lines to be charged or turned on for a period of time, by applying black to the data lines. The voltage is used to clear the level remaining in the pixel capacitance, so that the display device has a good display effect. This period of time is called full gate line opening (All Gate On) stage.
  • the GOA circuit may have a functional failure risk when implementing All Gate On, and thus the All Gate On function cannot be stably implemented.
  • the technical problem to be solved by the present invention is to provide a liquid crystal display device and a gate driving circuit thereof, which can stably implement All Gate On function.
  • the present invention provides a gate driving circuit of a liquid crystal display device, which includes a multi-level gate driving unit and a control chip, and each stage of the gate driving unit includes:
  • a first pull control unit configured to output a first pull control signal at the first node
  • the first pull unit is coupled to the first node, receives the first clock signal, and pulls the level of the output of the gate drive signal to the first level according to the first pull control signal and the first clock signal to output the gate drive signal ;
  • a second pull control unit configured to output a second pull control signal at the second node
  • a second pull unit coupled to the first node and the second node, receiving the first voltage reference signal, and pulling the level of the first node to a second level of the first voltage reference signal according to the second pull control signal;
  • a first control unit coupled to the first node, receiving the first control signal and the first voltage reference signal, and pulling the level of the first node to the second level according to the first control signal;
  • a second control unit coupled to the second node, receiving the first control signal and the second voltage reference signal, pulling the level of the second node to a third level of the second voltage reference signal according to the first control signal, and second Pulling the unit to pull the level of the gate drive signal to a second level;
  • a third control unit coupled to the gate driving signal output end, receiving the first control signal and the second control signal, and pulling the level of the gate driving signal according to the first control signal and the second control signal;
  • the control chip is configured to pull the first clock signal, the first voltage reference signal, the first control signal, and the second control signal to a first level, so that the scan lines driven by the gate driving circuit are all turned on.
  • the first pull control unit includes a first thin film transistor and a second thin film transistor
  • the first end of the first thin film transistor receives the first signal
  • the second end of the first thin film transistor receives the gate driving signal of the previous stage
  • the third end of the first thin film transistor is connected to the first node
  • the first end of the second thin film transistor receives the second signal
  • the second end of the second thin film transistor receives the gate driving signal of the subsequent stage
  • the third end of the second thin film transistor is connected to the first node.
  • the first pull unit includes a third thin film transistor and a first capacitor, the first end of the third thin film transistor receives the first clock signal, the second end of the third thin film transistor is connected to the first node, and the third thin film transistor is The three terminals are gate drive signal output ends, and the first capacitor is connected between the second end and the third end of the third thin film transistor.
  • the first control unit includes a fourth thin film transistor, the first end of the fourth thin film transistor is connected to the first node, the second end of the fourth thin film transistor receives the first control signal, and the third end of the fourth thin film transistor receives the first A reference voltage signal.
  • the second control unit includes a fifth thin film transistor, the first end of the fifth thin film transistor receives the second reference voltage signal, the second end of the fifth thin film transistor receives the first control signal, and the third end of the fifth thin film transistor The second node is connected.
  • the second pull control unit includes a sixth thin film transistor and a seventh thin film transistor.
  • the first end of the sixth thin film transistor receives the second clock signal, and the second end of the sixth thin film transistor is connected to the first end of the fourth thin film transistor.
  • the third end of the sixth thin film transistor and the third end of the seventh thin film transistor are connected to the second node, the first end of the seventh thin film transistor receives the second voltage reference signal, and the second end of the seventh thin film transistor receives the second end Clock signal
  • the second pulling unit includes an eighth thin film transistor, a ninth thin film transistor, a tenth thin film transistor, and a second capacitor, wherein the first end of the eighth thin film transistor is connected to the second end of the third thin film transistor, and the second end of the eighth thin film transistor
  • the terminal receives the first clock signal, the third end of the eighth thin film transistor is connected to the first end of the ninth thin film transistor, the second end of the ninth thin film transistor is connected to the third end of the seventh thin film transistor, and the ninth thin film transistor is connected
  • the third end receives the first reference voltage signal, the first end of the tenth thin film transistor is connected to the third end of the third thin film transistor, and the second end of the tenth thin film transistor is connected to the second end of the ninth thin film transistor, tenth
  • the third end of the thin film transistor receives the first reference voltage signal, and the second capacitor is connected between the second end and the third end of the tenth thin film transistor.
  • the third control unit includes an eleventh thin film transistor, the first end of the eleventh thin film transistor is connected to the third end of the third thin film transistor, and the second end of the eleventh thin film transistor receives the first control signal, the tenth A third terminal of a thin film transistor receives a second control signal.
  • the gate driving unit further includes a twelfth thin film transistor, the first end of the twelfth thin film transistor is connected to the first node, and the second end of the twelfth thin film transistor receives the second reference voltage signal, the twelfth thin film transistor The third end is connected to the third end of the second thin film transistor, the third end of the first thin film transistor, and the first end of the fourth thin film transistor.
  • the transistor, the eleventh thin film transistor, and the twelfth thin film transistor are all P-type thin film transistors;
  • the fourth thin film transistor When the first control signal and the second control signal are at a low level, the fourth thin film transistor is turned on, the level of the second end of the third thin film transistor is pulled to the second level, and the third thin film transistor is turned off; the fifth thin film transistor is turned on The third terminal of the tenth thin film transistor is pulled to a third level, the tenth thin film transistor is turned on, and the eleventh thin film transistor is turned on to pull the level of the gate driving signal to a second level.
  • the transistor, the eleventh thin film transistor, and the twelfth thin film transistor are all N-type thin film transistors.
  • the present invention provides a liquid crystal display device including a gate driving circuit including a multi-level gate driving unit and a control chip, and each stage of the gate driving unit includes:
  • a first pull control unit configured to output a first pull control signal at the first node
  • the first pull unit is coupled to the first node, receives the first clock signal, and pulls the level of the output of the gate drive signal to the first level according to the first pull control signal and the first clock signal to output the gate drive signal ;
  • a second pull control unit configured to output a second pull control signal at the second node
  • a second pull unit coupled to the first node and the second node, receiving the first voltage reference signal, and pulling the level of the first node to a second level of the first voltage reference signal according to the second pull control signal;
  • a first control unit coupled to the first node, receiving the first control signal and the first voltage reference signal, and pulling the level of the first node to the second level according to the first control signal;
  • a second control unit coupled to the second node, receiving the first control signal and the second voltage reference signal, pulling the level of the second node to a third level of the second voltage reference signal according to the first control signal, and second Pulling the unit to pull the level of the gate drive signal to a second level;
  • a third control unit coupled to the gate driving signal output end, receiving the first control signal and the second control signal, and pulling the level of the gate driving signal according to the first control signal and the second control signal;
  • the control chip is configured to pull the first clock signal, the first voltage reference signal, the first control signal, and the second control signal to a first level, so that the scan lines driven by the gate driving circuit are all turned on.
  • the first pull control unit includes a first thin film transistor and a second thin film transistor
  • the first end of the first thin film transistor receives the first signal
  • the second end of the first thin film transistor receives the gate driving signal of the previous stage
  • the third end of the first thin film transistor is connected to the first node
  • the first end of the second thin film transistor receives the second signal
  • the second end of the second thin film transistor receives the gate driving signal of the subsequent stage
  • the third end of the second thin film transistor is connected to the first node.
  • the first pull unit includes a third thin film transistor and a first capacitor, the first end of the third thin film transistor receives the first clock signal, the second end of the third thin film transistor is connected to the first node, and the third thin film transistor is The three terminals are gate drive signal output ends, and the first capacitor is connected between the second end and the third end of the third thin film transistor.
  • the first control unit includes a fourth thin film transistor, the first end of the fourth thin film transistor is connected to the first node, the second end of the fourth thin film transistor receives the first control signal, and the third end of the fourth thin film transistor receives the first A reference voltage signal.
  • the second control unit includes a fifth thin film transistor, the first end of the fifth thin film transistor receives the second reference voltage signal, the second end of the fifth thin film transistor receives the first control signal, and the third end of the fifth thin film transistor The second node is connected.
  • the second pull control unit includes a sixth thin film transistor and a seventh thin film transistor.
  • the first end of the sixth thin film transistor receives the second clock signal, and the second end of the sixth thin film transistor is connected to the first end of the fourth thin film transistor.
  • the third end of the sixth thin film transistor and the third end of the seventh thin film transistor are connected to the second node, the first end of the seventh thin film transistor receives the second voltage reference signal, and the second end of the seventh thin film transistor receives the second end Clock signal
  • the second pulling unit includes an eighth thin film transistor, a ninth thin film transistor, a tenth thin film transistor, and a second capacitor, wherein the first end of the eighth thin film transistor is connected to the second end of the third thin film transistor, and the second end of the eighth thin film transistor
  • the terminal receives the first clock signal, the third end of the eighth thin film transistor is connected to the first end of the ninth thin film transistor, the second end of the ninth thin film transistor is connected to the third end of the seventh thin film transistor, and the ninth thin film transistor is connected
  • the third end receives the first reference voltage signal, the first end of the tenth thin film transistor is connected to the third end of the third thin film transistor, and the second end of the tenth thin film transistor is connected to the second end of the ninth thin film transistor, tenth
  • the third end of the thin film transistor receives the first reference voltage signal, and the second capacitor is connected between the second end and the third end of the tenth thin film transistor.
  • the third control unit includes an eleventh thin film transistor, the first end of the eleventh thin film transistor is connected to the third end of the third thin film transistor, and the second end of the eleventh thin film transistor receives the first control signal, the tenth A third terminal of a thin film transistor receives a second control signal.
  • the gate driving unit further includes a twelfth thin film transistor, the first end of the twelfth thin film transistor is connected to the first node, and the second end of the twelfth thin film transistor receives the second reference voltage signal, the twelfth thin film transistor The third end is connected to the third end of the second thin film transistor, the third end of the first thin film transistor, and the first end of the fourth thin film transistor.
  • the transistor, the eleventh thin film transistor, and the twelfth thin film transistor are all P-type thin film transistors;
  • the fourth thin film transistor When the first control signal and the second control signal are at a low level, the fourth thin film transistor is turned on, the level of the second end of the third thin film transistor is pulled to the second level, and the third thin film transistor is turned off; the fifth thin film transistor is turned on The third terminal of the tenth thin film transistor is pulled to a third level, the tenth thin film transistor is turned on, and the eleventh thin film transistor is turned on to pull the level of the gate driving signal to a second level.
  • the transistor, the eleventh thin film transistor, and the twelfth thin film transistor are all N-type thin film transistors.
  • the gate driving circuit of the present invention comprises a multi-level gate driving unit and a control chip, and each stage of the gate driving unit comprises a first pulling control unit, a first pulling unit, and a second pulling a control unit, a second pull unit, a first control unit, a second control unit, and a third control unit, wherein the control chip is configured to pull the first clock signal, the first voltage reference signal, the first control signal, and the second control signal to One level, so that the scan lines driven by the gate drive circuit are all turned on, stably achieving All Gate On function.
  • FIG. 1 is a schematic structural view of a gate driving circuit according to a first embodiment of the present invention
  • FIG. 2 is a schematic structural view of the gate driving unit of FIG. 1;
  • FIG. 3 is a circuit diagram of a gate driving unit of a second embodiment of the present invention.
  • FIG. 4 is a timing diagram of the first clock signal, the second clock signal, the first control signal, the second control signal, and the gate driving signal of FIG. 3;
  • Figure 5 is a circuit diagram of a gate driving unit of a third embodiment of the present invention.
  • Fig. 6 is a view showing the configuration of a liquid crystal display device of a first embodiment of the present invention.
  • FIG. 1 is a schematic structural diagram of a gate driving circuit according to a first embodiment of the present invention.
  • the gate driving circuit disclosed in this embodiment is applied to a liquid crystal display device for driving a plurality of scanning lines of a liquid crystal display device to open a plurality of scanning lines.
  • the gate driving circuit 10 is connected to a plurality of scanning lines 20 for driving a plurality of scanning lines 20, and the gate driving circuit 10 includes a multi-stage gate driving unit 11 and a control chip 12, and a gate.
  • the driving unit 11 corresponds to one scanning line 20, and the output end of the gate driving unit 11 is connected to the scanning line 20.
  • n is an integer greater than or equal to 1.
  • the nth stage gate driving unit 11 includes a first pulling control unit 111, a first pulling unit 112, a second pulling control unit 113, a second pulling unit 114, a first control unit 115, and a second control.
  • Unit 116 and third control unit 117 are shown in FIG. 2, the nth stage gate driving unit 11.
  • the first pull control unit 111 is configured to output the first pull control signal CL1 at the first node Qn.
  • the first pull unit 112 is coupled to the first node Qn, and the first pull unit 112 receives the first clock signal CK1, and pulls the level of the gate drive signal output end to the first according to the first pull control signal CL1 and the first clock signal CK1.
  • the output gate drive signal Gn is at the first level, and the gate drive signal Gn is used to drive the scan line 20.
  • the first pull control signal CL1 is at a first level.
  • the second pull control unit 113 is for outputting the second pull control signal CL2 at the second node Pn.
  • the second pull unit 114 is coupled to the first node Qn and the second node Pn, and the second pull unit 114 receives the first voltage reference signal V1 and pulls the level of the first node Qn to the first voltage according to the second pull control signal CL2.
  • the first control unit 115 is coupled to the first node Qn, and the first control unit 115 receives the first control signal GAS1 and the first voltage reference signal V1, and pulls the level of the first node Qn to the second level according to the control signal GAS1. At this time, the first pull control signal CL1 is at the second level.
  • the second control unit 116 is coupled to the second node Pn, and the second control unit 116 receives the control signal GAS1 and the second voltage reference signal V2, and pulls the level of the second node Pn to the second voltage reference signal V2 according to the control signal GAS1.
  • the second pulling unit 114 is further coupled to the gate driving signal output end, and the second pulling unit 114 pulls the level of the gate driving signal Gn to the second level.
  • the first level is the same as the third level.
  • the third control unit 117 is coupled to the gate driving signal output end, and the third control unit 117 receives the first control signal GAS1 and the second control signal GAS2, and pulls the gate driving signal according to the first control signal GAS1 and the second control signal GAS2.
  • the level for example, the third control unit 117 pulls the level of the gate drive signal Gn to the second level according to the first control signal GAS1 and the second control signal GAS2.
  • the scan line 20 When the level of the gate drive signal Gn is at the first level, the scan line 20 is turned on; when the level of the gate drive signal Gn is at the second level, the scan line 20 is turned off, and the control chip 12 is used to pull the first clock signal. CK1, the first voltage reference signal V1, the first control signal GAS1, and the second control signal GAS2 reach a first level, and at this time, the level of the gate driving signal Gn is at a first level, and the gate driving signal Gn is driven.
  • the scan line 20 is turned on to turn on the scan line 20 driven by the gate drive circuit 10, and stably implements All. Gate On function.
  • the first control unit 115 pulls the level of the first node Qn to the second level according to the first control signal GAS1, the first pulling unit 112 is turned off; the second control unit 116 pulls according to the first control signal GAS1.
  • Level of the second node Pn to a third level of the second voltage reference signal V2, so that the second pull unit 114 pulls the level of the gate drive signal Gn to a second level; the third control unit 117 is according to the first The control signal GAS1 and the second control signal GAS2 pull the level of the gate drive signal Gn to a second level; at this time, the scan line 20 is turned off, thereby achieving All scan lines 20 return to the off level after the Gate On function ends.
  • the present invention also provides a gate driving unit of the second embodiment, which is described on the basis of the gate driving unit 11 disclosed in the first embodiment.
  • the first pull control unit 111 includes a first thin film transistor T1 and a second thin film transistor T2.
  • the first end of the first thin film transistor T1 receives the first signal U2D, and the second end of the first thin film transistor T1 receives The gate driving signal Gn-1 of the previous stage, the third end of the first thin film transistor T1 is connected to the first node Qn; the first end of the second thin film transistor T2 receives the second signal D2U, and the second thin film transistor T2
  • the second terminal receives the gate drive signal Gn+1 of the subsequent stage, and the third end of the second thin film transistor T2 is connected to the first node Qn.
  • the first pull control unit 111 is configured to control the forward and reverse scan signals of the gate drive unit, and select the input first according to the gate drive signal Gn-1 of the previous stage or the gate drive signal Gn+1 of the subsequent stage.
  • the third end of the first thin film transistor T1 and the third end of the second thin film transistor T2 output a first pull control signal CL1.
  • the first pull unit 112 includes a third thin film transistor T3 and a first capacitor C1.
  • the first end of the third thin film transistor T3 receives the first clock signal CK1, and the second end of the third thin film transistor T3 is connected to the first node Qn.
  • the third end of the three thin film transistor T3 is a gate driving signal output end, and the first capacitor C1 is connected between the second end and the third end of the third thin film transistor T3.
  • the first control unit 115 includes a fourth thin film transistor T4, the first end of the fourth thin film transistor T4 is connected to the first node Qn, and the second end of the fourth thin film transistor T4 receives the first control signal GAS1, and the fourth thin film transistor T4 The third terminal receives the first reference voltage signal V1.
  • the second control unit 116 includes a fifth thin film transistor T5.
  • the first end of the fifth thin film transistor T5 receives the second reference voltage signal V2, and the second end of the fifth thin film transistor T5 receives the first control signal GAS1, and the fifth thin film transistor T5.
  • the third end is connected to the second node Pn.
  • the second pull control unit 113 includes a sixth thin film transistor T6 and a seventh thin film transistor T7.
  • the first end of the sixth thin film transistor T6 receives the second clock signal CK2, and the second end of the sixth thin film transistor T6 and the fourth thin film transistor T4.
  • the first end is connected, the third end of the sixth thin film transistor T6 and the third end of the seventh thin film transistor T7 are connected to the second node Pn, and the first end of the seventh thin film transistor T7 receives the second voltage reference signal V2,
  • the second terminal of the seven thin film transistor T7 receives the second clock signal CK2.
  • the third end of the sixth thin film transistor T6 and the third end of the seventh thin film transistor T7 output a second pull control signal CL2.
  • the second pull unit 114 includes an eighth thin film transistor T8, a ninth thin film transistor T9, a tenth thin film transistor T10, and a second capacitor C2.
  • the first end of the eighth thin film transistor T8 is connected to the second end of the third thin film transistor T3.
  • the second end of the eighth thin film transistor T8 receives the first clock signal CK1, the third end of the eighth thin film transistor T8 is connected to the first end of the ninth thin film transistor T9, and the second end and the seventh thin film of the ninth thin film transistor T9
  • the third end of the transistor T7 is connected, the third end of the ninth thin film transistor T9 receives the first reference voltage signal V1, the first end of the tenth thin film transistor T10 is connected to the third end of the third thin film transistor T3, and the tenth thin film transistor
  • the second end of the T10 is connected to the second end of the ninth thin film transistor T10, the third end of the tenth thin film transistor T10 receives the first reference voltage signal V1, and the second capacitor C2 is connected to the second end of the tenth thin film transistor T10. Between the third ends.
  • the third control unit 117 includes an eleventh thin film transistor T11.
  • the first end of the eleventh thin film transistor T11 is connected to the third end of the third thin film transistor T3, and the second end of the eleventh thin film transistor T11 receives the first control signal.
  • GAS1 the third end of the eleventh thin film transistor T11 receives the second control signal GAS2.
  • the ninth thin film transistor T9, the tenth thin film transistor T10, and the eleventh thin film transistor T11 are all P-type thin film transistors, and the P-type thin film transistor is turned on when the gate is at a low level.
  • the first level and the third level are low level
  • the second level is high level, that is, the first reference voltage signal V1 is VGH (high level)
  • the second reference voltage signal V2 is VGL (low) Level).
  • the first clock signal CK1 is at a low level
  • the second clock signal CK2 is at a high level
  • the first control signal GAS1 and the second control signal GAS2 are both at a high level.
  • the first pull control signal CL1 output by the first pull control unit 111 is at a low level (first level)
  • the third thin film transistor T3 is turned on
  • the level of the gate drive signal output terminal and the first clock signal CK1 are turned on.
  • the gate drive signal Gn is at a low level
  • the scan line 20 corresponding to the gate drive signal Gn is turned on, that is, the first pull unit 112 pulls the gate drive signal according to the first pull control signal CL1 and the first clock signal CK1.
  • the level of the output terminal is at a first level (low level); at this time, the fourth thin film transistor T4, the fifth thin film transistor T5, the eleventh thin film transistor T11, and the seventh thin film transistor T7 are turned off, and the sixth thin film transistor T6 is turned off.
  • the eighth thin film transistor T8 is turned on, the second pull control signal CL2 is at a high level (second level), and the ninth thin film transistor T9 and the tenth thin film transistor T10 are turned off.
  • the first clock signal CK1 is at a high level
  • the second clock signal CK2 is at a high level
  • the first control signal GAS1 and the second control signal GAS2 are at a high level
  • the first pull control unit 111 The output first pull control signal CL1 is at a low level (first level)
  • the third thin film transistor T3 is turned on, and the level of the gate drive signal output terminal is the same as the level of the first clock signal CK1, and the gate drive signal is Gn is at a high level, and the scanning line 20 corresponding to the gate driving signal Gn is turned off.
  • the fourth thin film transistor T4, the fifth thin film transistor T5, the eleventh thin film transistor T11, the seventh thin film transistor T7, and the eighth thin film transistor T8 are turned off, the sixth thin film transistor T6 is turned on, and the second pull control signal CL2 is turned on.
  • the high level (second level), the ninth thin film transistor T9 and the tenth thin film transistor T10 are turned off.
  • the control chip 12 pulls the first clock signal CK1, the first voltage reference signal V1, the first control signal GAS1, and the second control signal GAS2 to a first level (low level), that is, the first The clock signal CK1 is at a low level, the second clock signal CK2 is at a low level, the first control signal GAS1 is at a low level, the second control signal GAS2 is at a low level, and the fourth thin film transistor T4 and the fifth thin film transistor T5 are The eleventh thin film transistor T11 is turned on, the seventh thin film transistor T4 is turned on, the second pull control signal CL2 is at a low level, the eighth thin film transistor T8 and the ninth thin film transistor T9 are turned on, and the first node Qn passes through the eighth film.
  • the transistor T8 and the ninth thin film transistor T9 receive the first voltage reference signal V1, that is, the second pull unit 114 pulls the level of the first node Qn to the first voltage reference signal V1 according to the second pull control signal CL2. The level of Qn is pulled low.
  • the third thin film transistor T3 and the sixth thin film transistor T6 are both turned on, the potential of the output gate driving signal Gn is a low level; the tenth thin film transistor is turned on, and the output gate driving signal Gn
  • the potential is the same as the potential of the first voltage reference signal V1; the eleventh thin film transistor T11 is turned on, pulling the output gate driving signal Gn
  • the potential is the same as the potential of the second control signal GAS2 to ensure that the output gate drive signal Gn is at a low level, the scan line 20 driven by the gate drive signal Gn is turned on, and the scan line 20 driven by the gate drive circuit 10 is further turned on. Open all, stable implementation of All Gate On function.
  • the first clock signal CK1 is at a high level
  • the second clock signal CK2 is at a high level
  • the first control signal GAS1 is at a low level
  • the second control signal GAS2 is at a high level
  • the fourth thin film transistor T4 is turned on to pull the potential of the first node Qn to a high level
  • the first pull control signal CL1 is at a high level, that is, the first control unit 115 pulls the first node Qn according to the first control signal GAS1.
  • the level is to the second level, at which time the third transistor T3 is turned off, that is, the first pull unit 112 is turned off.
  • the fifth thin film transistor T5 is turned on, pulling the potential of the second node Pn to a low level, and the second pull control signal CL2 is at a low level, that is, the second control unit 116 pulls the power of the second node Pn according to the first control signal GAS1.
  • the ninth thin film transistor T9 and the tenth thin film transistor T10 are turned on, and at this time, the tenth thin film transistor T10 pulls the level of the gate driving signal Gn to a high level, that is, The second pull unit 114 pulls the level of the gate drive signal Gn to a second level (high level).
  • the eleventh thin film transistor T11 is turned on, and the eleventh thin film transistor T11 pulls the level of the gate driving signal Gn equal to the level of the second control signal GAS2, that is, a high level.
  • the gate drive signal Gn is at a high level, and the scan line 20 driven by the gate drive signal Gn is turned off, thereby implementing All scan lines 20 return to the off level after the Gate On function ends.
  • the sixth thin film transistor T6, the seventh thin film transistor T7, and the eighth thin film transistor T8 are turned off.
  • the first thin film transistor T1, the second thin film transistor T2, the third thin film transistor T3, the fourth thin film transistor T4, the fifth thin film transistor T5, and the sixth thin film transistor T6 may be completely used by those skilled in the art.
  • the seventh thin film transistor T7, the eighth thin film transistor T8, the ninth thin film transistor T9, the tenth thin film transistor T10, and the eleventh thin film transistor T11 are provided as N-type thin film transistors, and the N-type thin film transistors are turned on when the gate is at a high level.
  • the potential of each node is opposite to the potential change at the time of the scan driving, and the first reference voltage signal V1 and the second reference voltage signal V2 are also opposite to the potential at the time of the scan driving, that is, when the N-type thin film transistor is used, A reference voltage signal V1 is at a low level, and the second reference voltage signal V2 is at a high level, which will not be described herein.
  • the present invention also provides a gate driving unit of the third embodiment, which is described on the basis of the gate driving unit disclosed in the second embodiment.
  • the gate driving unit disclosed in this embodiment is different from the gate driving unit disclosed in the second embodiment in that the gate driving unit further includes a twelfth thin film transistor T12, as shown in FIG.
  • the first end of the thin film transistor 12 is connected to the first node Qn, the second end of the twelfth thin film transistor T12 receives the second reference voltage signal V2, and the third end of the twelfth thin film transistor T12 and the second thin film transistor T2
  • the third end, the third end of the first thin film transistor T1, and the first end of the fourth thin film transistor T4 are connected.
  • the twelfth thin film transistor T12 is a P-type thin film transistor.
  • the second reference voltage signal V2 is at a low level, and the twelfth thin film transistor T12 is turned on.
  • the first thin film transistor T1, the second thin film transistor T2, the third thin film transistor T3, the fourth thin film transistor T4, the fifth thin film transistor T5, and the sixth thin film transistor T6 may be completely used by those skilled in the art.
  • the seventh thin film transistor T7, the eighth thin film transistor T8, the ninth thin film transistor T9, the tenth thin film transistor T10, the eleventh thin film transistor T11, and the twelfth thin film transistor T12 are N-type thin film transistors.
  • the present invention also provides a liquid crystal display device.
  • the liquid crystal display device 60 disclosed in the present embodiment includes a display panel 61 and a gate driving circuit 62 disclosed in the above embodiments, and details are not described herein.
  • liquid crystal display device 60 includes a mobile phone, a display or a television.
  • the gate driving circuit of the present invention includes a multi-level gate driving unit and a control chip, and each stage of the gate driving unit includes a first pulling control unit, a first pulling unit, a second pulling control unit, and a second pulling a unit, a first control unit, a second control unit, and a third control unit, the control chip is configured to pull the first clock signal, the first voltage reference signal, the first control signal, and the second control signal to the first level, to The scan lines driven by the gate drive circuit are all turned on to stably implement All Gate On function.
  • the first control unit pulls the level of the first node to the second level according to the first control signal GAS1, the first pulling unit is turned off; and the second control unit pulls the power of the second node according to the first control signal.
  • Leveling to a third level of the second voltage reference signal the second pull unit pulls the level of the gate drive signal to a second level, and the third control unit pulls the gate drive signal according to the first control signal and the second control signal Level to the second level, at which time the scan line driven by the gate drive signal is turned off, thereby achieving All scan lines return to the off level after the Gate On function ends.

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Liquid Crystal (AREA)

Abstract

一种液晶显示装置及其栅极驱动电路（10）。栅极驱动电路（10）包括多级栅极驱动单元（11）以及控制芯片（12），每级栅极驱动单元（11）包括第一拉动控制单元（111）、第一拉动单元（112）、第二拉动控制单元（113）、第二拉动单元（114）、第一控制单元（115）、第二控制单元（116）以及第三控制单元（117），控制芯片（12）用于拉动第一时钟信号（CK1）、第一电压参考信号（V1）、第一控制信号（GAS1）以及第二控制信号（GAS2）到第一电平。通过以上方式使栅极驱动电路（10）所驱动的扫描线（20）全部打开，稳定地实现All Gate On功能。

Description

一种液晶显示装置及其栅极驱动电路
【技术领域】
本发明涉及液晶显示技术领域，特别是涉及一种液晶显示装置及其栅极驱动电路。
【背景技术】
阵列基板行驱动（GOA，Gate Driver On Array 或Gate On Array）电路，是利用现有薄膜晶体管显示装置（TFT-LCD）阵列（Array）制程将栅线（Gate）行扫描驱动信号电路制作在阵列基板上，以实现对栅线逐行扫描的驱动方式的一项技术。其与传统的柔性电路板（COF）和玻璃电路板（COG）工艺相比，不仅节省了制作成本，而且还可以省去栅极方向邦定（Bonding）的工艺，对提升产能极为有利，并提高了显示装置的集成度。
在实际使用时，由于显示装置通常需要搭配触摸屏（Touch Panel）功能进行使用，因此GOA电路需要实现信号中停以配合触摸屏的功能，如配合触摸屏的扫描。通常情况下，GOA电路在实现信号中停后，需将显示装置进行黑屏唤醒，此时GOA电路需要在一段时间内将所有的栅线均设置为充电或导通状态，通过向数据线施加黑电压以清空像素电容中残留的电平，以使得显示装置的显示效果良好，此段时间称为栅线全开（All Gate On）阶段。但是现有技术中的GOA电路在实现All Gate On时会存在功能失效风险，进而不能稳定的实现All Gate On功能。
【发明内容】
本发明主要解决的技术问题是提供一种液晶显示装置及其栅极驱动电路，能够稳定地实现All Gate On功能。
本发明提供一种液晶显示装置的栅极驱动电路，其包括多级栅极驱动单元和控制芯片，每级栅极驱动单元包括：
第一拉动控制单元，用于在第一节点输出第一拉动控制信号；
第一拉动单元，其耦接第一节点，接收第一时钟信号，根据第一拉动控制信号和第一时钟信号拉动栅极驱动信号输出端的电平到第一电平，以输出栅极驱动信号；
第二拉动控制单元，用于在第二节点输出第二拉动控制信号；
第二拉动单元，其耦接第一节点和第二节点，接收第一电压参考信号，根据第二拉动控制信号拉动第一节点的电平到第一电压参考信号的第二电平；
第一控制单元，其耦接第一节点，接收第一控制信号和第一电压参考信号，根据第一控制信号拉动第一节点的电平到第二电平；
第二控制单元，其耦接第二节点，接收第一控制信号和第二电压参考信号，根据第一控制信号拉动第二节点的电平到第二电压参考信号的第三电平，第二拉动单元拉动栅极驱动信号的电平到第二电平；
第三控制单元，其耦接栅极驱动信号输出端，接收第一控制信号和第二控制信号，根据第一控制信号和第二控制信号拉动栅极驱动信号的电平；
其中，控制芯片用于拉动第一时钟信号、第一电压参考信号、第一控制信号以及第二控制信号到第一电平，以使栅极驱动电路所驱动的扫描线全部打开。
其中，第一拉动控制单元包括第一薄膜晶体管和第二薄膜晶体管；
第一薄膜晶体管的第一端接收第一信号，第一薄膜晶体管的第二端接收前一级的栅极驱动信号，第一薄膜晶体管的第三端与第一节点连接；
第二薄膜晶体管的第一端接收第二信号，第二薄膜晶体管的第二端接收后一级的栅极驱动信号，第二薄膜晶体管的第三端与第一节点连接。
其中，第一拉动单元包括第三薄膜晶体管和第一电容，第三薄膜晶体管的第一端接收第一时钟信号，第三薄膜晶体管的第二端与第一节点连接，第三薄膜晶体管的第三端为栅极驱动信号输出端，第一电容连接在第三薄膜晶体管的第二端和第三端之间。
其中，第一控制单元包括第四薄膜晶体管，第四薄膜晶体管的第一端与第一节点连接，第四薄膜晶体管的第二端接收第一控制信号，第四薄膜晶体管的第三端接收第一参考电压信号。
其中，第二控制单元包括第五薄膜晶体管，第五薄膜晶体管的第一端接收第二参考电压信号，第五薄膜晶体管的第二端接收第一控制信号，第五薄膜晶体管的第三端与第二节点连接。
其中，第二拉动控制单元包括第六薄膜晶体管和第七薄膜晶体管，第六薄膜晶体管的第一端接收第二时钟信号，第六薄膜晶体管的第二端与第四薄膜晶体管的第一端连接，第六薄膜晶体管的第三端和第七薄膜晶体管的第三端与第二节点连接，第七薄膜晶体管的第一端接收第二电压参考信号，第七薄膜晶体管的第二端接收第二时钟信号；
第二拉动单元包括第八薄膜晶体管、第九薄膜晶体管、第十薄膜晶体管以及第二电容，第八薄膜晶体管的第一端与第三薄膜晶体管的第二端连接，第八薄膜晶体管的第二端接收第一时钟信号，第八薄膜晶体管的第三端与第九薄膜晶体管的第一端连接，第九薄膜晶体管的第二端与第七薄膜晶体管的第三端连接，第九薄膜晶体管的第三端接收第一参考电压信号，第十薄膜晶体管的第一端与第三薄膜晶体管的第三端连接，第十薄膜晶体管的第二端与第九薄膜晶体管的第二端连接，第十薄膜晶体管的第三端接收第一参考电压信号，第二电容连接在第十薄膜晶体管的第二端和第三端之间。
其中，第三控制单元包括第十一薄膜晶体管，第十一薄膜晶体管的第一端与第三薄膜晶体管的第三端连接，第十一薄膜晶体管的第二端接收第一控制信号，第十一薄膜晶体管的第三端接收第二控制信号。
其中，栅极驱动单元进一步包括第十二薄膜晶体管，第十二薄膜晶体管的第一端与第一节点连接，第十二薄膜晶体管的第二端接收第二参考电压信号，第十二薄膜晶体管的第三端与第二薄膜晶体管的第三端、第一薄膜晶体管的第三端以及第四薄膜晶体管的第一端连接。
其中，第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管、第六薄膜晶体管、第七薄膜晶体管、第八薄膜晶体管、第九薄膜晶体管、第十薄膜晶体管、第十一薄膜晶体管以及第十二薄膜晶体管均为P型薄膜晶体管；
在第一控制信号和第二控制信号为低电平时，第四薄膜晶体管导通，第三薄膜晶体管的第二端的电平拉动到第二电平，第三薄膜晶体管截止；第五薄膜晶体管导通，第十薄膜晶体管的第二端的电平拉动到第三电平，第十薄膜晶体管导通，第十一薄膜晶体管导通，将栅极驱动信号的电平拉动到第二电平。
其中，第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管、第六薄膜晶体管、第七薄膜晶体管、第八薄膜晶体管、第九薄膜晶体管、第十薄膜晶体管、第十一薄膜晶体管以及第十二薄膜晶体管均为N型薄膜晶体管。
本发明提供一种液晶显示装置，其包括栅极驱动电路，栅极驱动电路包括多级栅极驱动单元和控制芯片，每级栅极驱动单元包括：
第一拉动控制单元，用于在第一节点输出第一拉动控制信号；
第一拉动单元，其耦接第一节点，接收第一时钟信号，根据第一拉动控制信号和第一时钟信号拉动栅极驱动信号输出端的电平到第一电平，以输出栅极驱动信号；
第二拉动控制单元，用于在第二节点输出第二拉动控制信号；
第二拉动单元，其耦接第一节点和第二节点，接收第一电压参考信号，根据第二拉动控制信号拉动第一节点的电平到第一电压参考信号的第二电平；
第一控制单元，其耦接第一节点，接收第一控制信号和第一电压参考信号，根据第一控制信号拉动第一节点的电平到第二电平；
第二控制单元，其耦接第二节点，接收第一控制信号和第二电压参考信号，根据第一控制信号拉动第二节点的电平到第二电压参考信号的第三电平，第二拉动单元拉动栅极驱动信号的电平到第二电平；
第三控制单元，其耦接栅极驱动信号输出端，接收第一控制信号和第二控制信号，根据第一控制信号和第二控制信号拉动栅极驱动信号的电平；
其中，控制芯片用于拉动第一时钟信号、第一电压参考信号、第一控制信号以及第二控制信号到第一电平，以使栅极驱动电路所驱动的扫描线全部打开。
其中，第一拉动控制单元包括第一薄膜晶体管和第二薄膜晶体管；
第一薄膜晶体管的第一端接收第一信号，第一薄膜晶体管的第二端接收前一级的栅极驱动信号，第一薄膜晶体管的第三端与第一节点连接；
第二薄膜晶体管的第一端接收第二信号，第二薄膜晶体管的第二端接收后一级的栅极驱动信号，第二薄膜晶体管的第三端与第一节点连接。
其中，第一拉动单元包括第三薄膜晶体管和第一电容，第三薄膜晶体管的第一端接收第一时钟信号，第三薄膜晶体管的第二端与第一节点连接，第三薄膜晶体管的第三端为栅极驱动信号输出端，第一电容连接在第三薄膜晶体管的第二端和第三端之间。
其中，第一控制单元包括第四薄膜晶体管，第四薄膜晶体管的第一端与第一节点连接，第四薄膜晶体管的第二端接收第一控制信号，第四薄膜晶体管的第三端接收第一参考电压信号。
其中，第二控制单元包括第五薄膜晶体管，第五薄膜晶体管的第一端接收第二参考电压信号，第五薄膜晶体管的第二端接收第一控制信号，第五薄膜晶体管的第三端与第二节点连接。
其中，第二拉动控制单元包括第六薄膜晶体管和第七薄膜晶体管，第六薄膜晶体管的第一端接收第二时钟信号，第六薄膜晶体管的第二端与第四薄膜晶体管的第一端连接，第六薄膜晶体管的第三端和第七薄膜晶体管的第三端与第二节点连接，第七薄膜晶体管的第一端接收第二电压参考信号，第七薄膜晶体管的第二端接收第二时钟信号；
第二拉动单元包括第八薄膜晶体管、第九薄膜晶体管、第十薄膜晶体管以及第二电容，第八薄膜晶体管的第一端与第三薄膜晶体管的第二端连接，第八薄膜晶体管的第二端接收第一时钟信号，第八薄膜晶体管的第三端与第九薄膜晶体管的第一端连接，第九薄膜晶体管的第二端与第七薄膜晶体管的第三端连接，第九薄膜晶体管的第三端接收第一参考电压信号，第十薄膜晶体管的第一端与第三薄膜晶体管的第三端连接，第十薄膜晶体管的第二端与第九薄膜晶体管的第二端连接，第十薄膜晶体管的第三端接收第一参考电压信号，第二电容连接在第十薄膜晶体管的第二端和第三端之间。
其中，第三控制单元包括第十一薄膜晶体管，第十一薄膜晶体管的第一端与第三薄膜晶体管的第三端连接，第十一薄膜晶体管的第二端接收第一控制信号，第十一薄膜晶体管的第三端接收第二控制信号。
其中，栅极驱动单元进一步包括第十二薄膜晶体管，第十二薄膜晶体管的第一端与第一节点连接，第十二薄膜晶体管的第二端接收第二参考电压信号，第十二薄膜晶体管的第三端与第二薄膜晶体管的第三端、第一薄膜晶体管的第三端以及第四薄膜晶体管的第一端连接。
其中，第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管、第六薄膜晶体管、第七薄膜晶体管、第八薄膜晶体管、第九薄膜晶体管、第十薄膜晶体管、第十一薄膜晶体管以及第十二薄膜晶体管均为P型薄膜晶体管；
在第一控制信号和第二控制信号为低电平时，第四薄膜晶体管导通，第三薄膜晶体管的第二端的电平拉动到第二电平，第三薄膜晶体管截止；第五薄膜晶体管导通，第十薄膜晶体管的第二端的电平拉动到第三电平，第十薄膜晶体管导通，第十一薄膜晶体管导通，将栅极驱动信号的电平拉动到第二电平。
其中，第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管、第六薄膜晶体管、第七薄膜晶体管、第八薄膜晶体管、第九薄膜晶体管、第十薄膜晶体管、第十一薄膜晶体管以及第十二薄膜晶体管均为N型薄膜晶体管。
通过上述方案，本发明的有益效果是：本发明的栅极驱动电路包括多级栅极驱动单元以及控制芯片，每级栅极驱动单元包括第一拉动控制单元、第一拉动单元、第二拉动控制单元、第二拉动单元、第一控制单元、第二控制单元以及第三控制单元，控制芯片用于拉动第一时钟信号、第一电压参考信号、第一控制信号以及第二控制信号到第一电平，以使栅极驱动电路所驱动的扫描线全部打开，稳定地实现All Gate On功能。
【附图说明】
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。其中：
图1是本发明第一实施例的栅极驱动电路的结构示意图；
图2是图1中栅极驱动单元的结构示意图；
图3是本发明第二实施例的栅极驱动单元的电路图；
图4是图3中第一时钟信号、第二时钟信号、第一控制信号、第二控制信号以及栅极驱动信号的时序图；
图5是本发明第三实施例的栅极驱动单元的电路图；
图6是本发明第一实施例的液晶显示装置的结构示意图。
【具体实施方式】
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性的劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请参见图1所示，图1是本发明第一实施例的栅极驱动电路的结构示意图。本实施例所揭示的栅极驱动电路应用于液晶显示装置，用于驱动液晶显示装置的多条扫描线，以使多条扫描线打开。
如图1所示，栅极驱动电路10与多条扫描线20连接，用于驱动多条扫描线20，该栅极驱动电路10包括多级栅极驱动单元11和控制芯片12，一个栅极驱动单元11对应一条扫描线20，栅极驱动单元11的输出端与扫描线20连接。
以下以第n级栅极驱动单元11进行详细说明，其中n为大于或等于1的整数。
如图2所示，第n级栅极驱动单元11包括第一拉动控制单元111、第一拉动单元112、第二拉动控制单元113、第二拉动单元114、第一控制单元115、第二控制单元116以及第三控制单元117。
第一拉动控制单元111用于在第一节点Qn输出第一拉动控制信号CL1。第一拉动单元112耦接第一节点Qn，第一拉动单元112接收第一时钟信号CK1，并根据第一拉动控制信号CL1和第一时钟信号CK1拉动栅极驱动信号输出端的电平到第一电平，输出栅极驱动信号Gn为第一电平，栅极驱动信号Gn用于驱动扫描线20。优选地，第一拉动控制信号CL1为第一电平。
第二拉动控制单元113用于在第二节点Pn输出第二拉动控制信号CL2。第二拉动单元114耦接第一节点Qn和第二节点Pn，第二拉动单元114接收第一电压参考信号V1，并根据第二拉动控制信号CL2拉动第一节点Qn的电平到第一电压参考信号V1的第二电平。
第一控制单元115耦接第一节点Qn，第一控制单元115接收第一控制信号GAS1和第一电压参考信号V1，并根据控制信号GAS1拉动第一节点Qn的电平到第二电平，此时第一拉动控制信号CL1为第二电平。
第二控制单元116耦接第二节点Pn，第二控制单元116接收控制信号GAS1和第二电压参考信号V2，并根据控制信号GAS1拉动第二节点Pn的电平到第二电压参考信号V2的第三电平。第二拉动单元114进一步耦接栅极驱动信号输出端，第二拉动单元114拉动栅极驱动信号Gn的电平到第二电平。优选地，第一电平与第三电平相同。
第三控制单元117耦接栅极驱动信号输出端，第三控制单元117接收第一控制信号GAS1和第二控制信号GAS2，并根据第一控制信号GAS1和第二控制信号GAS2拉动栅极驱动信号的电平，例如第三控制单元117根据第一控制信号GAS1和第二控制信号GAS2拉动栅极驱动信号Gn的电平到第二电平。
在栅极驱动信号Gn的电平为第一电平时，扫描线20打开；在栅极驱动信号Gn的电平为第二电平时，扫描线20关闭，控制芯片12用于拉动第一时钟信号CK1、第一电压参考信号V1、第一控制信号GAS1以及第二控制信号GAS2到第一电平，此时栅极驱动信号Gn的电平为第一电平，栅极驱动信号Gn所驱动的扫描线20打开，以使栅极驱动电路10所驱动的扫描线20全部打开，稳定地实现All Gate On功能。
在All Gate On功能结束后，第一控制单元115根据第一控制信号GAS1拉动第一节点Qn的电平到第二电平，第一拉动单元112断开；第二控制单元116根据第一控制信号GAS1拉动第二节点Pn的电平到第二电压参考信号V2的第三电平，以使第二拉动单元114拉动栅极驱动信号Gn的电平到第二电平；第三控制单元117根据第一控制信号GAS1和第二控制信号GAS2拉动栅极驱动信号Gn的电平到第二电平；此时扫描线20关闭，进而实现在All Gate On功能结束后所有扫描线20均回到关闭电平。
本发明还提供第二实施例的栅极驱动单元，其在第一实施例所揭示的栅极驱动单元11的基础上进行描述。如图3所示，第一拉动控制单元111包括第一薄膜晶体管T1和第二薄膜晶体管T2，第一薄膜晶体管T1的第一端接收第一信号U2D，第一薄膜晶体管T1的第二端接收前一级的栅极驱动信号Gn-1，第一薄膜晶体管T1的第三端与第一节点Qn连接；第二薄膜晶体管T2的第一端接收第二信号D2U，第二薄膜晶体管T2的第二端接收后一级的栅极驱动信号Gn+1，第二薄膜晶体管T2的第三端与第一节点Qn连接。其中，第一拉动控制单元111用于控制栅极驱动单元的正反扫描信号，并根据前一级的栅极驱动信号Gn-1或者后一级的栅极驱动信号Gn+1选择输入第一信号U2D或者第二信号D2U，其中第一信号U2D与第二信号D2U相反，例如第一信号U2D为高电平时，第二信号D2U为低电平。第一薄膜晶体管T1的第三端和第二薄膜晶体管T2的第三端输出第一拉动控制信号CL1。
第一拉动单元112包括第三薄膜晶体管T3和第一电容C1，第三薄膜晶体管T3的第一端接收第一时钟信号CK1，第三薄膜晶体管T3的第二端与第一节点Qn连接，第三薄膜晶体管T3的第三端为栅极驱动信号输出端，第一电容C1连接在第三薄膜晶体管T3的第二端和第三端之间。
第一控制单元115包括第四薄膜晶体管T4，第四薄膜晶体管T4的第一端与第一节点Qn连接，第四薄膜晶体管T4的第二端接收第一控制信号GAS1，第四薄膜晶体管T4的第三端接收第一参考电压信号V1。
第二控制单元116包括第五薄膜晶体管T5，第五薄膜晶体管T5的第一端接收第二参考电压信号V2，第五薄膜晶体管T5的第二端接收第一控制信号GAS1，第五薄膜晶体管T5的第三端与第二节点Pn连接。
第二拉动控制单元113包括第六薄膜晶体管T6和第七薄膜晶体管T7，第六薄膜晶体管T6的第一端接收第二时钟信号CK2，第六薄膜晶体管T6的第二端与第四薄膜晶体管T4的第一端连接，第六薄膜晶体管T6的第三端和第七薄膜晶体管T7的第三端与第二节点Pn连接，第七薄膜晶体管T7的第一端接收第二电压参考信号V2，第七薄膜晶体管T7的第二端接收第二时钟信号CK2。第六薄膜晶体管T6的第三端和第七薄膜晶体管T7的第三端输出第二拉动控制信号CL2。
第二拉动单元114包括第八薄膜晶体管T8、第九薄膜晶体管T9、第十薄膜晶体管T10以及第二电容C2，第八薄膜晶体管T8的第一端与第三薄膜晶体管T3的第二端连接，第八薄膜晶体管T8的第二端接收第一时钟信号CK1，第八薄膜晶体管T8的第三端与第九薄膜晶体管T9的第一端连接，第九薄膜晶体管T9的第二端与第七薄膜晶体管T7的第三端连接，第九薄膜晶体管T9的第三端接收第一参考电压信号V1，第十薄膜晶体管T10的第一端与第三薄膜晶体管T3的第三端连接，第十薄膜晶体管T10的第二端与第九薄膜晶体管T9的第二端连接，第十薄膜晶体管T10的第三端接收第一参考电压信号V1，第二电容C2连接在第十薄膜晶体管T10的第二端和第三端之间。
第三控制单元117包括第十一薄膜晶体管T11，第十一薄膜晶体管T11的第一端与第三薄膜晶体管T3的第三端连接，第十一薄膜晶体管T11的第二端接收第一控制信号GAS1，第十一薄膜晶体管T11的第三端接收第二控制信号GAS2。
优选地，第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3、第四薄膜晶体管T4、第五薄膜晶体管T5、第六薄膜晶体管T6、第七薄膜晶体管T7、第八薄膜晶体管T8、第九薄膜晶体管T9、第十薄膜晶体管T10以及第十一薄膜晶体管T11均为P型薄膜晶体管，P型薄膜晶体管在栅极为低电平时导通。
结合图4所示的时序图详细描述本实施例所揭示的栅极驱动单元的工作原理。
优选地，第一电平和第三电平为低电平，第二电平为高电平，即第一参考电压信号V1为VGH（高电平），第二参考电压信号V2为VGL（低电平）。
如图4所示，在时间t1-t2之间，第一时钟信号CK1为低电平，第二时钟信号CK2为高电平，第一控制信号GAS1和第二控制信号GAS2均为高电平；第一拉动控制单元111输出的第一拉动控制信号CL1为低电平（第一电平），第三薄膜晶体管T3导通，栅极驱动信号输出端的电平与第一时钟信号CK1的电平相同，栅极驱动信号Gn为低电平，与栅极驱动信号Gn对应的扫描线20打开，即第一拉动单元112根据第一拉动控制信号CL1和第一时钟信号CK1拉动栅极驱动信号输出端的电平到第一电平（低电平）；此时，第四薄膜晶体管T4、第五薄膜晶体管T5、第十一薄膜晶体管T11以及第七薄膜晶体管T7断开，第六薄膜晶体管T6和第八薄膜晶体管T8导通，第二拉动控制信号CL2为高电平（第二电平），第九薄膜晶体管T9和第十薄膜晶体管T10断开。
在时间t2-t3之间，第一时钟信号CK1为高电平，第二时钟信号CK2为高电平，第一控制信号GAS1和第二控制信号GAS2为高电平；第一拉动控制单元111输出的第一拉动控制信号CL1为低电平（第一电平），第三薄膜晶体管T3导通，栅极驱动信号输出端的电平与第一时钟信号CK1的电平相同，栅极驱动信号Gn为高电平，与栅极驱动信号Gn对应的扫描线20关闭。此时，第四薄膜晶体管T4、第五薄膜晶体管T5、第十一薄膜晶体管T11、第七薄膜晶体管T7以及第八薄膜晶体管T8断开，第六薄膜晶体管T6导通，第二拉动控制信号CL2为高电平（第二电平），第九薄膜晶体管T9和第十薄膜晶体管T10断开。
此时，所有的栅极驱动信号均为高电平，该栅极驱动电路处于GOA暂停状态，即栅极驱动信号Gn-1、Gn以及Gn+1均为高电平。
在时间t4-t5之间，控制芯片12拉动第一时钟信号CK1、第一电压参考信号V1、第一控制信号GAS1以及第二控制信号GAS2到第一电平（低电平），即第一时钟信号CK1为低电平，第二时钟信号CK2为低电平，第一控制信号GAS1为低电平，第二控制信号GAS2为低电平；第四薄膜晶体管T4、第五薄膜晶体管T5和第十一薄膜晶体管T11导通，第七薄膜晶体管T4导通，第二拉动控制信号CL2为低电平，第八薄膜晶体管T8和第九薄膜晶体管T9导通，第一节点Qn通过第八薄膜晶体管T8和第九薄膜晶体管T9接收第一电压参考信号V1，即第二拉动单元114根据第二拉动控制信号CL2拉动第一节点Qn的电平到第一电压参考信号V1，此时第一节点Qn的电平拉动到低电平。第三薄膜晶体管T3和第六薄膜晶体管T6均导通，输出栅极驱动信号Gn的电位为低电平；第十薄膜晶体管导通，输出栅极驱动信号Gn 的电位与第一电压参考信号V1的电位相同；第十一薄膜晶体管T11导通，拉动输出栅极驱动信号Gn 的电位与第二控制信号GAS2的电位相同，以保证输出栅极驱动信号Gn为低电平，栅极驱动信号Gn所驱动的扫描线20打开，进而栅极驱动电路10所驱动的扫描线20全部打开，稳定地实现All Gate On功能。
在All Gate On功能结束后，时间t5-t6，第一时钟信号CK1为高电平，第二时钟信号CK2为高电平，第一控制信号GAS1为低电平，第二控制信号GAS2为高电平；第四薄膜晶体管T4导通，以拉动第一节点Qn的电位到高电平，第一拉动控制信号CL1为高电平，即第一控制单元115根据第一控制信号GAS1拉动第一节点Qn的电平到第二电平，此时第三晶体管T3断开，即第一拉动单元112断开。第五薄膜晶体管T5导通，拉动第二节点Pn的电位到低电平，第二拉动控制信号CL2为低电平，即第二控制单元116根据第一控制信号GAS1拉动第二节点Pn的电平到第二电压参考信号V2的第三电平，第九薄膜晶体管T9和第十薄膜晶体管T10导通，此时第十薄膜晶体管T10拉动栅极驱动信号Gn的电平到高电平，即第二拉动单元114拉动栅极驱动信号Gn的电平到第二电平（高电平）。第十一薄膜晶体管T11导通，第十一薄膜晶体管T11拉动栅极驱动信号Gn的电平与第二控制信号GAS2的电平相等，即高电平。栅极驱动信号Gn为高电平，栅极驱动信号Gn所驱动的扫描线20关闭，进而实现在All Gate On功能结束后所有扫描线20均回到关闭电平。此时，第六薄膜晶体管T6、第七薄膜晶体管T7以及第八薄膜晶体管T8断开。
在其他实施例中，本领域的技术人员完全可以将第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3、第四薄膜晶体管T4、第五薄膜晶体管T5、第六薄膜晶体管T6、第七薄膜晶体管T7、第八薄膜晶体管T8、第九薄膜晶体管T9、第十薄膜晶体管T10以及第十一薄膜晶体管T11设置为N型薄膜晶体管，N型薄膜晶体管在栅极为高电平时导通。此时，各节点的电位与上述扫描驱动时的电位变化相反，且第一参考电压信号V1和第二参考电压信号V2也与上述扫描驱动时的电位相反，即当N型薄膜晶体管时，第一参考电压信号V1为低电平，第二参考电压信号V2为高电平，此处不再赘述。
本发明还提供第三实施例的栅极驱动单元，其在第二实施例所揭示的栅极驱动单元的基础上进行描述。本实施例所揭示的栅极驱动单元与第二实施例所揭示的栅极驱动单元的不同之处在于：栅极驱动单元进一步包括第十二薄膜晶体管T12，如图5所示，第十二薄膜晶体管12的第一端与第一节点Qn连接，第十二薄膜晶体管T12的第二端接收第二参考电压信号V2，第十二薄膜晶体管T12的第三端与第二薄膜晶体管T2的第三端、第一薄膜晶体管T1的第三端以及第四薄膜晶体管T4的第一端连接。
优选地，第十二薄膜晶体管T12为P型薄膜晶体管。第二参考电压信号V2为低电平，第十二薄膜晶体管T12导通。
在其他实施例中，本领域的技术人员完全可以将第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3、第四薄膜晶体管T4、第五薄膜晶体管T5、第六薄膜晶体管T6、第七薄膜晶体管T7、第八薄膜晶体管T8、第九薄膜晶体管T9、第十薄膜晶体管T10、第十一薄膜晶体管T11以及第十二薄膜晶体管T12为N型薄膜晶体管。
本发明还提供一种液晶显示装置，如图6所示，本实施例所揭示的液晶显示装置60包括显示面板61和上述实施例所揭示的栅极驱动电路62，此处不再赘述。
值得注意的是，本实施例所揭示的液晶显示装置60包括手机、显示器或者电视。
综上所述，本发明的栅极驱动电路包括多级栅极驱动单元和控制芯片，每级栅极驱动单元包括第一拉动控制单元、第一拉动单元、第二拉动控制单元、第二拉动单元、第一控制单元、第二控制单元、以及第三控制单元，控制芯片用于拉动第一时钟信号、第一电压参考信号、第一控制信号以及第二控制信号到第一电平，以使栅极驱动电路所驱动的扫描线全部打开，以稳定地实现All Gate On功能。此外，在All Gate On功能结束后，第一控制单元根据第一控制信号GAS1拉动第一节点的电平到第二电平，第一拉动单元断开；第二控制单元根据第一控制信号拉动第二节点的电平到第二电压参考信号的第三电平，第二拉动单元拉动栅极驱动信号的电平到第二电平，第三控制单元根据第一控制信号和第二控制信号拉动栅极驱动信号的电平到第二电平，此时栅极驱动信号所驱动的扫描线关闭，进而实现在All Gate On功能结束后所有扫描线均回到关闭电平。
以上所述仅为本发明的实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (20)

  1. 一种栅极驱动电路，其中，所述栅极驱动电路包括多级栅极驱动单元和控制芯片，每级所述栅极驱动单元包括：
    第一拉动控制单元，用于在第一节点输出第一拉动控制信号；
    第一拉动单元，其耦接所述第一节点，接收第一时钟信号，根据所述第一拉动控制信号和第一时钟信号拉动栅极驱动信号输出端的电平到第一电平，以输出栅极驱动信号；
    第二拉动控制单元，用于在第二节点输出第二拉动控制信号；
    第二拉动单元，其耦接所述第一节点和所述第二节点，接收第一电压参考信号，根据所述第二拉动控制信号拉动所述第一节点的电平到所述第一电压参考信号的第二电平；
    第一控制单元，其耦接所述第一节点，接收第一控制信号和所述第一电压参考信号，根据所述第一控制信号拉动所述第一节点的电平到所述第二电平；
    第二控制单元，其耦接所述第二节点，接收所述第一控制信号和第二电压参考信号，根据所述第一控制信号拉动所述第二节点的电平到所述第二电压参考信号的第三电平，所述第二拉动单元拉动所述栅极驱动信号的电平到所述第二电平；
    第三控制单元，其耦接所述栅极驱动信号输出端，接收所述第一控制信号和第二控制信号，根据所述第一控制信号和所述第二控制信号拉动所述栅极驱动信号的电平；
    其中，所述控制芯片用于拉动所述第一时钟信号、所述第一电压参考信号、所述第一控制信号以及第二控制信号到所述第一电平，以使所述栅极驱动电路所驱动的扫描线全部打开。
  2. 根据权利要求1所述的栅极驱动电路，其中，所述第一拉动控制单元包括第一薄膜晶体管和第二薄膜晶体管；
    所述第一薄膜晶体管的第一端接收第一信号，所述第一薄膜晶体管的第二端接收前一级的栅极驱动信号，所述第一薄膜晶体管的第三端与所述第一节点连接；
    所述第二薄膜晶体管的第一端接收第二信号，所述第二薄膜晶体管的第二端接收后一级的栅极驱动信号，所述第二薄膜晶体管的第三端与所述第一节点连接。
  3. 根据权利要求2所述的栅极驱动电路，其中，所述第一拉动单元包括第三薄膜晶体管和第一电容，所述第三薄膜晶体管的第一端接收所述第一时钟信号，所述第三薄膜晶体管的第二端与所述第一节点连接，所述第三薄膜晶体管的第三端为所述栅极驱动信号输出端，所述第一电容连接在所述第三薄膜晶体管的第二端和第三端之间。
  4. 根据权利要求3所述的栅极驱动电路，其中，所述第一控制单元包括第四薄膜晶体管，所述第四薄膜晶体管的第一端与所述第一节点连接，所述第四薄膜晶体管的第二端接收所述第一控制信号，所述第四薄膜晶体管的第三端接收所述第一参考电压信号。
  5. 根据权利要求4所述的栅极驱动电路，其中，所述第二控制单元包括第五薄膜晶体管，所述第五薄膜晶体管的第一端接收所述第二参考电压信号，所述第五薄膜晶体管的第二端接收所述第一控制信号，所述第五薄膜晶体管的第三端与所述第二节点连接。
  6. 根据权利要求5所述的栅极驱动电路，其中，所述第二拉动控制单元包括第六薄膜晶体管和第七薄膜晶体管，所述第六薄膜晶体管的第一端接收第二时钟信号，所述第六薄膜晶体管的第二端与所述第四薄膜晶体管的第一端连接，所述第六薄膜晶体管的第三端和所述第七薄膜晶体管的第三端与所述第二节点连接，所述第七薄膜晶体管的第一端接收所述第二电压参考信号，所述第七薄膜晶体管的第二端接收所述第二时钟信号；
    所述第二拉动单元包括第八薄膜晶体管、第九薄膜晶体管、第十薄膜晶体管以及第二电容，所述第八薄膜晶体管的第一端与所述第三薄膜晶体管的第二端连接，所述第八薄膜晶体管的第二端接收所述第一时钟信号，所述第八薄膜晶体管的第三端与所述第九薄膜晶体管的第一端连接，所述第九薄膜晶体管的第二端与所述第七薄膜晶体管的第三端连接，所述第九薄膜晶体管的第三端接收所述第一参考电压信号，所述第十薄膜晶体管的第一端与所述第三薄膜晶体管的第三端连接，所述第十薄膜晶体管的第二端与所述第九薄膜晶体管的第二端连接，所述第十薄膜晶体管的第三端接收所述第一参考电压信号，所述第二电容连接在所述第十薄膜晶体管的第二端和第三端之间。
  7. 根据权利要求6所述的栅极驱动电路，其中，所述第三控制单元包括第十一薄膜晶体管，所述第十一薄膜晶体管的第一端与所述第三薄膜晶体管的第三端连接，所述第十一薄膜晶体管的第二端接收所述第一控制信号，所述第十一薄膜晶体管的第三端接收所述第二控制信号。
  8. 根据权利要求7所述的栅极驱动电路，其中，所述栅极驱动单元进一步包括第十二薄膜晶体管，所述第十二薄膜晶体管的第一端与所述第一节点连接，所述第十二薄膜晶体管的第二端接收所述第二参考电压信号，所述第十二薄膜晶体管的第三端与所述第二薄膜晶体管的第三端、所述第一薄膜晶体管的第三端以及所述第四薄膜晶体管的第一端连接。
  9. 根据权利要求8所述的栅极驱动电路，其中，所述第一薄膜晶体管、所述第二薄膜晶体管、所述第三薄膜晶体管、所述第四薄膜晶体管、所述第五薄膜晶体管、所述第六薄膜晶体管、所述第七薄膜晶体管、所述第八薄膜晶体管、所述第九薄膜晶体管、所述第十薄膜晶体管、所述第十一薄膜晶体管以及所述第十二薄膜晶体管均为P型薄膜晶体管；
    在所述第一控制信号和所述第二控制信号均为低电平时，所述第四薄膜晶体管导通，所述第三薄膜晶体管的第二端的电平拉动到所述第二电平，所述第三薄膜晶体管截止；所述第五薄膜晶体管导通，所述第十薄膜晶体管的第二端的电平拉动到所述第三电平，所述第十薄膜晶体管导通，所述第十一薄膜晶体管导通，将所述栅极驱动信号的电平拉动到所述第二电平。
  10. 根据权利要求8所述的栅极驱动电路，其中，所述第一薄膜晶体管、所述第二薄膜晶体管、所述第三薄膜晶体管、所述第四薄膜晶体管、所述第五薄膜晶体管、所述第六薄膜晶体管、所述第七薄膜晶体管、所述第八薄膜晶体管、所述第九薄膜晶体管、所述第十薄膜晶体管、所述第十一薄膜晶体管以及所述第十二薄膜晶体管均为N型薄膜晶体管。
  11. 一种液晶显示装置，其中，所述液晶显示装置包括栅极驱动电路，所述栅极驱动电路包括多级栅极驱动单元和控制芯片，每级所述栅极驱动单元包括：
    第一拉动控制单元，用于在第一节点输出第一拉动控制信号；
    第一拉动单元，其耦接所述第一节点，接收第一时钟信号，根据所述第一拉动控制信号和第一时钟信号拉动栅极驱动信号输出端的电平到第一电平，以输出栅极驱动信号；
    第二拉动控制单元，用于在第二节点输出第二拉动控制信号；
    第二拉动单元，其耦接所述第一节点和所述第二节点，接收第一电压参考信号，根据所述第二拉动控制信号拉动所述第一节点的电平到所述第一电压参考信号的第二电平；
    第一控制单元，其耦接所述第一节点，接收第一控制信号和所述第一电压参考信号，根据所述第一控制信号拉动所述第一节点的电平到所述第二电平；
    第二控制单元，其耦接所述第二节点，接收所述第一控制信号和第二电压参考信号，根据所述第一控制信号拉动所述第二节点的电平到所述第二电压参考信号的第三电平，所述第二拉动单元拉动所述栅极驱动信号的电平到所述第二电平；
    第三控制单元，其耦接所述栅极驱动信号输出端，接收所述第一控制信号和第二控制信号，根据所述第一控制信号和所述第二控制信号拉动所述栅极驱动信号的电平；
    其中，所述控制芯片用于拉动所述第一时钟信号、所述第一电压参考信号、所述第一控制信号以及第二控制信号到所述第一电平，以使所述栅极驱动电路所驱动的扫描线全部打开。
  12. 根据权利要求11所述的液晶显示装置，其中，所述第一拉动控制单元包括第一薄膜晶体管和第二薄膜晶体管；
    所述第一薄膜晶体管的第一端接收第一信号，所述第一薄膜晶体管的第二端接收前一级的栅极驱动信号，所述第一薄膜晶体管的第三端与所述第一节点连接；
    所述第二薄膜晶体管的第一端接收第二信号，所述第二薄膜晶体管的第二端接收后一级的栅极驱动信号，所述第二薄膜晶体管的第三端与所述第一节点连接。
  13. 根据权利要求12所述的液晶显示装置，其中，所述第一拉动单元包括第三薄膜晶体管和第一电容，所述第三薄膜晶体管的第一端接收所述第一时钟信号，所述第三薄膜晶体管的第二端与所述第一节点连接，所述第三薄膜晶体管的第三端为所述栅极驱动信号输出端，所述第一电容连接在所述第三薄膜晶体管的第二端和第三端之间。
  14. 根据权利要求13所述的液晶显示装置，其中，所述第一控制单元包括第四薄膜晶体管，所述第四薄膜晶体管的第一端与所述第一节点连接，所述第四薄膜晶体管的第二端接收所述第一控制信号，所述第四薄膜晶体管的第三端接收所述第一参考电压信号。
  15. 根据权利要求14所述的液晶显示装置，其中，所述第二控制单元包括第五薄膜晶体管，所述第五薄膜晶体管的第一端接收所述第二参考电压信号，所述第五薄膜晶体管的第二端接收所述第一控制信号，所述第五薄膜晶体管的第三端与所述第二节点连接。
  16. 根据权利要求15所述的液晶显示装置，其中，所述第二拉动控制单元包括第六薄膜晶体管和第七薄膜晶体管，所述第六薄膜晶体管的第一端接收第二时钟信号，所述第六薄膜晶体管的第二端与所述第四薄膜晶体管的第一端连接，所述第六薄膜晶体管的第三端和所述第七薄膜晶体管的第三端与所述第二节点连接，所述第七薄膜晶体管的第一端接收所述第二电压参考信号，所述第七薄膜晶体管的第二端接收所述第二时钟信号；
    所述第二拉动单元包括第八薄膜晶体管、第九薄膜晶体管、第十薄膜晶体管以及第二电容，所述第八薄膜晶体管的第一端与所述第三薄膜晶体管的第二端连接，所述第八薄膜晶体管的第二端接收所述第一时钟信号，所述第八薄膜晶体管的第三端与所述第九薄膜晶体管的第一端连接，所述第九薄膜晶体管的第二端与所述第七薄膜晶体管的第三端连接，所述第九薄膜晶体管的第三端接收所述第一参考电压信号，所述第十薄膜晶体管的第一端与所述第三薄膜晶体管的第三端连接，所述第十薄膜晶体管的第二端与所述第九薄膜晶体管的第二端连接，所述第十薄膜晶体管的第三端接收所述第一参考电压信号，所述第二电容连接在所述第十薄膜晶体管的第二端和第三端之间。
  17. 根据权利要求16所述的液晶显示装置，其中，所述第三控制单元包括第十一薄膜晶体管，所述第十一薄膜晶体管的第一端与所述第三薄膜晶体管的第三端连接，所述第十一薄膜晶体管的第二端接收所述第一控制信号，所述第十一薄膜晶体管的第三端接收所述第二控制信号。
  18. 根据权利要求17所述的液晶显示装置，其中，所述栅极驱动单元进一步包括第十二薄膜晶体管，所述第十二薄膜晶体管的第一端与所述第一节点连接，所述第十二薄膜晶体管的第二端接收所述第二参考电压信号，所述第十二薄膜晶体管的第三端与所述第二薄膜晶体管的第三端、所述第一薄膜晶体管的第三端以及所述第四薄膜晶体管的第一端连接。
  19. 根据权利要求18所述的液晶显示装置，其中，所述第一薄膜晶体管、所述第二薄膜晶体管、所述第三薄膜晶体管、所述第四薄膜晶体管、所述第五薄膜晶体管、所述第六薄膜晶体管、所述第七薄膜晶体管、所述第八薄膜晶体管、所述第九薄膜晶体管、所述第十薄膜晶体管、所述第十一薄膜晶体管以及所述第十二薄膜晶体管均为P型薄膜晶体管；
    在所述第一控制信号和所述第二控制信号均为低电平时，所述第四薄膜晶体管导通，所述第三薄膜晶体管的第二端的电平拉动到所述第二电平，所述第三薄膜晶体管截止；所述第五薄膜晶体管导通，所述第十薄膜晶体管的第二端的电平拉动到所述第三电平，所述第十薄膜晶体管导通，所述第十一薄膜晶体管导通，将所述栅极驱动信号的电平拉动到所述第二电平。
  20. 根据权利要求18所述的液晶显示装置，其中，所述第一薄膜晶体管、所述第二薄膜晶体管、所述第三薄膜晶体管、所述第四薄膜晶体管、所述第五薄膜晶体管、所述第六薄膜晶体管、所述第七薄膜晶体管、所述第八薄膜晶体管、所述第九薄膜晶体管、所述第十薄膜晶体管、所述第十一薄膜晶体管以及所述第十二薄膜晶体管均为N型薄膜晶体管。
PCT/CN2015/090140 2015-09-14 2015-09-21 一种液晶显示装置及其栅极驱动电路 Ceased WO2017045215A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US14/786,071 US9799293B2 (en) 2015-09-14 2015-09-21 Liquid crystal display device and gate driving circuit

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201510583438.1A CN105185333B (zh) 2015-09-14 2015-09-14 一种液晶显示装置的栅极驱动电路
CN201510583438.1 2015-09-14

Publications (1)

Publication Number Publication Date
WO2017045215A1 true WO2017045215A1 (zh) 2017-03-23

Family

ID=54907367

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2015/090140 Ceased WO2017045215A1 (zh) 2015-09-14 2015-09-21 一种液晶显示装置及其栅极驱动电路

Country Status (3)

Country Link
US (1) US9799293B2 (zh)
CN (1) CN105185333B (zh)
WO (1) WO2017045215A1 (zh)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105139796B (zh) * 2015-09-23 2018-03-09 深圳市华星光电技术有限公司 一种goa电路、显示装置和goa电路的驱动方法
CN105118416B (zh) * 2015-09-23 2018-01-05 深圳市华星光电技术有限公司 一种goa电路、显示装置和goa电路的驱动方法
CN105118419B (zh) * 2015-09-28 2017-11-10 深圳市华星光电技术有限公司 一种显示装置、tft基板及goa驱动电路
CN105513550B (zh) * 2016-01-04 2019-02-01 武汉华星光电技术有限公司 Goa驱动电路
CN105513522B (zh) * 2016-01-28 2018-05-01 京东方科技集团股份有限公司 移位寄存器及其驱动方法、驱动电路和显示装置
CN107767833A (zh) * 2017-11-17 2018-03-06 武汉华星光电技术有限公司 一种goa电路
CN108257568B (zh) * 2018-02-01 2020-06-12 京东方科技集团股份有限公司 移位寄存器、栅极集成驱动电路、显示面板及显示装置
CN113870755B (zh) * 2020-06-30 2024-01-19 京东方科技集团股份有限公司 栅极驱动单元、栅极驱动电路、驱动方法及显示装置
CN113270072B (zh) * 2021-07-19 2021-10-22 深圳市柔宇科技股份有限公司 扫描驱动单元、扫描驱动电路、阵列基板及显示器

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101000417A (zh) * 2006-01-10 2007-07-18 三星电子株式会社 栅极驱动器和薄膜晶体管衬底及其液晶显示器
CN101000751A (zh) * 2006-12-30 2007-07-18 友达光电股份有限公司 栅极驱动电路及其驱动电路单元
CN102479477A (zh) * 2010-11-26 2012-05-30 京东方科技集团股份有限公司 移位寄存器单元、栅极驱动电路和显示装置
CN102629444A (zh) * 2011-08-22 2012-08-08 北京京东方光电科技有限公司 栅极集成驱动电路、移位寄存器及显示屏
CN103258495A (zh) * 2013-05-07 2013-08-21 京东方科技集团股份有限公司 移位寄存单元、移位寄存器和显示装置
CN103680387A (zh) * 2013-12-24 2014-03-26 合肥京东方光电科技有限公司 一种移位寄存器及其驱动方法、显示装置
CN103745700A (zh) * 2013-12-27 2014-04-23 深圳市华星光电技术有限公司 自修复型栅极驱动电路
CN103928008A (zh) * 2014-04-24 2014-07-16 深圳市华星光电技术有限公司 一种用于液晶显示的goa电路及液晶显示装置
CN104318909A (zh) * 2014-11-12 2015-01-28 京东方科技集团股份有限公司 移位寄存器单元、栅极驱动电路及其驱动方法、显示面板
CN104537992A (zh) * 2014-12-30 2015-04-22 深圳市华星光电技术有限公司 用于液晶显示装置的goa电路
CN104715710A (zh) * 2015-04-10 2015-06-17 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、扫描驱动电路、显示装置

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101383133B (zh) * 2008-10-20 2010-12-01 友达光电股份有限公司 一种用于消除残影的移位缓存器单元
KR101250128B1 (ko) * 2010-03-19 2013-04-05 샤프 가부시키가이샤 시프트 레지스터
CN102968975B (zh) * 2012-12-10 2015-06-17 京东方科技集团股份有限公司 液晶显示装置及其栅驱动电路电压控制方法及控制电路
CN104464666B (zh) * 2014-12-09 2017-01-18 昆山龙腾光电有限公司 一种栅极驱动电路及其显示装置
CN104575420B (zh) 2014-12-19 2017-01-11 深圳市华星光电技术有限公司 一种扫描驱动电路
US9484111B2 (en) 2014-12-30 2016-11-01 Shenzhen China Star Optoelectronics Technology Co., Ltd. Bidirectional scanning GOA circuit
CN104575353B (zh) * 2014-12-30 2017-02-22 厦门天马微电子有限公司 一种驱动电路、阵列基板及显示装置
CN104537991B (zh) * 2014-12-30 2017-04-19 深圳市华星光电技术有限公司 正反向扫描的栅极驱动电路
CN104575433A (zh) * 2015-02-04 2015-04-29 京东方科技集团股份有限公司 Goa复位电路及驱动方法、阵列基板、显示面板和装置
CN104732951B (zh) 2015-04-21 2017-03-01 京东方科技集团股份有限公司 移位寄存器及其驱动方法、栅极驱动装置、显示面板
KR20170010283A (ko) * 2015-07-17 2017-01-26 삼성디스플레이 주식회사 게이트 구동 회로 및 이를 갖는 표시 장치

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101000417A (zh) * 2006-01-10 2007-07-18 三星电子株式会社 栅极驱动器和薄膜晶体管衬底及其液晶显示器
CN101000751A (zh) * 2006-12-30 2007-07-18 友达光电股份有限公司 栅极驱动电路及其驱动电路单元
CN102479477A (zh) * 2010-11-26 2012-05-30 京东方科技集团股份有限公司 移位寄存器单元、栅极驱动电路和显示装置
CN102629444A (zh) * 2011-08-22 2012-08-08 北京京东方光电科技有限公司 栅极集成驱动电路、移位寄存器及显示屏
CN103258495A (zh) * 2013-05-07 2013-08-21 京东方科技集团股份有限公司 移位寄存单元、移位寄存器和显示装置
CN103680387A (zh) * 2013-12-24 2014-03-26 合肥京东方光电科技有限公司 一种移位寄存器及其驱动方法、显示装置
CN103745700A (zh) * 2013-12-27 2014-04-23 深圳市华星光电技术有限公司 自修复型栅极驱动电路
CN103928008A (zh) * 2014-04-24 2014-07-16 深圳市华星光电技术有限公司 一种用于液晶显示的goa电路及液晶显示装置
CN104318909A (zh) * 2014-11-12 2015-01-28 京东方科技集团股份有限公司 移位寄存器单元、栅极驱动电路及其驱动方法、显示面板
CN104537992A (zh) * 2014-12-30 2015-04-22 深圳市华星光电技术有限公司 用于液晶显示装置的goa电路
CN104715710A (zh) * 2015-04-10 2015-06-17 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、扫描驱动电路、显示装置

Also Published As

Publication number Publication date
CN105185333B (zh) 2018-05-11
CN105185333A (zh) 2015-12-23
US9799293B2 (en) 2017-10-24
US20170162150A1 (en) 2017-06-08

Similar Documents

Publication Publication Date Title
WO2017045215A1 (zh) 一种液晶显示装置及其栅极驱动电路
WO2017049688A1 (zh) 一种goa电路及其驱动方法、液晶显示器
WO2017215040A1 (zh) 栅极驱动电路及液晶显示装置
WO2016106802A1 (zh) 用于液晶显示装置的goa电路
WO2016070458A1 (zh) 液晶显示面板及其栅极驱动电路
WO2017049687A1 (zh) 一种goa电路、显示装置和goa电路的驱动方法
WO2017045216A1 (zh) 一种液晶显示装置及其栅极驱动电路
WO2018209743A1 (zh) Goa电路以及液晶显示器
WO2018018723A1 (zh) 扫描驱动电路及具有该电路的平面显示装置
WO2017054262A1 (zh) 一种goa电路及液晶显示器
WO2018192026A1 (zh) 扫描驱动电路
WO2017054260A1 (zh) 一种显示装置、tft基板及goa驱动电路
WO2016090671A1 (zh) 一种扫描驱动电路
WO2019205208A1 (zh) 一种多路复用型驱动电路以及驱动方法、显示设备
WO2017049704A1 (zh) 一种goa电路及液晶显示器
WO2018018724A1 (zh) 扫描驱动电路及具有该电路的平面显示装置
WO2020093494A1 (zh) 显示面板的驱动电路及其方法，以及显示装置
WO2017015982A1 (zh) 一种液晶显示面板及装置
WO2017045220A1 (zh) 一种goa电路及液晶显示器
WO2018120286A1 (zh) 一种驱动电路及显示面板
WO2017084146A1 (zh) 液晶显示设备及goa电路
WO2018035995A1 (zh) 扫描驱动电路
WO2016090670A1 (zh) 一种扫描驱动电路
WO2018045625A1 (zh) 平面显示装置及其扫描驱动电路
WO2017028350A1 (zh) 液晶显示装置及其goa扫描电路

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 14786071

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 15903904

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 15903904

Country of ref document: EP

Kind code of ref document: A1