WO2017031774A1 - 一种goa电路及液晶显示器 - Google Patents

一种goa电路及液晶显示器 Download PDF

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Publication number
WO2017031774A1
WO2017031774A1 PCT/CN2015/088379 CN2015088379W WO2017031774A1 WO 2017031774 A1 WO2017031774 A1 WO 2017031774A1 CN 2015088379 W CN2015088379 W CN 2015088379W WO 2017031774 A1 WO2017031774 A1 WO 2017031774A1
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WIPO (PCT)
Prior art keywords
transistor
gate
signal
control
unit
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Application number
PCT/CN2015/088379
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English (en)
French (fr)
Inventor
肖军城
赵莽
Original Assignee
深圳市华星光电技术有限公司
武汉华星光电技术有限公司
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Application filed by 深圳市华星光电技术有限公司, 武汉华星光电技术有限公司 filed Critical 深圳市华星光电技术有限公司
Priority to US14/787,299 priority Critical patent/US9818357B2/en
Publication of WO2017031774A1 publication Critical patent/WO2017031774A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Definitions

  • the present invention relates to the field of liquid crystals, and in particular to a GOA circuit and a liquid crystal display.
  • All Gate The On function refers to setting all the gate driving signals in the GOA circuit to an active level to simultaneously charge all horizontal scanning lines, thereby clearing the residual charge of each pixel in the liquid crystal display to solve the residual image when the machine is turned on and off. problem.
  • the technical problem to be solved by the present invention is to provide a GOA circuit and a liquid crystal display, which can avoid generating redundant pulse signals on the horizontal scanning line before the output of the first gate driving signal, thereby ensuring normal operation of the GOA circuit.
  • a technical solution adopted by the present invention is to provide a GOA circuit for a liquid crystal display, wherein the GOA circuit includes a plurality of cascaded GOA units, and each GOA unit is used in the first stage.
  • the corresponding horizontal scanning line in the display area is charged by the clock, the second-level clock, the first control clock, and the second control clock, and the first-stage clock and the second-stage clock are used to control the GOA unit.
  • the input of the level signal and the generation of the gate driving signal, the first control clock and the second control clock are used to control the gate driving signal to be at a first level, wherein the level signal is a start pulse signal or an adjacent GOA unit Gate drive signal;
  • the GOA unit includes a forward and reverse scanning unit, an input control unit, a pull-up maintaining unit, an output control unit, a GAS signal acting unit, and a bootstrap capacitor unit;
  • the forward and reverse scanning unit is configured to control forward driving or reverse driving of the GOA circuit, and Controlling the common signal point to maintain the second level under the control of the first control clock or the second control clock;
  • the input control unit is configured to control the input of the level transmission signal according to the first stage transmission clock to complete charging of the gate signal point
  • the pull-up maintaining unit is configured to control the gate signal point to maintain the first level during the inactive period according to the common signal point; and the output control unit is configured to control the gate driving signal corresponding to the gate signal point according to the second-level pass clock Output;
  • the GAS signal action unit is configured to control the gate drive signal to be at a second level to achieve charging of the horizontal scan line corresponding to the GOA unit; and
  • the bootstrap capacitor unit is configured to re-raise the voltage of the gate signal point
  • the front and back scanning unit includes a first transistor, a second transistor, a third transistor and a fourth transistor, the gate of the first transistor receiving the first scan control signal, and the source of the first transistor receiving the gate of the output of the next stage GOA unit Driving the signal, the gate of the second transistor receives the second scan control signal, the source of the second transistor receives the gate drive signal output by the GOA unit of the previous stage, and the drains of the first transistor and the second transistor are connected to each other and input
  • the control unit is connected, the gate of the third transistor receives the first scan control signal, the source of the third transistor receives the first control clock, the gate of the fourth transistor receives the second scan control signal, and the source of the fourth transistor receives the first
  • the second control clock, the drains of the third transistor and the fourth transistor are connected to each other and connected to the pull-up sustaining unit;
  • the input control unit includes a fifth transistor, the gate of the fifth transistor receives the first cascade signal, and the source of the fifth transistor The pole is connected to the drain
  • the gate of the ninth transistor is connected to the drains of the third transistor and the fourth transistor, the source of the ninth transistor is connected to the second constant voltage source, the drain of the ninth transistor is connected to the common signal point, and the tenth transistor is The gate is connected to the common signal point, the source of the tenth transistor is connected to the gate driving signal, the drain of the tenth transistor is connected to the first constant voltage source, and one end of the first capacitor is connected to the first constant voltage source, first The other end of the capacitor is connected to a common signal point;
  • the output control unit includes an eleventh transistor and a second capacitor, the gate of the eleventh transistor is connected to the gate signal point, and the drain and gate of the eleventh transistor are connected Signal connection, the source of the eleventh transistor receives the second-stage clock, one end of the second capacitor is connected to the gate signal point, and the other end of the second capacitor is connected to the gate drive signal;
  • the GAS signal action unit includes the thirteenth The transistor and the fourteenth transistor, the gate of the thirteenth transistor, the gate
  • the GOA circuit further includes a control module, configured to control, after the GOA circuit simultaneously charges all the horizontal scan lines, a gate drive signal other than the first one of the gate drive signals on the horizontal scan line by the start pulse signal Reset to a first level to avoid generating redundant pulse signals on the horizontal scan line before the first gate drive signal is output;
  • the control module includes a plurality of first control transistors corresponding to the plurality of GOA units in addition to the first GOA unit, and the first end and the second end of the plurality of first control transistors are connected to receive the start pulse signal, and the plurality of The third end of the first control transistor is connected to a common signal point of the corresponding GOA unit;
  • the first control transistor is a PMOS transistor, and the first end, the second end, and the third end of the first control transistor correspond to a gate, a source, and a drain of the PMOS transistor; wherein, when the start pulse signal is turned on, the pulse signal is started.
  • the common signal point of each GOA unit except the first GOA unit is controlled to be low to reset the gate drive signal on the horizontal scan line to a high level.
  • another technical solution adopted by the present invention is to provide a GOA circuit for a liquid crystal display, wherein the GOA circuit includes a plurality of cascaded GOA units, and each GOA unit is used in the first The horizontal scanning line corresponding to the display area is charged by the level transmission clock, the second stage transmission clock, the first control clock, and the second control clock, and the first stage clock and the second stage clock are used to control the GOA unit.
  • the input of the level signal and the generation of the gate driving signal, the first control clock and the second control clock are used to control the gate driving signal to be at a first level, wherein the level signal is a start pulse signal or an adjacent GOA a gate driving signal of the unit; the GOA circuit further includes a control module, wherein the control module is configured to control the first one of the gate driving signals on the horizontal scanning line by the starting pulse signal after the GOA circuit simultaneously charges all the horizontal scanning lines The gate drive signal is reset to the first level, thereby avoiding generating redundant pulse signals on the horizontal scan line before the output of the first gate drive signal
  • the GOA unit includes a forward and reverse scanning unit, an input control unit, a pull-up maintaining unit, an output control unit, a GAS signal acting unit, and a bootstrap capacitor unit; the forward and reverse scanning unit is configured to control forward driving or reverse driving of the GOA circuit.
  • the input control unit is configured to control the input of the level transmission signal according to the first stage transmission clock to complete the gate signal point Charging;
  • the pull-up maintaining unit is configured to control the gate signal point to maintain the first level during the inactive period according to the common signal point;
  • the output control unit is configured to control the gate driving corresponding to the gate signal point according to the second-level clock
  • the GAS signal action unit is used to control the gate drive signal to be at the second level to achieve charging of the horizontal scan line corresponding to the GOA unit;
  • the bootstrap capacitor unit is used to raise the voltage of the gate signal point again .
  • the control module includes a plurality of first control transistors corresponding to the plurality of GOA units in addition to the first GOA unit, and the first end and the second end of the plurality of first control transistors are connected to receive the start pulse signal.
  • a third end of the plurality of first control transistors is coupled to a common signal point of the corresponding GOA unit.
  • the first control transistor is a PMOS transistor, and the first end, the second end, and the third end of the first control transistor correspond to a gate, a source, and a drain of the PMOS transistor; wherein, when the start pulse signal is turned on, the pulse signal is started.
  • the common signal point of each GOA unit except the first GOA unit is controlled to be low to reset the gate drive signal on the horizontal scan line to a high level.
  • the first control transistor is an NMOS transistor, and the first end, the second end, and the third end of the first control transistor correspond to a gate, a source, and a drain of the NMOS transistor; wherein, when the start pulse signal is turned on, the start pulse
  • the signal control is at a high level for the common signal point of each GOA unit except for the first GOA unit to reset the gate drive signal on the horizontal scan line to a low level.
  • the control module includes a second control transistor.
  • the first end and the second end of the second control transistor are connected to receive a start pulse signal, and the third end of the second control transistor is respectively associated with each GOA unit except the first GOA unit.
  • the common signal point is connected.
  • the second control transistor is a PMOS transistor, and the first end, the second end, and the third end of the second control transistor correspond to a gate, a source, and a drain of the PMOS transistor; wherein, when the start pulse signal is turned on, the start pulse The signal control is at a low level for the common signal point of each GOA unit except for the first GOA unit to reset the gate drive signal on the horizontal scan line to a high level.
  • the second control transistor is an NMOS transistor, and the first end, the second end, and the third end of the first control transistor correspond to a gate, a source, and a drain of the NMOS transistor; wherein, when the start pulse signal is turned on, the start pulse
  • the signal control is at a high level for the common signal point of each GOA unit except for the first GOA unit to reset the gate drive signal on the horizontal scan line to a low level.
  • the front and back scanning unit includes a first transistor, a second transistor, a third transistor and a fourth transistor.
  • the gate of the first transistor receives the first scan control signal, and the source of the first transistor receives the output of the next stage GOA unit.
  • a gate driving signal, a gate of the second transistor receives the second scan control signal, a source of the second transistor receives a gate driving signal output by the GOA unit of the previous stage, and the drains of the first transistor and the second transistor are connected to each other Connected to the input control unit, the gate of the third transistor receives the first scan control signal, the source of the third transistor receives the first control clock, the gate of the fourth transistor receives the second scan control signal, and the source of the fourth transistor Receiving a second control clock, the drains of the third transistor and the fourth transistor are connected to each other and connected to the pull-up sustaining unit;
  • the input control unit includes a fifth transistor, the gate of the fifth transistor receiving the first cascade signal, the fifth transistor The source is connected to the drain
  • the other end of the first capacitor is connected to the common signal point;
  • the output control unit includes an eleventh transistor and a second capacitor, the gate of the eleventh transistor is connected to the gate signal point, and the drain of the eleventh transistor is The pole drive signal is connected, the source of the eleventh transistor receives the second stage clock, the second capacitor has one end connected to the gate signal point, and the other end of the second capacitor is connected to the gate drive signal;
  • the GAS signal action unit includes The thirteenth transistor and the fourteenth transistor, the gate of the thirteenth transistor, the gate and the drain of the fourteenth transistor receive the GAS signal, the drain of the thirteenth transistor is connected to the first constant voltage source, and the thirteenth transistor The source is connected to the common signal point, and the source of the thirteenth transistor is connected to the gate driving signal;
  • the bootstrap capacitor unit includes a bootstrap capacitor, one end of the bootstrap capacitor is connected to the gate driving signal, and the other end of the bootstrap capacitor is grounded
  • the GOA unit further includes a voltage stabilizing unit and a pull
  • a liquid crystal display including a GOA circuit, the GOA circuit including a plurality of cascaded GOA units, each GOA unit for transmitting a clock at the first stage And driving the corresponding horizontal scanning line in the display area under the driving of the second-level clock, the first control clock, and the second control clock, and the first-level clock and the second-level clock are used to control the level transmission of the GOA unit.
  • the input of the signal and the generation of the gate driving signal, the first control clock and the second control clock are used to control the gate driving signal to be at a first level, wherein the level signal is a start pulse signal or a gate of an adjacent GOA unit a pole drive signal;
  • the GOA circuit further includes a control module, wherein the control module is configured to control, in addition to the first one of the gate drive signals on the horizontal scan line, by the start pulse signal after the GOA circuit simultaneously charges all the horizontal scan lines
  • the gate drive signal is reset to a first level to avoid generating redundant pulse signals on the horizontal scan line prior to the output of the first gate drive signal.
  • the GOA unit includes a forward and reverse scanning unit, an input control unit, a pull-up maintaining unit, an output control unit, a GAS signal acting unit, and a bootstrap capacitor unit; the forward and reverse scanning unit is configured to control forward driving or reverse driving of the GOA circuit.
  • the input control unit is configured to control the input of the level transmission signal according to the first stage transmission clock to complete the gate signal point Charging;
  • the pull-up maintaining unit is configured to control the gate signal point to maintain the first level during the inactive period according to the common signal point;
  • the output control unit is configured to control the gate driving corresponding to the gate signal point according to the second-level clock
  • the GAS signal action unit is used to control the gate drive signal to be at the second level to achieve charging of the horizontal scan line corresponding to the GOA unit;
  • the bootstrap capacitor unit is used to raise the voltage of the gate signal point again .
  • the control module includes a plurality of first control transistors corresponding to the plurality of GOA units in addition to the first GOA unit, and the first end and the second end of the plurality of first control transistors are connected to receive the start pulse signal.
  • a third end of the plurality of first control transistors is coupled to a common signal point of the corresponding GOA unit.
  • the first control transistor is a PMOS transistor, and the first end, the second end, and the third end of the first control transistor correspond to a gate, a source, and a drain of the PMOS transistor; wherein, when the start pulse signal is turned on, the pulse signal is started.
  • the common signal point of each GOA unit except the first GOA unit is controlled to be low to reset the gate drive signal on the horizontal scan line to a high level.
  • the first control transistor is an NMOS transistor, and the first end, the second end, and the third end of the first control transistor correspond to a gate, a source, and a drain of the NMOS transistor; wherein, when the start pulse signal is turned on, the start pulse
  • the signal control is at a high level for the common signal point of each GOA unit except for the first GOA unit to reset the gate drive signal on the horizontal scan line to a low level.
  • the control module includes a second control transistor.
  • the first end and the second end of the second control transistor are connected to receive a start pulse signal, and the third end of the second control transistor is respectively associated with each GOA unit except the first GOA unit.
  • the common signal point is connected.
  • the second control transistor is a PMOS transistor, and the first end, the second end, and the third end of the second control transistor correspond to a gate, a source, and a drain of the PMOS transistor; wherein, when the start pulse signal is turned on, the start pulse The signal control is at a low level for the common signal point of each GOA unit except for the first GOA unit to reset the gate drive signal on the horizontal scan line to a high level.
  • the second control transistor is an NMOS transistor, and the first end, the second end, and the third end of the first control transistor correspond to a gate, a source, and a drain of the NMOS transistor; wherein, when the start pulse signal is turned on, the start pulse
  • the signal control is at a high level for the common signal point of each GOA unit except for the first GOA unit to reset the gate drive signal on the horizontal scan line to a low level.
  • the front and back scanning unit includes a first transistor, a second transistor, a third transistor and a fourth transistor.
  • the gate of the first transistor receives the first scan control signal, and the source of the first transistor receives the output of the next stage GOA unit.
  • a gate driving signal, a gate of the second transistor receives the second scan control signal, a source of the second transistor receives a gate driving signal output by the GOA unit of the previous stage, and the drains of the first transistor and the second transistor are connected to each other Connected to the input control unit, the gate of the third transistor receives the first scan control signal, the source of the third transistor receives the first control clock, the gate of the fourth transistor receives the second scan control signal, and the source of the fourth transistor Receiving a second control clock, the drains of the third transistor and the fourth transistor are connected to each other and connected to the pull-up sustaining unit;
  • the input control unit includes a fifth transistor, the gate of the fifth transistor receiving the first cascade signal, the fifth transistor The source is connected to the drain
  • the other end of the first capacitor is connected to the common signal point;
  • the output control unit includes an eleventh transistor and a second capacitor, the gate of the eleventh transistor is connected to the gate signal point, and the drain of the eleventh transistor is The pole drive signal is connected, the source of the eleventh transistor receives the second stage clock, the second capacitor has one end connected to the gate signal point, and the other end of the second capacitor is connected to the gate drive signal;
  • the GAS signal action unit includes The thirteenth transistor and the fourteenth transistor, the gate of the thirteenth transistor, the gate and the drain of the fourteenth transistor receive the GAS signal, the drain of the thirteenth transistor is connected to the first constant voltage source, and the thirteenth transistor The source is connected to the common signal point, and the source of the thirteenth transistor is connected to the gate driving signal;
  • the bootstrap capacitor unit includes a bootstrap capacitor, one end of the bootstrap capacitor is connected to the gate driving signal, and the other end of the bootstrap capacitor is grounded
  • the GOA unit further includes a voltage stabilizing unit and a pull
  • the gate driving signal on the horizontal scanning line is controlled to be reset to the first level by the start pulse signal, that is, invalid.
  • the level can avoid generating redundant pulse signals on the horizontal scan line before the output of the first gate drive signal, thereby ensuring the normal operation of the GOA circuit.
  • FIG. 1 is a schematic structural view of a GOA circuit according to a first embodiment of the present invention
  • FIG. 2 is a schematic structural diagram of a GOA circuit according to a second embodiment of the present invention.
  • FIG. 3 is a circuit schematic diagram of a GOA unit in the GOA circuit shown in FIG. 2;
  • Fig. 5 is a block diagram showing the structure of a GOA circuit according to a third embodiment of the present invention.
  • FIG. 1 is a schematic structural view of a GOA circuit according to a first embodiment of the present invention.
  • the GOA circuit 10 includes a plurality of cascaded GOA units 11 and a control module 12.
  • Each GOA unit 11 is configured to charge a corresponding horizontal scan line in the display area under the driving of the first stage transfer clock CK_A1, the second stage transfer clock CK_A2, the first control clock CK_B1, and the second control clock CK_B2.
  • the first stage clock CK_A1 and the second level clock CK_A2 are used to control the input of the level signal CON_1 of the GOA unit 11 and the generation of the gate drive signal GATE(N) (N is a natural number), and the first control clock CK_B1
  • the second control clock CK_B2 is used to control the gate driving signal GATE(N) to be at a first level, that is, an inactive level, wherein the level signal CON_1 is a start pulse signal or a gate driving signal of an adjacent GOA unit 11. .
  • the control module 12 is connected to the start pulse signal STV and each of the GOA units 11 except for the first GOA unit 11, for simultaneously charging the horizontal scanning lines in the GOA circuit 10, that is, completing All. Gate on After the function, the start pulse signal STV controls the gate drive signal Gate(N) other than the first-stage gate drive signal GATE(1) on the horizontal scan line to be reset to the first level, that is, the inactive level, thereby Avoid generating redundant pulse signals on the horizontal scan line before the output of the first gate drive signal GATE(1).
  • FIG. 2 is a schematic structural view of a GOA circuit according to a second embodiment of the present invention.
  • the second embodiment of the present invention is described by taking a GOA circuit formed by cascading odd-numbered GOA units as an example, wherein the GOA circuit is a PMOS circuit.
  • the GOA circuit 20 includes cascaded odd-numbered GOA units 21 and a control module 22.
  • the GOA circuit 20 including the cascaded odd-numbered GOA unit 21 means that the GOA circuit 20 is formed by cascading the first, third, fifth, ... 2N+1 (N is a natural number) level GOA units 21.
  • the GOA circuit 20 receives the first clock signal CK1, the second clock signal CK2, the third clock signal CK3, and the fourth clock signal CK4, wherein the first clock signal CK1, the second clock signal CK2, the third clock signal CK3, The fourth clock signal CK4 is effective in one clock cycle.
  • FIG. 3 is a circuit schematic diagram of the GOA unit in the GOA circuit shown in FIG. 2.
  • the GOA unit 21 includes a forward/reverse scan unit 100, an input control unit 200, a pull-up maintaining unit 300, an output control unit 400, a GAS signal action unit 500, and a bootstrap capacitor unit 600.
  • the first forward/reverse scan unit 100 is configured to control forward driving or reverse driving of the GOA circuit 20, and control the common signal point P(2N+1) to be maintained under the control of the first control clock CK_LB1 or the second control clock CK_LB2.
  • the second level In this embodiment, the second level is a low level.
  • the input control unit 200 is configured to control the input of the level transmission signal according to the first stage transmission clock CK_LA1 to complete charging of the gate signal point Q(2N+1) (N is a natural number).
  • the pull-up maintaining unit 300 is configured to control the gate signal point Q(2N+1) to maintain the first level during the inactive period according to the common signal point P(2N+1).
  • the first level is a high level.
  • the output control unit 400 is configured to control the output of the gate drive signal G(2N+1) corresponding to the gate signal point Q(2N+1) according to the second-stage transfer clock CK_LA2.
  • the GAS signal action unit 500 is for controlling the gate drive signal G(2N+1) to be at an active level to implement charging of the horizontal scan line corresponding to the GOA unit 21.
  • the effective level of the gate drive signal G(2N+1) is a low level.
  • the bootstrap capacitor unit 600 is used to raise the voltage of the gate signal point Q(2N+1) again.
  • the front and back scanning unit 100 includes a first transistor PT0, a second transistor PT1, a third transistor PT2, and a fourth transistor PT3, and the gate of the first transistor PT0 receives the first scan control signal, that is, the reverse scan control signal.
  • the source of the first transistor PT0 receives the gate drive signal G(2N+3) output by the next stage GOA unit 21, and the gate of the second transistor PT1 receives the second scan control signal, that is, the forward scan control signal U2D
  • the source of the second transistor PT1 receives the gate drive signal G(2N-1) outputted by the GOA unit of the previous stage, and the drains of the first transistor PT0 and the second transistor PT1 are connected to each other and connected to the input control unit 200.
  • the gate of the three transistor PT2 receives the first scan control signal, that is, the reverse scan control signal D2U, the source of the third transistor PT2 receives the first control clock CK_LB1, and the gate of the fourth transistor PT3 receives the second scan control signal.
  • the forward scan control signal U2D, the source of the fourth transistor PT3 receives the second control clock CK_LB2, and the drains of the third transistor PT2 and the fourth transistor PT3 are connected to each other and connected to the pull-up maintaining unit 300.
  • the source of the second transistor PT1 receives the start pulse signal STV.
  • the source of the first transistor PT0 receives the start pulse signal STV.
  • the input control unit 200 includes a fifth transistor PT4, the gate of the fifth transistor PT4 receives the first-stage transfer clock CK_LA1, and the source of the fifth transistor PT4 is connected to the drains of the first transistor PT0 and the second transistor PT1, and the fifth transistor The drain of PT4 is connected to the gate signal point Q(2N+1).
  • the pull-up maintaining unit 300 includes a sixth transistor PT5, a seventh transistor PT6, a ninth transistor PT8, a tenth transistor PT9, and a first capacitor C1, and a gate of the sixth transistor PT5 is connected to a common signal point P(2N+1),
  • the source of the sixth transistor PT5 is connected to the drain of the fifth transistor PT4, and the drain of the sixth transistor PT5 is connected to the first constant voltage source, that is, the positive voltage constant voltage source VGH, and the gate and the fifth of the seventh transistor PT6.
  • the drain of the transistor PT4 is connected, the source of the seventh transistor PT6 is connected to the common signal point P(2N+1), and the drain of the seventh transistor PT6 is connected to the first constant voltage source, that is, the positive voltage constant voltage source VGH.
  • the gate of the nine-transistor PT8 is connected to the drains of the third transistor PT2 and the fourth transistor PT3, and the source of the ninth transistor PT8 is connected to the second constant voltage source, that is, the negative voltage constant voltage source VGL, and the drain of the ninth transistor PT8
  • the pole is connected to the common signal point P(2N+1)
  • the gate of the tenth transistor PT9 is connected to the common signal point P(2N+1)
  • the source and gate drive signal G(2N+1) of the tenth transistor PT9 Connected, the drain of the tenth transistor PT9 is connected to the first constant voltage source, that is, the positive voltage constant voltage source VGH, and the first capacitor C
  • One end of 1 is connected to a first constant voltage source, that is, a positive voltage constant voltage source VGH, and the other end of the first capacitor C1 is connected to a common signal point (2N+1).
  • the output control unit 400 includes an eleventh transistor PT10 and a second capacitor C2.
  • the gate of the eleventh transistor PT10 is connected to the gate signal point Q(2N+1), and the drain and gate driving signals of the eleventh transistor PT10 are connected.
  • Q (2N+1) is connected, the source of the eleventh transistor PT10 receives the second-stage transfer clock CK_LA2, one end of the second capacitor C2 is connected to the gate signal point Q(2N+1), and the other end of the second capacitor C2 Connected to the gate drive signal G(2N+1);
  • the GAS signal action unit 500 includes a thirteenth transistor PT12 and a fourteenth transistor PT13.
  • the gate of the thirteenth transistor PT12, the gate and the drain of the fourteenth transistor PT13 receive the GAS signal GAS, and the drain of the thirteenth transistor PT12
  • the first constant voltage source is connected to the first constant voltage source, that is, the positive voltage constant voltage source VGH
  • the source of the thirteenth transistor PT12 is connected to the common signal point P(2N+1)
  • the source of the thirteenth transistor PT12 is connected to the gate driving signal G ( 2N+1).
  • the bootstrap capacitor unit 600 includes a bootstrap capacitor Cload, one end of the bootstrap capacitor Cload and a gate drive signal G (2N+1) connection, the other end of the bootstrap capacitor Cload is connected to the ground signal GND.
  • the GOA unit 21 further includes a voltage stabilizing unit 700 for implementing voltage regulation of the gate signal point Q(2N+1) and leakage prevention of the gate signal point Q(2N+1).
  • the voltage stabilizing unit 700 includes an eighth transistor PT7 serially connected between the source of the fifth transistor PT4 and the gate signal point Q(2N+1), and the gate of the eighth transistor PT7
  • the second constant voltage source is also connected to the negative voltage constant voltage source VGL
  • the drain of the eighth transistor PT7 is connected to the drain of the fifth transistor PT4, and the source and gate signal point Q (2N+1) of the eighth transistor PT7 connection.
  • the GOA unit 21 further includes a pull-up assisting unit 800 for preventing leakage of the fifth transistor PT4 and the sixth transistor PT5 during charging of the gate signal point Q(2N+1)
  • the pull-up auxiliary unit 800 includes a twelfth transistor PT11, the gate of the twelfth transistor PT11 is connected to the drains of the first transistor PT0 and the second transistor PT1, and the source and the common signal of the twelfth transistor PT11.
  • the point P (2N+1) is connected, and the drain of the twelve-transistor PT11 is connected to the first constant voltage source, that is, the positive voltage constant voltage source VGH.
  • the first stage clock CK_LA1 is the first clock signal CK1
  • the second stage clock CK_LA2 For the third clock signal CK3, the first control clock CK_LB1 is the second clock signal CK2, and the second control clock CK_LB2 is the fourth clock signal CK4.
  • the second stage clock CK_LA2 is the third clock signal CK3
  • the first stage clock CK_LA1 is the first clock signal CK1.
  • the second control clock CK_LB2 is the fourth clock signal CK4, and the first control clock CK_LB2 is the second clock signal CK2.
  • the GOA circuit is an NMOS circuit
  • all the transistors are NMOS transistors
  • the first scan control signal corresponds to the forward scan control signal U2D
  • the second scan control signal corresponds to the inverted scan control signal D2U
  • a constant voltage source corresponds to a negative pressure constant voltage source VGL
  • a second constant voltage source corresponds to a positive pressure constant voltage source VGH.
  • the control module 22 includes a first control transistor T1 corresponding to the remaining GOA units 21 in addition to the first stage GOA unit 21, and the first end and the second end of the first control transistor T1 are connected. Receiving the start pulse signal STV, the third end of the first control transistor T1 is connected to the common signal point P(2N+1) of the corresponding GOA unit 21.
  • the first control transistor T1 is a PMOS transistor, and the first end, the second end, and the third end of the first control transistor T1 correspond to the gate, the source, and the drain of the PMOS transistor; wherein, when the start pulse When the signal STV is turned on, the start pulse signal STV controls the common signal point P(2N+1) of each GOA unit except the first GOA unit to be at a low level to make the gate drive signal G (2N) on the horizontal scan line. +1) Reset to high level.
  • the first control transistor T1 when the GOA circuit is an NMOS circuit, the first control transistor T1 may also be an NMOS transistor, and the first end, the second end, and the third end of the first control transistor T1 correspond to the gate and source of the NMOS transistor. a pole and a drain; wherein, when the start pulse signal STV is turned on, the start pulse signal STV controls the common signal point P(2N+1) of each GOA unit except the first GOA unit to be at a high level for horizontal scanning The gate drive signal G(2N+1) on the line is reset to a low level.
  • Fig. 4 is a timing chart showing the operation of the GOA circuit of the second embodiment of the present invention.
  • the second embodiment of the present invention is described by taking a GOA circuit formed by cascading odd-numbered GOA units as an example, wherein the GOA circuit is a PMOS circuit.
  • the GOA circuit 20 implements All.
  • the Gate On function outputs a low level signal to the gate drive signal G(2N+1) corresponding to each odd-level horizontal scanning line.
  • the gate drive signal G(2N+1) corresponding to each odd-level horizontal scan line does not immediately become a high level, but will remain Cload. Holding a low level signal.
  • the GOA circuit As the forward driving as an example, if the gate driving signal corresponding to the odd-level horizontal scanning line cannot be discharged to the high level before the third clock signal CK3 is valid, the odd-numbered stages except the first-level horizontal scanning line A redundant pulse signal is generated on the horizontal scan line. Specifically, the first-level horizontal scan line is driven by the first-stage GOA unit. Since the level-transmitted signal of the first-stage GOA unit is the start-up pulse signal STV, the first-stage GOA unit is normally driven, and no redundant pulse signal is generated. .
  • the third-level horizontal scan line is driven by the third-stage GOA unit, and the level-transmitted signal of the third-stage GOA unit is the gate drive signal G(1) of the first-stage GOA unit, when the first clock signal CK1 is low. Since the gate drive signal G(1) holds Cload Holding a low level signal, the low level signal of the gate drive signal G(1) is transmitted to the gate signal point Q(3) of the third stage GOA unit, so that the third stage GOA unit 21 precedes the first The stage GOA unit 21 operates, and causes the gate drive signal G(3) outputted by the third stage GOA unit 21 to generate a redundant pulse, which will continue to affect the gate drive signal of the next stage GOA unit 21. . For the same reason, when the first clock signal CK1 is active, the gate drive signals of the seventh stage, the tenth stage, ... the 4th N+3 stage GOA unit generate redundant pulses.
  • the GOA circuit 20 implements All Gate. After the On function, before the first clock signal CK1 is valid, the start pulse signal STV is set to a low level and is sequentially valid with the first clock signal CK1, the second clock signal CK2, the third clock signal CK3, and the fourth clock signal CK4. After that, the start pulse signal STV changes from a low level to a high level.
  • the start pulse signal STV is at a low level
  • the first control transistor T1 since the first control transistor T1 is turned on, the third stage, the fifth stage, ..., the common signal point P(2N+1) of the GON unit 21 of the 2N+1th stage
  • the high level is changed from the high level to the low level so that the gate drive signal G(2N+1) becomes a high level signal before the third clock signal CK3 is asserted, thereby avoiding the generation of redundant pulse signals.
  • the driving sequence of the first clock signal CK1, the second clock signal CK2, the third clock signal CK3, and the fourth clock signal CK4, which are normally maintained, is driven to the GOA circuit 20 to achieve normal charging of the horizontal scanning line.
  • Fig. 5 is a block diagram showing the structure of a GOA circuit according to a third embodiment of the present invention.
  • a third embodiment of the present invention is described by taking a GOA circuit formed by cascading odd-numbered GOA units as an example, wherein the GOA circuit is a PMOS circuit.
  • the difference between the third embodiment shown in FIG. 5 and the second embodiment shown in FIG. 2 is that:
  • the control module 23 includes a second control transistor T2.
  • the first end and the second end of the second control transistor T2 are connected to receive the start pulse signal STV, and the third end of the second control transistor T3 is respectively divided.
  • the common signal points P(2N+1) of the plurality of GOA units 21 outside one GOA unit 21 are connected.
  • the second control transistor T2 is a PMOS transistor, and the first end, the second end, and the third end of the second control transistor T2 correspond to a gate, a source, and a drain of the PMOS transistor; wherein, when the start pulse When the signal STV is turned on, the start pulse signal controls the common signal point P(2N+1) of each GOA unit 21 except the first GOA unit to be at a low level to make the gate drive signal G (2N) on the horizontal scan line. +1) Reset to high level.
  • the second control transistor T2 may also be an NMOS transistor, and the first end, the second end, and the third end of the second control transistor T2 correspond to the gate and source of the NMOS transistor. a pole and a drain; wherein, when the start pulse signal STV is turned on, the start pulse signal controls the common signal point P(2N+1) of each GOA unit 21 to be at a high level to cause the gate drive signal G on the horizontal scan line (2N+1) Reset to low level.
  • the operation timing of the GOA circuit of the third embodiment shown in FIG. 5 is the same as the operation timing of the GOA circuit of the second embodiment shown in FIG. 2. For the sake of simplicity, details are not described herein again.
  • the liquid crystal display includes a GOA circuit in which odd-numbered GOA units are cascaded and a GOA circuit in which even-numbered GOA units are cascaded, and GOA circuits and odd-numbered stages formed by cascading even-numbered GOA units.
  • the GOA circuit formed by cascading the GOA units is similarly processed, and for the sake of simplicity, it will not be described in detail herein.
  • the present invention further provides a liquid crystal display comprising the above GOA circuit.
  • the gate driving signal on the horizontal scanning line is controlled to be reset to the first level by the start pulse signal, that is, invalid.
  • the level can avoid generating redundant pulse signals on the horizontal scan line before the output of the first gate drive signal, thereby ensuring the normal operation of the GOA circuit.

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Abstract

公开了一种GOA电路及液晶显示器。该GOA电路（10）包括多个级联的GOA单元（11）和控制模块（12），每一GOA单元（11）用于在第一级传时钟（CK-A1）、第二级传时钟（CK-A2）、第一控制时钟（CK-B1）、第二控制时钟（CK-B2）的驱动下对显示区域中对应的水平扫描线进行充电，控制模块（12）用于在GOA电路（10）对所有水平扫描线同时充电后，通过启动脉冲信号（STV）控制水平扫描线上的栅极驱动信号（GATE（1），GATE（M），GATE（N））复位至第一电平也即无效电平，能够避免在第一个栅极驱动信号（GATE（1））输出之前在水平扫描线上产生冗余的脉冲信号，从而保证GOA电路（10）正常工作。

Description

一种GOA电路及液晶显示器
【技术领域】
本发明涉及液晶领域，特别是涉及一种GOA电路及液晶显示器。
【背景技术】
现有的GOA（Gate driver on array）电路在搭配All Gate On功能时，由于自举电容的存在，GOA电路中的栅极驱动信号在All Gate On功能完成后，不会马上变为无效电平，从而存在产生冗余的栅极驱动信号、进而导致电路出现失效的可能。
其中，All Gate On功能是指将GOA电路中的所有栅极驱动信号设置为有效电平以同时对所有水平扫描线进行充电，从而清除液晶显示器中每个像素点残存的电荷以解决开关机时出现残影的问题。
【发明内容】
本发明主要解决的技术问题是提供一种GOA电路及液晶显示器，能够避免在第一个栅极驱动信号输出之前在水平扫描线上产生冗余的脉冲信号，从而保证GOA电路的正常工作。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种GOA电路，用于液晶显示器，其中，该GOA电路包括级联的多个GOA单元，每一GOA单元用于在第一级传时钟、第二级传时钟、第一控制时钟、第二控制时钟的驱动下对显示区域中对应的水平扫描线进行充电，第一级传时钟、第二级传时钟用于控制GOA单元的级传信号的输入以及栅极驱动信号的产生，第一控制时钟、第二控制时钟用于控制栅极驱动信号处于第一电平，其中，级传信号为启动脉冲信号或相邻的GOA单元的栅极驱动信号；
GOA单元包括正反扫描单元、输入控制单元、上拉维持单元、输出控制单元、GAS信号作用单元和自举电容单元；正反扫描单元用于控制GOA电路的正向驱动或反向驱动，并在第一控制时钟或第二控制时钟的控制下，控制公共信号点保持第二电平；输入控制单元用于根据第一级传时钟控制级传信号的输入以完成对栅极信号点的充电；上拉维持单元用于根据公共信号点控制栅极信号点在非作用期间保持第一电平；输出控制单元用于根据第二级传时钟控制与栅极信号点对应的栅极驱动信号的输出；GAS信号作用单元用于控制栅极驱动信号处于第二电平，以实现与GOA单元对应的水平扫描线的充电；自举电容单元用于对栅极信号点的电压进行再次抬升；
正反扫描单元包括第一晶体管、第二晶体管、第三晶体管和第四晶体管，第一晶体管的栅极接收第一扫描控制信号，第一晶体管的源极接收下一级GOA单元输出的栅极驱动信号，第二晶体管的栅极接收第二扫描控制信号，第二晶体管的源极接收上一级GOA单元输出的栅极驱动信号，第一晶体管和第二晶体管的漏极相互连接后与输入控制单元连接，第三晶体管的栅极接收第一扫描控制信号，第三晶体管的源极接收第一控制时钟，第四晶体管的栅极接收第二扫描控制信号，第四晶体管的源极接收第二控制时钟，第三晶体管和第四晶体管的漏极相互连接后与上拉维持单元连接；输入控制单元包括第五晶体管，第五晶体管的栅极接收第一级连信号，第五晶体管的源极与第一晶体管、第二晶体管的漏极连接，第五晶体管的漏极与栅极信号点连接；上拉维持单元包括第六晶体管、第七晶体管、第九晶体管、第十晶体管和第一电容，第六晶体管的栅极与公共信号点连接，第六晶体管的源极与第五晶体管的漏极连接，第六晶体管的漏极与第一恒压源连接，第七晶体管的栅极与五晶体管的漏极连接，第七晶体管的源极与公共信号点连接，第七晶体管的漏极与第一恒压源连接，第九晶体管的栅极与第三晶体管、第四晶体管的漏极连接，第九晶体管的源极与第二恒压源连接，第九晶体管的漏极与公共信号点连接，第十晶体管的栅极与公共信号点连接，第十晶体管的源极与栅极驱动信号连接，第十晶体管的漏极与第一恒压源连接，第一电容的一端与第一恒压源连接，第一电容的另一端与公共信号点连接；输出控制单元包括第十一晶体管和第二电容，第十一晶体管的栅极与栅极信号点连接，第十一晶体管的漏极与栅极驱动信号连接，第十一晶体管的源极接收第二级传时钟，第二电容的一端与栅极信号点连接，第二电容的另一端与栅极驱动信号连接；GAS信号作用单元包括第十三晶体管和第十四晶体管，第十三晶体管的栅极、第十四晶体管的栅极和漏极接收GAS信号，第十三晶体管的漏极连接第一恒压源，第十三晶体管的源极连接公共信号点，第十三晶体管的源极连接栅极驱动信号；自举电容单元包括自举电容，自举电容的一端与栅极驱动信号连接，自举电容的另一端与地信号连接；GOA单元进一步包括稳压单元和上拉辅助单元，稳压单元包括第八晶体管，第八晶体管串接于第五晶体管的源极与栅极信号点之间，第八晶体管的栅极与第二恒压源连接，第八晶体管的漏极与第五晶体管的漏极连接，第八晶体管的源极与栅极信号点连接；上拉辅助单元包括第十二晶体管，第十二晶体管的栅极与第一晶体管、第二晶体管的漏极连接，第十二晶体管的源极与公共信号点连接，十二晶体管的漏极与正压恒压源连接；
GOA电路进一步包括控制模块，控制模块用于在GOA电路对所有水平扫描线同时充电后，通过启动脉冲信号控制水平扫描线上的除第一个所述栅极驱动信号之外的栅极驱动信号复位至第一电平，从而避免在第一个栅极驱动信号输出之前在水平扫描线上产生冗余的脉冲信号；
控制模块包括除第一个GOA单元外，与多个GOA单元一一对应的多个第一控制晶体管，多个第一控制晶体管的第一端、第二端连接后接收启动脉冲信号，多个第一控制晶体管的第三端与对应的GOA单元的公共信号点连接；
其中，第一控制晶体管为PMOS管，第一控制晶体管的第一端、第二端、第三端对应PMOS管的栅极、源极和漏极；其中，当启动脉冲信号开启时启动脉冲信号控制除第一个GOA单元外每一GOA单元的公共信号点处于低电平以使水平扫描线上的栅极驱动信号复位至高电平。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种GOA电路，用于液晶显示器，其中，该GOA电路包括级联的多个GOA单元，每一GOA单元用于在第一级传时钟、第二级传时钟、第一控制时钟、第二控制时钟的驱动下对显示区域中对应的水平扫描线进行充电，第一级传时钟、第二级传时钟用于控制GOA单元的级传信号的输入以及栅极驱动信号的产生，第一控制时钟、第二控制时钟用于控制栅极驱动信号处于第一电平，其中，级传信号为启动脉冲信号或相邻的GOA单元的栅极驱动信号；GOA电路进一步包括控制模块，控制模块用于在GOA电路对所有水平扫描线同时充电后，通过启动脉冲信号控制水平扫描线上的除第一个所述栅极驱动信号之外的栅极驱动信号复位至第一电平，从而避免在第一个栅极驱动信号输出之前在水平扫描线上产生冗余的脉冲信号。
其中，GOA单元包括正反扫描单元、输入控制单元、上拉维持单元、输出控制单元、GAS信号作用单元和自举电容单元；正反扫描单元用于控制GOA电路的正向驱动或反向驱动，并在第一控制时钟或第二控制时钟的控制下，控制公共信号点保持第二电平；输入控制单元用于根据第一级传时钟控制级传信号的输入以完成对栅极信号点的充电；上拉维持单元用于根据公共信号点控制栅极信号点在非作用期间保持第一电平；输出控制单元用于根据第二级传时钟控制与栅极信号点对应的栅极驱动信号的输出；GAS信号作用单元用于控制栅极驱动信号处于第二电平，以实现与GOA单元对应的水平扫描线的充电；自举电容单元用于对栅极信号点的电压进行再次抬升。
其中，控制模块包括除第一个GOA单元外，与多个GOA单元一一对应的多个第一控制晶体管，多个第一控制晶体管的第一端、第二端连接后接收启动脉冲信号，多个第一控制晶体管的第三端与对应的GOA单元的公共信号点连接。
其中，第一控制晶体管为PMOS管，第一控制晶体管的第一端、第二端、第三端对应PMOS管的栅极、源极和漏极；其中，当启动脉冲信号开启时启动脉冲信号控制除第一个GOA单元外每一GOA单元的公共信号点处于低电平以使水平扫描线上的栅极驱动信号复位至高电平。
其中，第一控制晶体管为NMOS管，第一控制晶体管的第一端、第二端、第三端对应NMOS管的栅极、源极和漏极；其中，当启动脉冲信号开启时，启动脉冲信号控制除第一个GOA单元外每一GOA单元的公共信号点处于高电平以使水平扫描线上的栅极驱动信号复位至低电平。
其中，控制模块包括第二控制晶体管，第二控制晶体管的第一端、第二端连接后接收启动脉冲信号，第二控制晶体管的第三端分别与除第一个GOA单元外每一GOA单元的公共信号点连接。
其中，第二控制晶体管为PMOS管，第二控制晶体管的第一端、第二端、第三端对应PMOS管的栅极、源极和漏极；其中，当启动脉冲信号开启时，启动脉冲信号控制除第一个GOA单元外每一GOA单元的公共信号点处于低电平以使水平扫描线上的栅极驱动信号复位至高电平。
其中，第二控制晶体管为NMOS管，第一控制晶体管的第一端、第二端、第三端对应NMOS管的栅极、源极和漏极；其中，当启动脉冲信号开启时，启动脉冲信号控制除第一个GOA单元外每一GOA单元的公共信号点处于高电平以使水平扫描线上的栅极驱动信号复位至低电平。
其中，正反扫描单元包括第一晶体管、第二晶体管、第三晶体管和第四晶体管，第一晶体管的栅极接收第一扫描控制信号，第一晶体管的源极接收下一级GOA单元输出的栅极驱动信号，第二晶体管的栅极接收第二扫描控制信号，第二晶体管的源极接收上一级GOA单元输出的栅极驱动信号，第一晶体管和第二晶体管的漏极相互连接后与输入控制单元连接，第三晶体管的栅极接收第一扫描控制信号，第三晶体管的源极接收第一控制时钟，第四晶体管的栅极接收第二扫描控制信号，第四晶体管的源极接收第二控制时钟，第三晶体管和第四晶体管的漏极相互连接后与上拉维持单元连接；输入控制单元包括第五晶体管，第五晶体管的栅极接收第一级连信号，第五晶体管的源极与第一晶体管、第二晶体管的漏极连接，第五晶体管的漏极与栅极信号点连接；上拉维持单元包括第六晶体管、第七晶体管、第九晶体管、第十晶体管和第一电容，第六晶体管的栅极与公共信号点连接，第六晶体管的源极与第五晶体管的漏极连接，第六晶体管的漏极与第一恒压源连接，第七晶体管的栅极与五晶体管的漏极连接，第七晶体管的源极与公共信号点连接，第七晶体管的漏极与第一恒压源连接，第九晶体管的栅极与第三晶体管、第四晶体管的漏极连接，第九晶体管的源极与第二恒压源连接，第九晶体管的漏极与公共信号点连接，第十晶体管的栅极与公共信号点连接，第十晶体管的源极与栅极驱动信号连接，第十晶体管的漏极与第一恒压源连接，第一电容的一端与第一恒压源连接，第一电容的另一端与公共信号点连接；输出控制单元包括第十一晶体管和第二电容，第十一晶体管的栅极与栅极信号点连接，第十一晶体管的漏极与栅极驱动信号连接，第十一晶体管的源极接收第二级传时钟，第二电容的一端与栅极信号点连接，第二电容的另一端与栅极驱动信号连接；GAS信号作用单元包括第十三晶体管和第十四晶体管，第十三晶体管的栅极、第十四晶体管的栅极和漏极接收GAS信号，第十三晶体管的漏极连接第一恒压源，第十三晶体管的源极连接公共信号点，第十三晶体管的源极连接栅极驱动信号；自举电容单元包括自举电容，自举电容的一端与栅极驱动信号连接，自举电容的另一端与地信号连接；GOA单元进一步包括稳压单元和上拉辅助单元，稳压单元包括第八晶体管，第八晶体管串接于第五晶体管的源极与栅极信号点之间，第八晶体管的栅极与第二恒压源连接，第八晶体管的漏极与第五晶体管的漏极连接，第八晶体管的源极与栅极信号点连接；上拉辅助单元包括第十二晶体管，第十二晶体管的栅极与第一晶体管、第二晶体管的漏极连接，第十二晶体管的源极与公共信号点连接，十二晶体管的漏极与正压恒压源连接。
为解决上述技术问题，本发明采用的又一个技术方案是：提供一种液晶显示器，包括GOA电路，该GOA电路包括级联的多个GOA单元，每一GOA单元用于在第一级传时钟、第二级传时钟、第一控制时钟、第二控制时钟的驱动下对显示区域中对应的水平扫描线进行充电，第一级传时钟、第二级传时钟用于控制GOA单元的级传信号的输入以及栅极驱动信号的产生，第一控制时钟、第二控制时钟用于控制栅极驱动信号处于第一电平，其中，级传信号为启动脉冲信号或相邻的GOA单元的栅极驱动信号；GOA电路进一步包括控制模块，控制模块用于在GOA电路对所有水平扫描线同时充电后，通过启动脉冲信号控制水平扫描线上的除第一个所述栅极驱动信号之外的栅极驱动信号复位至第一电平，从而避免在第一个栅极驱动信号输出之前在水平扫描线上产生冗余的脉冲信号。
其中，GOA单元包括正反扫描单元、输入控制单元、上拉维持单元、输出控制单元、GAS信号作用单元和自举电容单元；正反扫描单元用于控制GOA电路的正向驱动或反向驱动，并在第一控制时钟或第二控制时钟的控制下，控制公共信号点保持第二电平；输入控制单元用于根据第一级传时钟控制级传信号的输入以完成对栅极信号点的充电；上拉维持单元用于根据公共信号点控制栅极信号点在非作用期间保持第一电平；输出控制单元用于根据第二级传时钟控制与栅极信号点对应的栅极驱动信号的输出；GAS信号作用单元用于控制栅极驱动信号处于第二电平，以实现与GOA单元对应的水平扫描线的充电；自举电容单元用于对栅极信号点的电压进行再次抬升。
其中，控制模块包括除第一个GOA单元外，与多个GOA单元一一对应的多个第一控制晶体管，多个第一控制晶体管的第一端、第二端连接后接收启动脉冲信号，多个第一控制晶体管的第三端与对应的GOA单元的公共信号点连接。
其中，第一控制晶体管为PMOS管，第一控制晶体管的第一端、第二端、第三端对应PMOS管的栅极、源极和漏极；其中，当启动脉冲信号开启时启动脉冲信号控制除第一个GOA单元外每一GOA单元的公共信号点处于低电平以使水平扫描线上的栅极驱动信号复位至高电平。
其中，第一控制晶体管为NMOS管，第一控制晶体管的第一端、第二端、第三端对应NMOS管的栅极、源极和漏极；其中，当启动脉冲信号开启时，启动脉冲信号控制除第一个GOA单元外每一GOA单元的公共信号点处于高电平以使水平扫描线上的栅极驱动信号复位至低电平。
其中，控制模块包括第二控制晶体管，第二控制晶体管的第一端、第二端连接后接收启动脉冲信号，第二控制晶体管的第三端分别与除第一个GOA单元外每一GOA单元的公共信号点连接。
其中，第二控制晶体管为PMOS管，第二控制晶体管的第一端、第二端、第三端对应PMOS管的栅极、源极和漏极；其中，当启动脉冲信号开启时，启动脉冲信号控制除第一个GOA单元外每一GOA单元的公共信号点处于低电平以使水平扫描线上的栅极驱动信号复位至高电平。
其中，第二控制晶体管为NMOS管，第一控制晶体管的第一端、第二端、第三端对应NMOS管的栅极、源极和漏极；其中，当启动脉冲信号开启时，启动脉冲信号控制除第一个GOA单元外每一GOA单元的公共信号点处于高电平以使水平扫描线上的栅极驱动信号复位至低电平。
其中，正反扫描单元包括第一晶体管、第二晶体管、第三晶体管和第四晶体管，第一晶体管的栅极接收第一扫描控制信号，第一晶体管的源极接收下一级GOA单元输出的栅极驱动信号，第二晶体管的栅极接收第二扫描控制信号，第二晶体管的源极接收上一级GOA单元输出的栅极驱动信号，第一晶体管和第二晶体管的漏极相互连接后与输入控制单元连接，第三晶体管的栅极接收第一扫描控制信号，第三晶体管的源极接收第一控制时钟，第四晶体管的栅极接收第二扫描控制信号，第四晶体管的源极接收第二控制时钟，第三晶体管和第四晶体管的漏极相互连接后与上拉维持单元连接；输入控制单元包括第五晶体管，第五晶体管的栅极接收第一级连信号，第五晶体管的源极与第一晶体管、第二晶体管的漏极连接，第五晶体管的漏极与栅极信号点连接；上拉维持单元包括第六晶体管、第七晶体管、第九晶体管、第十晶体管和第一电容，第六晶体管的栅极与公共信号点连接，第六晶体管的源极与第五晶体管的漏极连接，第六晶体管的漏极与第一恒压源连接，第七晶体管的栅极与五晶体管的漏极连接，第七晶体管的源极与公共信号点连接，第七晶体管的漏极与第一恒压源连接，第九晶体管的栅极与第三晶体管、第四晶体管的漏极连接，第九晶体管的源极与第二恒压源连接，第九晶体管的漏极与公共信号点连接，第十晶体管的栅极与公共信号点连接，第十晶体管的源极与栅极驱动信号连接，第十晶体管的漏极与第一恒压源连接，第一电容的一端与第一恒压源连接，第一电容的另一端与公共信号点连接；输出控制单元包括第十一晶体管和第二电容，第十一晶体管的栅极与栅极信号点连接，第十一晶体管的漏极与栅极驱动信号连接，第十一晶体管的源极接收第二级传时钟，第二电容的一端与栅极信号点连接，第二电容的另一端与栅极驱动信号连接；GAS信号作用单元包括第十三晶体管和第十四晶体管，第十三晶体管的栅极、第十四晶体管的栅极和漏极接收GAS信号，第十三晶体管的漏极连接第一恒压源，第十三晶体管的源极连接公共信号点，第十三晶体管的源极连接栅极驱动信号；自举电容单元包括自举电容，自举电容的一端与栅极驱动信号连接，自举电容的另一端与地信号连接；GOA单元进一步包括稳压单元和上拉辅助单元，稳压单元包括第八晶体管，第八晶体管串接于第五晶体管的源极与栅极信号点之间，第八晶体管的栅极与第二恒压源连接，第八晶体管的漏极与第五晶体管的漏极连接，第八晶体管的源极与栅极信号点连接；上拉辅助单元包括第十二晶体管，第十二晶体管的栅极与第一晶体管、第二晶体管的漏极连接，第十二晶体管的源极与公共信号点连接，十二晶体管的漏极与正压恒压源连接。
本发明的有益效果是：本发明的GOA电路及液晶显示器通过GOA电路对所有水平扫描线同时充电后，通过启动脉冲信号控制水平扫描线上的栅极驱动信号复位至第一电平也即无效电平，从而能够避免在第一个栅极驱动信号输出之前在水平扫描线上产生冗余的脉冲信号，进而保证了GOA电路的正常工作。
【附图说明】
图1是本发明第一实施例的GOA电路的结构示意图；
图2是本发明第二实施例的GOA电路的结构示意图；
图3是图2所示GOA电路中GOA单元的电路原理图；
图4是本发明第二实施例的GOA电路的工作时序图；
图5是本发明第三实施例的GOA电路的结构示意图。
【具体实施方式】
在说明书及权利要求书当中使用了某些词汇来指称特定的组件，所属领域中的技术人员应可理解，制造商可能会用不同的名词来称呼同样的组件。本说明书及权利要求书并不以名称的差异来作为区分组件的方式，而是以组件在功能上的差异来作为区分的基准。下面结合附图和实施例对本发明进行详细说明。
图1是本发明第一实施例的GOA电路的结构示意图。如图1所示，GOA电路10包括级联的多个GOA单元11和控制模块12。
每一GOA单元11用于在第一级传时钟CK_A1、第二级传时钟CK_A2、第一控制时钟CK_B1、第二控制时钟CK_B2的驱动下对显示区域中对应的水平扫描线进行充电。其中，第一级传时钟CK_A1、第二级传时钟CK_A2用于控制GOA单元11的级传信号CON_1的输入以及栅极驱动信号GATE（N）（N为自然数）的产生，第一控制时钟CK_B1、第二控制时钟CK_B2用于控制栅极驱动信号GATE（N）处于第一电平也即无效电平，其中，级传信号CON_1为启动脉冲信号或相邻的GOA单元11的栅极驱动信号。
控制模块12分别与启动脉冲信号STV和除第一个GOA单元11外的每个GOA单元11连接，用于在GOA电路10对水平扫描线同时充电也即完成All Gate on 功能后，通过启动脉冲信号STV控制水平扫描线上的除第一级栅极驱动信号GATE（1）外的其它栅极驱动信号Gate（N）复位至第一电平也即无效电平，从而避免在第一个栅极驱动信号GATE（1）输出之前在水平扫描线上产生冗余的脉冲信号。
图2是本发明第二实施例的GOA电路的结构示意图。本发明第二实施例以奇数级GOA单元级联形成的GOA电路为例来说明，其中GOA电路为PMOS电路。如图2所示，GOA电路20包括级联的奇数级GOA单元21和控制模块22。
其中，GOA电路20包括级联的奇数级GOA单元21是指GOA电路20由第一级、第三级、第五级、…第2N+1（N为自然数）级GOA单元21级联形成。
其中，GOA电路20接收第一时钟信号CK1、第二时钟信号CK2、第三时钟信号CK3、第四时钟信号CK4，其中，第一时钟信号CK1、第二时钟信号CK2、第三时钟信号CK3、第四时钟信号CK4在一个时钟周期依次分时有效。
请一并参考图3，图3是图2所示GOA电路中GOA单元的电路原理图。如图3所示，GOA单元21包括正反扫描单元100、输入控制单元200、上拉维持单元300、输出控制单元400、GAS信号作用单元500和自举电容单元600。
第一正反扫描单元100用于控制GOA电路20的正向驱动或反向驱动，并在第一控制时钟CK_LB1或第二控制时钟CK_LB2的控制下，控制公共信号点P（2N+1）保持第二电平。在本实施例中，第二电平为低电平。
输入控制单元200用于根据第一级传时钟CK_LA1控制级传信号的输入以完成对栅极信号点Q（2N+1）（N为自然数）的充电。
上拉维持单元300用于根据公共信号点P（2N+1）控制栅极信号点Q（2N+1）在非作用期间保持第一电平。在本实施例中，第一电平为高电平。
输出控制单元400用于根据第二级传时钟CK_LA2控制与栅极信号点Q（2N+1）对应的栅极驱动信号G（2N+1）的输出。
GAS信号作用单元500用于控制栅极驱动信号G（2N+1）处于有效电平，以实现GOA单元21对应的水平扫描线的充电。在本实施例中，栅极驱动信号G（2N+1）的有效电平为低电平。
自举电容单元600用于对栅极信号点Q（2N+1）的电压进行再次抬升。
具体来说，正反扫描单元100包括第一晶体管PT0、第二晶体管PT1、第三晶体管PT2和第四晶体管PT3，第一晶体管PT0的栅极接收第一扫描控制信号也即反向扫描控制信号D2U，第一晶体管PT0的源极接收下一级GOA单元21输出的栅极驱动信号G（2N+3），第二晶体管PT1的栅极接收第二扫描控制信号也即正向扫描控制信号U2D，第二晶体管PT1的源极接收上一级GOA单元输出的栅极驱动信号G（2N-1），第一晶体管PT0和第二晶体管PT1的漏极相互连接后与输入控制单元200连接，第三晶体管PT2的栅极接收第一扫描控制信号也即反向扫描控制信号D2U，第三晶体管PT2的源极接收第一控制时钟CK_LB1，第四晶体管PT3的栅极接收第二扫描控制信号也即正向扫描控制信号U2D，第四晶体管PT3的源极接收第二控制时钟CK_LB2，第三晶体管PT2和第四晶体管PT3的漏极相互连接后与上拉维持单元300连接。
其中，在第一级GOA单元中，第二晶体管PT1的源极接收启动脉冲信号STV。在最后一级GOA单元中，第一晶体管PT0的源极接收启动脉冲信号STV。
输入控制单元200包括第五晶体管PT4，第五晶体管PT4的栅极接收第一级传时钟CK_LA1，第五晶体管PT4的源极与第一晶体管PT0、第二晶体管PT1的漏极连接，第五晶体管PT4的漏极与栅极信号点Q（2N+1）连接。
上拉维持单元300包括第六晶体管PT5、第七晶体管PT6、第九晶体管PT8、第十晶体管PT9和第一电容C1，第六晶体管PT5的栅极与公共信号点P（2N+1）连接，第六晶体管PT5的源极与第五晶体管PT4的漏极连接，第六晶体管PT5的漏极与第一恒压源也即正压恒压源VGH连接，第七晶体管PT6的栅极与第五晶体管PT4的漏极连接，第七晶体管PT6的源极与公共信号点P（2N+1）连接，第七晶体管PT6的漏极与第一恒压源也即正压恒压源VGH连接，第九晶体管PT8的栅极与第三晶体管PT2、第四晶体管PT3的漏极连接，第九晶体管PT8的源极与第二恒压源也即负压恒压源VGL连接，第九晶体管PT8的漏极与公共信号点P（2N+1）连接，第十晶体管PT9的栅极与公共信号点P（2N+1）连接，第十晶体管PT9的源极与栅极驱动信号G（2N+1）连接，第十晶体管PT9的漏极与第一恒压源也即正压恒压源VGH连接，第一电容C1的一端与第一恒压源也即正压恒压源VGH连接，第一电容C1的另一端与公共信号点（2N+1）连接。
输出控制单元400包括第十一晶体管PT10和第二电容C2，第十一晶体管PT10的栅极与栅极信号点Q（2N+1）连接，第十一晶体管PT10的漏极与栅极驱动信号Q（2N+1）连接，第十一晶体管PT10的源极接收第二级传时钟CK_LA2，第二电容C2的一端与栅极信号点Q（2N+1）连接，第二电容C2的另一端与栅极驱动信号G（2N+1）连接；
GAS信号作用单元500包括第十三晶体管PT12和第十四晶体管PT13，第十三晶体管PT12的栅极、第十四晶体管PT13的栅极和漏极接收GAS信号GAS，第十三晶体管PT12的漏极连接第一恒压源也即正压恒压源VGH，第十三晶体管PT12的源极连接公共信号点P（2N+1），第十三晶体管PT12的源极连接栅极驱动信号G（2N+1）。
自举电容单元600包括自举电容Cload，自举电容Cload的一端与栅极驱动信号G (2N+1)连接，自举电容Cload的另一端与地信号GND连接。
优选地，GOA单元21进一步包括稳压单元700，稳压单元700用于实现栅极信号点Q（2N+1）的稳压以及栅极信号点Q（2N+1）的漏电防治。具体来说，稳压单元700包括第八晶体管PT7，第八晶体管PT7串接于第五晶体管PT4的源极与栅极信号点Q(2N+1)之间，第八晶体管PT7的栅极与第二恒压源也即负压恒压源VGL连接，第八晶体管PT7的漏极与第五晶体管PT4的漏极连接，第八晶体管PT7的源极与栅极信号点Q（2N+1）连接。
优选地，GOA单元21进一步包括上拉辅助单元800，上拉辅助单元800用于防止第五晶体管PT4和第六晶体管PT5在对栅极信号点Q（2N+1）进行充电的过程中出现漏电的问题。具体来说，上拉辅助单元800包括第十二晶体管PT11，第十二晶体管PT11的栅极与第一晶体管PT0、第二晶体管PT1的漏极连接，第十二晶体管PT11的源极与公共信号点P（2N+1）连接，十二晶体管PT11的漏极与第一恒压源也即正压恒压源VGH连接。
在GOA电路20中，在第一级、第五级、…第4N+1（N为自然数）级GOA单元21中，第一级传时钟CK_LA1为第一时钟信号CK1，第二级传时钟CK_LA2为第三时钟信号CK3，第一控制时钟CK_LB1为第二时钟信号CK2，第二控制时钟CK_LB2为第四时钟信号CK4。在第三级、第七级、…第4N+3（N为自然数）级GOA单元21中，第二级传时钟CK_LA2为第三时钟信号CK3，第一级传时钟CK_LA1为第一时钟信号CK1，第二控制时钟CK_LB2为第四时钟信号CK4，第一控制时钟CK_LB2为第二时钟信号CK2。
本领域的技术人员可以理解，当GOA电路为NMOS电路时，上述所有晶体管为NMOS晶体管，第一扫描控制信号对应正向扫描控制信号U2D，第二扫描控制信号对应反相扫描控制信号D2U，第一恒压源对应负压恒压源VGL，第二恒压源对应正压恒压源VGH。
请继续参考图2，控制模块22包括除第一级GOA单元21外，与剩余的GOA单元21一一对应的第一控制晶体管T1，第一控制晶体管T1的第一端、第二端连接后接收启动脉冲信号STV，第一控制晶体管T1的第三端与对应的GOA单元21的公共信号点P（2N+1）连接。
在本实施例中，第一控制晶体管T1为PMOS管，第一控制晶体管T1的第一端、第二端、第三端对应PMOS管的栅极、源极和漏极；其中，当启动脉冲信号STV开启时，启动脉冲信号STV控制除第一个GOA单元外的每一GOA单元的公共信号点P（2N+1）处于低电平以使水平扫描线上的栅极驱动信号G（2N+1）复位至高电平。
在其它实施例中，当GOA电路为NMOS电路时，第一控制晶体管T1也可以为NMOS管，第一控制晶体管T1的第一端、第二端、第三端对应NMOS管的栅极、源极和漏极；其中，当启动脉冲信号STV开启时，启动脉冲信号STV控制除第一个GOA单元外的每一GOA单元的公共信号点P（2N+1）处于高电平以使水平扫描线上的栅极驱动信号G（2N+1）复位至低电平。
图4是本发明第二实施例的GOA电路的工作时序图。本发明第二实施例以奇数级GOA单元级联形成的GOA电路为例来说明，其中GOA电路为PMOS电路。如图4所示，当GAS信号GAS有效也即为低电平信号时，GOA电路20实现All Gate On功能，与各奇数级水平扫描线对应的栅极驱动信号G（2N+1）输出低电平信号。当GOA电路20完成All Gate On功能后，由于自举电容Cload的存在，与各奇数级水平扫描线对应的栅极驱动信号G（2N+1）不会马上变为高电平，而会保持Cload holding的低电平信号。
以GOA电路为正向驱动为例，如果与奇数级水平扫描线对应的栅极驱动信号在第三时钟信号CK3有效之前不能放电至高电平，则除第一级水平扫描线以外，其它奇数级水平扫描线上会产生冗余的脉冲信号。具体来说，第一级水平扫描线由第一级GOA单元驱动，由于第一级GOA单元的级传信号为启动脉冲信号STV，第一级GOA单元正常驱动，不会产生冗余的脉冲信号。第三级水平扫描线由第三级GOA单元驱动，而第三级GOA单元的级传信号为第一级GOA单元的栅极驱动信号G（1），当第一时钟信号CK1为低电平时，由于栅极驱动信号G（1）保持Cload holding的低电平信号，则栅极驱动信号G（1）的低电平信号会传递至第三级GOA单元的栅极信号点Q（3），使得第三级GOA单元21先于第一级GOA单元21工作，并使得第三级GOA单元21输出的栅极驱动信号G（3）产生一个冗余的脉冲，这个冗余的脉冲会继续影响下一级GOA单元21的栅极驱动信号。基于相同的理由，在第一时钟信号CK1有效时，第七级、第十一级、…第4N+3级GOA单元的栅极驱动信号均会产生冗余的脉冲。
为了避免上述问题的产生，如图4所示，GOA电路20实现All Gate On功能后，在第一时钟信号CK1有效之前，设置启动脉冲信号STV为低电平并随着第一时钟信号CK1、第二时钟信号CK2、第三时钟信号CK3、第四时钟信号CK4依次有效后，启动脉冲信号STV由低电平变为高电平。其中，当启动脉冲信号STV为低电平时，由于第一控制晶体管T1导通，第三级、第五级、…，第2N+1级的GOA单元21的公共信号点P（2N+1）从高电平变为低电平，从而使得在第三时钟信号CK3有效之前栅极驱动信号G（2N+1）变为高电平信号，从而避免了冗余的脉冲信号的产生。随后，保持正常的第一时钟信号CK1、第二时钟信号CK2、第三时钟信号CK3、第四时钟信号CK4的驱动顺序对GOA电路20进行驱动，即可实现对水平扫描线的正常充电。
图5是本发明第三实施例的GOA电路的结构示意图。本发明第三实施例以奇数级GOA单元级联形成的GOA电路为例来说明，其中GOA电路为PMOS电路。图5所示的第三实施例与图2所示的第二实施例的区别在于：
如图5所示，控制模块23包括第二控制晶体管T2，第二控制晶体管T2的第一端、第二端连接后接收启动脉冲信号STV，第二控制晶体管T3的第三端分别与除第一个GOA单元21外的多个GOA单元21的公共信号点P（2N+1）连接。
在本实施例中，第二控制晶体管T2为PMOS管，第二控制晶体管T2的第一端、第二端、第三端对应PMOS管的栅极、源极和漏极；其中，当启动脉冲信号STV开启时，启动脉冲信号控制除第一个GOA单元外的每一GOA单元21的公共信号点P（2N+1）处于低电平以使水平扫描线上的栅极驱动信号G（2N+1）复位至高电平。
在其它实施例中，当GOA电路为NMOS电路时，第二控制晶体管T2也可以为NMOS管，第二控制晶体管T2的第一端、第二端、第三端对应NMOS管的栅极、源极和漏极；其中，当启动脉冲信号STV开启时，启动脉冲信号控制每一GOA单元21的公共信号点P（2N+1）处于高电平以使水平扫描线上的栅极驱动信号G（2N+1）复位至低电平。
另外，图5所示第三实施例的GOA电路的工作时序和图2所示第二实施例的GOA电路的工作时序相同，为简约起见，在此不再赘述。
本领域的技术人员可以理解，液晶显示器包括奇数级的GOA单元级联形成的GOA电路和偶数级的GOA单元级联形成的GOA电路，由于偶数级的GOA单元级联形成的GOA电路与奇数级的GOA单元级联形成的GOA电路的处理方式类似，为简约起见，在此不再详述。
本发明进一步提供一种液晶显示器，包括了上述GOA电路。
本发明的有益效果是：本发明的GOA电路及液晶显示器通过GOA电路对所有水平扫描线同时充电后，通过启动脉冲信号控制水平扫描线上的栅极驱动信号复位至第一电平也即无效电平，从而能够避免在第一个栅极驱动信号输出之前在水平扫描线上产生冗余的脉冲信号，进而保证了GOA电路的正常工作。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (20)

  1. 一种GOA电路，用于液晶显示器，其中，所述GOA电路包括级联的多个GOA单元，每一所述GOA单元用于在第一级传时钟、第二级传时钟、第一控制时钟、第二控制时钟的驱动下对显示区域中对应的水平扫描线进行充电，所述第一级传时钟、第二级传时钟用于控制所述GOA单元的级传信号的输入以及栅极驱动信号的产生，所述第一控制时钟、第二控制时钟用于控制所述栅极驱动信号处于第一电平，其中，所述级传信号为启动脉冲信号或相邻的所述GOA单元的所述栅极驱动信号；
    所述GOA单元包括正反扫描单元、输入控制单元、上拉维持单元、输出控制单元、GAS信号作用单元和自举电容单元；
    所述正反扫描单元用于控制所述GOA电路的正向驱动或反向驱动，并在所述第一控制时钟或第二控制时钟的控制下，控制公共信号点保持第二电平；
    所述输入控制单元用于根据所述第一级传时钟控制所述级传信号的输入以完成对栅极信号点的充电；
    所述上拉维持单元用于根据所述公共信号点控制所述栅极信号点在非作用期间保持所述第一电平；
    所述输出控制单元用于根据所述第二级传时钟控制与所述栅极信号点对应的所述栅极驱动信号的输出；
    所述GAS信号作用单元用于控制所述栅极驱动信号处于所述第二电平，以实现与所述GOA单元对应的所述水平扫描线的充电；
    所述自举电容单元用于对所述栅极信号点的电压进行再次抬升；
    所述正反扫描单元包括第一晶体管、第二晶体管、第三晶体管和第四晶体管，所述第一晶体管的栅极接收第一扫描控制信号，所述第一晶体管的源极接收下一级所述GOA单元输出的所述栅极驱动信号，所述第二晶体管的栅极接收第二扫描控制信号，所述第二晶体管的源极接收上一级所述GOA单元输出的所述栅极驱动信号，所述第一晶体管和所述第二晶体管的漏极相互连接后与所述输入控制单元连接，所述第三晶体管的栅极接收所述第一扫描控制信号，所述第三晶体管的源极接收所述第一控制时钟，所述第四晶体管的栅极接收所述第二扫描控制信号，所述第四晶体管的源极接收所述第二控制时钟，所述第三晶体管和所述第四晶体管的漏极相互连接后与所述上拉维持单元连接；
    所述输入控制单元包括第五晶体管，所述第五晶体管的栅极接收所述第一级连信号，所述第五晶体管的源极与所述第一晶体管、第二晶体管的漏极连接，所述第五晶体管的漏极与栅极信号点连接；
    所述上拉维持单元包括第六晶体管、第七晶体管、第九晶体管、第十晶体管和第一电容，所述第六晶体管的栅极与公共信号点连接，所述第六晶体管的源极与所述第五晶体管的漏极连接，所述第六晶体管的漏极与第一恒压源连接，所述第七晶体管的栅极与所述五晶体管的漏极连接，所述第七晶体管的源极与所述公共信号点连接，所述第七晶体管的漏极与所述第一恒压源连接，所述第九晶体管的栅极与所述第三晶体管、第四晶体管的漏极连接，所述第九晶体管的源极与第二恒压源连接，所述第九晶体管的漏极与所述公共信号点连接，所述第十晶体管的栅极与所述公共信号点连接，所述第十晶体管的源极与所述栅极驱动信号连接，所述第十晶体管的漏极与所述第一恒压源连接，所述第一电容的一端与所述第一恒压源连接，所述第一电容的另一端与所述公共信号点连接；
    所述输出控制单元包括第十一晶体管和第二电容，所述第十一晶体管的栅极与所述栅极信号点连接，所述第十一晶体管的漏极与所述栅极驱动信号连接，所述第十一晶体管的源极接收所述第二级传时钟，所述第二电容的一端与所述栅极信号点连接，所述第二电容的另一端与所述栅极驱动信号连接；
    所述GAS信号作用单元包括第十三晶体管和第十四晶体管，所述第十三晶体管的栅极、第十四晶体管的栅极和漏极接收GAS信号，所述第十三晶体管的漏极连接所述第一恒压源，所述第十三晶体管的源极连接所述公共信号点，所述第十三晶体管的源极连接所述栅极驱动信号；
    所述自举电容单元包括自举电容，所述自举电容的一端与所述栅极驱动信号连接，所述自举电容的另一端与地信号连接；
    所述GOA单元进一步包括稳压单元和上拉辅助单元，所述稳压单元包括第八晶体管，所述第八晶体管串接于所述第五晶体管的源极与所述栅极信号点之间，所述第八晶体管的栅极与所述第二恒压源连接，所述第八晶体管的漏极与所述第五晶体管的漏极连接，所述第八晶体管的源极与所述栅极信号点连接；所述上拉辅助单元包括第十二晶体管，所述第十二晶体管的栅极与所述第一晶体管、第二晶体管的漏极连接，所述第十二晶体管的源极与所述公共信号点连接，所述十二晶体管的漏极与所述正压恒压源连接。
    所述GOA电路进一步包括控制模块，所述控制模块用于在所述GOA电路对所有所述水平扫描线同时充电后，通过所述启动脉冲信号控制所述水平扫描线上除第一个所述栅极驱动信号之外的所述栅极驱动信号复位至所述第一电平，从而避免在第一个所述栅极驱动信号输出之前在所述水平扫描线上产生冗余的脉冲信号；
    所述控制模块包括除第一个所述GOA单元外，与多个所述GOA单元一一对应的多个第一控制晶体管，多个所述第一控制晶体管的第一端、第二端连接后接收所述启动脉冲信号，多个所述第一控制晶体管的第三端与对应的所述GOA单元的所述公共信号点连接。
  2. 根据权利要求1所述的GOA电路，其中，所述第一控制晶体管为PMOS管，所述第一控制晶体管的所述第一端、第二端、第三端对应所述PMOS管的栅极、源极和漏极；其中，当所述启动脉冲信号开启时，所述启动脉冲信号控制除第一个所述GOA单元外每一所述GOA单元的所述公共信号点处于低电平以使所述水平扫描线上的所述栅极驱动信号复位至高电平。
  3. 一种GOA电路，用于液晶显示器，其中，所述GOA电路包括级联的多个GOA单元，每一所述GOA单元用于在第一级传时钟、第二级传时钟、第一控制时钟、第二控制时钟的驱动下对显示区域中对应的水平扫描线进行充电，所述第一级传时钟、第二级传时钟用于控制所述GOA单元的级传信号的输入以及栅极驱动信号的产生，所述第一控制时钟、第二控制时钟用于控制所述栅极驱动信号处于第一电平，其中，所述级传信号为启动脉冲信号或相邻的所述GOA单元的所述栅极驱动信号；
    所述GOA电路进一步包括控制模块，所述控制模块用于在所述GOA电路对所有所述水平扫描线同时充电后，通过所述启动脉冲信号控制所述水平扫描线上除第一个所述栅极驱动信号之外的所述栅极驱动信号复位至所述第一电平，从而避免在第一个所述栅极驱动信号输出之前在所述水平扫描线上产生冗余的脉冲信号。
  4. 根据权利要求3所述的GOA电路，其中，所述GOA单元包括正反扫描单元、输入控制单元、上拉维持单元、输出控制单元、GAS信号作用单元和自举电容单元；
    所述正反扫描单元用于控制所述GOA电路的正向驱动或反向驱动，并在所述第一控制时钟或第二控制时钟的控制下，控制公共信号点保持第二电平；
    所述输入控制单元用于根据所述第一级传时钟控制所述级传信号的输入以完成对栅极信号点的充电；
    所述上拉维持单元用于根据所述公共信号点控制所述栅极信号点在非作用期间保持所述第一电平；
    所述输出控制单元用于根据所述第二级传时钟控制与所述栅极信号点对应的所述栅极驱动信号的输出；
    所述GAS信号作用单元用于控制所述栅极驱动信号处于所述第二电平，以实现与所述GOA单元对应的所述水平扫描线的充电；
    所述自举电容单元用于对所述栅极信号点的电压进行再次抬升。
  5. 根据权利要求4所述的GOA电路，其中，所述控制模块包括除第一个所述GOA单元外，与多个所述GOA单元一一对应的多个第一控制晶体管，多个所述第一控制晶体管的第一端、第二端连接后接收所述启动脉冲信号，多个所述第一控制晶体管的第三端与对应的所述GOA单元的所述公共信号点连接。
  6. 根据权利要求5所述的GOA电路，其中，所述第一控制晶体管为PMOS管，所述第一控制晶体管的所述第一端、第二端、第三端对应所述PMOS管的栅极、源极和漏极；其中，当所述启动脉冲信号开启时，所述启动脉冲信号控制除第一个所述GOA单元外每一所述GOA单元的所述公共信号点处于低电平以使所述水平扫描线上的所述栅极驱动信号复位至高电平。
  7. 根据权利要求5所述的GOA电路，其中，所述第一控制晶体管为NMOS管，所述第一控制晶体管的所述第一端、第二端、第三端对应所述NMOS管的栅极、源极和漏极；其中，当所述启动脉冲信号开启时，所述启动脉冲信号控制除第一个所述GOA单元外每一所述GOA单元的所述公共信号点处于高电平以使所述水平扫描线上的所述栅极驱动信号复位至低电平。
  8. 根据权利要求4所述的GOA电路，其中，所述控制模块包括第二控制晶体管，所述第二控制晶体管的第一端、第二端连接后接收所述启动脉冲信号，所述第二控制晶体管的第三端分别与除第一个所述GOA单元外每一所述GOA单元的所述公共信号点连接。
  9. 根据权利要求8所述的GOA电路，其中，所述第二控制晶体管为PMOS管，所述第二控制晶体管的所述第一端、第二端、第三端对应所述PMOS管的栅极、源极和漏极；其中，当所述启动脉冲信号开启时，所述启动脉冲信号控制除第一个所述GOA单元外每一所述GOA单元的公共信号点处于低电平以使所述水平扫描线上的所述栅极驱动信号复位至高电平。
  10. 根据权利要求8所述的GOA电路，其中，所述第二控制晶体管为NMOS管，所述第一控制晶体管的所述第一端、第二端、第三端对应所述NMOS管的栅极、源极和漏极；其中，当所述启动脉冲信号开启时，所述启动脉冲信号控制除第一个所述GOA单元外每一所述GOA单元的公共信号点处于高电平以使所述水平扫描线上的所述栅极驱动信号复位至低电平。
  11. 根据权利要求4所述的GOA电路，其中，
    所述正反扫描单元包括第一晶体管、第二晶体管、第三晶体管和第四晶体管，所述第一晶体管的栅极接收第一扫描控制信号，所述第一晶体管的源极接收下一级所述GOA单元输出的所述栅极驱动信号，所述第二晶体管的栅极接收第二扫描控制信号，所述第二晶体管的源极接收上一级所述GOA单元输出的所述栅极驱动信号，所述第一晶体管和所述第二晶体管的漏极相互连接后与所述输入控制单元连接，所述第三晶体管的栅极接收所述第一扫描控制信号，所述第三晶体管的源极接收所述第一控制时钟，所述第四晶体管的栅极接收所述第二扫描控制信号，所述第四晶体管的源极接收所述第二控制时钟，所述第三晶体管和所述第四晶体管的漏极相互连接后与所述上拉维持单元连接；
    所述输入控制单元包括第五晶体管，所述第五晶体管的栅极接收所述第一级连信号，所述第五晶体管的源极与所述第一晶体管、第二晶体管的漏极连接，所述第五晶体管的漏极与栅极信号点连接；
    所述上拉维持单元包括第六晶体管、第七晶体管、第九晶体管、第十晶体管和第一电容，所述第六晶体管的栅极与公共信号点连接，所述第六晶体管的源极与所述第五晶体管的漏极连接，所述第六晶体管的漏极与第一恒压源连接，所述第七晶体管的栅极与所述五晶体管的漏极连接，所述第七晶体管的源极与所述公共信号点连接，所述第七晶体管的漏极与所述第一恒压源连接，所述第九晶体管的栅极与所述第三晶体管、第四晶体管的漏极连接，所述第九晶体管的源极与第二恒压源连接，所述第九晶体管的漏极与所述公共信号点连接，所述第十晶体管的栅极与所述公共信号点连接，所述第十晶体管的源极与所述栅极驱动信号连接，所述第十晶体管的漏极与所述第一恒压源连接，所述第一电容的一端与所述第一恒压源连接，所述第一电容的另一端与所述公共信号点连接；
    所述输出控制单元包括第十一晶体管和第二电容，所述第十一晶体管的栅极与所述栅极信号点连接，所述第十一晶体管的漏极与所述栅极驱动信号连接，所述第十一晶体管的源极接收所述第二级传时钟，所述第二电容的一端与所述栅极信号点连接，所述第二电容的另一端与所述栅极驱动信号连接；
    所述GAS信号作用单元包括第十三晶体管和第十四晶体管，所述第十三晶体管的栅极、第十四晶体管的栅极和漏极接收GAS信号，所述第十三晶体管的漏极连接所述第一恒压源，所述第十三晶体管的源极连接所述公共信号点，所述第十三晶体管的源极连接所述栅极驱动信号；
    所述自举电容单元包括自举电容，所述自举电容的一端与所述栅极驱动信号连接，所述自举电容的另一端与地信号连接；
    所述GOA单元进一步包括稳压单元和上拉辅助单元，所述稳压单元包括第八晶体管，所述第八晶体管串接于所述第五晶体管的源极与所述栅极信号点之间，所述第八晶体管的栅极与所述第二恒压源连接，所述第八晶体管的漏极与所述第五晶体管的漏极连接，所述第八晶体管的源极与所述栅极信号点连接；所述上拉辅助单元包括第十二晶体管，所述第十二晶体管的栅极与所述第一晶体管、第二晶体管的漏极连接，所述第十二晶体管的源极与所述公共信号点连接，所述十二晶体管的漏极与所述正压恒压源连接。
  12. 一种液晶显示器，其中，包括GOA电路，所述GOA电路包括级联的多个GOA单元，每一所述GOA单元用于在第一级传时钟、第二级传时钟、第一控制时钟、第二控制时钟的驱动下对显示区域中对应的水平扫描线进行充电，所述第一级传时钟、第二级传时钟用于控制所述GOA单元的级传信号的输入以及栅极驱动信号的产生，所述第一控制时钟、第二控制时钟用于控制所述栅极驱动信号处于第一电平，其中，所述级传信号为启动脉冲信号或相邻的所述GOA单元的所述栅极驱动信号；
    所述GOA电路进一步包括控制模块，所述控制模块用于在所述GOA电路对所有所述水平扫描线同时充电后，通过所述启动脉冲信号控制所述水平扫描线上除第一个所述栅极驱动信号之外的所述栅极驱动信号复位至所述第一电平，从而避免在第一个所述栅极驱动信号输出之前在所述水平扫描线上产生冗余的脉冲信号。
  13. 根据权利要求12所述的液晶显示器，其中，所述GOA单元包括正反扫描单元、输入控制单元、上拉维持单元、输出控制单元、GAS信号作用单元和自举电容单元；
    所述正反扫描单元用于控制所述GOA电路的正向驱动或反向驱动，并在所述第一控制时钟或第二控制时钟的控制下，控制公共信号点保持第二电平；
    所述输入控制单元用于根据所述第一级传时钟控制所述级传信号的输入以完成对栅极信号点的充电；
    所述上拉维持单元用于根据所述公共信号点控制所述栅极信号点在非作用期间保持所述第一电平；
    所述输出控制单元用于根据所述第二级传时钟控制与所述栅极信号点对应的所述栅极驱动信号的输出；
    所述GAS信号作用单元用于控制所述栅极驱动信号处于所述第二电平，以实现与所述GOA单元对应的所述水平扫描线的充电；
    所述自举电容单元用于对所述栅极信号点的电压进行再次抬升。
  14. 根据权利要求13所述的液晶显示器，其中，所述控制模块包括除第一个所述GOA单元外，与多个所述GOA单元一一对应的多个第一控制晶体管，多个所述第一控制晶体管的第一端、第二端连接后接收所述启动脉冲信号，多个所述第一控制晶体管的第三端与对应的所述GOA单元的所述公共信号点连接。
  15. 根据权利要求14所述的液晶显示器，其中，所述第一控制晶体管为PMOS管，所述第一控制晶体管的所述第一端、第二端、第三端对应所述PMOS管的栅极、源极和漏极；其中，当所述启动脉冲信号开启时，所述启动脉冲信号控制除第一个所述GOA单元外每一所述GOA单元的所述公共信号点处于低电平以使所述水平扫描线上的所述栅极驱动信号复位至高电平。
  16. 根据权利要求14所述的液晶显示器，其中，所述第一控制晶体管为NMOS管，所述第一控制晶体管的所述第一端、第二端、第三端对应所述NMOS管的栅极、源极和漏极；其中，当所述启动脉冲信号开启时，所述启动脉冲信号控制除第一个所述GOA单元外每一所述GOA单元的所述公共信号点处于高电平以使所述水平扫描线上的所述栅极驱动信号复位至低电平。
  17. 根据权利要求13所述的液晶显示器，其中，所述控制模块包括第二控制晶体管，所述第二控制晶体管的第一端、第二端连接后接收所述启动脉冲信号，所述第二控制晶体管的第三端分别与除第一个所述GOA单元外每一所述GOA单元的所述公共信号点连接。
  18. 根据权利要求17所述的液晶显示器，其中，所述第二控制晶体管为PMOS管，所述第二控制晶体管的所述第一端、第二端、第三端对应所述PMOS管的栅极、源极和漏极；其中，当所述启动脉冲信号开启时，所述启动脉冲信号控制除第一个所述GOA单元外每一所述GOA单元的公共信号点处于低电平以使所述水平扫描线上的所述栅极驱动信号复位至高电平。
  19. 根据权利要求17所述的液晶显示器，其中，所述第二控制晶体管为NMOS管，所述第一控制晶体管的所述第一端、第二端、第三端对应所述NMOS管的栅极、源极和漏极；其中，当所述启动脉冲信号开启时，所述启动脉冲信号控制除第一个所述GOA单元外每一所述GOA单元的公共信号点处于高电平以使所述水平扫描线上的所述栅极驱动信号复位至低电平。
  20. 根据权利要求13所述的液晶显示器，其中，
    所述正反扫描单元包括第一晶体管、第二晶体管、第三晶体管和第四晶体管，所述第一晶体管的栅极接收第一扫描控制信号，所述第一晶体管的源极接收下一级所述GOA单元输出的所述栅极驱动信号，所述第二晶体管的栅极接收第二扫描控制信号，所述第二晶体管的源极接收上一级所述GOA单元输出的所述栅极驱动信号，所述第一晶体管和所述第二晶体管的漏极相互连接后与所述输入控制单元连接，所述第三晶体管的栅极接收所述第一扫描控制信号，所述第三晶体管的源极接收所述第一控制时钟，所述第四晶体管的栅极接收所述第二扫描控制信号，所述第四晶体管的源极接收所述第二控制时钟，所述第三晶体管和所述第四晶体管的漏极相互连接后与所述上拉维持单元连接；
    所述输入控制单元包括第五晶体管，所述第五晶体管的栅极接收所述第一级连信号，所述第五晶体管的源极与所述第一晶体管、第二晶体管的漏极连接，所述第五晶体管的漏极与栅极信号点连接；
    所述上拉维持单元包括第六晶体管、第七晶体管、第九晶体管、第十晶体管和第一电容，所述第六晶体管的栅极与公共信号点连接，所述第六晶体管的源极与所述第五晶体管的漏极连接，所述第六晶体管的漏极与第一恒压源连接，所述第七晶体管的栅极与所述五晶体管的漏极连接，所述第七晶体管的源极与所述公共信号点连接，所述第七晶体管的漏极与所述第一恒压源连接，所述第九晶体管的栅极与所述第三晶体管、第四晶体管的漏极连接，所述第九晶体管的源极与第二恒压源连接，所述第九晶体管的漏极与所述公共信号点连接，所述第十晶体管的栅极与所述公共信号点连接，所述第十晶体管的源极与所述栅极驱动信号连接，所述第十晶体管的漏极与所述第一恒压源连接，所述第一电容的一端与所述第一恒压源连接，所述第一电容的另一端与所述公共信号点连接；
    所述输出控制单元包括第十一晶体管和第二电容，所述第十一晶体管的栅极与所述栅极信号点连接，所述第十一晶体管的漏极与所述栅极驱动信号连接，所述第十一晶体管的源极接收所述第二级传时钟，所述第二电容的一端与所述栅极信号点连接，所述第二电容的另一端与所述栅极驱动信号连接；
    所述GAS信号作用单元包括第十三晶体管和第十四晶体管，所述第十三晶体管的栅极、第十四晶体管的栅极和漏极接收GAS信号，所述第十三晶体管的漏极连接所述第一恒压源，所述第十三晶体管的源极连接所述公共信号点，所述第十三晶体管的源极连接所述栅极驱动信号；
    所述自举电容单元包括自举电容，所述自举电容的一端与所述栅极驱动信号连接，所述自举电容的另一端与地信号连接；
    所述GOA单元进一步包括稳压单元和上拉辅助单元，所述稳压单元包括第八晶体管，所述第八晶体管串接于所述第五晶体管的源极与所述栅极信号点之间，所述第八晶体管的栅极与所述第二恒压源连接，所述第八晶体管的漏极与所述第五晶体管的漏极连接，所述第八晶体管的源极与所述栅极信号点连接；所述上拉辅助单元包括第十二晶体管，所述第十二晶体管的栅极与所述第一晶体管、第二晶体管的漏极连接，所述第十二晶体管的源极与所述公共信号点连接，所述十二晶体管的漏极与所述正压恒压源连接。
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