WO2017028495A1 - 阵列基板及其制造方法以及包括其的显示装置 - Google Patents

阵列基板及其制造方法以及包括其的显示装置 Download PDF

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WO2017028495A1
WO2017028495A1 PCT/CN2016/071592 CN2016071592W WO2017028495A1 WO 2017028495 A1 WO2017028495 A1 WO 2017028495A1 CN 2016071592 W CN2016071592 W CN 2016071592W WO 2017028495 A1 WO2017028495 A1 WO 2017028495A1
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Prior art keywords
layer
lead
gate
source
drain
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PCT/CN2016/071592
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English (en)
French (fr)
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肖志莲
赵海生
刘冲
彭志龙
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京东方科技集团股份有限公司
北京京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US15/122,888 priority Critical patent/US9837448B2/en
Priority to EP16754164.8A priority patent/EP3339948B1/en
Publication of WO2017028495A1 publication Critical patent/WO2017028495A1/zh
Priority to US15/801,376 priority patent/US9991291B2/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • G—PHYSICS
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    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13454—Drivers integrated on the active matrix substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
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    • H01L27/0288—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1296—Multistep manufacturing methods adapted to increase the uniformity of device parameters
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1041—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
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    • H01L29/78669—Amorphous silicon transistors with inverted-type structure, e.g. with bottom gate
    • G—PHYSICS
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    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133388—Constructional arrangements; Manufacturing methods with constructional differences between the display region and the peripheral region
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136204—Arrangements to prevent high voltage or static electricity failures
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    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/136295—Materials; Compositions; Manufacture processes

Definitions

  • the present invention relates to the field of layout design of GOA units on TFT substrates, and in particular to array substrates and methods of fabricating the same, and display devices including the same.
  • GOA Gate Driver On Array or (Gate On Array) technology TFT-LCD, which integrates the gate driving circuit of the LCD panel on the substrate, thereby improving the integration of the LCD panel and reducing the gate.
  • the use rate of the driver IC is widely used.
  • ESD electrostatic discharge
  • the display area and the GOA circuit driving area are connected by a gate-source drain circuit (collectively referred to as a display area), and an external signal is transmitted to the display area through the metal lead to drive the display area to operate.
  • a gate-source drain circuit collectively referred to as a display area
  • the inventor has continuously studied to find out the area where the display area is connected to the driving signal area from the defective product, that is, the area where the metal line of the gate and the metal line connected to the source and drain intersect each other, ESD is easily generated and electrostatic breakdown occurs. That is, the area is the weakest area in the circuit. The reason is due to factors such as high wiring, narrow bezel, etc., such as tight wiring, semiconductor pad and gate tip structure. Therefore, there is a need for an improved GOA layout design that overcomes the above technical problems.
  • the present invention proposes an improved GOA circuit design that solves the GOA electrostatic discharge problem mentioned above and reduces the probability of display panels being abnormal due to ESD.
  • the semiconductor pad layer mainly functions as a gate source layer for climbing the gate, there is no switching effect, but the conductivity of the semiconductor material is increased under high temperature conditions, which is the key to induce static electricity.
  • the film deposition process is carried out at a high temperature, the lowest temperature is 120 °, and the highest temperature is 360 °, which is an important step of film deposition and cannot be changed.
  • the present invention therefore modifies the semiconductor underlayer in the high-risk factor and thus the active layer in the driver circuit region that is connected to the display region and the GOA cell (ie, non- Crystal silicon) is removed to reduce the high probability of static electricity.
  • the present invention provides an array substrate including a display region and a driving circuit region, the driving circuit region including a GOA unit including a substrate, a gate electrode layer, an insulating layer, and an active layer And a source/drain electrode layer, and the driving circuit region further includes a gate lead connected to the gate electrode layer and a source/drain layer lead located in the same layer as the source/drain electrode layer, wherein the gate lead and Only the insulating layer is formed between portions of the source/drain layer leads that intersect each other.
  • the portions of the leads that intersect each other are wider relative to the leads of the surrounding area. This further reduces the chance of ESD occurring in this part.
  • an induced discharge region is formed in which a dummy electrode portion in the same layer as the source/drain layer lead is formed and connected to a dummy electrode portion of the gate lead and an insulating layer and an active layer formed between the two layers of dummy electrode portions.
  • the preferred embodiment induces ESD that may be present in the peripheral active area to the induced discharge zone for ESD, thereby further reducing the likelihood of ESD occurring in the active working area.
  • the virtual electrode portion has a shape with a pointed end.
  • the virtual electrode portion with the tip can further promote the occurrence of ESD.
  • the dummy electrode portion has a triangular, rectangular or prismatic shape.
  • the dummy electrode portion in the same layer as the source drain layer lead and the dummy electrode portion connected to the gate lead are two substantially parallel extending lines, and the spacing between the two lines is sufficient Small to induce ESD discharge.
  • the virtual electrode portion has a weakened region that is susceptible to breakage in the event of an ESD event.
  • the preferred embodiment minimizes the effects of ESD events by providing a weak region in the dummy electrode portion so that the weak region can be directly broken, i.e., blown, when an ESD event occurs in the induced discharge region.
  • a method of fabricating an array substrate includes: providing a substrate; forming a gate electrode layer on the substrate; and a gate lead connected to the gate electrode layer; Forming an insulating layer on the substrate of the gate electrode layer and the gate lead, the insulating layer covering the gate electrode layer and the gate lead; forming a shape on the insulating layer Forming an active layer; and forming a source/drain electrode layer and a source/drain layer lead on the substrate, wherein the active layer does not cover a region where the gate lead and the source/drain layer lead cross each other.
  • the method further includes forming an induced discharge region in a free region around the gate lead and the source/drain layer lead, wherein a connection is formed at the induced discharge region while forming the gate lead To a dummy electrode portion of the gate lead, and forming a dummy electrode portion in the same layer as the source/drain layer lead in the induced discharge region while forming the source/drain layer lead, and at the above two kinds of dummy electrodes
  • the insulating layer and the active layer are formed between the portions.
  • the active layer consists of two layers of a-Si and N + a-Si material.
  • the method further comprises the step of forming a passivation layer.
  • a display device comprising the array substrate as described above.
  • the present invention reduces the incidence of ESD by modifying the GOA cell design, and in particular, improving the design of the intersections in the lead regions.
  • FIG. 1 is a schematic diagram showing the layout of a general array substrate for a display panel
  • FIG. 2 illustrates a schematic plan view of a drive circuit region in a prior art array substrate
  • FIG. 3 illustrates a schematic partial cross-sectional view of a drive circuit region in a prior art array substrate taken according to arrows A-A in FIG. 2;
  • FIG. 4 illustrates a schematic plan view of a drive circuit region in an array substrate in accordance with the present invention
  • Figure 5 illustrates a schematic partial cross-sectional view of a drive circuit region in an array substrate according to the present invention, taken according to arrows A-A in Figure 4;
  • Figure 6 illustrates a method of fabricating an array substrate in accordance with the present invention, in which several basic steps are illustrated.
  • the word “above” with respect to a portion, element or layer of material that is formed or positioned “above” the surface may be used herein to mean that the portion, element or layer of material is positioned "directly on” the implied surface ( For example, placing, forming, depositing, etc., for example, in direct contact therewith.
  • the word “above” as used in relation to a portion, element or layer of material formed or positioned “above” a surface may be used herein to mean that the portion, element or layer of material is positioned (eg, placed, formed, deposited, etc.) "Indirectly on” the surface implied, with one or more additional portions, elements or layers disposed between the suggested surface and the portion, element or layer of material.
  • FIG. 1 illustrates a layout diagram of a general array substrate for a display panel.
  • the array substrate includes a display area 1 and a driving circuit area 2.
  • the display area 1 includes a gate, a source and a drain, an insulating layer, and an active layer, which are also referred to as pixel display areas.
  • the portion other than the display area 1 is referred to as a drive circuit area 2.
  • a GOA unit and a lead connecting the GOA unit to the display area and a lead for transmitting an external signal are disposed in the drive circuit area 2.
  • the GOA unit mainly functions as a circuit, and generally has a gate electrode layer, an insulating layer, an active layer, a source/drain electrode layer, a passivation layer, and the like.
  • the gate electrode layer and the drain-source electrode layer are generally made of a metal material
  • the insulating layer is generally formed of silicon nitride or the like
  • the active layer is generally made of a semiconductor material, such as including a-Si and n + a, respectively.
  • FIG. 2 illustrates a schematic plan view of a drive circuit region in a prior art array substrate.
  • 2 is an enlarged schematic view of the position of the drawing in FIG. 1.
  • the gate, the source and the drain of the display area 1 are connected to the GOA unit, and the third line is the gate metal line drawn from the pixel of the display area, and is connected to the GOA unit through the via hole and the jumper.
  • Drive circuit area 2 has a connection to the GOA unit
  • the gate lead 3 of the gate electrode layer and the source/drain layer lead 4 in the same layer as the source/drain electrode layer.
  • FIG. 3 illustrates a schematic partial cross-sectional view of a drive circuit region in a prior art array substrate taken according to arrow AA of FIG. 2.
  • the inventors have found that when an active layer (which includes amorphous silicon) is formed between the two types of leads, the semiconductor material in the active layer is increased in electrical conductivity at a high temperature, which is the key to inducing static electricity. Therefore, when the metal line connected to the gate is too thin or too densely arranged, superimposed or very close to the amorphous silicon (ie, a-Si) in the active layer, it is easy to induce contact discharge or adjacent discharge, which often results in the gate lead Electrostatic breakdown between the source and drain leads leads to an abnormal display of the picture.
  • the star in Figure 2 is a schematic representation of the weak location where ESD is prone to occur, ie the high ESD area.
  • Figure 4 illustrates a schematic plan view of a drive circuit region in an array substrate in accordance with the present invention.
  • the active layer is not formed, so that the portion where the gate lead 3 and the source/drain layer lead 4 cross each other There is no semiconductor switch between the active layer, which greatly reduces the probability of ESD occurring at the intersection of 3 and 4 and adjacent positions, thus turning it into non-ESD high Area.
  • FIG. 5 shows a schematic partial cross-section of the drive circuit region in the array substrate according to the present invention, taken according to arrow A-A in FIG.
  • the portions of the gate lead 3 and the source/drain layer leads 4 that intersect each other may be wider than the leads of the surrounding area. This can further reduce the chance of ESD occurring at the intersection.
  • the array substrate according to the present invention also provides an induced discharge region in a free area in the drive circuit region.
  • the induced discharge zone is the area that actively induces the occurrence of ESD.
  • the induced discharge region is insulated by a dummy electrode portion 7 connected to the gate lead, another dummy electrode portion 8 in the same layer as the source/drain layer lead, and two dummy electrode portions.
  • the layer and the active layer (shown schematically by reference numeral 9) are formed. The above several layers are superposed on each other, so that the induced discharge region forms a structure similar to a thin film transistor, and becomes a high-emission region of ESD.
  • ESD can be induced to occur at the induced discharge region, that is, the static electricity in the nearby region is released at the induced discharge region. This indirectly reduces the probability of ESD occurrence in the actual active lead area. Since the induced discharge region is a dummy electrode portion, the electrostatic discharge at the region does not cause damage to the effective lead portion. For example, if the electrostatic discharge at the induced discharge region causes the dummy electrode portion connected to the gate lead or the source/drain layer lead to be broken, this does not affect the normal operation of the actual effective lead of the surrounding region.
  • the virtual electrode portion at the virtual discharge region may have a shape with a pointed end.
  • it may be a triangle, a rectangle, a prism, or the like.
  • the dummy electrode portion may be two mutually parallel lines (including one line connected to the gate lead 3 and another line in the same layer as the source/drain layer lead), and the two lines are sufficiently thin and close enough To become an ESD high-incidence zone, as schematically illustrated in FIG.
  • the dummy electrode portion 7 connected to the gate lead 3 and the dummy electrode portion 8 in the same layer as the drain-source layer lead 4 may have different shapes. Although the dummy electrode portions 7 and 8 are superposed on each other in FIG.
  • the object of the present invention can be achieved in that the dummy electrode portions 7 and 8 are partially superposed or close to each other.
  • the dummy electrode portion at the virtual discharge region has a finer structure than the actual effective leads around.
  • the insulating layer and the active layer 9 at the dummy discharge region shown in FIG. 4 are of an exemplary shape, which may also be the same or similar shape as the dummy electrode portion or sandwiched between two layers of dummy electrode portions. Any other shape between.
  • the virtual electrode portion has a weakened region that is susceptible to breakage in the event of an ESD event.
  • the weak region can be directly broken, that is, blown, when the ESD event occurs in the induced discharge region, thereby minimizing the influence of the ESD event.
  • the above virtual discharge area is not necessarily only one, and it may be distributed at various idle positions in the drive circuit area as needed.
  • Fig. 6 is a view schematically showing a method of manufacturing an array substrate according to the present invention.
  • a substrate is provided.
  • a gate electrode layer and a gate lead connected to the gate electrode layer are formed on the substrate.
  • an insulating layer is formed on the substrate on which the gate electrode layer and the gate lead are formed, the insulating layer covering the gate electrode layer and the gate lead.
  • an active layer is formed on the insulating layer.
  • a source/drain electrode layer and a source/drain layer lead are formed on the substrate, wherein the active layer does not cover a region where the gate lead and the source/drain layer lead cross each other.
  • the manufacturing method further includes the additional step of forming an induced discharge region in a free region around the gate lead and the source/drain layer leads, wherein Forming a dummy electrode portion connected to the gate lead at the induced discharge region while forming the gate lead, and forming and the source in the induced discharge region while forming the source/drain layer lead
  • the drain layer leads the dummy electrode portion of the same layer, and an insulating layer and an active layer are formed between the two kinds of dummy electrode portions.
  • the manufacturing method further includes a subsequent step of forming a passivation layer or the like. These subsequent steps are not the focus of the present invention, and a detailed description thereof will be omitted herein.

Abstract

一种阵列基板及其制造方法以及包括该阵列基板的显示装置。其中阵列包括显示区（1）和驱动电路区（2），所述驱动电路区（2）包括GOA单元，所述GOA单元包括基板、栅电极层、绝缘层（5）、有源层和源漏电极层，并且所述驱动电路区（2）还包括连接到所述栅电极层的栅极引线（3）以及位于与所述源漏电极层同一层的源漏层引线（4），其中在所述栅极引线（3）和所述源漏层引线（4）中相互交叉的部分之间仅形成有所述绝缘层（5）。

Description

阵列基板及其制造方法以及包括其的显示装置 技术领域
本发明涉及TFT基板上的GOA单元的布局设计的领域，并特别涉及阵列基板及其制造方法以及包括其的显示装置。
背景技术
GOA(即Gate driver On Array或(Gate On Array)技术TFT-LCD中的一种设计，其将LCD面板的栅极驱动电路集成在基板上，从而提高了LCD面板的集成度，减少了栅极驱动IC的使用率，由此得到广泛运用。而现有技术中的TFT(薄膜晶体管)基板上的GOA存在一些问题，其中发现在GOA电路中经常发生静电放电(ESD)不良，即由于ESD引发GOA电路静电击穿，降低了TFT基板的良品率。而ESD不良是多种ADS产品中异常显示(Abnormal Display)的主要问题，不良率高达4％。
在常规的显示基板中，显示区与GOA电路驱动区域是由栅源漏极电路连接而成(其统称为显示区)，外部信号通过金属引线传入显示区，驱动显示区域工作。发明人经过不断的研究，从不良品中发现显示区与驱动信号区连接的区域，也就是栅极的金属线与连接到源漏极的金属线相互交叉的区域容易发生ESD而造成静电击穿，即该区域是电路中最薄弱的区域。其原因在于高PPI、窄边框等要求导致的布线紧密、半导体垫层和栅极尖端结构等因素。因此，需要一种能够克服以上技术问题的改进的GOA布局设计。
发明内容
鉴于现有技术的技术缺陷，本发明提出了改进的GOA电路设计，其解决了上文中提到的GOA静电放电问题，降低了显示面板由于ESD导致异常的几率。具体地，由于半导体垫层在引线中主要是起到栅源垫层爬坡作用，无开关作用，但因半导体材质在高温情况下，导电性能会增加，是诱发静电的关键。但是产品制程中，膜层沉积工艺都是高温进行，最低温度在120°，最高温度达360°，其是膜层沉积的重要步骤，不能更改。因此本发明通过更改高发因素中的半导体垫层，并且因此将与显示区域和GOA单元相连的驱动电路区中的有源层(即非 晶硅)去除，来降低静电高发几率。
根据本发明的一方面，本发明提出了一种阵列基板，包括显示区和驱动电路区，所述驱动电路区包括GOA单元，所述GOA单元包括基板、栅电极层、绝缘层、有源层和源漏电极层，并且所述驱动电路区还包括连接到所述栅电极层的栅极引线以及位于与所述源漏电极层同一层的源漏层引线，其中在所述栅极引线和所述源漏层引线中相互交叉的部分之间仅形成有所述绝缘层。根据该技术方案，在栅极引线和源漏层引线相互交叉的区域之间不具有有源层，即不具有半导体材料层，从而消除了这个区域变成薄膜晶体管开关的可能性，由此大大降低了在该区域中发生ESD的几率。
根据优选实施例，所述引线中相互交叉的部分相对于周围区域的引线更宽。这进一步降低了在该部分发生ESD的几率。
根据优选实施例，在所述引线相互交叉的区域旁边的空闲区域中，形成有诱导放电区，在所述诱导放电区中形成有与所述源漏层引线同层的虚拟电极部分和连接到所述栅极引线的虚拟电极部分以及形成在所述两层虚拟电极部分之间的绝缘层和有源层。该优选实施例将周边有效区域中可能存在的静电诱导到该诱导放电区进行ESD，从而进一步降低了在有效工作区域中发生ESD的几率。
根据优选实施例，所述虚拟电极部分具有带有尖端的形状。带有尖端的虚拟电极部分可以进一步促进发生ESD。根据进一步优选实施例，所述虚拟电极部分具有三角形、矩形或棱形的形状。
根据优选实施例，与所述源漏层引线同层的虚拟电极部分和连接到所述栅极引线的虚拟电极部分是两条大致平行延伸的线，而两条所述线之间的间距足够小以诱发ESD放电。
根据优选实施例，所述虚拟电极部分中具有薄弱区域，所述薄弱区域易于在发生ESD事件时断裂。该优选实施例通过在虚拟电极部分中设置薄弱区域，从而可以在诱导放电区发生ESD事件时，使该薄弱区域直接断裂，即被烧断，从而将ESD事件的影响最小化。
根据本发明的另一方面，提供了一种阵列基板的制造方法，包括：提供基板；在所述基板上形成栅电极层以及连接到所述栅电极层的栅极引线；在形成有所述栅电极层和栅极引线的所述基板上形成绝缘层，所述绝缘层覆盖所述栅电极层以及所述栅极引线；在所述绝缘层上形 成有源层；以及在所述基板形成源漏电极层和源漏层引线，其中所述有源层未覆盖所述栅极引线和源漏层引线相互交叉的区域。
根据优选实施例，该方法还包括：在所述栅极引线和源漏层引线周围的空闲区域中形成诱导放电区，其中在形成所述栅极引线的同时在所述诱导放电区处形成连接到所述栅极引线的虚拟电极部分，并且在形成所述源漏层引线的同时在所述诱导放电区形成与所述源漏层引线同层的虚拟电极部分，并且在上述两种虚拟电极部分之间形成所述绝缘层和所述有源层。
根据优选实施例，所述有源层由a-Si和N+a-Si两层材料层构成。
根据优选实施例，该方法还包括形成钝化层的步骤。
根据本发明的另一方面，还提供了一种显示装置，其包括如上文所述的阵列基板。
本发明通过更改GOA单元设计，特别是改进了引线区中的交叉部分的设计，从而降低ESD发生率。
附图说明
包括附图以提供对实施例的进一步理解并且附图被并入本说明书中并且构成本说明书的一部分。附图图示了实施例并且与描述一起用于解释实施例的原理。将容易认识到其它实施例和实施例的很多预期优点，因为通过引用以下详细描述，它们变得被更好地理解。附图的元件不一定是相互按照比例的。同样的参考数字指代对应的类似部件。
图1图示了一般的用于显示面板的阵列基板的布局示意图；
图2图示了现有技术的阵列基板中的驱动电路区的示意性平面图；
图3图示了根据图2中的箭头A-A截取的现有技术的阵列基板中的驱动电路区的示意性部分截面图；
图4图示了根据本发明的阵列基板中的驱动电路区的示意性平面图；
图5图示了根据图4中的箭头A-A截取的根据本发明的阵列基板中的驱动电路区的示意性部分截面图；以及
图6图示了根据本发明的阵列基板的制造方法，其中图示了几个基本步骤。
具体实施方式
在以下详细描述中，参考附图，该附图形成详细描述的一部分，并且通过其中可实践本发明的说明性具体实施例来示出。对此，参考描述的图的取向来使用方向术语，例如“顶”、“底”、“左”、“右”、“上”、“下”等。因为实施例的部件可被定位于若干不同取向中，为了图示的目的使用方向术语并且方向术语绝非限制。应当理解的是，可以利用其他实施例或可以做出逻辑改变，而不背离本发明的范围。因此以下详细描述不应当在限制的意义上被采用，并且本发明的范围由所附权利要求来限定。
此外，关于形成或定位在表面“之上”的部分、元件或材料层使用的词语“之上”可以在本文被用于表示该部分、元件或材料层“直接在”暗示的表面上定位(例如放置、形成、沉积等)，例如与其直接接触。关于形成或定位在表面“之上”的部分、元件或材料层使用的词语“之上”可以在本文被用于表示该部分、元件或材料层被定位(例如放置、形成、沉积等)为“间接在”所暗示的表面上，而具有被布置在所暗示的表面和该部分、元件或材料层之间的一个或多个附加部分、元件或层。
应当理解的是，本文描述的各个示例性实施例的特征可以相互组合，除非特别另外指出。
图1图示了一般的用于显示面板的阵列基板的布局示意图。由图1可看出，该阵列基板包括显示区1和驱动电路区2。显示区1内包含栅极、源漏极、绝缘层、有源层，也称为像素显示区域。在显示区1以外部分称为驱动电路区2。该驱动电路区2中布置有GOA单元以及将GOA单元连接到显示区的引线和输送外部信号的引线。该GOA单元主要是起到电路驱动作用，一般具有栅电极层、绝缘层、有源层和源漏电极层、钝化层等。其中栅电极层和漏源电极层一般由金属材料制成，而绝缘层一般由氮化硅或类似材料形成，有源层一般由半导体材料制成，如包括分别由a-Si和n+a-Si材料制成的两个层。
图2图示了现有技术的阵列基板中的驱动电路区的示意性平面图。该图2为图1中画图位置处的放大示意图。其中，显示区1中的栅极、源漏极连接GOA单元，3表示从显示区的像素引出的栅极金属线，通过过孔、跳线连接到GOA单元。驱动电路区2具有连接到GOA单元 中的栅电极层的栅极引线3，以及与源漏电极层同层的源漏层引线4。而由于栅极引线3和源漏层引线4之间在高度上存在差别，因而两者相互交叉的时候需要在两者之间设置垫层(或称为爬坡层)，而为了简化工艺，本领域的常规做法是一般采用在GOA电路制作工艺中形成的栅极绝缘层5(其一般由氮化硅形成)和有源层6作为该垫层，这在图3中可清楚看出，图3图示了根据图2中的箭头A-A截取的现有技术的阵列基板中的驱动电路区的示意性部分截面图。然而，发明人发现在两种引线之间形成有源层(其包括非晶硅)的时候，有源层中的半导体材质在高温情况下，导电性能会增加，这是诱发静电的关键。从而当连接到栅极的金属线过细或者布局过密，与有源层中的非晶硅(即a-Si)叠加或非常接近时，易诱导接触放电或邻近放电，这常常导致栅极引线与源漏层引线之间的静电击穿，导致画面异常显示。图2中星标示意性标出容易发生ESD的薄弱位置，即ESD高发区。
图4图示了根据本发明的阵列基板中的驱动电路区的示意性平面图。从图4可看出，在栅极引线3与源漏层引线4之间仅存在绝缘层5，而并不形成有源层，从而在栅极引线3和源漏层引线4相互交叉的部分之间并不会由于有源层的存在而变成半导体开关，这很大程度上降低了在3和4相互交叉的位置处以及邻近位置处发生ESD的几率，从而将其变成非ESD高发区。这在图5的截面图(其示出了根据图4中的箭头A-A截取的根据本发明的阵列基板中的驱动电路区的示意性部分截面)中可更清楚看出。尽管在栅极引线3和源漏层引线4相互交叉的部分之间不存在有源层，但是其间还具有绝缘层5，绝缘层5仍然能够实现垫层的作用，因此并不影响栅极引线3和源漏层引线4之间的相互交叉，这同样在图5的截面图中可以清楚看出。而且，有源层6的去除并不需要增加额外的工序，仅需改进用于在基板上形成有源层6的掩模图形，从而该改进是成本低廉的。需要注意的是，尽管在图4中给出了虚拟放电区的两种示例，但是这两种示例仅为示例性形式，并不构成对本发明的限制。另外在图4和图5中示出的结构仅仅是示意性的，其元件之间的相互大小和结构可以根据实际情况而不同。
根据优选的实施例，该栅极引线3和源漏层引线4中相互交叉的部分可以比周围区域的引线更宽。这可进一步降低在交叉部分处发生ESD的几率。
另外，根据进一步的实施例，根据本发明的阵列基板还在驱动电路区中的空闲区域设置诱导放电区。该诱导放电区顾名思义就是主动诱导ESD发生的区域。其中，诱导放电区由连接到所述栅极引线的一层虚拟电极部分7、与所述源漏层引线同层的另一层虚拟电极部分8、以及两个虚拟电极部分之间形成的绝缘层和有源层(由附图标记9示意性示出)构成。上述几个层相互叠加，从而该诱导放电区形成了类似薄膜晶体管的结构，成为ESD高发区。而由于该ESD高发区设置在实际有效引线附近，所以能够诱导ESD在该诱导放电区处发生，即，使附近区域的静电在诱导放电区处释放。这间接降低了实际有效引线区域的ESD发生几率。而由于诱导放电区为虚拟电极部分，所以该区域处的静电放电并不会导致有效引线部分的损坏。例如该诱导放电区处的静电放电引起连接到栅极引线或源漏层引线的虚拟电极部分断路的话，这并不影响周围区域的实际有效引线的正常工作。
而根据优选的实施例，该虚拟放电区处的虚拟电极部分可以具有带有尖端的形状。例如其可以是三角形、矩形、棱形等形状。替代地，该虚拟电极部分可以是两条相互平行的线(其中包括连接到栅极引线3的一条线和与源漏层引线同层的另一条线)，而两条线足够细并且足够靠近以变成ESD高发区，如图4中示意性图示的那样。附加地，连接到栅极引线3的虚拟电极部分7和与漏源层引线4同层的虚拟电极部分8可以具有不同的形状。尽管在图4中示出了虚拟电极部分7和8两者相互叠加，但是在虚拟电极部分7和8相互部分叠加或相互靠近也能实现本发明的目的。优选地，该虚拟放电区处的虚拟电极部分具有比周围的实际有效引线更细密的结构。需要注意的是，图4中示出的虚拟放电区处的绝缘层和有源层9为示例性形状，其还可以是与虚拟电极部分相同或相似的形状或夹在两层虚拟电极部分之间的任何其它形状。
根据优选实施例，该虚拟电极部分中具有薄弱区域，所述薄弱区域易于在发生ESD事件时断裂。通过在虚拟电极部分中设置薄弱区域，从而可以在诱导放电区发生ESD事件时，使该薄弱区域直接断裂，即被烧断，从而将ESD事件的影响最小化。
当然，上述虚拟放电区不一定仅仅为一个，其可以根据需要分布在驱动电路区中的各个空闲位置处。
本领域技术人员清楚的是，阵列基板中的以上各个部件可以通过沉积、涂覆光刻胶、掩模曝光显影等步骤或其它本领域已知的工艺形成，这些工艺步骤不是本发明的重点，在此省略对其的具体描述。
图6示意性示出了根据本发明的阵列基板的制造方法。其中在步骤S1，提供基板。在步骤S2，在所述基板上形成栅电极层以及连接到所述栅电极层的栅极引线。在步骤S3，在形成有所述栅电极层和栅极引线的所述基板上形成绝缘层，所述绝缘层覆盖所述栅电极层以及所述栅极引线。在步骤S4，在所述绝缘层上形成有源层。在步骤S5，在所述基板形成源漏电极层和源漏层引线，其中所述有源层未覆盖所述栅极引线和源漏层引线相互交叉的区域。
以上步骤为根据本发明的阵列基板的制造方法的主要步骤。根据本发明的优选实施例，除了图上列出的步骤之外，该制造方法还包括以下附加步骤：在所述栅极引线和源漏层引线周围的空闲区域中形成诱导放电区，其中在形成所述栅极引线的同时在所述诱导放电区处形成连接到所述栅极引线的虚拟电极部分，并且在形成所述源漏层引线的同时在所述诱导放电区形成与所述源漏层引线同层的虚拟电极部分，并且在上述两种虚拟电极部分之间形成绝缘层和有源层。值得注意的是，在所述虚拟电极部分之间形成的绝缘层和有源层可以与在所述栅电极层上的绝缘层和有源层同时形成。另外，该制造方法还包括形成钝化层等后续步骤。这些后续步骤不是本发明的重点，在此省略对其的详细描述。
以上描述了本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。
在本申请的描述中，需要理解的是，术语“上”、“下”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。另外，尽管在方法权利要求中以一定顺序列出了各个步骤，但是这些步骤并不一定以所列出的步骤来执行，相反在不背离本发明的精神和主旨的情况下可以以相反或并行的方式执行。措词‘包 括’并不排除在权利要求未列出的元件或步骤的存在。元件前面的措词‘一’或‘一个’并不排除多个这样的元件的存在。在相互不同从属权利要求中记载某些措施的简单事实不表明这些措施的组合不能被用于改进。在权利要求中的任何参考符号不应当被解释为限制范围。

Claims (12)

  1. 一种阵列基板，包括显示区和驱动电路区，所述驱动电路区中包括GOA单元和将所述GOA单元连接到所述显示区的引线，所述GOA单元包括基板、栅电极层、绝缘层、有源层和源漏电极层，并且所述驱动电路区包括连接到所述栅电极层的栅极引线以及位于与所述源漏电极层同一层的源漏层引线，其中在所述栅极引线和所述源漏层引线中相互交叉的部分之间仅形成有所述绝缘层。
  2. 根据权利要求1所述的阵列基板，其中所述引线中相互交叉的部分相对于周围区域的引线更宽。
  3. 根据权利要求1所述的阵列基板，其中在所述引线相互交叉的区域旁边的空闲区域中，形成有诱导放电区，在所述诱导放电区中形成有与所述源漏层引线同层的虚拟电极部分和连接到所述栅极引线的虚拟电极部分以及形成在所述两层虚拟电极部分之间的绝缘层和有源层。
  4. 根据权利要求3所述的阵列基板，其中所述虚拟电极部分具有带有尖端的形状。
  5. 根据权利要求4所述的阵列基板，其中所述虚拟电极部分具有三角形、矩形或棱形的形状。
  6. 根据权利要求3所述的阵列基板，其中与所述源漏层引线同层的虚拟电极部分和连接到所述栅极引线的虚拟电极部分是两条大致平行延伸的线，而两条所述线之间的间距足够小以诱发ESD放电。
  7. 根据权利要求3到6中的任一项所述的阵列基板，其中所述虚拟电极部分中具有薄弱区域，所述薄弱区域易于在发生ESD事件时断裂。
  8. 一种阵列基板的制造方法，包括：
    提供基板；
    在所述基板上形成栅电极层以及连接到所述栅电极层的栅极引线；
    在形成有所述栅电极层和栅极引线的所述基板上形成绝缘层，所述绝缘层覆盖所述栅电极层以及所述栅极引线；
    在所述绝缘层上形成有源层；以及
    在所述基板形成源漏电极层和源漏层引线，其中所述有源层未覆盖所述栅极引线和源漏层引线相互交叉的区域。
  9. 根据权利要求8所述的制造方法，其中还包括：
    在所述栅极引线和源漏层引线周围的空闲区域中形成诱导放电区，其中在形成所述栅极引线的同时在所述诱导放电区处形成连接到所述栅极引线的虚拟电极部分，并且在形成所述源漏层引线的同时在所述诱导放电区形成与所述源漏层引线同层的虚拟电极部分，并且在上述两种虚拟电极部分之间形成所述绝缘层和所述有源层。
  10. 根据权利要求8或9所述的制造方法，其中所述有源层由a-Si和N+a-Si两层材料层构成。
  11. 根据权利要求8所述的制造方法，其中还包括形成钝化层的步骤。
  12. 一种显示装置，其包括如权利要求1-7中的任一项所述的阵列基板。
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