CN105093751A - 预防esd的goa布局设计 - Google Patents

预防esd的goa布局设计 Download PDF

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CN105093751A
CN105093751A CN201510506313.9A CN201510506313A CN105093751A CN 105093751 A CN105093751 A CN 105093751A CN 201510506313 A CN201510506313 A CN 201510506313A CN 105093751 A CN105093751 A CN 105093751A
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layer
lead
source
dummy electrodes
drain
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CN105093751B (zh
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肖志莲
赵海生
刘冲
彭志龙
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BOE Technology Group Co Ltd
Beijing BOE Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Beijing BOE Optoelectronics Technology Co Ltd
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Priority to US15/122,888 priority patent/US9837448B2/en
Priority to PCT/CN2016/071592 priority patent/WO2017028495A1/zh
Priority to EP16754164.8A priority patent/EP3339948B1/en
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Abstract

预防ESD的GOA布局设计，本发明涉及一种阵列基板，包括显示区和驱动电路区，所述驱动电路区包括GOA单元，所述GOA单元包括基板、栅电极层、绝缘层、有源层和源漏电极层，并且所述驱动电路区还包括连接到所述栅电极层的栅极引线以及位于与所述源漏电极层同一层的源漏层引线，其中在所述栅极引线和所述源漏层引线中相互交叉的部分之间仅形成有所述绝缘层。本发明还涉及一种阵列基板的制造方法以及一种包括该阵列基板的显示装置。

Description

预防ESD的GOA布局设计
技术领域
本发明涉及TFT基板上的GOA单元的布局设计的领域，并特别涉及TFT基板上的GOA单元处的静电放电（ESD）预防的领域。
背景技术
GOA（即GatedriverOnArray或（GateOnArray）技术TFT-LCD中的一种设计，其将LCD面板的栅极驱动电路集成在基板上，从而提高了LCD面板的集成度，减少了栅极驱动IC的使用率，由此得到广泛运用。而现有技术中的TFT（薄膜晶体管）基板上的GOA存在一些问题，其中发现在GOA电路中经常发生静电放电（ESD）不良，即由于ESD引发GOA电路静电击穿，降低了TFT基板的良品率。而ESD不良是多种ADS产品中异常显示（AbnormalDisplay）的主要问题，不良率高达4%。
在常规的显示基板中，显示区与GOA电路驱动区域是由栅源漏极电路连接而成（其统称为显示区），外部信号通过金属引线传入显示区，驱动显示区域工作。发明人经过不断的研究，从不良品中发现显示区与驱动信号区连接的区域,也就是栅极的金属线与连接到源漏极的金属线相互交叉的区域容易发生ESD而造成静电击穿，即该区域是电路中最薄弱的区域。其原因在于高PPI、窄边框等要求导致的布线紧密、半导体垫层和栅极尖端结构等因素。因此，需要一种能够克服以上技术问题的改进的GOA布局设计。
发明内容
鉴于现有技术的技术缺陷，本发明提出了改进的GOA电路设计，其解决了上文中提到的GOA静电放电问题，降低了显示面板由于ESD导致异常的几率。具体地，由于半导体垫层在引线中主要是起到栅源垫层爬坡作用，无开关作用，但因半导体材质在高温情况下，导电性能会增加，是诱发静电的关键。但是产品制程中，膜层沉积工艺都是高温进行，最低温度在120°，最高温度达360°,其是膜层沉积的重要步骤，不能更改。因此本发明通过更改高发因素中的半导体垫层，并且因此将与显示区域和GOA单元相连的驱动电路区中的有源层（即非晶硅）去除，来降低静电高发几率。
根据本发明的一方面，本发明提出了一种阵列基板，包括显示区和驱动电路区，所述驱动电路区包括GOA单元，所述GOA单元包括基板、栅电极层、绝缘层、有源层和源漏电极层，并且所述驱动电路区还包括连接到所述栅电极层的栅极引线以及位于与所述源漏电极层同一层的源漏层引线，其中在所述栅极引线和所述源漏层引线中相互交叉的部分之间仅形成有所述绝缘层。根据该技术方案，在栅极引线和源漏层引线相互交叉的区域之间不具有有源层，即不具有半导体材料层，从而消除了这个区域变成薄膜晶体管开关的可能性，由此大大降低了在该区域中发生ESD的几率。
根据优选实施例，所述引线中相互交叉的部分相对于周围区域的引线更宽。这进一步降低了在该部分发生ESD的几率。
根据优选实施例，在所述引线相互交叉的区域旁边的空闲区域中，形成有诱导放电区，在所述诱导放电区中形成有与所述源漏层引线同层的虚拟电极部分和连接到所述栅极引线的虚拟电极部分以及形成在所述两层虚拟电极部分之间的绝缘层和有源层。该优选实施例将周边有效区域中可能存在的静电诱导到该诱导放电区进行ESD，从而进一步降低了在有效工作区域中发生ESD的几率。
根据优选实施例，所述虚拟电极部分具有带有尖端的形状。带有尖端的虚拟电极部分可以进一步促进发生ESD。根据进一步优选实施例，所述虚拟电极部分具有三角形、矩形或棱形的形状。
根据优选实施例，与所述源漏层引线同层的虚拟电极部分和连接到所述栅极引线的虚拟电极部分是两条大致平行延伸的线，而两条所述线之间的间距足够小以诱发ESD放电。
根据优选实施例，所述虚拟电极部分中具有薄弱区域，所述薄弱区域易于在发生ESD事件时断裂。该优选实施例通过在虚拟电极部分中设置薄弱区域，从而可以在诱导放电区发生ESD事件时，使该薄弱区域直接断裂，即被烧断，从而将ESD事件的影响最小化。
根据本发明的另一方面，提供了一种阵列基板的制造方法，包括：提供基板；在所述基板上形成栅电极层以及连接到所述栅电极层的栅极引线；在形成有所述栅电极层和栅极引线的所述基板上形成绝缘层，所述绝缘层覆盖所述栅电极层以及所述栅极引线；在所述绝缘层上形成有源层；以及在所述基板形成源漏电极层和源漏层引线，其中所述有源层未覆盖所述栅极引线和源漏层引线相互交叉的区域。
根据优选实施例，该方法还包括：在所述栅极引线和源漏层引线周围的空闲区域中形成诱导放电区，其中在形成所述栅极引线的同时在所述诱导放电区处形成连接到所述栅极引线的虚拟电极部分，并且在形成所述源漏层引线的同时在所述诱导放电区形成与所述源漏层引线同层的虚拟电极部分，并且在上述两种虚拟电极部分之间形成所述绝缘层和所述有源层。
根据优选实施例，所述有源层由a-Si和N+a-Si两层材料层构成。
根据优选实施例，该方法还包括形成钝化层的步骤。
根据本发明的另一方面，还提供了一种显示装置，其包括如上文所述的阵列基板。
本发明通过更改GOA单元设计，特别是改进了引线区中的交叉部分的设计，从而降低ESD发生率。
附图说明
包括附图以提供对实施例的进一步理解并且附图被并入本说明书中并且构成本说明书的一部分。附图图示了实施例并且与描述一起用于解释实施例的原理。将容易认识到其它实施例和实施例的很多预期优点，因为通过引用以下详细描述，它们变得被更好地理解。附图的元件不一定是相互按照比例的。同样的参考数字指代对应的类似部件。
图1图示了一般的用于显示面板的阵列基板的布局示意图；
图2图示了现有技术的阵列基板中的驱动电路区的示意性平面图；
图3图示了根据图2中的箭头A-A截取的现有技术的阵列基板中的驱动电路区的示意性部分截面图；
图4图示了根据本发明的阵列基板中的驱动电路区的示意性平面图；
图5图示了根据图4中的箭头A-A截取的根据本发明的阵列基板中的驱动电路区的示意性部分截面图；以及
图6图示了根据本发明的阵列基板的制造方法，其中图示了几个基本步骤。
具体实施方式
在以下详细描述中，参考附图，该附图形成详细描述的一部分，并且通过其中可实践本发明的说明性具体实施例来示出。对此，参考描述的图的取向来使用方向术语，例如“顶”、“底”、“左”、“右”、“上”、“下”等。因为实施例的部件可被定位于若干不同取向中，为了图示的目的使用方向术语并且方向术语绝非限制。应当理解的是，可以利用其他实施例或可以做出逻辑改变，而不背离本发明的范围。因此以下详细描述不应当在限制的意义上被采用，并且本发明的范围由所附权利要求来限定。
此外，关于形成或定位在表面“之上”的部分、元件或材料层使用的词语“之上”可以在本文被用于表示该部分、元件或材料层“直接在”暗示的表面上定位（例如放置、形成、沉积等），例如与其直接接触。关于形成或定位在表面“之上”的部分、元件或材料层使用的词语“之上”可以在本文被用于表示该部分、元件或材料层被定位（例如放置、形成、沉积等）为“间接在”所暗示的表面上，而具有被布置在所暗示的表面和该部分、元件或材料层之间的一个或多个附加部分、元件或层。
应当理解的是，本文描述的各个示例性实施例的特征可以相互组合，除非特别另外指出。
图1图示了一般的用于显示面板的阵列基板的布局示意图。由图1可看出，该阵列基板包括显示区1和驱动电路区2。显示区1内包含栅极、源漏极、绝缘层、有源层，也称为像素显示区域。在显示区1以外部分称为驱动电路区2。该驱动电路区2中布置有GOA单元以及将GOA单元连接到显示区的引线和输送外部信号的引线。该GOA单元主要是起到电路驱动作用，一般具有栅电极层、绝缘层、有源层和源漏电极层、钝化层等。其中栅电极层和漏源电极层一般由金属材料制成，而绝缘层一般由氮化硅或类似材料形成，有源层一般由半导体材料制成，如包括分别由a-Si和n+a-Si材料制成的两个层。
图2图示了现有技术的阵列基板中的驱动电路区的示意性平面图。该图2为图1中画圈位置处的放大示意图。其中，显示区1中的栅极、源漏极连接GOA单元，3表示从显示区的像素引出的栅极金属线，通过过孔、跳线连接到GOA单元。驱动电路区2具有连接到GOA单元中的栅电极层的栅极引线3，以及与源漏电极层同层的源漏层引线4。而由于栅极引线3和源漏层引线4之间在高度上存在差别，因而两者相互交叉的时候需要在两者之间设置垫层（或称为爬坡层），而为了简化工艺，本领域的常规做法是一般采用在GOA电路制作工艺中形成的栅极绝缘层5（其一般由氮化硅形成）和有源层6作为该垫层，这在图3中可清楚看出，图3图示了根据图2中的箭头A-A截取的现有技术的阵列基板中的驱动电路区的示意性部分截面图。然而，发明人发现在两种引线之间形成有源层（其包括非晶硅）的时候，有源层中的半导体材质在高温情况下，导电性能会增加，这是诱发静电的关键。从而当连接到栅极的金属线过细或者布局过密，与有源层中的非晶硅（即a-Si）叠加或非常接近时，易诱导接触放电或邻近放电，这常常导致栅极引线与源漏层引线之间的静电击穿，导致画面异常显示。图2中星标示意性标出容易发生ESD的薄弱位置，即ESD高发区。
图4图示了根据本发明的阵列基板中的驱动电路区的示意性平面图。从图4可看出，在栅极引线3与源漏层引线4之间仅存在绝缘层5，而并不形成有源层，从而在栅极引线3和源漏层引线4相互交叉的部分之间并不会由于有源层的存在而变成半导体开关，这很大程度上降低了在3和4相互交叉的位置处以及邻近位置处发生ESD的几率，从而将其变成非ESD高发区。这在图5的截面图（其示出了根据图4中的箭头A-A截取的根据本发明的阵列基板中的驱动电路区的示意性部分截面）中可更清楚看出。尽管在栅极引线3和源漏层引线4相互交叉的部分之间不存在有源层，但是其间还具有绝缘层5，绝缘层5仍然能够实现垫层的作用，因此并不影响栅极引线3和源漏层引线4之间的相互交叉，这同样在图5的截面图中可以清楚看出。而且，有源层6的去除并不需要增加额外的工序，仅需改进用于在基板上形成有源层6的掩模图形，从而该改进是成本低廉的。需要注意的是，尽管在图4中给出了虚拟放电区的两种示例，但是这两种示例仅为示例性形式，并不构成对本发明的限制。另外在图4和图5中示出的结构仅仅是示意性的，其元件之间的相互大小和结构可以根据实际情况而不同。
根据优选的实施例，该栅极引线3和源漏层引线4中相互交叉的部分可以比周围区域的引线更宽。这可进一步降低在交叉部分处发生ESD的几率。
另外，根据进一步的实施例，根据本发明的阵列基板还在驱动电路区中的空闲区域设置诱导放电区。该诱导放电区顾名思义就是主动诱导ESD发生的区域。其中，诱导放电区由连接到所述栅极引线的一层虚拟电极部分7、与所述源漏层引线同层的另一层虚拟电极部分8、以及两个虚拟电极部分之间形成的绝缘层和有源层（由附图标记9示意性示出）构成。上述几个层相互叠加，从而该诱导放电区形成了类似薄膜晶体管的结构，成为ESD高发区。而由于该ESD高发区设置在实际有效引线附近，所以能够诱导ESD在该诱导放电区处发生，即，使附近区域的静电在诱导放电区处释放。这间接降低了实际有效引线区域的ESD发生几率。而由于诱导放电区为虚拟电极部分，所以该区域处的静电放电并不会导致有效引线部分的损坏。例如该诱导放电区处的静电放电引起连接到栅极引线或源漏层引线的虚拟电极部分断路的话，这并不影响周围区域的实际有效引线的正常工作。
而根据优选的实施例，该虚拟放电区处的虚拟电极部分可以具有带有尖端的形状。例如其可以是三角形、矩形、棱形等形状。替代地，该虚拟电极部分可以是两条相互平行的线（其中包括连接到栅极引线3的一条线和与源漏层引线同层的另一条线），而两条线足够细并且足够靠近以变成ESD高发区，如图4中示意性图示的那样。附加地，连接到栅极引线3的虚拟电极部分7和与漏源层引线4同层的虚拟电极部分8可以具有不同的形状。尽管在图4中示出了虚拟电极部分7和8两者相互叠加，但是在虚拟电极部分7和8相互部分叠加或相互靠近也能实现本发明的目的。优选地，该虚拟放电区处的虚拟电极部分具有比周围的实际有效引线更细密的结构。需要注意的是，图4中示出的虚拟放电区处的绝缘层和有源层9为示例性形状，其还可以是与虚拟电极部分相同或相似的形状或夹在两层虚拟电极部分之间的任何其它形状。
根据优选实施例，该虚拟电极部分中具有薄弱区域，所述薄弱区域易于在发生ESD事件时断裂。通过在虚拟电极部分中设置薄弱区域，从而可以在诱导放电区发生ESD事件时，使该薄弱区域直接断裂，即被烧断，从而将ESD事件的影响最小化。
当然，上述虚拟放电区不一定仅仅为一个，其可以根据需要分布在驱动电路区中的各个空闲位置处。
本领域技术人员清楚的是，阵列基板中的以上各个部件可以通过沉积、涂覆光刻胶、掩模曝光显影等步骤或其它本领域已知的工艺形成，这些工艺步骤不是本发明的重点，在此省略对其的具体描述。
图6示意性示出了根据本发明的阵列基板的制造方法。其中在步骤S1，提供基板。在步骤S2，在所述基板上形成栅电极层以及连接到所述栅电极层的栅极引线。在步骤S3，在形成有所述栅电极层和栅极引线的所述基板上形成绝缘层，所述绝缘层覆盖所述栅电极层以及所述栅极引线。在步骤S4，在所述绝缘层上形成有源层。在步骤S5，在所述基板形成源漏电极层和源漏层引线，其中所述有源层未覆盖所述栅极引线和源漏层引线相互交叉的区域。
以上步骤为根据本发明的阵列基板的制造方法的主要步骤。根据本发明的优选实施例，除了图上列出的步骤之外，该制造方法还包括以下附加步骤：在所述栅极引线和源漏层引线周围的空闲区域中形成诱导放电区，其中在形成所述栅极引线的同时在所述诱导放电区处形成连接到所述栅极引线的虚拟电极部分，并且在形成所述源漏层引线的同时在所述诱导放电区形成与所述源漏层引线同层的虚拟电极部分，并且在上述两种虚拟电极部分之间形成绝缘层和有源层。值得注意的是，在所述虚拟电极部分之间形成的绝缘层和有源层可以与在所述栅电极层上的绝缘层和有源层同时形成。另外，该制造方法还包括形成钝化层等后续步骤。这些后续步骤不是本发明的重点，在此省略对其的详细描述。
以上描述了本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。
在本申请的描述中，需要理解的是，术语“上”、“下”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。另外，尽管在方法权利要求中以一定顺序列出了各个步骤，但是这些步骤并不一定以所列出的步骤来执行，相反在不背离本发明的精神和主旨的情况下可以以相反或并行的方式执行。措词‘包括’并不排除在权利要求未列出的元件或步骤的存在。元件前面的措词‘一’或‘一个’并不排除多个这样的元件的存在。在相互不同从属权利要求中记载某些措施的简单事实不表明这些措施的组合不能被用于改进。在权利要求中的任何参考符号不应当被解释为限制范围。

Claims (12)

1.一种阵列基板，包括显示区和驱动电路区，所述驱动电路区中包括GOA单元和将所述GOA单元连接到所述显示区的引线，所述GOA单元包括基板、栅电极层、绝缘层、有源层和源漏电极层，并且所述驱动电路区包括连接到所述栅电极层的栅极引线以及位于与所述源漏电极层同一层的源漏层引线，其中在所述栅极引线和所述源漏层引线中相互交叉的部分之间仅形成有所述绝缘层。
2.根据权利要求1所述的阵列基板，其中所述引线中相互交叉的部分相对于周围区域的引线更宽。
3.根据权利要求1所述的阵列基板，其中在所述引线相互交叉的区域旁边的空闲区域中，形成有诱导放电区，在所述诱导放电区中形成有与所述源漏层引线同层的虚拟电极部分和连接到所述栅极引线的虚拟电极部分以及形成在所述两层虚拟电极部分之间的绝缘层和有源层。
4.根据权利要求3所述的阵列基板，其中所述虚拟电极部分具有带有尖端的形状。
5.根据权利要求4所述的阵列基板，其中所述虚拟电极部分具有三角形、矩形或棱形的形状。
6.根据权利要求3所述的阵列基板，其中与所述源漏层引线同层的虚拟电极部分和连接到所述栅极引线的虚拟电极部分是两条大致平行延伸的线，而两条所述线之间的间距足够小以诱发ESD放电。
7.根据权利要求3到6中的任一项所述的阵列基板，其中所述虚拟电极部分中具有薄弱区域，所述薄弱区域易于在发生ESD事件时断裂。
8.一种阵列基板的制造方法，包括：
提供基板；
在所述基板上形成栅电极层以及连接到所述栅电极层的栅极引线；
在形成有所述栅电极层和栅极引线的所述基板上形成绝缘层，所述绝缘层覆盖所述栅电极层以及所述栅极引线；
在所述绝缘层上形成有源层；以及
在所述基板形成源漏电极层和源漏层引线，其中所述有源层未覆盖所述栅极引线和源漏层引线相互交叉的区域。
9.根据权利要求8所述的制造方法，其中还包括：
在所述栅极引线和源漏层引线周围的空闲区域中形成诱导放电区，其中在形成所述栅极引线的同时在所述诱导放电区处形成连接到所述栅极引线的虚拟电极部分，并且在形成所述源漏层引线的同时在所述诱导放电区形成与所述源漏层引线同层的虚拟电极部分，并且在上述两种虚拟电极部分之间形成所述绝缘层和所述有源层。
10.根据权利要求8或9所述的制造方法，其中所述有源层由a-Si和N+a-Si两层材料层构成。
11.根据权利要求8所述的制造方法，其中还包括形成钝化层的步骤。
12.一种显示装置，其包括如权利要求1-7中的任一项所述的阵列基板。
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Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105549288A (zh) * 2016-03-04 2016-05-04 京东方科技集团股份有限公司 一种阵列基板及其制备方法、显示装置
WO2017028495A1 (zh) * 2015-08-18 2017-02-23 京东方科技集团股份有限公司 阵列基板及其制造方法以及包括其的显示装置
CN106526929A (zh) * 2016-12-30 2017-03-22 武汉华星光电技术有限公司 一种goa电路及阵列基板、液晶面板
CN106972029A (zh) * 2017-03-23 2017-07-21 武汉华星光电技术有限公司 一种包含单元屏的基板结构及清洗机静电防护方法
CN107452352A (zh) * 2017-08-30 2017-12-08 深圳市华星光电半导体显示技术有限公司 Goa阵列基板及显示面板
CN108717939A (zh) * 2018-06-01 2018-10-30 京东方科技集团股份有限公司 静电释放保护电路、阵列基板和显示装置
CN111367130A (zh) * 2020-04-27 2020-07-03 Tcl华星光电技术有限公司 阵列基板、显示面板及显示装置
US11037889B2 (en) 2019-02-22 2021-06-15 Innolux Corporation Display device
CN113437086A (zh) * 2020-03-18 2021-09-24 上海和辉光电有限公司 阵列基板及其制造方法和显示装置

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109449168B (zh) * 2018-11-14 2021-05-18 合肥京东方光电科技有限公司 导线结构及其制造方法、阵列基板和显示装置
CN112331676B (zh) * 2020-11-02 2022-07-26 厦门天马微电子有限公司 一种阵列基板、显示面板及显示装置
CN113161370B (zh) * 2021-02-26 2024-02-09 厦门天马微电子有限公司 阵列基板、显示面板和显示装置

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080185590A1 (en) * 2007-02-07 2008-08-07 Byoung-June Kim Thin Film Transistor Array Panel and Method for Manufacturing the Same
CN101826534A (zh) * 2009-03-05 2010-09-08 株式会社半导体能源研究所 半导体装置及其制造方法
KR20150067564A (ko) * 2013-12-10 2015-06-18 엘지디스플레이 주식회사 표시장치용 표시패널

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3714243B2 (ja) * 2001-12-11 2005-11-09 セイコーエプソン株式会社 半導体装置、電気光学装置、および電子機器
JP3920649B2 (ja) * 2002-01-31 2007-05-30 株式会社日立製作所 画像表示装置および液晶表示装置
JP5207163B2 (ja) * 2007-03-30 2013-06-12 Ｎｌｔテクノロジー株式会社 埋込配線の形成方法、表示装置用基板及び当該基板を有する表示装置
KR20100127290A (ko) * 2008-04-23 2010-12-03 가부시키가이샤 고베 세이코쇼 표시 장치용 Ａｌ 합금막, 표시 장치 및 스퍼터링 타깃
US8618863B2 (en) * 2010-03-24 2013-12-31 Sharp Kabushiki Kaisha Signal distribution circuit, signal distribution device, and display device
CN103018991B (zh) * 2012-12-24 2015-01-28 京东方科技集团股份有限公司 一种阵列基板及其制造方法、显示装置
CN103413811B (zh) * 2013-07-23 2016-04-13 北京京东方光电科技有限公司 阵列基板及其制造方法、显示装置
KR102089074B1 (ko) 2013-11-07 2020-03-13 엘지디스플레이 주식회사 표시패널용 어레이 기판 및 그 제조방법
CN103730473B (zh) 2013-12-25 2016-02-10 北京京东方光电科技有限公司 阵列基板及其制造方法、显示装置
KR102343892B1 (ko) * 2015-01-15 2021-12-27 삼성디스플레이 주식회사 가요성 표시 장치
CN104658973B (zh) 2015-02-28 2017-10-24 京东方科技集团股份有限公司 阵列基板及其制作方法、显示装置
US9581873B2 (en) * 2015-04-27 2017-02-28 Shenzhen China Star Optoelectronics Technology Co., Ltd. Gate driver on array circuit repair method
CN105093751B (zh) 2015-08-18 2018-09-11 京东方科技集团股份有限公司 预防esd的goa布局设计

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080185590A1 (en) * 2007-02-07 2008-08-07 Byoung-June Kim Thin Film Transistor Array Panel and Method for Manufacturing the Same
CN101826534A (zh) * 2009-03-05 2010-09-08 株式会社半导体能源研究所 半导体装置及其制造方法
KR20150067564A (ko) * 2013-12-10 2015-06-18 엘지디스플레이 주식회사 표시장치용 표시패널

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9991291B2 (en) 2015-08-18 2018-06-05 Boe Technology Group Co., Ltd. Array substrate and manufacturing method thereof and display apparatus
WO2017028495A1 (zh) * 2015-08-18 2017-02-23 京东方科技集团股份有限公司 阵列基板及其制造方法以及包括其的显示装置
US9837448B2 (en) 2015-08-18 2017-12-05 Boe Technology Group Co., Ltd. Array substrate and manufacturing method thereof and display apparatus
CN105549288A (zh) * 2016-03-04 2016-05-04 京东方科技集团股份有限公司 一种阵列基板及其制备方法、显示装置
CN105549288B (zh) * 2016-03-04 2021-03-02 京东方科技集团股份有限公司 一种阵列基板及其制备方法、显示装置
CN106526929A (zh) * 2016-12-30 2017-03-22 武汉华星光电技术有限公司 一种goa电路及阵列基板、液晶面板
CN106972029A (zh) * 2017-03-23 2017-07-21 武汉华星光电技术有限公司 一种包含单元屏的基板结构及清洗机静电防护方法
CN106972029B (zh) * 2017-03-23 2020-04-14 武汉华星光电技术有限公司 一种包含单元屏的基板结构及清洗机静电防护方法
CN107452352B (zh) * 2017-08-30 2020-03-27 深圳市华星光电半导体显示技术有限公司 Goa阵列基板及显示面板
CN107452352A (zh) * 2017-08-30 2017-12-08 深圳市华星光电半导体显示技术有限公司 Goa阵列基板及显示面板
CN108717939A (zh) * 2018-06-01 2018-10-30 京东方科技集团股份有限公司 静电释放保护电路、阵列基板和显示装置
CN108717939B (zh) * 2018-06-01 2020-06-12 京东方科技集团股份有限公司 静电释放保护电路、阵列基板和显示装置
US11037889B2 (en) 2019-02-22 2021-06-15 Innolux Corporation Display device
CN113437086A (zh) * 2020-03-18 2021-09-24 上海和辉光电有限公司 阵列基板及其制造方法和显示装置
CN111367130A (zh) * 2020-04-27 2020-07-03 Tcl华星光电技术有限公司 阵列基板、显示面板及显示装置

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