WO2017015981A1 - 一种多晶硅薄膜晶体管的制作方法 - Google Patents

一种多晶硅薄膜晶体管的制作方法 Download PDF

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WO2017015981A1
WO2017015981A1 PCT/CN2015/086251 CN2015086251W WO2017015981A1 WO 2017015981 A1 WO2017015981 A1 WO 2017015981A1 CN 2015086251 W CN2015086251 W CN 2015086251W WO 2017015981 A1 WO2017015981 A1 WO 2017015981A1
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Prior art keywords
photoresist
layer
film transistor
thin film
polysilicon
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PCT/CN2015/086251
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English (en)
French (fr)
Inventor
李子健
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武汉华星光电技术有限公司
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Publication of WO2017015981A1 publication Critical patent/WO2017015981A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a method for fabricating a polysilicon thin film transistor.
  • CMos Complementary Metal Oxide Semiconductor, Complementary Metal Oxide
  • LDD asymmetric lightly doped drain
  • a method for fabricating a polysilicon thin film transistor comprising:
  • the remaining photoresist is removed.
  • the step of forming a polysilicon layer on the glass substrate includes:
  • the amorphous silicon layer is subjected to an excimer laser annealing operation to form a polysilicon layer.
  • the method further includes:
  • Ion implantation is light dose B doping to form a channel.
  • the step of exposing and etching the photoresist by using a halftone mask reticle includes:
  • the semi-exposed photoresist is etched away.
  • the method further includes:
  • the remaining photoresist is removed.
  • the method further includes:
  • the method further includes:
  • Ions are implanted with low dose P doping to form N-.
  • the method further includes:
  • Ions are implanted with low dose P doping to form N-.
  • a method for fabricating a polysilicon thin film transistor includes:
  • Ions are implanted with high doses of B doping to form P+.
  • the step of forming a polysilicon layer on the glass substrate comprises:
  • the amorphous silicon layer is subjected to an excimer laser annealing operation to form a polysilicon layer.
  • the method further includes:
  • Ion implantation is light dose B doping to form a channel.
  • the step of exposing and etching the photoresist by using a halftone mask reticle comprises:
  • the semi-exposed photoresist is etched away.
  • the method further includes:
  • the remaining photoresist is removed.
  • the method further includes:
  • the B dose is lower than the high dose P.
  • the method further comprises:
  • the remaining photoresist is removed.
  • the method further includes:
  • Ions are implanted with low dose P doping to form N-.
  • the method further includes:
  • Ions are implanted with low dose P doping to form N-.
  • the present invention completes CMos (Complementary Metal) with two halftone masks.
  • Oxide Semiconductor, complementary metal oxide semiconductors and gates are defined and form LDDs. Therefore, the number of masks is reduced from 4 to 2, which greatly enhances the competitiveness; therefore, the manufacturing method of the polysilicon thin film transistor provided by the invention can effectively reduce the number of masks and effectively reduce the cost.
  • FIG. 1 is a schematic diagram showing an implementation process of a method for fabricating a polysilicon thin film transistor according to an embodiment of the present invention
  • FIG. 2 is a schematic flow chart showing an implementation process of a method for fabricating a polysilicon thin film transistor according to Embodiment 1 of the present invention
  • FIG. 3 is a schematic flow chart showing the implementation of a method for fabricating a polysilicon thin film transistor according to Embodiment 2 of the present invention
  • FIG. 4 is a schematic structural diagram of sequentially forming a buffer layer and a polysilicon layer on a glass substrate according to an embodiment of the present invention
  • FIG. 5 is a schematic structural diagram of ion implantation light dose B doping according to an embodiment of the present invention.
  • FIG. 6A and FIG. 6B are schematic diagrams showing the structure of coating a photoresist on a polysilicon layer according to an embodiment of the present invention
  • FIG. 7A and FIG. 7B are schematic diagrams showing the structure of etching away excess polysilicon according to an embodiment of the present invention.
  • FIG. 8A and FIG. 8B are schematic diagrams showing the structure of the photoresist 13 etched away from the half exposure according to an embodiment of the present invention
  • 9A and 9B are schematic diagrams showing the structure of ion implantation high dose P doping to form N+ according to an embodiment of the present invention.
  • FIG. 10A and FIG. 10B are schematic diagrams showing the structure of removing the remaining photoresist according to an embodiment of the present invention.
  • FIG. 11A and FIG. 11B are schematic diagrams showing the structure of forming an insulating layer and a gate layer according to an embodiment of the present invention.
  • FIG. 12A and FIG. 12B are schematic diagrams showing the structure of coating a photoresist on a gate layer according to an embodiment of the present invention
  • FIG. 13A and FIG. 13B are schematic diagrams showing the structure of etching away excess gates according to an embodiment of the present invention.
  • FIG. 14A and FIG. 14B are schematic diagrams showing the structure of ion implantation high dose B doping to form P+ according to an embodiment of the present invention
  • FIG. 15A and FIG. 15B are schematic diagrams showing the structure of etching a semi-exposed photoresist according to an embodiment of the present invention.
  • FIG. 16A and FIG. 16B are schematic diagrams showing the structure of etching exposed gates according to an embodiment of the present invention.
  • 17A and 17B are schematic diagrams showing the structure of ion implantation low dose P doping to form N- according to an embodiment of the present invention
  • FIG. 18A and FIG. 18B are schematic diagrams showing the structure of removing the remaining photoresist according to an embodiment of the present invention.
  • the present invention completes CMos (Complementary Metal) by using a two-tone halftone mask.
  • Oxide Semiconductor, complementary metal oxide semiconductors and gates are defined and form LDDs. Therefore, the number of masks is reduced from 4 to 2, which greatly enhances the competitiveness; therefore, the manufacturing method of the polysilicon thin film transistor provided by the invention can effectively reduce the number of masks and effectively reduce the cost.
  • FIG. 1 is a schematic diagram showing an implementation process of a method for fabricating a polysilicon thin film transistor according to an embodiment of the present invention; the method for fabricating the polysilicon thin film transistor mainly includes the following steps:
  • step S101 a glass substrate is provided, and a buffer layer and a polysilicon layer are sequentially formed on the glass substrate;
  • the step of forming a polysilicon layer on the glass substrate comprises:
  • the amorphous silicon layer is subjected to an excimer laser annealing operation to form a polysilicon layer.
  • step S102 a photoresist is coated on the polysilicon layer, and the photoresist is exposed and etched by using a halftone mask.
  • the step of exposing and etching the photoresist by using a halftone mask reticle comprises:
  • the semi-exposed photoresist is etched away.
  • step S103 IMP (IMPLANT, ion implantation) high dose P doping, forming N+;
  • step S104 an insulating layer and a gate layer are sequentially formed on the entire surface of the glass substrate;
  • the step of forming an insulating layer on the entire surface of the glass substrate comprises:
  • An insulating layer is deposited on the entire surface of the glass substrate by chemical vapor deposition.
  • the step of forming a gate layer on the entire surface of the glass substrate comprises:
  • a gate layer is deposited on the insulating layer by physical vapor deposition.
  • step S105 a photoresist is coated on the gate layer, and the photoresist is exposed by using a halftone mask.
  • step S106 the IMP ions are implanted with a high dose of B doping to form P+.
  • the B dose is lower than the high dose P to avoid the disappearance of N+.
  • FIG. 2 is a schematic flowchart showing the implementation of a method for fabricating a polysilicon thin film transistor according to Embodiment 1 of the present invention
  • step S201 a glass substrate is provided, and a buffer layer and a polysilicon layer are sequentially formed on the glass substrate;
  • the step of forming a polysilicon layer on the glass substrate comprises:
  • the amorphous silicon layer is subjected to an excimer laser annealing operation to form a polysilicon layer.
  • step S202 the IMP ion is implanted with a light dose B doping to form a channel
  • step S203 a photoresist is coated on the polysilicon layer, and the photoresist is exposed and etched by using a halftone mask.
  • the step of exposing and etching the photoresist by using a halftone mask reticle comprises:
  • the semi-exposed photoresist is etched away.
  • step S204 IMP ions are implanted with high dose P doping to form N+;
  • step S205 the remaining photoresist is removed
  • step S206 an insulating layer and a gate layer are sequentially formed on the entire surface of the glass substrate;
  • the step of forming an insulating layer on the entire surface of the glass substrate comprises:
  • An insulating layer is deposited on the entire surface of the glass substrate by chemical vapor deposition.
  • the step of forming a gate layer on the entire surface of the glass substrate comprises:
  • a gate layer is deposited on the insulating layer by physical vapor deposition.
  • step S207 a photoresist is coated on the gate layer, and the photoresist is exposed by using a halftone mask.
  • step S208 the excess gate is etched away
  • step S209 the IMP ions are implanted with a high dose of B doping to form P+.
  • the B dose is lower than the high dose P to avoid the disappearance of N+.
  • step S210 the semi-exposed photoresist is etched away
  • step S211 the exposed gate is etched away.
  • step S212 the remaining photoresist is removed.
  • step S213 the IMP ions are implanted with a low dose of P doping to form N-.
  • FIG. 3 is a schematic flowchart showing the implementation of a method for fabricating a polysilicon thin film transistor according to Embodiment 2 of the present invention
  • step S301 a glass substrate is provided, and a buffer layer and a polysilicon layer are sequentially formed on the glass substrate;
  • FIG. 4 is a schematic structural diagram of sequentially forming a buffer layer and a polysilicon layer on a glass substrate according to an embodiment of the present invention.
  • a buffer layer 11 is formed on the glass substrate 10, and then an amorphous silicon layer is formed on the buffer layer 11; an excimer laser annealing operation is performed on the amorphous silicon layer to form a polysilicon layer 12.
  • the step of forming a polysilicon layer on the glass substrate comprises:
  • the amorphous silicon layer is subjected to an excimer laser annealing operation to form a polysilicon layer.
  • step S302 the IMP ions are implanted with a light dose B doping to form a channel
  • FIG. 5 is a schematic structural diagram of ion implantation light dose B doping according to an embodiment of the present invention.
  • a small amount of boron is implanted by an ion implantation process for adjusting the TFT (Thin Film Transistor, the voltage of a thin film transistor.
  • TFT Thin Film Transistor
  • step S303 a photoresist is coated on the polysilicon layer, and the photoresist is exposed and etched by using a halftone mask.
  • FIG. 6A and FIG. 6B are schematic diagrams showing the structure of coating a photoresist on a polysilicon layer according to an embodiment of the invention.
  • a photoresist 13 is coated on the polysilicon layer 12, and then the photoresist 13 is exposed and etched using a halftone mask.
  • Cmos is composed of NTFT (N+) and PTFT (P+) on a glass substrate, and therefore, one of the TFTs is formed while the area of the other TFT is required to be blocked by the photoresist.
  • the pattern of the active layer NTFT and the PTFT is defined in the primary halftone mask reticle exposure development.
  • FIG. 7A and FIG. 7B are schematic diagrams showing the structure of etching away excess polysilicon according to an embodiment of the present invention.
  • the two TFTs on one glass substrate are simultaneously etched to remove excess polysilicon by an etching process to form active layer NTFT and PTFT patterns.
  • FIG. 8A and FIG. 8B are schematic diagrams showing the structure of the photoresist that is etched away from the half exposure according to an embodiment of the invention.
  • the photoresist pattern of FIGS. 8A and 8B is formed by using an ashing process (resistive etching) to uniformly thin the photoresist.
  • the step of exposing and etching the photoresist by using a halftone mask reticle comprises:
  • the semi-exposed photoresist is etched away.
  • step S304 the IMP ions are implanted with a high dose of P doping to form N+;
  • FIG. 9A and FIG. 9B are schematic diagrams showing the structure of ion implantation high dose P doping to form N+ according to an embodiment of the present invention.
  • an NTFT (N+) is formed by an ion implantation process in which a PTFT (P+) region is required to be blocked by a photoresist to avoid ion implantation.
  • step S305 the remaining photoresist is removed
  • FIG. 10A and FIG. 10B are schematic diagrams showing the structure of removing the remaining photoresist according to an embodiment of the present invention.
  • the strip photoresist removal process is used to wash away all the photoresist on the active layer NTFT and the PTFT, and thus the regions of the NTFT and PTFT have been defined, and the N+ position of the NTFT region has been implanted with ions to form the N+ region.
  • step S306 an insulating layer and a gate layer are sequentially formed on the entire surface of the glass substrate;
  • FIG. 11A and FIG. 11B are schematic diagrams showing the structure of forming an insulating layer and a gate layer according to an embodiment of the present invention.
  • an insulating layer 14 is formed on the entire surface of the glass substrate 10, and then a gate layer 15 is formed on the insulating layer 14.
  • an insulating film insulating layer
  • a metal film gate layer
  • the step of forming an insulating layer on the entire surface of the glass substrate comprises:
  • An insulating layer is deposited on the entire surface of the glass substrate by chemical vapor deposition.
  • the step of forming a gate layer on the entire surface of the glass substrate comprises:
  • a gate layer is deposited on the insulating layer by physical vapor deposition.
  • step S307 a photoresist is coated on the gate layer, and the photoresist is exposed by using a halftone mask.
  • FIG. 12A and FIG. 12B are schematic diagrams showing the structure of coating a photoresist on a gate layer according to an embodiment of the present invention.
  • a photoresist 16 is coated on the gate layer 15, and then the photoresist 16 is exposed using a halftone mask.
  • the scanning line patterns of the NTFT and the PTFT are defined in the primary halftone mask reticle exposure development.
  • step S308 the excess gate is etched away
  • FIG. 13A and FIG. 13B are schematic diagrams showing the structure of etching away excess gates according to an embodiment of the present invention.
  • the etching lines of the two TFTs on one glass substrate are simultaneously etched to remove excess metal film by an etching process to form a scan line pattern of the NTFT and the PTFT.
  • step S309 the IMP ions are implanted with a high dose of B doping to form P+.
  • FIG. 14A and FIG. 14B are schematic diagrams showing the structure of ion implantation high dose B doping to form P+ according to an embodiment of the present invention.
  • the PTFT (P+) is formed by an ion implantation process.
  • the NTFT (N+) region channel position needs to be blocked by the photoresist to avoid ion implantation (the NTFT region is not completely blocked because the illumination needs to be reduced once).
  • the PTFT ion implantation dose is less than the ion implantation dose when the NTFT was formed.
  • the B dose is lower than the high dose P to avoid the disappearance of N+.
  • step S310 the semi-exposed photoresist is etched away
  • FIG. 15A and FIG. 15B are schematic structural diagrams of etching off a half-exposed photoresist according to an embodiment of the present invention.
  • the photoresist pattern shown in FIGS. 15A and 15B is formed by an ashing process (resistive etching) so that the photoresist is uniformly thinned.
  • step S311 the exposed gate is etched away.
  • FIG. 16A and FIG. 16B are schematic structural diagrams of etching away exposed gates according to an embodiment of the present invention.
  • the excess metal on both sides of the NTFT scan line is further removed by an etching process to form a final scan line pattern of the NTFT.
  • step S312 the IMP ions are implanted with a low dose of P doping to form N-.
  • FIG. 17A and FIG. 17B are schematic diagrams showing the structure of ion implantation low dose P doping to form N- according to an embodiment of the present invention.
  • the self-aligning ion implantation process is used to form the N-position of the NTFT region, where the process ion implantation dose strengthens N+ and weakens the P+ region, so the dose is much smaller than the ion implantation dose of the P+ region. .
  • step S313 the remaining photoresist is removed.
  • FIG. 18A and FIG. 18B are schematic diagrams showing the structure of removing the remaining photoresist according to an embodiment of the present invention.
  • the strip photoresist is used to wash away all the photoresist on the glass substrate, and the CMOS fabrication is completed.
  • the present invention uses a two-tone halftone mask to complete CMos (Complementary Metal Oxide).
  • CMos Complementary Metal Oxide
  • Semiconductor, complementary metal oxide semiconductors and gates are defined and form LDDs. Therefore, the number of masks is reduced from 4 to 2, which greatly enhances the competitiveness; therefore, the manufacturing method of the polysilicon thin film transistor provided by the invention can effectively reduce the number of masks and effectively reduce the cost.

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Abstract

一种多晶硅薄膜晶体管的制作方法：在玻璃基板上形成缓冲层及多晶硅层（S101）；在多晶硅层上涂布光阻，采用半色调掩模光罩对光阻曝光和刻蚀（S102）；离子植入高剂量P掺杂，形成N+（S103）；在玻璃基板上形成绝缘层和栅极层（S104）；在栅极层上涂布光阻，采用半色调掩模光罩对光阻曝光（S105）；离子植入高剂量B掺杂，形成P+（S106）。该方法能减少光罩数，有效降低成本。

Description

一种多晶硅薄膜晶体管的制作方法 技术领域
本发明涉及显示技术领域，特别涉及一种多晶硅薄膜晶体管的制作方法。
 背景技术
在LTPS（Low Temperature Poly-silicon，低温多晶硅技术）现行制作工艺中，为了完成CMos（互补金属氧化物半导体，Complementary Metal Oxide Semiconductor）和gate（栅极）的定义，并形成LDD（非对称轻掺杂漏），其需要4道普通的掩模才能完成，更有为了LDD的效果而采用5道掩模的工艺。因此，传统工艺会导致PH产能的紧张，设备需求数量大，而且成本高。
故，有必要提出一种新的技术方案，以解决上述技术问题。
 技术问题
本发明的目的在于提供一种多晶硅薄膜晶体管的制作方法，其能减少光罩数，能有效降低成本。
 技术解决方案
一种多晶硅薄膜晶体管的制作方法，其中所述多晶硅薄膜晶体管的制作方法包括：
提供一玻璃基板，在所述玻璃基板上依次形成缓冲层以及多晶硅层；
在所述多晶硅层上涂布一光阻，并采用半色调掩模光罩对所述光阻进行曝光和刻蚀；
离子植入高剂量P掺杂，形成N+；
在所述玻璃基板全表面上依次形成绝缘层和栅极层；
在所述栅极层上涂布一光阻，并采用半色调掩模光罩对所述光阻进行曝光；
离子植入高剂量B掺杂，形成P+；其中，所述B剂量低于所述高剂量P；
蚀刻掉半曝的所述光阻；
蚀刻掉暴露的栅极；
去除掉剩下的所述光阻。
其中在所述玻璃基板上形成多晶硅层的步骤，包括：
在所述缓冲层上形成一非晶硅层；
对所述非晶硅层进行准分子激光退火操作，形成多晶硅层。
其中在所述玻璃基板上形成多晶硅层的步骤之后，还包括：
离子植入轻剂量B掺杂，形成沟道。
其中所述采用半色调掩模光罩对所述光阻进行曝光和刻蚀的步骤，包括：
采用半色调掩模光罩对所述光阻进行曝光；
蚀刻掉多余的多晶硅；
蚀刻掉半曝的所述光阻。
其中所述离子植入高剂量P掺杂，形成N+的步骤之后，还包括：
去除掉剩下的所述光阻。
其中在所述栅极层上涂布一光阻，并采用半色调掩模光罩对所述光阻进行曝光的步骤之后，还包括：
蚀刻掉多余的栅极。
其中所述去除掉剩下的所述光阻的步骤之后，还包括：
离子植入低剂量P掺杂，形成N-。
其中所述去除掉剩下的所述光阻的步骤之前，还包括：
离子植入低剂量P掺杂，形成N-。
一种多晶硅薄膜晶体管的制作方法，所述多晶硅薄膜晶体管的制作方法包括：
提供一玻璃基板，在所述玻璃基板上依次形成缓冲层以及多晶硅层；
在所述多晶硅层上涂布一光阻，并采用半色调掩模光罩对所述光阻进行曝光和刻蚀；
离子植入高剂量P掺杂，形成N+；
在所述玻璃基板全表面上依次形成绝缘层和栅极层；
在所述栅极层上涂布一光阻，并采用半色调掩模光罩对所述光阻进行曝光；
离子植入高剂量B掺杂，形成P+。
优选的，在所述的多晶硅薄膜晶体管的制作方法中，在所述玻璃基板上形成多晶硅层的步骤，包括：
在所述缓冲层上形成一非晶硅层；
对所述非晶硅层进行准分子激光退火操作，形成多晶硅层。
优选的，在所述的多晶硅薄膜晶体管的制作方法中，在所述玻璃基板上形成多晶硅层的步骤之后，还包括：
离子植入轻剂量B掺杂，形成沟道。
优选的，在所述的多晶硅薄膜晶体管的制作方法中，所述采用半色调掩模光罩对所述光阻进行曝光和刻蚀的步骤，包括：
采用半色调掩模光罩对所述光阻进行曝光；
蚀刻掉多余的多晶硅；
蚀刻掉半曝的所述光阻。
优选的，在所述的多晶硅薄膜晶体管的制作方法中，所述离子植入高剂量P掺杂，形成N+的步骤之后，还包括：
去除掉剩下的所述光阻。
优选的，在所述的多晶硅薄膜晶体管的制作方法中，在所述栅极层上涂布一光阻，并采用半色调掩模光罩对所述光阻进行曝光的步骤之后，还包括：
蚀刻掉多余的栅极。
优选的，在所述的多晶硅薄膜晶体管的制作方法中，所述B剂量低于所述高剂量P。
优选的，在所述的多晶硅薄膜晶体管的制作方法中，所述离子植入高剂量B掺杂，形成P+的步骤之后，还包括：
蚀刻掉半曝的所述光阻；
蚀刻掉暴露的栅极；
去除掉剩下的所述光阻。
优选的，在所述的多晶硅薄膜晶体管的制作方法中，所述去除掉剩下的所述光阻的步骤之后，还包括：
离子植入低剂量P掺杂，形成N-。
优选的，在所述的多晶硅薄膜晶体管的制作方法中，所述去除掉剩下的所述光阻的步骤之前，还包括：
离子植入低剂量P掺杂，形成N-。
 有益效果
相对现有技术，本发明采用2道半色调掩模光罩完成CMos（Complementary Metal Oxide Semiconductor，互补金属氧化物半导体）和栅极的定义，并形成LDD。从而使得掩模数量从4道减少到了2道，大大提升了竞争力；因此本发明提供的多晶硅薄膜晶体管的制作方法能有效减少光罩数，且能有效降低成本。
 附图说明
图1为本发明实施例提供的多晶硅薄膜晶体管的制作方法的实现流程示意图;
图2为本发明实施例一提供的多晶硅薄膜晶体管的制作方法的实现流程示意图；
图3为本发明实施例二提供的多晶硅薄膜晶体管的制作方法的实现流程示意图；
图4为本发明实施例提供的在玻璃基板上依次形成缓冲层以及多晶硅层的结构示意图；
图5为本发明实施例提供的离子植入轻剂量B掺杂的结构示意图；
图6 A和图6B为本发明实施例提供的在多晶硅层上涂布一光阻的结构示意图；
图7A和图7B为本发明实施例提供的蚀刻掉多余的多晶硅的结构示意图；
图8 A和图8B为本发明实施例提供的蚀刻掉半曝的所述光阻13的结构示意图；
图9 A和图9B为本发明实施例提供的离子植入高剂量P掺杂形成N+的结构示意图；
图10 A和图10B为本发明实施例提供的去除掉剩下的所述光阻的结构示意图；
图11A和图11B为本发明实施例提供的形成绝缘层和栅极层的结构示意图；
图12A和图12B为本发明实施例提供的在栅极层上涂布一光阻的结构示意图；
图13A和图13B为本发明实施例提供的蚀刻掉多余的栅极的结构示意图；
图14A和图14B为本发明实施例提供的离子植入高剂量B掺杂形成P+的结构示意图；
图15A和图15B为本发明实施例提供的蚀刻掉半曝的光阻的结构示意图；
图16A和图16B为本发明实施例提供的蚀刻掉暴露的栅极的结构示意图；
图17A和图17B为本发明实施例提供的离子植入低剂量P掺杂形成N-的结构示意图；
图18A和图18B为本发明实施例提供的去除掉剩下的光阻的结构示意图。
 本发明的最佳实施方式
本说明书所使用的词语“实施例”意指用作实例、示例或例证。此外，本说明书和所附权利要求中所使用的冠词“一”一般地可以被解释为意指“一个或多个”，除非另外指定或从上下文清楚导向单数形式。
在本发明实施例中，本发明采用2道半色调掩模光罩完成CMos（Complementary Metal Oxide Semiconductor，互补金属氧化物半导体）和栅极的定义，并形成LDD。从而使得掩模数量从4道减少到了2道，大大提升了竞争力；因此本发明提供的多晶硅薄膜晶体管的制作方法能有效减少光罩数，且能有效降低成本。
请参阅图1，图1为本发明实施例提供的多晶硅薄膜晶体管的制作方法的实现流程示意图；所述多晶硅薄膜晶体管的制作方法主要包括以下步骤：
在步骤S101中，提供一玻璃基板，在所述玻璃基板上依次形成缓冲层以及多晶硅层；
在本发明实施例中，在所述玻璃基板上形成多晶硅层的步骤，包括：
在所述缓冲层上形成一非晶硅层；
对所述非晶硅层进行准分子激光退火操作，形成多晶硅层。
在步骤S102中，在所述多晶硅层上涂布一光阻，并采用半色调掩模光罩对所述光阻进行曝光和刻蚀；
在本发明实施例中，所述采用半色调掩模光罩对所述光阻进行曝光和刻蚀的步骤，包括：
采用半色调掩模光罩对所述光阻进行曝光；
蚀刻掉多余的多晶硅；
蚀刻掉半曝的所述光阻。
在步骤S103中，IMP（IMPLANT，离子植入）高剂量P掺杂，形成N+；
在步骤S104中，在所述玻璃基板全表面上依次形成绝缘层和栅极层；
在本发明实施例中，在所述玻璃基板全表面上形成绝缘层的步骤，包括：
采用化学气相沉积在所述玻璃基板全表面上沉积一绝缘层。
在所述玻璃基板全表面上形成栅极层的步骤，包括：
采用物理气相沉积在所述绝缘层上沉积一栅极层。
在步骤S105中，在所述栅极层上涂布一光阻，并采用半色调掩模光罩对所述光阻进行曝光；
在步骤S106中，IMP离子植入高剂量B掺杂，形成P+。
在本发明实施例中，所述B剂量低于所述高剂量P，以免造成N+的消失。
为了说明本发明所述的技术方案，下面通过具体实施例来进行说明。
实施例一
请参阅图2，图2为本发明实施例一提供的多晶硅薄膜晶体管的制作方法的实现流程示意图；其主要包括以下步骤：
在步骤S201中，提供一玻璃基板，在所述玻璃基板上依次形成缓冲层以及多晶硅层；
在本发明实施例中，在所述玻璃基板上形成多晶硅层的步骤，包括：
在所述缓冲层上形成一非晶硅层；
对所述非晶硅层进行准分子激光退火操作，形成多晶硅层。
在步骤S202中，IMP离子植入轻剂量B掺杂，形成沟道；
在步骤S203中，在所述多晶硅层上涂布一光阻，并采用半色调掩模光罩对所述光阻进行曝光和刻蚀；
在本发明实施例中，所述采用半色调掩模光罩对所述光阻进行曝光和刻蚀的步骤，包括：
采用半色调掩模光罩对所述光阻进行曝光；
蚀刻掉多余的多晶硅；
蚀刻掉半曝的所述光阻。
在步骤S204中，IMP离子植入高剂量P掺杂，形成N+；
在步骤S205中，去除掉剩下的所述光阻；
在步骤S206中，在所述玻璃基板全表面上依次形成绝缘层和栅极层；
在本发明实施例中，在所述玻璃基板全表面上形成绝缘层的步骤，包括：
采用化学气相沉积在所述玻璃基板全表面上沉积一绝缘层。
在所述玻璃基板全表面上形成栅极层的步骤，包括：
采用物理气相沉积在所述绝缘层上沉积一栅极层。
在步骤S207中，在所述栅极层上涂布一光阻，并采用半色调掩模光罩对所述光阻进行曝光；
在步骤S208中，蚀刻掉多余的栅极；
在步骤S209中，IMP离子植入高剂量B掺杂，形成P+。
在本发明实施例中，所述B剂量低于所述高剂量P，以免造成N+的消失。
在步骤S210中，蚀刻掉半曝的所述光阻；
在步骤S211中，蚀刻掉暴露的栅极。
在步骤S212中，去除掉剩下的所述光阻。
在步骤S213中，IMP离子植入低剂量P掺杂，形成N-。
实施例二
请参阅图3，图3为本发明实施例二提供的多晶硅薄膜晶体管的制作方法的实现流程示意图；其主要包括以下步骤：
在步骤S301中，提供一玻璃基板，在所述玻璃基板上依次形成缓冲层以及多晶硅层；
请参阅图4，为本发明实施例提供的在玻璃基板上依次形成缓冲层以及多晶硅层的结构示意图。首先在所述玻璃基板10上形成缓冲层11，然后，在所述缓冲层上11形成一非晶硅层；对所述非晶硅层进行准分子激光退火操作，形成多晶硅层12。
在本发明实施例中，在所述玻璃基板上形成多晶硅层的步骤，包括：
在所述缓冲层上形成一非晶硅层；
对所述非晶硅层进行准分子激光退火操作，形成多晶硅层。
在步骤S302中，IMP离子植入轻剂量B掺杂，形成沟道；
请参阅图5，为本发明实施例提供的离子植入轻剂量B掺杂的结构示意图。在本实施例中，在未定义NTFT（N+）和PTFT（P+）情况下，用离子植入工艺植入少量的硼用于调整TFT（Thin Film Transistor，薄膜晶体管）的电压。具体的，在整面玻璃基板上的多晶硅都植入少量的硼。
在步骤S303中，在所述多晶硅层上涂布一光阻，并采用半色调掩模光罩对所述光阻进行曝光和刻蚀；
请参阅图6A和图6B，为本发明实施例提供的在多晶硅层上涂布一光阻的结构示意图。首先，在所述多晶硅层12上涂布一光阻13，然后，并采用半色调掩模光罩对所述光阻13进行曝光和刻蚀。在本实施例中，Cmos是由NTFT（N+）和PTFT（P+）组成在一块玻璃基板上，因此，在制作其中一个TFT的同时另一个TFT的区域需要光阻遮挡。在本实施例中，在一次半色调掩模光罩曝光显影中定义主动层NTFT和PTFT的图案。
图7A和图7B为本发明实施例提供的蚀刻掉多余的多晶硅的结构示意图。在本实施例中，采用刻蚀工艺，在一块玻璃基板上的两种TFT同时受到刻蚀去除多余的多晶硅，形成主动层NTFT和PTFT图案。
图8A和图8B为本发明实施例提供的蚀刻掉半曝的所述光阻的结构示意图。在本实施例中，采用灰化工艺（光阻刻蚀）使得光阻均匀减薄后形成如图8A和图8B的光阻图案。
在本发明实施例中，所述采用半色调掩模光罩对所述光阻进行曝光和刻蚀的步骤，包括：
采用半色调掩模光罩对所述光阻进行曝光；
蚀刻掉多余的多晶硅；
蚀刻掉半曝的所述光阻。
在步骤S304中，IMP离子植入高剂量P掺杂，形成N+；
请参阅图9A和图9B，为本发明实施例提供的离子植入高剂量P掺杂形成N+的结构示意图。在本实施例中，采用离子植入工艺形成NTFT（N+），在此工艺中PTFT（P+）区域需要光阻遮挡住避免受到离子植入。
在步骤S305中，去除掉剩下的所述光阻；
请参阅图10A和图10B，为本发明实施例提供的去除掉剩下的所述光阻的结构示意图。在本实施例中，采用strip清除工艺洗掉主动层NTFT和PTFT上全部光阻，至此NTFT和PTFT的区域已经定义完成，并且NTFT区域的N+位置已经植入离子形成N+区。
在步骤S306中，在所述玻璃基板全表面上依次形成绝缘层和栅极层；
请参阅图11A和图11B，为本发明实施例提供的形成绝缘层和栅极层的结构示意图。首先，在所述玻璃基板10全表面上形成绝缘层14，然后在绝缘层14上形成栅极层15。在本实施例中，采用化学气相沉积工艺在整面玻璃基板上沉积一层绝缘膜（绝缘层），之后用物理气相成膜工艺沉积一层金属膜（栅极层）。
在本发明实施例中，在所述玻璃基板全表面上形成绝缘层的步骤，包括：
采用化学气相沉积在所述玻璃基板全表面上沉积一绝缘层。
在所述玻璃基板全表面上形成栅极层的步骤，包括：
采用物理气相沉积在所述绝缘层上沉积一栅极层。
在步骤S307中，在所述栅极层上涂布一光阻，并采用半色调掩模光罩对所述光阻进行曝光；
请参阅图12A和图12B，为本发明实施例提供的在栅极层上涂布一光阻的结构示意图。首先，在所述栅极层15上涂布一光阻16，然后，采用半色调掩模光罩对所述光阻16进行曝光。在本实施例中，在一次半色调掩模光罩曝光显影中定义NTFT和PTFT的扫描线图案。
在步骤S308中，蚀刻掉多余的栅极；
请参阅图13A和图13B，为本发明实施例提供的蚀刻掉多余的栅极的结构示意图。在本实施例中，采用刻蚀工艺，在一块玻璃基板上的两种TFT的扫描线同时受到刻蚀去除多余的金属膜，形成NTFT和PTFT的扫描线图案。
在步骤S309中，IMP离子植入高剂量B掺杂，形成P+。
请参阅图14A和图14B，为本发明实施例提供的离子植入高剂量B掺杂形成P+的结构示意图。在本实施例中，采用离子植入工艺形成PTFT（P+），在此工艺中NTFT（N+）区域通道位置需要光阻遮挡住避免受到离子植入（NTFT区域未全部遮挡是因为需要减少光照一次定义全部扫描线）。因N+和P+可以相互中和抵消，所以此次PTFT离子植入剂量要少于前次形成NTFT时的离子植入剂量。
在本发明实施例中，所述B剂量低于所述高剂量P，以免造成N+的消失。
在步骤S310中，蚀刻掉半曝的所述光阻；
请参阅图15A和图15B，为本发明实施例提供的蚀刻掉半曝的光阻的结构示意图。在本实施例中，采用灰化工艺（光阻刻蚀）使得光阻均匀减薄后形成如图15A和图15B所示的光阻图案。
在步骤S311中，蚀刻掉暴露的栅极。
请参阅图16A和图16B，为本发明实施例提供的蚀刻掉暴露的栅极的结构示意图。在本实施例中，采用刻蚀工艺进一步去除NTFT扫描线两侧多余的金属，形成NTFT最终的扫描线图案。
在步骤S312中，IMP离子植入低剂量P掺杂，形成N-。
请参阅图17A和图17B，为本发明实施例提供的离子植入低剂量P掺杂形成N-的结构示意图。在本实施例中，采用self-align离子植入工艺形成NTFT区域的N-位置，此处工艺离子植入剂量会加强N+，减弱P+区域，因此剂量会远远小于P+区域的离子植入剂量。
在步骤S313中，去除掉剩下的所述光阻。
请参阅图18A和图18B，为本发明实施例提供的去除掉剩下的光阻的结构示意图。在本实施例中，采用strip工艺洗掉玻璃基板上全部光阻，至此CMOS制作完成。
综上所述，本发明采用2道半色调掩模光罩完成CMos（Complementary Metal Oxide Semiconductor，互补金属氧化物半导体）和栅极的定义，并形成LDD。从而使得掩模数量从4道减少到了2道，大大提升了竞争力；因此本发明提供的多晶硅薄膜晶体管的制作方法能有效减少光罩数，且能有效降低成本。
尽管已经相对于一个或多个实现方式示出并描述了本发明，但是本领域技术人员基于对本说明书和附图的阅读和理解将会想到等价变型和修改。本发明包括所有这样的修改和变型，并且仅由所附权利要求的范围限制。特别地关于由上述组件执行的各种功能，用于描述这样的组件的术语旨在对应于执行所述组件的指定功能（例如其在功能上是等价的）的任意组件（除非另外指示），即使在结构上与执行本文所示的本说明书的示范性实现方式中的功能的公开结构不等同。此外，尽管本说明书的特定特征已经相对于若干实现方式中的仅一个被公开，但是这种特征可以与如可以对给定或特定应用而言是期望和有利的其他实现方式的一个或多个其他特征组合。而且，就术语“包括”、“具有”、“含有”或其变形被用在具体实施方式或权利要求中而言，这样的术语旨在以与术语“包含”相似的方式包括。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (18)

  1. 一种多晶硅薄膜晶体管的制作方法，其中所述多晶硅薄膜晶体管的制作方法包括：
    提供一玻璃基板，在所述玻璃基板上依次形成缓冲层以及多晶硅层；
    在所述多晶硅层上涂布一光阻，并采用半色调掩模光罩对所述光阻进行曝光和刻蚀；
    离子植入高剂量P掺杂，形成N+；
    在所述玻璃基板全表面上依次形成绝缘层和栅极层；
    在所述栅极层上涂布一光阻，并采用半色调掩模光罩对所述光阻进行曝光；
    离子植入高剂量B掺杂，形成P+；其中，所述B剂量低于所述高剂量P；
    蚀刻掉半曝的所述光阻；
    蚀刻掉暴露的栅极；
    去除掉剩下的所述光阻。
  2. 根据权利要求1所述的多晶硅薄膜晶体管的制作方法，其中在所述玻璃基板上形成多晶硅层的步骤，包括：
    在所述缓冲层上形成一非晶硅层；
    对所述非晶硅层进行准分子激光退火操作，形成多晶硅层。
  3. 根据权利要求1或2所述的多晶硅薄膜晶体管的制作方法，其中在所述玻璃基板上形成多晶硅层的步骤之后，还包括：
    离子植入轻剂量B掺杂，形成沟道。
  4. 根据权利要求1所述的多晶硅薄膜晶体管的制作方法，其中所述采用半色调掩模光罩对所述光阻进行曝光和刻蚀的步骤，包括：
    采用半色调掩模光罩对所述光阻进行曝光；
    蚀刻掉多余的多晶硅；
    蚀刻掉半曝的所述光阻。
  5. 根据权利要求1所述的多晶硅薄膜晶体管的制作方法，其中所述离子植入高剂量P掺杂，形成N+的步骤之后，还包括：
    去除掉剩下的所述光阻。
  6. 根据权利要求1所述的多晶硅薄膜晶体管的制作方法，其中在所述栅极层上涂布一光阻，并采用半色调掩模光罩对所述光阻进行曝光的步骤之后，还包括：
    蚀刻掉多余的栅极。
  7. 根据权利要求1所述的多晶硅薄膜晶体管的制作方法，其中所述去除掉剩下的所述光阻的步骤之后，还包括：
    离子植入低剂量P掺杂，形成N-。
  8. 根据权利要求1所述的多晶硅薄膜晶体管的制作方法，其中所述去除掉剩下的所述光阻的步骤之前，还包括：
    离子植入低剂量P掺杂，形成N-。
  9. 一种多晶硅薄膜晶体管的制作方法，其中所述多晶硅薄膜晶体管的制作方法包括：
    提供一玻璃基板，在所述玻璃基板上依次形成缓冲层以及多晶硅层；
    在所述多晶硅层上涂布一光阻，并采用半色调掩模光罩对所述光阻进行曝光和刻蚀；
    离子植入高剂量P掺杂，形成N+；
    在所述玻璃基板全表面上依次形成绝缘层和栅极层；
    在所述栅极层上涂布一光阻，并采用半色调掩模光罩对所述光阻进行曝光；
    离子植入高剂量B掺杂，形成P+。
  10. 根据权利要求9所述的多晶硅薄膜晶体管的制作方法，其中在所述玻璃基板上形成多晶硅层的步骤，包括：
    在所述缓冲层上形成一非晶硅层；
    对所述非晶硅层进行准分子激光退火操作，形成多晶硅层。
  11. 根据权利要求9或10所述的多晶硅薄膜晶体管的制作方法，其中在所述玻璃基板上形成多晶硅层的步骤之后，还包括：
    离子植入轻剂量B掺杂，形成沟道。
  12. 根据权利要求9所述的多晶硅薄膜晶体管的制作方法，其中所述采用半色调掩模光罩对所述光阻进行曝光和刻蚀的步骤，包括：
    采用半色调掩模光罩对所述光阻进行曝光；
    蚀刻掉多余的多晶硅；
    蚀刻掉半曝的所述光阻。
  13. 根据权利要求9所述的多晶硅薄膜晶体管的制作方法，其中所述离子植入高剂量P掺杂，形成N+的步骤之后，还包括：
    去除掉剩下的所述光阻。
  14. 根据权利要求9所述的多晶硅薄膜晶体管的制作方法，其中在所述栅极层上涂布一光阻，并采用半色调掩模光罩对所述光阻进行曝光的步骤之后，还包括：
    蚀刻掉多余的栅极。
  15. 根据权利要求9所述的多晶硅薄膜晶体管的制作方法，其中所述B剂量低于所述高剂量P。
  16. 根据权利要求9所述的多晶硅薄膜晶体管的制作方法，其中所述离子植入高剂量B掺杂，形成P+的步骤之后，还包括：
    蚀刻掉半曝的所述光阻；
    蚀刻掉暴露的栅极；
    去除掉剩下的所述光阻。
  17. 根据权利要求16所述的多晶硅薄膜晶体管的制作方法，其中所述去除掉剩下的所述光阻的步骤之后，还包括：
    离子植入低剂量P掺杂，形成N-。
  18. 根据权利要求16所述的多晶硅薄膜晶体管的制作方法，其中所述去除掉剩下的所述光阻的步骤之前，还包括：
    离子植入低剂量P掺杂，形成N-。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1716571A (zh) * 2004-06-30 2006-01-04 三星Sdi株式会社 互补金属氧化物半导体薄膜晶体管和制造其的方法
CN1917155A (zh) * 2005-08-18 2007-02-21 三星电子株式会社 薄膜晶体管基板及其制造
US20070045627A1 (en) * 2005-08-13 2007-03-01 Samsung Electronics Co., Ltd Thin film transistor substrate and method of manufacturing the same
CN103681350A (zh) * 2012-09-17 2014-03-26 薛英家 薄膜晶体管的制作方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100395884C (zh) * 2003-11-07 2008-06-18 友达光电股份有限公司 形成cmos晶体管的方法
KR100669457B1 (ko) * 2004-11-24 2007-01-15 삼성에스디아이 주식회사 박막 트랜지스터, 이를 구비한 평판 표시 장치 및 그제조방법
CN100339964C (zh) * 2005-04-29 2007-09-26 友达光电股份有限公司 具有轻掺杂漏极的金属氧化物半导体的制作方法
TWI257177B (en) * 2005-07-27 2006-06-21 Quanta Display Inc Manufacturing processes for a thin film transistor and a pixel structure

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1716571A (zh) * 2004-06-30 2006-01-04 三星Sdi株式会社 互补金属氧化物半导体薄膜晶体管和制造其的方法
US20070045627A1 (en) * 2005-08-13 2007-03-01 Samsung Electronics Co., Ltd Thin film transistor substrate and method of manufacturing the same
CN1917155A (zh) * 2005-08-18 2007-02-21 三星电子株式会社 薄膜晶体管基板及其制造
CN103681350A (zh) * 2012-09-17 2014-03-26 薛英家 薄膜晶体管的制作方法

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