WO2016204987A1 - Pvd deposition and anneal of multi-layer metal-dielectric film - Google Patents

Pvd deposition and anneal of multi-layer metal-dielectric film Download PDF

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Publication number
WO2016204987A1
WO2016204987A1 PCT/US2016/035826 US2016035826W WO2016204987A1 WO 2016204987 A1 WO2016204987 A1 WO 2016204987A1 US 2016035826 W US2016035826 W US 2016035826W WO 2016204987 A1 WO2016204987 A1 WO 2016204987A1
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WIPO (PCT)
Prior art keywords
layer
substrate
adhesion layer
film stack
adhesion
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PCT/US2016/035826
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English (en)
French (fr)
Inventor
Minrui Yu
Kai Ma
Thomas Kwon
Kaushal K. Singh
Er-Xuan Ping
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Applied Materials Inc
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Applied Materials Inc
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Priority to KR1020187001800A priority Critical patent/KR102506953B1/ko
Priority to CN201680032205.5A priority patent/CN107873107B/zh
Priority to JP2017565799A priority patent/JP6979881B2/ja
Publication of WO2016204987A1 publication Critical patent/WO2016204987A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H10P14/43—
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C28/00—Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D
    • C23C28/30—Coatings combining at least one metallic layer and at least one inorganic non-metallic layer
    • C23C28/32—Coatings combining at least one metallic layer and at least one inorganic non-metallic layer including at least one pure metallic layer
    • C23C28/322—Coatings combining at least one metallic layer and at least one inorganic non-metallic layer including at least one pure metallic layer only coatings of metal elements only
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C28/00—Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D
    • C23C28/30—Coatings combining at least one metallic layer and at least one inorganic non-metallic layer
    • C23C28/34—Coatings combining at least one metallic layer and at least one inorganic non-metallic layer including at least one inorganic non-metallic material layer, e.g. metal carbide, nitride, boride, silicide layer and their mixtures, enamels, phosphates and sulphates
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C28/00—Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D
    • C23C28/30—Coatings combining at least one metallic layer and at least one inorganic non-metallic layer
    • C23C28/34—Coatings combining at least one metallic layer and at least one inorganic non-metallic layer including at least one inorganic non-metallic material layer, e.g. metal carbide, nitride, boride, silicide layer and their mixtures, enamels, phosphates and sulphates
    • C23C28/345—Coatings combining at least one metallic layer and at least one inorganic non-metallic layer including at least one inorganic non-metallic material layer, e.g. metal carbide, nitride, boride, silicide layer and their mixtures, enamels, phosphates and sulphates with at least one oxide layer
    • H10P14/22—
    • H10P14/418—
    • H10P14/44—
    • H10P95/90—
    • H10W20/031—
    • H10W20/032—
    • H10W20/064—
    • H10W20/075—
    • H10W20/425—
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
    • C23C14/0641—Nitrides
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/40—Oxides
    • C23C16/401—Oxides containing silicon

Definitions

  • Embodiments of the present disclosure generally relate to methods for depositing thin metal film on dielectrics to form multiple structures of metal- dielectrics, and more particularly to methods for forming a film stack wherein the film stack includes a thin metal film.
  • VLSI very large scale integration
  • ULSI ultra large-scale integration
  • Reliably producing sub-half micron and smaller features is one of the key technology challenges for next generation very large scale integration (VLSI) and ultra large-scale integration (ULSI) of semiconductor devices.
  • VLSI very large scale integration
  • ULSI ultra large-scale integration
  • Reliable formation of gate structures on the substrate is important to VLSI and ULSI success and to the continued effort to increase circuit density and quality of individual substrates and die.
  • interconnects such as vias, trenches, contacts, gate structures and other features, as well as the dielectric materials therebetween
  • the widths of interconnects decrease to 45 nm and 32 nm dimensions, whereas the thickness of the dielectric layers remain substantially constant, with the result of increasing the aspect ratios of the features.
  • three dimensional (3D) stacking of semiconductor chips is often utilized to improve performance of the transistors. By arranging transistors in three dimensions instead of conventional two dimensions, multiple transistors may be placed in the integrated circuits (ICs) very close to each other. Three dimensional (3D) stacking of semiconductor chips reduces wire lengths and keeps wiring delay low.
  • stair-like structures are often utilized to allow multiple interconnection structures to be disposed thereon, forming high-density of vertical transistor devices.
  • a method for filming a film stack on a substrate includes depositing a first adhesion layer on an oxide layer formed on the substrate, and depositing a metal layer on the first adhesion layer, wherein the first adhesion layer and the metal layer form a stress neutral structure.
  • a film stack structure formed on a substrate includes a first adhesion layer and a metal layer.
  • the first adhesion layer is deposited on an oxide layer formed on the substrate.
  • the metal layer is deposited on the adhesion layer.
  • the first adhesion layer and the metal layer form a stress neutral structure.
  • a method for filming a film stack on a substrate includes depositing a first adhesion layer on an oxide layer formed on the substrate, depositing a metal layer on the first adhesion layer, and depositing a second adhesion layer on the metal layer wherein the first adhesion layer, the metal layer, and the second adhesion layer form a stress neutral structure.
  • Figure 1 depicts a method of forming a film stack on a substrate, according to one embodiment.
  • Figures 2A-2D illustrate a film stack formed on a substrate at intervals of the method in Figure 1 .
  • Figure 3 depicts a method of forming a film stack on a substrate, according to one embodiment.
  • Figure 4A-4E illustrate a film stack formed on a substrate at intervals of the method in Figure 3.
  • Figure 5 illustrates a processing system for forming a film stack on a substrate, according to one embodiment.
  • a method for forming a film stack on a substrate includes depositing a first adhesion layer on an oxide layer formed on the substrate, and depositing a metal layer on the first adhesion layer, wherein the first adhesion layer and the metal layer form a stress neutral structure.
  • Figure 1 illustrates one embodiment of a method 100 for forming a film stack on a substrate.
  • Figures 2A-2D illustrate cross-sectional views of the substrate at different stages of the method of Figure 1 .
  • Figure 2A depicts a substrate 200 having an oxide layer 202 formed on the substrate 200.
  • the oxide layer 202 may be deposited on the substrate through plasma-enhanced chemical vapor deposition (PECVD) or physical vapor deposition (PVD).
  • PECVD plasma-enhanced chemical vapor deposition
  • PVD physical vapor deposition
  • the oxide layer for example, may be made from TEOS.
  • the oxide layer 202 has a thickness 205. In one embodiment, the thickness 205 of the oxide layer 202 may be no greater than 250 A.
  • Method 100 begins at block 102 by depositing a first adhesion layer 204 on the oxide layer 202, as shown in Figure 2B.
  • the first adhesion layer 204 may be deposited using a physical vapor deposition or other suitable process.
  • the first adhesion layer 204 may be a nitride film.
  • the first adhesion layer 204 may be titanium nitride (TiN) or tungsten-nitride (WN).
  • a metal layer 206 is deposited over the surface of the first adhesion layer 204, as shown in Figure 2C.
  • the metal layer 206 may be deposited using a PVD process or other suitable process.
  • the metal layer 206 may be, for example, tungsten (W).
  • the metal layer 206 has a sheet resistance of less than 15Q/D .
  • the first adhesion layer 204 and the metal layer 206 form a stress neutral structure.
  • the first adhesion layer 204 exhibits compressive stress, meaning that force pushes against the underlying substrate, while the metal layer 206 exhibits tensile stress, meaning the force pulls on the underlying substrate.
  • the first adhesion layer 204 exhibits tensile stress and the metal layer 206 exhibits compressive stress.
  • the first adhesion layer 204 and the metal layer 206 may have a total thickness 208 not exceeding 200 A.
  • a bilayer of WN and W may be deposited on the oxide layer 202 such that the WN layer has a thickness of 40 A and the W layer has a thickness of 160 A.
  • the metal layer 206, the first adhesion layer 204, and the oxide layer 202 are collectively referred to as an oxide-metal (OM) structure 209.
  • Each OM structure 209 is formed such that the resulting substrate bow of each OM structure 209 is less than 1 ⁇ , as shown in Figure 2D.
  • the less than 1 ⁇ substrate bow is due to the stress neutral structure formed by the first adhesion layer 204 and the metal layer 206.
  • the force of the metal layer 206 pulls on the substrate 200.
  • the forces may nearly cancel, resulting in a substrate bow of less than 1 ⁇ .
  • the film stack is optionally transferred to an anneal chamber for an anneal process.
  • Annealing the film stack may further reduce the bow of the substrate and the resistance of the metal layer 206.
  • the film stack may be annealed for two hours at 500° C.
  • the film stack may be annealed for a shorter duration at a higher temperature.
  • Figure 3 illustrates one embodiment of a method 300 for forming a film stack on a substrate.
  • Figures 4A-4E illustrate cross-sectional views of a substrate at different stages of the method 300 of Figure 3.
  • Figure 4A depicts a substrate 400 having an oxide layer 402 formed on the substrate 400.
  • the oxide layer 402 may be deposited on the substrate through a PECVD process.
  • the oxide layer may be a TEOS layer.
  • the oxide layer 402 has a thickness 405. In one embodiment, the thickness 405 of the oxide layer 402 may be no greater than 250 A.
  • Method 300 begins at block 302 by depositing a first adhesion layer 404 on the oxide layer 402, as illustrated in Figure 4B.
  • the first adhesion layer 404 may be deposited using a PVD or other suitable process.
  • the first adhesion layer 404 may be a nitride film.
  • the first adhesion layer 404 may be TiN or WN.
  • a metal layer 406 is deposited over the surface of the first adhesion layer 404, as illustrated in Figure 4C.
  • the metal layer 406 may be deposited using a PVD process or other suitable process.
  • the metal layer 406 may be, for example, W.
  • the metal layer 406 has a sheet resistance less than 15 ⁇ /D.
  • a second adhesion layer 410 is deposited on the metal layer 406, as illustrated in Figure 4D.
  • the second adhesion layer 410 may be deposited using a PVD or other suitable process.
  • the second adhesion layer 410 may be a nitride film.
  • the second adhesion layer 410 may be TiN or WN.
  • the second adhesion layer 410 may be the same as the first adhesion layer 404.
  • the first adhesion layer 404 and the second adhesion layer 410 are WN.
  • the first adhesion layer 404 and the second adhesion layer 410 may be different materials.
  • the first adhesion layer 404, the metal layer 406, and the second adhesion layer 410 form a stress neutral structure.
  • the first adhesion layer 404 and the second adhesion layer 410 may exhibit compressive stress, while the metal layer 406 exhibits tensile stress.
  • the first adhesion layer 404 and the second adhesion layer 410 may exhibit tensile stress and the metal layer 406 exhibits compressive stress.
  • the first adhesion layer 404 and the second adhesion layer 410 may be TiN, which exhibits compressive stress, meaning that force pushes on the underlying substrate.
  • the metal layer 406 may be W, which exhibits tensile stress, meaning the force pulls against the underlying substrate.
  • the first adhesion layer 404, metal layer 406, and the second adhesion layer 410 may have a total thickness 408 not exceeding 200 A.
  • a tri-layer of TiN/W/TiN may be deposited on the oxide layer 402 such that the TiN layers have thicknesses of 30 A each and the W layer has a thickness of 140 A.
  • the first adhesion layer 404, the metal layer 406, the second adhesion layer 410, and the oxide layer 402 are collectively referred to as an oxide-metal (OM) structure 409.
  • Each OM structure 409 is formed such that the resulting substrate bow of each OM structure 409 is less than 1 ⁇ , as illustrated in Figure 4E.
  • the less than 1 ⁇ substrate bow is due to the stress neutral structure formed by the first adhesion layer 404, the metal layer 406, and the second adhesion layer 410.
  • the force of the first adhesion layer 404 pulls on the substrate 400 the force of the metal layer 406 pushes on the substrate 400, and the force of the second adhesion layer 410 pulls on the substrate 400.
  • the forces may cancel, resulting in a substrate bow of less than 1 ⁇ per OM structure 409.
  • the film stack is optionally transferred to an anneal chamber for an anneal process.
  • Annealing the film stack may further reduce the bow of the substrate and the sheet resistance of the metal layer 406.
  • the film stack may be annealed for two hours at 500° C.
  • the film stack may be annealed for a shorter duration at a higher temperature.
  • FIG. 5 illustrates a multi-chamber processing system 500.
  • the processing system 500 may include load lock chambers 502, 504, a robot 506, a transfer chamber 508, processing chambers 510, 512, 514, 516, 518, 528, and a controller 520.
  • the load lock chambers 502, 504 allow for the transfer of substrates (not shown) into and out of the processing system 500.
  • Load lock chambers 502, 504 may pump down the substrates introduced into the processing system 500 to maintain a vacuum seal.
  • the robot 506 may transfer the substrates between load lock chambers 502, 504 and the processing chambers 510, 512, 514, 516, 518, and 528.
  • the robot 506 may also transfer the substrates between the load lock chambers 502, 504 and the transfer chamber 508.
  • Each processing chamber 510, 512, 514, 516, 518, and 528 may be outfitted to perform a number of substrate operations such as atomic layer deposition (ALD), chemical vapor deposition (CVD), PVD, etch, pre-clean, degas, heat, orientation, or other substrate processes. Additionally, each processing chamber 510, 512, 514, 516, 518, and 528 may be outfitted to deposit an oxide layer, a first adhesion layer, a metal layer, or a second adhesion layer.
  • the controller 520 may be configured to operate all aspects of the processing system 500, such as the methods disclosed in Figure 1 and Figure 3.
  • the controller 520 may be configured to control the method of forming a metal interconnect on a substrate.
  • the controller 520 includes a programmable central processing unit (CPU) 522 that is operable with a memory 524 and a mass storage device, an input control unit, and a display unit (not shown), such as power supplies, clocks, cache, input/output (I/O) circuits, and the liner, coupled to the various components of the processing system to facilitate control of the substrate processing.
  • the controller 520 also includes hardware for monitoring substrate processing through sensors in the processing system 500, including sensors monitoring the precursor, process gas, and purge gas flow. Other sensors that measure system parameters, such as substrate temperature, chamber atmosphere pressure, and the like, may also provide information to the controller 520.
  • the CPU 522 may be one of any form of general purpose computer processor that can be used in an industrial setting, such as a programmable logic controller (PLC), for controlling various chambers and sub-processors.
  • the memory 524 is coupled to the CPU 522 and the memory 524 is non-transitory and may be one or more of readily available memory such as random access memory (RAM), read only memory (ROM), floppy disk drive, hard disk, or any other form of digital storage, local or remote.
  • Support circuits 526 are coupled to the CPU 522 for supporting the processor in a conventional manner.
  • Charged species generation, heating, and other processes are generally stored in the memory 524, typically as software routine.
  • the software routine may also be stored and/or executed by a second CPU (not shown) that is remotely located from the hardware being controlled by the CPU 522.
  • the memory 524 is in the form of computer-readable storage media that contains instructions, that when executed by the CPU 522, facilitates the operation of the processing system 500.
  • the instructions in the memory 524 are in the form of a program product such as a program that implements the method of the present disclosure.
  • the program code may conform to any one of a number of different programming languages.
  • the disclosure may be implemented as a program product stored on a computer- readable storage media for use with a computer system.
  • the program(s) of the program product define functions of the embodiments (including the methods described herein).
  • Illustrative computer-readable storage media include, but are not limited to: (i) non-writable storage media (e.g.
  • read-only memory devices within a computer such as CD-ROM disks readable by a CD-ROM drive, flash memory, ROM chips, or any type of solid-state non-volatile semiconductor memory) on which information is permanently stored; and (ii) writable storage media (e.g., floppy disks within a diskette drive or hard-disk drive or any type of solid-state random-access semiconductor memory) on which alterable information is stored.
  • writable storage media e.g., floppy disks within a diskette drive or hard-disk drive or any type of solid-state random-access semiconductor memory
  • a substrate is transferred to a first processing chamber for deposition of an oxide layer.
  • the first processing chamber is a PECVD chamber configured to deposit TEOS on the substrate.
  • the TEOS layer has a thickness of 250 A.
  • the TEOS layer is deposited through a PECVD process.
  • the deposited TEOS has a thickness of 250 A.
  • the robot transfers the substrate having the TEOS layer deposited thereon to a second processing chamber for deposition of a first adhesion layer.
  • the second processing chamber is a PVD chamber configured to deposit a layer of WN on the TEOS layer.
  • the layer of WN has a thickness of 40 A.
  • the WN may be deposited at a rate of 5.0 A/s.
  • the WN layer exhibits compressive stress.
  • the robot transfers the substrate having the first adhesion layer deposited thereon to a third processing chamber for deposition of a metal layer.
  • the third processing chamber is a CVD chamber configured to deposit a layer of W on the WN adhesion layer.
  • the layer of W has a thickness of 160 A.
  • the W layer exhibits tensile stress.
  • the W may be deposited at a rate of 17.6 A/s.
  • the TEOS layer, the WN layer, and the W layer are collectively referred to as an OM structure.
  • the robot transfers the substrate among the processing chambers until the desired number of OM structures is deposited on the substrate. For example, 120 OM structures may be deposited on the substrate.
  • Each OM structure has a substrate bow less than 1 ⁇ due to the stress neutral structure formed by the WN layer and the W layer. Thus, the total substrate bow of the 120 OM structures is less than 120 ⁇ .
  • the substrate may be transferred out of the processing system and into a chamber for annealing. Annealing the film stack formed on the substrate can reduce the substrate bow further as well as the sheet resistance of the metal layer. The film stack is annealed for two hours at 500° C.
  • a substrate is transferred to a first processing chamber for deposition of an oxide layer.
  • the first processing chamber is a PECVD chamber configured to deposit TEOS on the substrate.
  • the TEOS layer has a thickness of 250 A.
  • the TEOS layer is deposited through a PECVD process.
  • the deposited TEOS has a thickness of 250 A.
  • the robot transfers the substrate having the TEOS layer deposited thereon to a second processing chamber for deposition of a first adhesion layer.
  • the second processing chamber is a low-powered radio frequency PVD (LP RFPVD) chamber configured to deposit a layer of TiN on the TEOS layer.
  • the layer of TiN has a thickness of 60 A.
  • the TiN may be deposited at a rate of 0.5 A/s.
  • the TiN layer exhibits compressive stress.
  • the robot transfers the substrate having the first adhesion layer deposited thereon to a third processing chamber for deposition of a metal layer.
  • the third processing chamber is a PVD chamber configured to deposit a layer of W on the TiN adhesion layer.
  • the layer of W has a thickness of 140 A.
  • the W may be deposited at a rate of 17.6 A/s.
  • the W layer exhibits tensile stress.
  • the TEOS layer, the TiN layer, and the W layer are collectively referred to as an OM structure .
  • the robot transfers the substrate among the processing chambers until the desired number of OM structures is deposited on the substrate.
  • 120 OM structures may be deposited on the substrate.
  • Each OM structure has a substrate bow less than 1 ⁇ due to the stress neutral structure formed by the TiN layer and the W layer.
  • the total substrate bow of the 120 OM structures is less than 120 ⁇ .
  • a substrate is transferred to a first processing chamber for deposition of an oxide layer.
  • the first processing chamber is a PECVD chamber configured to deposit TEOS on the substrate.
  • the TEOS layer has a thickness of 250 A.
  • the TEOS layer is deposited through a PECVD process.
  • the deposited TEOS has a thickness of 250 A.
  • the robot transfers the substrate having the TEOS layer deposited thereon to a second processing chamber for deposition of a first adhesion layer.
  • the second processing chamber is a PVD chamber configured to deposit a layer of WN on the TEOS layer.
  • the layer of WN has a thickness of 30 A.
  • the WN may be deposited at a rate of 5.0 A/s.
  • the first WN layer exhibits compressive stress.
  • the robot transfers the substrate having the first adhesion layer deposited thereon to a third processing chamber for deposition of a metal layer.
  • the third processing chamber is a CVD chamber configured to deposit a layer of W on the WN adhesion layer.
  • the layer of W has a thickness of 140 A.
  • the W may be deposited at a rate of 17.6 A/s.
  • the W layer exhibits tensile stress.
  • the robot transfers the substrate having the metal layer deposited thereon to a fourth processing chamber for deposition of a second adhesion layer.
  • the fourth processing chamber is a PVD chamber configured to deposit a second layer of WN on the metal W layer.
  • the layer of WN has a thickness of 30 A.
  • the WN may be deposited at a rate of 5.0 A/s.
  • the second WN layer exhibits compressive stress.
  • the TEOS layer, the first WN layer, the W layer, and the second WN layer are collectively referred to as an OM structure.
  • the robot transfers the substrate among the processing chambers until the desired number of OM structures is deposited on the substrate.
  • 120 OM structures may be deposited on the substrate.
  • Each OM structure has a substrate bow less than 1 ⁇ , due to the stress neutral structure formed by the first WN layer, the W layer, and the second WN layer.
  • the total substrate bow of the 120 OM structures is less than 120 ⁇ .
  • the substrate may be transferred out of the processing system and into a chamber for annealing.
  • the film stack is annealed for two hours at 500° C.

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PCT/US2016/035826 2015-06-19 2016-06-03 Pvd deposition and anneal of multi-layer metal-dielectric film Ceased WO2016204987A1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1020187001800A KR102506953B1 (ko) 2015-06-19 2016-06-03 다층 금속 유전체 필름의 pvd 퇴적 및 어닐링
CN201680032205.5A CN107873107B (zh) 2015-06-19 2016-06-03 多层金属介电膜的物理气相沉积及退火处理
JP2017565799A JP6979881B2 (ja) 2015-06-19 2016-06-03 多層金属誘電体膜のｐｖｄ堆積とアニール

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14/745,367 US10879177B2 (en) 2015-06-19 2015-06-19 PVD deposition and anneal of multi-layer metal-dielectric film
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US20160372330A1 (en) 2016-12-22
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JP2018527456A (ja) 2018-09-20
KR102506953B1 (ko) 2023-03-08
CN107873107A (zh) 2018-04-03
JP6979881B2 (ja) 2021-12-15
TWI705149B (zh) 2020-09-21
CN107873107B (zh) 2022-01-28
TW201704508A (zh) 2017-02-01

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