WO2016187893A1 - 一种多相位时钟产生电路及液晶显示面板 - Google Patents

一种多相位时钟产生电路及液晶显示面板 Download PDF

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Publication number
WO2016187893A1
WO2016187893A1 PCT/CN2015/080468 CN2015080468W WO2016187893A1 WO 2016187893 A1 WO2016187893 A1 WO 2016187893A1 CN 2015080468 W CN2015080468 W CN 2015080468W WO 2016187893 A1 WO2016187893 A1 WO 2016187893A1
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WIPO (PCT)
Prior art keywords
shift register
diode
register unit
stage
thin film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2015/080468
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English (en)
French (fr)
Inventor
朱江
郭东胜
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US14/770,511 priority Critical patent/US9697789B2/en
Publication of WO2016187893A1 publication Critical patent/WO2016187893A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/18—Timing circuits for raster scan displays
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G11C19/287—Organisation of a multiplicity of shift registers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
    • H03K5/15013—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs
    • H03K5/1506—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with parallel driven output stages; with synchronously driven series connected output stages
    • H03K5/15093—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with parallel driven output stages; with synchronously driven series connected output stages using devices arranged in a shift register
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present invention relates to the field of displays, and in particular to a multi-phase clock generating circuit and a liquid crystal display panel.
  • LCD TVs are widely used due to their small size, low weight, low power consumption and high resolution.
  • the liquid crystal panel driving circuit generally includes a timing controller chip, a line scan driving chip, and the like.
  • the liquid crystal panel uses the line scan driving chip on the liquid crystal panel side to save resources.
  • the line scan driving chip is often required to provide multiple clock signals, and these clock signals have a certain phase with each other. difference. As shown in FIG.
  • the present invention constructs a multi-phase clock generating circuit including:
  • a shift register including N shift register units, wherein the N shift register units are cascaded with each other; each of the shift register units has a first input terminal, a second input terminal, and a first output terminal, The first input terminal inputs a start control signal, the start control signal is used to control the shift register to be turned on; the second input terminal inputs a delay control signal, and the delay control signal is used to control the shift register a unit output, the first output end of the shift register unit of the nth stage is connected to the first input end of the shift register unit of the n+1th stage, wherein N ⁇ 2, 1 ⁇ n ⁇ N;
  • a thin film transistor group comprising N thin film transistors, wherein the thin film transistors are in one-to-one correspondence with the shift register unit; each of the thin film transistors has a third input end, a control end, and a second output end; each of the thin films a third input terminal of the transistor inputs a main clock signal, the main clock signal is used to provide a reference clock; a second output end of each of the thin film transistors outputs a subclock signal, the subclock signal is input to the display panel a row scan driving chip; wherein a control end of the nth stage thin film transistor is respectively connected to (N-n+1) first output terminals of the shift register unit;
  • a first diode group including N first diodes, the first diodes are in one-to-one correspondence with the shift register unit; an anode of the first diode is connected to the shift register unit a first output end, a cathode of the first diode is connected to a control end of the thin film transistor;
  • a second diode group comprising N-1 second diodes, wherein the shift register unit of each adjacent two stages is connected by a second diode; the nth second pole a cathode of the tube is connected to a cathode of the first diode of the shift register unit of the nth stage, and an anode of the nth second diode is connected to the first two of the shift register unit of the n+1th stage The cathode of the pole tube;
  • the phase difference between the nth sub-clock signal and the n+1th sub-clock signal is determined according to the period of the delay control signal.
  • an output time of the plurality of sub-clock signals is determined according to an output time of a high level of the start control signal.
  • the first output terminal of the shift register unit of the Nth stage is connected to the first input terminal of the shift register unit of the first stage through a third diode, An anode of the third diode is connected to a first output end of the Nth stage shift register unit; a cathode of the third diode is connected to a first stage shift register unit An input.
  • the present invention constructs a multi-phase clock generating circuit including:
  • a shift register including N shift register units, wherein the N shift register units are cascaded with each other; each of the shift register units has a first input terminal, a second input terminal, and a first output terminal, The first input terminal inputs a start control signal, the start control signal is used to control the shift register to be turned on; the second input terminal inputs a delay control signal, and the delay control signal is used to control the shift register a unit output, the first output end of the shift register unit of the nth stage is connected to the first input end of the shift register unit of the n+1th stage, wherein N ⁇ 2, 1 ⁇ n ⁇ N;
  • a thin film transistor group comprising N thin film transistors, wherein the thin film transistors are in one-to-one correspondence with the shift register unit; each of the thin film transistors has a third input end, a control end, and a second output end; each of the thin films a third input terminal of the transistor inputs a main clock signal, the main clock signal is used to provide a reference clock; a second output end of each of the thin film transistors outputs a subclock signal, the subclock signal is input to the display panel The row scan driving chip; wherein the control terminals of the nth stage thin film transistor are respectively connected to (N-n+1) first output terminals of the shift register unit.
  • the multi-phase clock generating circuit further includes a first diode group, the first diode group including N first diodes, the first The diodes are in one-to-one correspondence with the shift register unit;
  • An anode of the first diode is coupled to a first output of the shift register unit, and a cathode of the first diode is coupled to a control terminal of the thin film transistor.
  • the multi-phase clock generating circuit further includes a second diode group including N-1 second diodes, each phase The shift register unit of two adjacent stages is connected by a second diode;
  • a cathode of the nth second diode is connected to a cathode of a first diode of the nth stage of the shift register unit, and an anode of the nth second diode is connected to an n+1th stage The cathode of the first diode of the shift register unit.
  • the phase difference between the n-th sub-clock signal and the n+1-th sub-clock signal is determined according to the period of the delay control signal.
  • an output time of the plurality of sub-clock signals is determined according to an output time of a high level of the start control signal.
  • the first output terminal of the shift register unit of the Nth stage is connected to the first input terminal of the shift register unit of the first stage through a third diode, An anode of the third diode is connected to a first output end of the Nth stage shift register unit; a cathode of the third diode is connected to a first stage shift register unit An input.
  • the invention also provides a liquid crystal display panel comprising:
  • the row scan driving chip is configured to supply a scan signal to the scan line;
  • the scan signal is generated according to a multi-channel sub-clock signal of the multi-phase clock generating circuit;
  • the multi-phase clock generation circuit includes:
  • a shift register including N shift register units, wherein the N shift register units are cascaded with each other; each of the shift register units has a first input terminal, a second input terminal, and a first output terminal, The first input terminal inputs a start control signal, the start control signal is used to control the shift register to be turned on; the second input terminal inputs a delay control signal, and the delay control signal is used to control the shift register a unit output, the first output end of the shift register unit of the nth stage is connected to the first input end of the shift register unit of the n+1th stage, wherein N ⁇ 2, 1 ⁇ n ⁇ N;
  • a thin film transistor group comprising N thin film transistors, wherein the thin film transistors are in one-to-one correspondence with the shift register unit; each of the thin film transistors has a third input end, a control end, and a second output end; each of the thin films a third input terminal of the transistor inputs a main clock signal, the main clock signal is used to provide a reference clock; a second output end of each of the thin film transistors outputs a subclock signal, the subclock signal is input to the display panel The row scan driving chip; wherein the control terminals of the nth stage thin film transistor are respectively connected to (N-n+1) first output terminals of the shift register unit.
  • the multi-phase clock generating circuit further includes a first diode group, the first diode group including N first diodes, the first diode
  • the tube has a one-to-one correspondence with the shift register unit;
  • An anode of the first diode is coupled to a first output of the shift register unit, and a cathode of the first diode is coupled to a control terminal of the thin film transistor.
  • the multi-phase clock generating circuit further includes a second diode group, and the second diode group includes N-1 second diodes, each adjacent to two The shift register unit of the stage is connected by a second diode;
  • a cathode of the nth second diode is connected to a cathode of a first diode of the nth stage of the shift register unit, and an anode of the nth second diode is connected to an n+1th stage The cathode of the first diode of the shift register unit.
  • the phase difference between the nth sub-clock signal and the n+1th sub-clock signal is determined according to the period of the delay control signal.
  • the output time of the plurality of sub-clock signals is determined according to the output time of the high level of the start control signal.
  • the output time of the plurality of sub-clock signals is determined according to the output time of the high level of the start control signal.
  • the first output terminal of the shift register unit of the Nth stage is connected to the first input terminal of the shift register unit of the first stage through a third diode,
  • An anode of the third diode is connected to the first output end of the shift register unit of the Nth stage;
  • a cathode of the third diode is connected to the first input of the shift register unit of the first stage end.
  • the multi-phase clock generating circuit and the liquid crystal display panel of the present invention can improve the clock generating circuit of the prior art, so that only one clock signal needs to be input to generate a multi-channel clock with phase offset, and the timing control chip is reduced.
  • the number of pins reduces the cost of production.
  • 1 is a schematic diagram showing the connection between a conventional timing controller chip and a multi-phase clock generating circuit
  • FIG. 2 is a schematic structural diagram of a multi-phase clock generating circuit of the present invention.
  • FIG. 3 is a timing diagram of control signals of the multi-phase clock generating circuit of the present invention.
  • FIG. 4 is a schematic diagram showing the connection of the timing controller chip of the present invention and the multi-phase clock generating circuit.
  • FIG. 2 is a schematic structural diagram of a multi-phase clock generating circuit according to the present invention.
  • the multi-phase clock generating circuit of the present invention as shown in FIG. 1, the input signal thereof includes: a delay control signal CP, a start control signal ST, and a main clock signal CLK;
  • the multi-phase clock generating circuit includes: a shift register 13 and a thin film transistor group T0-Tn;
  • the shift register 13 includes N shift register units 14 that are cascaded with each other (without limiting the order of cascading), where N ⁇ 2, and the shift register unit 14 is triggered, for example.
  • Each of the shift register units has a first input terminal, a second input terminal, and a first output terminal, and the first input terminal of each of the shift register units inputs a start control signal, The start control signal is used to control the shift register to be turned on; the second input terminal of each of the shift register units inputs a delay control signal, and the delay control signal is used to control the shift register unit Outputting, the first output end of the shift register unit of the nth stage is connected to the first input end of the shift register unit of the n+1th stage; the shift register unit is, for example, a flip-flop, wherein N ⁇ 2 , 1 ⁇ n ⁇ N.
  • the thin film transistor group includes N thin film transistors T0-Tn, the thin film transistors are in one-to-one correspondence with the shift register unit, that is, each shift register unit is connected to one thin film transistor; each of the thin film transistors has a third input end a control terminal, a second output terminal; a third input terminal of each of the thin film transistors inputs a main clock signal CLK, the main clock signal CLK is used to provide a reference clock; and a second output end of each of the thin film transistors a subclock signal for inputting to a row scan driving chip of the display panel; wherein a control end of the nth stage thin film transistor is respectively associated with (N-n+1) the shift register unit The first output is connected.
  • the shift register unit FF0 of the first stage has a first input terminal 22, a second input terminal 21 and a first output terminal 23, and the first input terminal 22 inputs the start control signal ST, the second The input terminal 21 inputs a delay control signal CP, and the first output terminal 23 of the first stage shift register unit FF0 is connected to the first input terminal 25 of the second stage flip-flop FF1; and the first output terminal 23 is also connected a thin film transistor T0; a third input end of the thin film transistor T0 is connected to the main clock signal CLK, a second output end of the thin film transistor T0 outputs a first sub-clock signal CLK1; and a control end of the thin film transistor T0 is respectively
  • the shift register unit FF0- The first output of FFn is connected.
  • the second stage shift register unit FF1 has a first input terminal 25, a second input terminal 24, and a first output terminal 26.
  • the first input terminal 25 is connected to the first stage of the first stage shift register unit FF0.
  • the output terminal 23; the second input terminal 24 is connected to the delay control signal CP;
  • the first output terminal 26 is connected with a thin film transistor T1, and the first output terminal 26 is also connected to the third stage shift register unit FF2.
  • a first input end; a third input end of the thin film transistor T1 is connected to the main clock signal CLK, a second output end of the thin film transistor T1 outputs a second sub-clock signal CLK2; and a control end of the thin film transistor T1 is respectively And the shift register unit FF1-
  • the first output of FFn is connected.
  • the first output end of the third stage shift register unit FF2 is connected with a thin film transistor T2, and the second output end of the thin film transistor T2 outputs a third way subclock signal CLK3;
  • the fourth stage shift register unit a thin film transistor T3 is connected to the first output end of the FF3, and a second output terminal of the thin film transistor T3 outputs a fourth sub-clock signal CLK4;
  • the first output of the nth-stage shift register unit FFn-1 a thin film transistor Tn-1 is connected to the terminal, and a second output terminal of the thin film transistor Tn-1 outputs an nth sub-clock signal CLK(n);
  • the first output of the n+1th stage shift register unit FFn A thin film transistor Tn is connected to the terminal, and a second output terminal of the thin film transistor Tn outputs an n+1th sub-clock signal CLK(n+1); the remaining flip-flops are similar.
  • the multi-stage shift register unit When the start control signal is at a high level, and when the delay control signal comes to a rising edge, corresponding to the one-stage shift register unit output, so by the control action of the delay control signal, the multi-stage shift register unit generates the phase
  • the multi-phase clock generation circuit of the invention only needs to input one clock signal, and can obtain multiple clock signals, thereby reducing the number of output pins of the timing control chip and the input tube of the multi-phase clock generation circuit. The number of feet reduces production costs.
  • the multi-phase clock generating circuit further includes a first diode group, the first diode group including N first diodes, as shown by 31-36 in FIG. 2, the a diode is in one-to-one correspondence with the shift register unit; an anode of the first diode is connected to a first output end of the corresponding shift register unit, and a cathode connection of the first diode is correspondingly The control terminal of the thin film transistor.
  • a diode 31 is disposed between the control terminal of the thin film transistor T0 and the first output terminal 23 of the shift register unit FF0 of the first stage, and the anode of the first diode 31 is connected to the first stage.
  • the first output terminal 23 of the shift register unit, the cathode of the first diode 31 is connected to the control terminal of the thin film transistor T0.
  • the multi-phase clock generating circuit further includes a second diode group, the second diode group includes N-1 second diodes, and the shift register unit of each adjacent two stages passes through a a second diode connection; a cathode of the nth second diode is connected to a cathode of a first diode of the nth stage of the shift register unit, and an nth second diode The anode is connected to the cathode of the first diode of the shift register unit of the n+1th stage.
  • a second diode 41 is disposed between the cathode of the first diode 31 of the shift register unit FF0 of the first stage and the cathode of the first diode 32 of the shift register unit FF1 of the second stage,
  • the cathode of the second diode 41 is connected to the cathode of the first diode 31 of the shift register unit FF0 of the first stage, and the anode of the second diode 41 is connected to the shift register of the second stage.
  • a second diode 42 is disposed between the cathode of the first diode 32 of the shift register unit FF1 of the second stage and the cathode of the first diode 33 of the shift register unit FF2 of the third stage; a cathode of the first diode 34 of the shift register unit FF(n-2) of the n-1th stage and a first diode 35 of the shift register unit FF(n-1) of the nth stage
  • a second diode 44 is disposed between the cathodes; a cathode of the first diode 35 of the nth stage shift register unit FF(n-1) and a shift register unit FF of the n+1th stage (
  • a second diode 45 is disposed between the cathodes of the first diode 36 of n). The remaining diodes are similar.
  • the signal outputted by the first stage can be transmitted to the upper-stage shift register unit or the corresponding multi-stage shift register unit through the second diode.
  • the control terminal of the thin film transistor, thereby reducing the high-level output time of the ST and reducing the power consumption; the connection mode of the second diode is such that the shift register unit of the upper stage is prevented when the shift register unit is triggered by the upper stage
  • the output signal flows directly to the control terminal of the thin film transistor corresponding to the subsequent shift register unit, preventing T0-Tn from simultaneously outputting the sub-clock signal, so that the sub-clock signal cannot be delayed.
  • the first diode can prevent the subsequent stage shift register unit from transmitting its output signal to the control terminal of the thin film transistor corresponding to the upper stage or the multi-stage shift register unit, and the signal flows to the front multi-stage shift.
  • the first output of the registration unit can prevent the subsequent stage shift register unit from transmitting its output signal to the control terminal of the thin film transistor corresponding to the upper stage or the multi-stage shift register unit, and the signal flows to the front multi-stage shift.
  • the second second diode 42 can prevent the signal at the output end of the shift register unit FF2 from flowing to the shift register unit FF3-FFn corresponding to the control terminal of the thin film transistor, avoiding CLK3- The CLKn is simultaneously outputted, and the first diode 33 of the shift register unit of the third stage can prevent the signal of the output terminal of the shift register unit FF2 from flowing to the first output terminal of the shift register unit FF1 - FF2.
  • the first output end of the shift register unit of the Nth stage is connected to the first input end of the shift register unit of the first stage through a third diode, and the anode connection of the third diode a first output end of the shift register unit of the Nth stage; a cathode of the third diode is connected to a first input end of the shift register unit of the first stage.
  • the first output terminal 46 of the last stage shift register FFn is also connected to the first input terminal 22 of the shift register unit FF0 of the first stage, and the anode of the third diode 47 is connected to the last stage.
  • a first output terminal 46 of the shift register FFn, a cathode of the third diode 47 is connected to the first input terminal 22 of the shift register unit FF0 of the first stage.
  • the output time of the multi-channel clock signal generated by the multi-phase clock can be lengthened.
  • the timing controller chip 50 only needs to output three signals to the multi-phase clock generating circuit 51, and the multi-phase clock generating circuit 51 can generate the multi-channel sub-clock signals CLK1-CLKn to the row scanning driving chip 52, which is reduced.
  • the number of pins of the timing controller chip 50 and the multi-phase clock generating circuit 51, and the existing multi-phase clock generating circuit requires input of multiple clock signals, and the production cost is high.
  • the multi-phase clock generating circuit of the present invention is seen. Only one clock signal needs to be input, and by controlling the delay control signal, multiple phase clocks can be formed, which reduces the pins of the corresponding chip, because the production cost can be reduced.
  • the working principle of the multi-phase clock generating circuit of the present invention is as shown in FIG. 3,
  • ST is high level, and when the time is t1, the first rising edge of the CP signal comes, so that FF0 triggers, FF0 outputs a high pulse, and the thin film transistor T0 is closed, so that the CLK signal outputs CLK1 through the output end of T0;
  • the fourth rising edge of the CP signal comes, so that FF3 is triggered, FF3 outputs a high pulse, and the thin film transistor T3 is closed due to the thin film transistors T2 and T0.
  • the control terminal of T1 is connected to the output terminal of FF3, thus also making the thin film transistors T2 and T0 T1 is closed; the CLK signal is outputted through the output terminal of T0, CLK1 is outputted through the output terminal of T1, CLK3 is outputted through the output terminal of T2, and CLK4 is outputted through the output terminal of T3;
  • the time phase difference between the nth sub-clock signal and the n+1th sub-clock signal is determined according to the period of the delay control signal. That is, CLK1, CLK2, ... CLKn sequentially output the CLK signal, and the phase difference between each other can be controlled by the period of the CP signal, and as the period of the CP is larger, the corresponding phase difference between the clock signals is also larger. As shown in FIG. 2, the phase difference between CLK1 and CLK2 is equal to the period t2-t1 of the CP.
  • the output time of the plurality of subclock signals is determined according to an output time of the high level of the start control signal.
  • the output time of the CLK signal by each channel can be controlled by the high-level output time of the ST signal (ie, when CLK1_CLKn is output). The larger the duty ratio of the ST signal, the longer the CLK is output by each channel. .
  • the output of the D flip-flop when the rising edge of the ST signal arrives, the rising edge of the CP signal, the output of the D flip-flop outputs a high level until ST is low, and the next rising edge of the CP, the D flip-flop The output of the output is low, so that the thin film transistor is turned off and the corresponding subclock signal is no longer output. Therefore, the longer the high-level output of the ST signal is, the longer the high level of the output of the D flip-flop is. Therefore, the larger the duty ratio of the ST signal, the longer the output of the D flip-flop is, and the longer the CLK is output by each channel. .
  • the multi-phase clock generating circuit and the liquid crystal display device of the present invention can improve the clock generating circuit of the prior art, so that only one clock signal needs to be input to generate a multi-channel clock with phase offset, and the timing control chip and the clock are reduced.
  • the number of pins of the power management chip reduces the production cost.
  • the present invention also provides a liquid crystal display panel including a plurality of data lines and a plurality of scan lines and a plurality of pixel units defined by the data lines and the scan lines;
  • the row scan driving chip is configured to supply a scan signal to the scan line;
  • the scan signal is generated according to a multi-channel sub-clock signal of the multi-phase clock generating circuit;
  • the multi-phase clock generation circuit includes:
  • a shift register including N shift register units, wherein the N shift register units are cascaded with each other; each of the shift register units has a first input terminal, a second input terminal, and a first output terminal, The first input terminal inputs a start control signal, the start control signal is used to control the shift register to be turned on; the second input terminal inputs a delay control signal, and the delay control signal is used to control the shift register a unit output, the first output end of the shift register unit of the nth stage is connected to the first input end of the shift register unit of the n+1th stage, wherein N ⁇ 2, 1 ⁇ n ⁇ N;
  • a thin film transistor group comprising N thin film transistors, wherein the thin film transistors are in one-to-one correspondence with the shift register unit; each of the thin film transistors has a third input end, a control end, and a second output end; each of the thin films a third input terminal of the transistor inputs a main clock signal, the main clock signal is used to provide a reference clock; a second output end of each of the thin film transistors outputs a subclock signal, the subclock signal is input to the display panel The row scan driving chip; wherein the control terminals of the nth stage thin film transistor are respectively connected to (N-n+1) first output terminals of the shift register unit.
  • the multi-phase clock generating circuit further includes a first diode group, the first diode group includes N first diodes, the first diode and the shift register unit One-to-one correspondence;
  • An anode of the first diode is coupled to a first output of the shift register unit, and a cathode of the first diode is coupled to a control terminal of the thin film transistor.
  • the multi-phase clock generating circuit further includes a second diode group, the second diode group includes N-1 second diodes, and the shift register unit of each adjacent two stages Connected by a second diode;
  • a cathode of the nth second diode is connected to a cathode of a first diode of the nth stage of the shift register unit, and an anode of the nth second diode is connected to an n+1th stage The cathode of the first diode of the shift register unit.
  • a phase difference between the nth sub-clock signal and the n+1th sub-clock signal is determined according to a period of the delay control signal.
  • the output time of the plurality of subclock signals is determined according to an output time of the high level of the start control signal.
  • the first output end of the shift register unit of the Nth stage is connected to the first input end of the shift register unit of the first stage through a third diode, and the anode connection of the third diode a first output end of the shift register unit of the Nth stage; a cathode of the third diode is connected to a first input end of the shift register unit of the first stage.
  • the liquid crystal display panel of the present invention may include any of the above-described multi-phase clock generating circuits. Since the multi-phase clock generating circuit has been described in detail above, it will not be described herein.
  • the multi-phase clock generating circuit and the liquid crystal display panel of the present invention can improve the clock generating circuit of the prior art, so that only one clock signal can be input to generate a multi-channel clock with phase offset, and the timing control chip and the clock are reduced.
  • the number of pins of the power management chip reduces the production cost.

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Abstract

一种多相位时钟产生电路（51）及液晶显示面板，所述电路（51）包括：移位寄存器（13），包括N个相互级联的移位寄存单元（14）；第n级移位寄存单元（FF(n-1)）的第一输出端与第n+1级移位寄存单元（FFn）的第一输入端连接；薄膜晶体管组（T0-Tn），包括N个薄膜晶体管（T0-Tn）；第n级薄膜晶体管（Tn-1）的控制端分别与(N-n+1)个移位寄存单元（14）的第一输出端连接。

Description

一种多相位时钟产生电路及液晶显示面板 技术领域
本发明涉及显示器领域，特别是涉及一种多相位时钟产生电路及液晶显示面板。
 背景技术
液晶电视因具有体积小，重量小，功耗小，解析度高的特点而被广泛应用。
液晶面板驱动电路一般包括时序控制器芯片，行扫描驱动芯片等。液晶面板将行扫描驱动芯片做在液晶面板侧来达到节省资源的目的，但是为了达到更好的视觉效果，常需要行扫描驱动芯片提供多路时钟信号，这些时钟信号相互之间有一定的相位差。如图1所示，现有的时序控制器芯片与多相位时钟产生电路的连接示意图，由于时序控制器芯片10向多相位时钟产生电路11输入多路时钟信号CLK1-CLKn，多相位时钟产生电路11再将多路时钟信号CLK1-CLKn输出给行扫描驱动芯片12，由于需要输出多路时钟信号，从而增加了时序控制芯片10和行扫描驱动芯片12的引脚，同时增加了驱动电路的成本。
因此，有必要提供一种多相位时钟产生电路及液晶显示面板，以解决现有技术所存在的问题。
 技术问题
本发明的目的在于提供一种多相位时钟产生电路及液晶显示面板，以解决现有技术中时序控制芯片需要具有多路时钟信号对应的输出管脚的技术问题，增加了生产成本。
 技术解决方案
为解决上述技术问题，本发明构造了一种多相位时钟产生电路，其包括：
移位寄存器，包括N个移位寄存单元，所述N个移位寄存单元相互级联；每个所述移位寄存单元具有第一输入端、第二输入端以及第一输出端，所述第一输入端输入起始控制信号，所述起始控制信号用于控制所述移位寄存器开启；所述第二输入端输入延迟控制信号，所述延迟控制信号用于控制所述移位寄存单元输出，第n级所述移位寄存单元的第一输出端与第n+1级所述移位寄存单元的第一输入端连接，其中N≥2，1≤n≤N；以及
薄膜晶体管组，包括N个薄膜晶体管，所述薄膜晶体管与所述移位寄存单元一一对应；每个所述薄膜晶体管具有第三输入端、控制端、第二输出端；每个所述薄膜晶体管的第三输入端输入主时钟信号，所述主时钟信号用于提供参考时钟；每个所述薄膜晶体管的第二输出端输出子时钟信号，所述子时钟信号用于输入到显示面板的行扫描驱动芯片中；其中第n级所述薄膜晶体管的控制端分别与（N-n+1）个所述移位寄存单元的第一输出端连接；
第一二极管组，包括N个第一二极管，所述第一二极管与所述移位寄存单元一一对应；所述第一二极管的阳极连接所述移位寄存单元的第一输出端，所述第一二极管的阴极连接所述薄膜晶体管的控制端；
第二二极管组，包括N-1个第二二极管，每相邻两级的所述移位寄存单元通过一所述第二二极管连接；第n个所述第二二极管的阴极连接第n级所述移位寄存单元的第一二极管的阴极，第n个所述第二二极管的阳极连接第n+1级所述移位寄存单元的第一二极管的阴极；
其中，根据所述延迟控制信号的周期确定第n路子时钟信号和第n+1路子时钟信号之间的相位差。
在本发明的所述多相位时钟产生电路中，根据所述起始控制信号的高电平的输出时间确定多路所述子时钟信号的输出时间。
在本发明的所述多相位时钟产生电路中，第N级所述移位寄存单元的第一输出端通过第三二极管与第1级所述移位寄存单元的第一输入端连接，所述第三二极管的阳极连接所述第N级所述移位寄存单元的第一输出端；所述第三二极管的阴极连接所述第1级所述移位寄存单元的第一输入端。
为解决上述技术问题，本发明构造了一种多相位时钟产生电路，其包括：
移位寄存器，包括N个移位寄存单元，所述N个移位寄存单元相互级联；每个所述移位寄存单元具有第一输入端、第二输入端以及第一输出端，所述第一输入端输入起始控制信号，所述起始控制信号用于控制所述移位寄存器开启；所述第二输入端输入延迟控制信号，所述延迟控制信号用于控制所述移位寄存单元输出，第n级所述移位寄存单元的第一输出端与第n+1级所述移位寄存单元的第一输入端连接，其中N≥2，1≤n≤N；以及
薄膜晶体管组，包括N个薄膜晶体管，所述薄膜晶体管与所述移位寄存单元一一对应；每个所述薄膜晶体管具有第三输入端、控制端、第二输出端；每个所述薄膜晶体管的第三输入端输入主时钟信号，所述主时钟信号用于提供参考时钟；每个所述薄膜晶体管的第二输出端输出子时钟信号，所述子时钟信号用于输入到显示面板的行扫描驱动芯片中；其中第n级所述薄膜晶体管的控制端分别与（N-n+1）个所述移位寄存单元的第一输出端连接。
在本发明的所述多相位时钟产生电路中，所述多相位时钟产生电路还包括第一二极管组，所述第一二极管组包括N个第一二极管，所述第一二极管与所述移位寄存单元一一对应；
所述第一二极管的阳极连接所述移位寄存单元的第一输出端，所述第一二极管的阴极连接所述薄膜晶体管的控制端。
在本发明的所述多相位时钟产生电路中，所述多相位时钟产生电路还包括第二二极管组，所述第二二极管组包括N-1个第二二极管，每相邻两级的所述移位寄存单元通过一所述第二二极管连接；
第n个所述第二二极管的阴极连接第n级所述移位寄存单元的第一二极管的阴极，第n个所述第二二极管的阳极连接第n+1级所述移位寄存单元的第一二极管的阴极。
在本发明的所述多相位时钟产生电路中，根据所述延迟控制信号的周期确定第n路子时钟信号和第n+1路子时钟信号之间的相位差。
在本发明的所述多相位时钟产生电路中，根据所述起始控制信号的高电平的输出时间确定多路所述子时钟信号的输出时间。
在本发明的所述多相位时钟产生电路中，第N级所述移位寄存单元的第一输出端通过第三二极管与第1级所述移位寄存单元的第一输入端连接，所述第三二极管的阳极连接所述第N级所述移位寄存单元的第一输出端；所述第三二极管的阴极连接所述第1级所述移位寄存单元的第一输入端。
本发明还提供一种液晶显示面板，其包括：
多条数据线和多条扫描线以及由所述数据线和所述扫描线限定的多个像素单元；以及
行扫描驱动芯片，所述行扫描驱动芯片用于向所述扫描线提供扫描信号；所述扫描信号根据多相位时钟产生电路的多路子时钟信号产生；
其中所述多相位时钟产生电路，包括：
移位寄存器，包括N个移位寄存单元，所述N个移位寄存单元相互级联；每个所述移位寄存单元具有第一输入端、第二输入端以及第一输出端，所述第一输入端输入起始控制信号，所述起始控制信号用于控制所述移位寄存器开启；所述第二输入端输入延迟控制信号，所述延迟控制信号用于控制所述移位寄存单元输出，第n级所述移位寄存单元的第一输出端与第n+1级所述移位寄存单元的第一输入端连接，其中N≥2，1≤n≤N；以及
薄膜晶体管组，包括N个薄膜晶体管，所述薄膜晶体管与所述移位寄存单元一一对应；每个所述薄膜晶体管具有第三输入端、控制端、第二输出端；每个所述薄膜晶体管的第三输入端输入主时钟信号，所述主时钟信号用于提供参考时钟；每个所述薄膜晶体管的第二输出端输出子时钟信号，所述子时钟信号用于输入到显示面板的行扫描驱动芯片中；其中第n级所述薄膜晶体管的控制端分别与（N-n+1）个所述移位寄存单元的第一输出端连接。
在本发明的所述液晶显示面板中，所述多相位时钟产生电路还包括第一二极管组，所述第一二极管组包括N个第一二极管，所述第一二极管与所述移位寄存单元一一对应；
所述第一二极管的阳极连接所述移位寄存单元的第一输出端，所述第一二极管的阴极连接所述薄膜晶体管的控制端。
在本发明的所述液晶显示面板中，所述多相位时钟产生电路还包括第二二极管组，所述第二二极管组包括N-1个第二二极管，每相邻两级的所述移位寄存单元通过一所述第二二极管连接；
第n个所述第二二极管的阴极连接第n级所述移位寄存单元的第一二极管的阴极，第n个所述第二二极管的阳极连接第n+1级所述移位寄存单元的第一二极管的阴极。
在本发明的所述液晶显示面板中，根据所述延迟控制信号的周期确定第n路子时钟信号和第n+1路子时钟信号之间的相位差。
在本发明的所述液晶显示面板中，根据所述起始控制信号的高电平的输出时间确定多路所述子时钟信号的输出时间。
在本发明的所述液晶显示面板中，根据所述起始控制信号的高电平的输出时间确定多路所述子时钟信号的输出时间。
在本发明的所述液晶显示面板中，第N级所述移位寄存单元的第一输出端通过第三二极管与第1级所述移位寄存单元的第一输入端连接，所述第三二极管的阳极连接所述第N级所述移位寄存单元的第一输出端；所述第三二极管的阴极连接所述第1级所述移位寄存单元的第一输入端。
 有益效果
本发明的多相位时钟产生电路及液晶显示面板，通过对现有技术的时钟产生电路进行改进，使得只需要输入一路时钟信号就可以产生具有相位偏移的多路时钟，减少了时序控制芯片的管脚数，从而降低了生产成本。
 附图说明
图1为现有的时序控制器芯片与多相位时钟产生电路的连接示意图；
图2为本发明多相位时钟产生电路的结构示意图；
图3为本发明多相位时钟产生电路的控制信号的时序图；
图4本发明的时序控制器芯片与多相位时钟产生电路的连接示意图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。
在图中，结构相似的单元是以相同标号表示。
请参照图2，图2为本发明多相位时钟产生电路的结构示意图。
本发明的多相位时钟产生电路，如图1所示，其输入信号包括：延迟控制信号CP、起始控制信号ST、一主时钟信号CLK；
所述多相位时钟产生电路包括：移位寄存器13和薄膜晶体管组T0-Tn；
所述移位寄存器13包括N个移位寄存单元14，所述N个移位寄存单元相互级联（不限定级联的顺序），其中N≥2，所述移位寄存单元14譬如为触发器FF0-FFn；每个所述移位寄存单元具有第一输入端、第二输入端以及第一输出端，每个所述移位寄存单元的所述第一输入端输入起始控制信号，所述起始控制信号用于控制所述移位寄存器开启；每个所述移位寄存单元的所述第二输入端输入延迟控制信号，所述延迟控制信号用于控制所述移位寄存单元输出，第n级所述移位寄存单元的第一输出端与第n+1级所述移位寄存单元的第一输入端连接；所述移位寄存单元譬如为触发器，其中N≥2，1≤n≤N。
薄膜晶体管组包括N个薄膜晶体管T0-Tn，所述薄膜晶体管与所述移位寄存单元一一对应，即每个移位寄存单元连接一个薄膜晶体管；每个所述薄膜晶体管具有第三输入端、控制端、第二输出端；每个所述薄膜晶体管的第三输入端输入主时钟信号CLK，所述主时钟信号CLK用于提供参考时钟；每个所述薄膜晶体管的第二输出端输出子时钟信号，所述子时钟信号用于输入到显示面板的行扫描驱动芯片中；其中第n级所述薄膜晶体管的控制端分别与（N-n+1）个所述移位寄存单元的第一输出端连接。
譬如第1级所述移位寄存单元FF0具有第一输入端22、第二输入端21以及第一输出端23，所述第一输入端22输入所述起始控制信号ST，所述第二输入端21输入延迟控制信号CP，第1级所述移位寄存单元FF0的第一输出端23连接第2级触发器FF1的第一输入端25；且所述第一输出端23还连接有薄膜晶体管T0；所述薄膜晶体管T0的第三输入端连接所述主时钟信号CLK，所述薄膜晶体管T0的第二输出端输出第1路子时钟信号CLK1；所述薄膜晶体管T0的控制端分别与所述移位寄存单元FF0- FFn的第一输出端连接。
所述第二级移位寄存单元FF1具有第一输入端25、第二输入端24、第一输出端26，所述第一输入端25连接所述第一级移位寄存单元FF0的第一输出端23；所述第二输入端24连接所述延迟控制信号CP；所述第一输出端26连接有薄膜晶体管T1，所述第一输出端26还连接第三级移位寄存单元FF2的第一输入端；所述薄膜晶体管T1的第三输入端连接所述主时钟信号CLK，所述薄膜晶体管T1的第二输出端输出第2路子时钟信号CLK2；所述薄膜晶体管T1的控制端分别与所述移位寄存单元FF1- FFn的第一输出端连接。
所述第三级移位寄存单元FF2的所述第一输出端连接有薄膜晶体管T2，所述薄膜晶体管T2的第二输出端输出第3路子时钟信号CLK3；所述第四级移位寄存单元FF3的所述第一输出端连接有薄膜晶体管T3，所述薄膜晶体管T3的第二输出端输出第4路子时钟信号CLK4；所述第n级移位寄存单元FFn-1的所述第一输出端连接有薄膜晶体管Tn-1，所述薄膜晶体管Tn-1的第二输出端输出第n路子时钟信号CLK(n)；所述第n+1级移位寄存单元FFn的所述第一输出端连接有薄膜晶体管Tn，所述薄膜晶体管Tn的第二输出端输出第n+1路子时钟信号CLK(n+1)；其余触发器与此类似。
当起始控制信号为高电平，且当延迟控制信号每到来一个上升沿时，对应一级移位寄存单元输出，因此通过延迟控制信号的控制作用，使得多级移位寄存单元产生具有相位差的多路子时钟信号，本发明的多相位时钟产生电路只需要输入一路时钟信号，就能得到多路时钟信号，从而减少了时序控制芯片的输出管脚数以及多相位时钟产生电路的输入管脚数，降低了生产成本。
优选地，所述多相位时钟产生电路还包括第一二极管组，所述第一二极管组包括N个第一二极管，如图2中的31-36所示，所述第一二极管与所述移位寄存单元一一对应；所述第一二极管的阳极连接相应的所述移位寄存单元的第一输出端，所述第一二极管的阴极连接相应的所述薄膜晶体管的控制端。
譬如所述薄膜晶体管T0的控制端与第1级所述移位寄存单元FF0的第一输出端23之间设置有一二极管31，所述第一二级管31的阳极连接所述第1级所述移位寄存单元的第一输出端23，所述第一二极管31的阴极连接所述薄膜晶体管T0的控制端。
所述多相位时钟产生电路还包括第二二极管组，所述第二二极管组包括N-1个第二二极管，每相邻两级的所述移位寄存单元通过一所述第二二极管连接；第n个所述第二二极管的阴极连接第n级所述移位寄存单元的第一二极管的阴极，第n个所述第二二极管的阳极连接第n+1级所述移位寄存单元的第一二极管的阴极。
第1级所述移位寄存单元FF0的第一二极管31的阴极和第2级所述移位寄存单元FF1的第一二极管32的阴极之间设置有一第二二极管41，所述第二二极管41的阴极连接第1级所述移位寄存单元FF0的第一二极管31的阴极，所述第二二极管41的阳极连接第2级所述移位寄存单元FF1的第一二极管32的阴极。第2级所述移位寄存单元FF1的第一二极管32的阴极和第3级所述移位寄存单元FF2的第一二极管33的阴极之间设置有一第二二极管42；第n-1级所述移位寄存单元FF（n-2）的第一二极管34的阴极和第n级所述移位寄存单元FF（n-1）的第一二极管35的阴极之间设置有一第二二极管44；第n级所述移位寄存单元FF（n-1）的第一二极管35的阴极和第n+1级所述移位寄存单元FF(n)的第一二极管36的阴极之间设置有一第二二极管45。其余的二极管与此类似。
通过设置第二二极管，能够在后面一级移位寄存单元触发时，将其输出的信号通过第二二极管传递给上一级移位寄存单元或者上面多级移位寄存单元对应的薄膜晶体管的控制端，从而减少ST的高电平输出时间，降低能耗；其第二二极管的连接方式，使得在上一级移位寄存单元触发时，防止上一级移位寄存单元输出的信号直接流向其后的移位寄存单元对应的薄膜晶体管的控制端中，避免T0-Tn同时输出子时钟信号，导致不能使得子时钟信号产生延迟。同时第一二级管能够防止，后面一级移位寄存单元将其输出信号传递给上面一级或者多级移位寄存单元对应的薄膜晶体管的控制端时，该信号流向前面的多级移位寄存单元的第一输出端。
譬如以第3级移位寄存单元为例，第二个第二二极管42能够防止，移位寄存单元FF2输出端的信号流向移位寄存单元FF3—FFn对应薄膜晶体管的控制端，避免CLK3- CLKn同时输出，第3级移位寄存单元的第一二极管33，能够防止移位寄存单元FF2输出端的信号流向移位寄存单元FF1—FF2的第一输出端。
优选地，第N级所述移位寄存单元的第一输出端通过第三二极管与第1级所述移位寄存单元的第一输入端连接，所述第三二极管的阳极连接所述第N级所述移位寄存单元的第一输出端；所述第三二极管的阴极连接所述第1级所述移位寄存单元的第一输入端。
譬如最后一级移位寄存器FFn的第一输出端46还连接至所述第1级所述移位寄存单元FF0的第一输入端22，所述第三二极管47的阳极连接最后一级移位寄存器FFn的第一输出端46，所述第三二极管47的阴极连接至所述第1级所述移位寄存单元FF0的第一输入端22。
通过将最后一级移位寄存单元的输出信号传递给第一级移位寄存单元的第一输入端，能够使得多相位时钟产生的多路子时钟信号的输出时间延长。
如图4所示，时序控制器芯片50仅需要输出3个信号给多相位时钟产生电路51、多相位时钟产生电路51就能产生多路子时钟信号CLK1-CLKn给行扫描驱动芯片52，减少了时序控制器芯片50和多相位时钟产生电路51的管脚数目，而现有的多相位时钟产生电路需要输入多路时钟信号，生产成本较高，对比看出，本发明的多相位时钟产生电路只需要输入一个时钟信号，通过延迟控制信号的控制，就可以形成多个相位时钟，减少了相应芯片的管脚，因为可以降低生产成本。
本发明的多相位时钟产生电路的工作原理为：如图3所示，
当ST为高电平时，且CP信号为上升沿时，使得FF0触发，FF0输出一个高脉冲，薄膜晶体管T0闭合，使得CLK信号通过T0的输出端输出CLK1；当CP信号的第二个上升沿到来时，使得FF1触发，FF0将ST的信号传递给FF1。
譬如ST为高电平，且在时间为t1时，CP信号第一个上升沿到来，使得FF0触发，FF0输出一个高脉冲，薄膜晶体管T0闭合，使得CLK信号通过T0的输出端输出CLK1；
在时间为t2时，CP信号第二个上升沿到来，使得FF1触发，FF1输出一个高脉冲，薄膜晶体管T1闭合，由于薄膜晶体管T0的控制端连接FF1的输出端，因此也会使得薄膜晶体管T0闭合，使得CLK信号通过T0的输出端输出CLK1以及通过T1的输出端输出CLK2；
在时间为t3时，CP信号第三个上升沿到来，使得FF2触发，FF2输出一个高脉冲，薄膜晶体管T2闭合；由于薄膜晶体管T1、T0的控制端连接FF2的输出端，因此也会使得薄膜晶体管T1、 T0闭合；使得CLK信号通过T0的输出端输出CLK1、通过T1的输出端输出CLK2、以及通过T2的输出端输出CLK3；
在时间为t4时，CP信号第四个上升沿到来，使得FF3触发，FF3输出一个高脉冲，薄膜晶体管T3闭合，由于薄膜晶体管T2、T0 、T1的控制端连接FF3的输出端，因此也会使得薄膜晶体管T2 、T0 、T1闭合；使得CLK信号通过T0的输出端输出CLK1、通过T1的输出端输出CLK2、通过T2的输出端输出CLK3、通过T3的输出端输出CLK4；
在时间为tn+1时，CP信号第n个上升沿到来，使得FFn触发，FFn输出一个高脉冲，薄膜晶体管Tn闭合，由于薄膜晶体管Tn-1、以及Tn-2至T0的控制端连接FFn的输出端，因此也会使得薄膜晶体管Tn-1至T0闭合；使得CLK信号通过T0—Tn的输出端输出CLK1—CLKn+1。
优选地，根据所述延迟控制信号的周期确定第n路子时钟信号和第n+1路子时钟信号之间的时相位差。即CLK1，CLK2…CLKn依次输出CLK信号，相互之间的相位差可以通过CP信号的周期控制，且当CP的周期越大，时钟信号之间对应的相位差也越大。譬如图2，CLK1和CLK2之间的相位差等于所述CP的周期t2-t1。
优选地，根据所述起始控制信号的高电平的输出时间确定多路所述子时钟信号的输出时间。可以通过ST信号的高电平的输出时间来控制CLK信号被各通道输出的时间（即何时输出CLK1—CLKn），ST信号的占空比越大，CLK被各通道输出的时间也越长。
根据D触发器的原理，当ST信号的上升沿到来之后，CP信号的上升沿时，D触发器的输出端输出高电平，直至ST为低，且CP的下一个上升沿，D触发器的输出端输出低电平，使得薄膜晶体管断开不再输出相应的子时钟信号。所以ST信号的高电平输出的时间越长，D触发器的输出端输出的高电平亦越久。因此ST信号的占空比越大，D触发器的输出端输出的高电平亦越久，CLK被各通道输出的时间也越长 。
本发明的多相位时钟产生电路及液晶显示装置，通过对现有技术的时钟产生电路进行改进，使得只需要输入一路时钟信号就可以产生具有相位偏移的多路时钟，减少了时序控制芯片和电源管理芯片的管脚数，从而降低了生产成本。
本发明还提供一种液晶显示面板，其包括多条数据线和多条扫描线以及由所述数据线和所述扫描线限定的多个像素单元；以及
行扫描驱动芯片，所述行扫描驱动芯片用于向所述扫描线提供扫描信号；所述扫描信号根据多相位时钟产生电路的多路子时钟信号产生；
其中所述多相位时钟产生电路，包括：
移位寄存器，包括N个移位寄存单元，所述N个移位寄存单元相互级联；每个所述移位寄存单元具有第一输入端、第二输入端以及第一输出端，所述第一输入端输入起始控制信号，所述起始控制信号用于控制所述移位寄存器开启；所述第二输入端输入延迟控制信号，所述延迟控制信号用于控制所述移位寄存单元输出，第n级所述移位寄存单元的第一输出端与第n+1级所述移位寄存单元的第一输入端连接，其中N≥2，1≤n≤N；以及
薄膜晶体管组，包括N个薄膜晶体管，所述薄膜晶体管与所述移位寄存单元一一对应；每个所述薄膜晶体管具有第三输入端、控制端、第二输出端；每个所述薄膜晶体管的第三输入端输入主时钟信号，所述主时钟信号用于提供参考时钟；每个所述薄膜晶体管的第二输出端输出子时钟信号，所述子时钟信号用于输入到显示面板的行扫描驱动芯片中；其中第n级所述薄膜晶体管的控制端分别与（N-n+1）个所述移位寄存单元的第一输出端连接。
优选地，所述多相位时钟产生电路还包括第一二极管组，所述第一二极管组包括N个第一二极管，所述第一二极管与所述移位寄存单元一一对应；
所述第一二极管的阳极连接所述移位寄存单元的第一输出端，所述第一二极管的阴极连接所述薄膜晶体管的控制端。
优选地，所述多相位时钟产生电路还包括第二二极管组，所述第二二极管组包括N-1个第二二极管，每相邻两级的所述移位寄存单元通过一所述第二二极管连接；
第n个所述第二二极管的阴极连接第n级所述移位寄存单元的第一二极管的阴极，第n个所述第二二极管的阳极连接第n+1级所述移位寄存单元的第一二极管的阴极。
优选地，根据所述延迟控制信号的周期确定所述第n路子时钟信号和第n+1路子时钟信号之间的相位差。
优选地，根据所述起始控制信号的高电平的输出时间确定多路所述子时钟信号的输出时间。
优选地，第N级所述移位寄存单元的第一输出端通过第三二极管与第1级所述移位寄存单元的第一输入端连接，所述第三二极管的阳极连接所述第N级所述移位寄存单元的第一输出端；所述第三二极管的阴极连接所述第1级所述移位寄存单元的第一输入端。
本发明的液晶显示面板可包括上述任何一种多相位时钟产生电路，鉴于多相位时钟产生电路在上文已有详细的描述，此处不再赘述。
本发明的多相位时钟产生电路及液晶显示面板，通过对现有技术的时钟产生电路进行改进，使得只需要输入一路时钟信号就可以产生具有相位偏移的多路时钟，减少了时序控制芯片和电源管理芯片的管脚数，从而降低了生产成本。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (15)

  1. 一种多相位时钟产生电路，其包括：
    移位寄存器，包括N个移位寄存单元，所述N个移位寄存单元相互级联；每个所述移位寄存单元具有第一输入端、第二输入端以及第一输出端，所述第一输入端输入起始控制信号，所述起始控制信号用于控制所述移位寄存器开启；所述第二输入端输入延迟控制信号，所述延迟控制信号用于控制所述移位寄存单元输出，第n级所述移位寄存单元的第一输出端与第n+1级所述移位寄存单元的第一输入端连接，其中N≥2，1≤n≤N；以及
    薄膜晶体管组，包括N个薄膜晶体管，所述薄膜晶体管与所述移位寄存单元一一对应；每个所述薄膜晶体管具有第三输入端、控制端、第二输出端；每个所述薄膜晶体管的第三输入端输入主时钟信号，所述主时钟信号用于提供参考时钟；每个所述薄膜晶体管的第二输出端输出子时钟信号，所述子时钟信号用于输入到显示面板的行扫描驱动芯片中；其中第n级所述薄膜晶体管的控制端分别与（N-n+1）个所述移位寄存单元的第一输出端连接；
    第一二极管组，包括N个第一二极管，所述第一二极管与所述移位寄存单元一一对应；所述第一二极管的阳极连接所述移位寄存单元的第一输出端，所述第一二极管的阴极连接所述薄膜晶体管的控制端；
    第二二极管组，包括N-1个第二二极管，每相邻两级的所述移位寄存单元通过一所述第二二极管连接；第n个所述第二二极管的阴极连接第n级所述移位寄存单元的第一二极管的阴极，第n个所述第二二极管的阳极连接第n+1级所述移位寄存单元的第一二极管的阴极；
    其中，根据所述延迟控制信号的周期确定第n路子时钟信号和第n+1路子时钟信号之间的相位差。
  2. 根据权利要求1所述的多相位时钟产生电路，其中根据所述起始控制信号的高电平的输出时间确定多路所述子时钟信号的输出时间。
  3. 根据权利要求1所述的多相位时钟产生电路，其中
    第N级所述移位寄存单元的第一输出端通过第三二极管与第1级所述移位寄存单元的第一输入端连接，所述第三二极管的阳极连接所述第N级所述移位寄存单元的第一输出端；所述第三二极管的阴极连接所述第1级所述移位寄存单元的第一输入端。
  4. 一种多相位时钟产生电路，其包括：
    移位寄存器，包括N个移位寄存单元，所述N个移位寄存单元相互级联；每个所述移位寄存单元具有第一输入端、第二输入端以及第一输出端，所述第一输入端输入起始控制信号，所述起始控制信号用于控制所述移位寄存器开启；所述第二输入端输入延迟控制信号，所述延迟控制信号用于控制所述移位寄存单元输出，第n级所述移位寄存单元的第一输出端与第n+1级所述移位寄存单元的第一输入端连接，其中N≥2，1≤n≤N；以及
    薄膜晶体管组，包括N个薄膜晶体管，所述薄膜晶体管与所述移位寄存单元一一对应；每个所述薄膜晶体管具有第三输入端、控制端、第二输出端；每个所述薄膜晶体管的第三输入端输入主时钟信号，所述主时钟信号用于提供参考时钟；每个所述薄膜晶体管的第二输出端输出子时钟信号，所述子时钟信号用于输入到显示面板的行扫描驱动芯片中；其中第n级所述薄膜晶体管的控制端分别与（N-n+1）个所述移位寄存单元的第一输出端连接。
  5. 根据权利要求4所述的多相位时钟产生电路，其中所述多相位时钟产生电路还包括第一二极管组，所述第一二极管组包括N个第一二极管，所述第一二极管与所述移位寄存单元一一对应；
    所述第一二极管的阳极连接所述移位寄存单元的第一输出端，所述第一二极管的阴极连接所述薄膜晶体管的控制端。
  6. 根据权利要求5所述的多相位时钟产生电路，其中所述多相位时钟产生电路还包括第二二极管组，所述第二二极管组包括N-1个第二二极管，每相邻两级的所述移位寄存单元通过一所述第二二极管连接；
    第n个所述第二二极管的阴极连接第n级所述移位寄存单元的第一二极管的阴极，第n个所述第二二极管的阳极连接第n+1级所述移位寄存单元的第一二极管的阴极。
  7. 根据权利要求4所述的多相位时钟产生电路，其中根据所述延迟控制信号的周期确定第n路子时钟信号和第n+1路子时钟信号之间的相位差。
  8. 根据权利要求4所述的多相位时钟产生电路，其中根据所述起始控制信号的高电平的输出时间确定多路所述子时钟信号的输出时间。
  9. 根据权利要求4所述的多相位时钟产生电路，其中
    第N级所述移位寄存单元的第一输出端通过第三二极管与第1级所述移位寄存单元的第一输入端连接，所述第三二极管的阳极连接所述第N级所述移位寄存单元的第一输出端；所述第三二极管的阴极连接所述第1级所述移位寄存单元的第一输入端。
  10. 一种液晶显示面板，其包括：
    多条数据线和多条扫描线以及由所述数据线和所述扫描线限定的多个像素单元；以及
    行扫描驱动芯片，用于向所述扫描线提供扫描信号；所述扫描信号根据多相位时钟产生电路的多路子时钟信号产生；
    其中所述多相位时钟产生电路，包括：
    移位寄存器，包括N个移位寄存单元，所述N个移位寄存单元相互级联；每个所述移位寄存单元具有第一输入端、第二输入端以及第一输出端，所述第一输入端输入起始控制信号，所述起始控制信号用于控制所述移位寄存器开启；所述第二输入端输入延迟控制信号，所述延迟控制信号用于控制所述移位寄存单元输出，第n级所述移位寄存单元的第一输出端与第n+1级所述移位寄存单元的第一输入端连接，其中N≥2，1≤n≤N；以及
    薄膜晶体管组，包括N个薄膜晶体管，所述薄膜晶体管与所述移位寄存单元一一对应；每个所述薄膜晶体管具有第三输入端、控制端、第二输出端；每个所述薄膜晶体管的第三输入端输入主时钟信号，所述主时钟信号用于提供参考时钟；每个所述薄膜晶体管的第二输出端输出子时钟信号，所述子时钟信号用于输入到显示面板的行扫描驱动芯片中；其中第n级所述薄膜晶体管的控制端分别与（N-n+1）个所述移位寄存单元的第一输出端连接。
  11. 根据权利要求10所述的液晶显示面板，其中所述多相位时钟产生电路还包括第一二极管组，所述第一二极管组包括N个第一二极管，所述第一二极管与所述移位寄存单元一一对应；
    所述第一二极管的阳极连接所述移位寄存单元的第一输出端，所述第一二极管的阴极连接所述薄膜晶体管的控制端。
  12. 根据权利要求11所述的液晶显示面板，其中所述多相位时钟产生电路还包括第二二极管组，所述第二二极管组包括N-1个第二二极管，每相邻两级的所述移位寄存单元通过一所述第二二极管连接；
    第n个所述第二二极管的阴极连接第n级所述移位寄存单元的第一二极管的阴极，第n个所述第二二极管的阳极连接第n+1级所述移位寄存单元的第一二极管的阴极。
  13. 根据权利要求10所述的液晶显示面板，其中根据所述延迟控制信号的周期确定第n路子时钟信号和第n+1路子时钟信号之间的相位差。
  14. 根据权利要求10所述的液晶显示面板，其中根据所述起始控制信号的高电平的输出时间确定多路所述子时钟信号的输出时间。
  15. 根据权利要求10所述的液晶显示面板，其中
    第N级所述移位寄存单元的第一输出端通过第三二极管与第1级所述移位寄存单元的第一输入端连接，所述第三二极管的阳极连接所述第N级所述移位寄存单元的第一输出端；所述第三二极管的阴极连接所述第1级所述移位寄存单元的第一输入端。
PCT/CN2015/080468 2015-05-27 2015-06-01 一种多相位时钟产生电路及液晶显示面板 Ceased WO2016187893A1 (zh)

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