WO2016161776A1 - 显示面板、显示面板驱动方法及显示装置 - Google Patents

显示面板、显示面板驱动方法及显示装置 Download PDF

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Publication number
WO2016161776A1
WO2016161776A1 PCT/CN2015/090076 CN2015090076W WO2016161776A1 WO 2016161776 A1 WO2016161776 A1 WO 2016161776A1 CN 2015090076 W CN2015090076 W CN 2015090076W WO 2016161776 A1 WO2016161776 A1 WO 2016161776A1
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WIPO (PCT)
Prior art keywords
multiplexer
gate
type
line
data
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PCT/CN2015/090076
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English (en)
French (fr)
Inventor
杨明
董学
陈小川
许睿
王磊
王倩
刘鹏
卢鹏程
Original Assignee
京东方科技集团股份有限公司
北京京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US14/915,542 priority Critical patent/US9767725B2/en
Publication of WO2016161776A1 publication Critical patent/WO2016161776A1/zh
Priority to US15/687,877 priority patent/US10255840B2/en

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2085—Special arrangements for addressing the individual elements of the matrix, other than by driving respective rows and columns in combination
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0804—Sub-multiplexed active matrix panel, i.e. wherein one active driving circuit is used at pixel level for multiple image producing elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0297—Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2003—Display of colours

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a display panel, a display panel driving method, and a display device.
  • the display panel includes a source driving chip and a gate driving unit.
  • the source driving chip is responsible for receiving image data and buffering image data, converting the digital signal into an analog signal, and finally transmitting the converted analog signal to each data line of the display panel through the output buffer;
  • the gate driving The unit is responsible for implementing the progressive scan, generating the gate line scan signals corresponding to the respective gate lines according to the timing control, sequentially loading the gate line scan signals to the corresponding gate lines to control the pixel switches corresponding to the respective gate lines to be turned on line by line, so that the image is The data enters the storage capacitor of each row of pixels, and finally achieves the normal display of the image.
  • a source driving chip and a gate driving unit are simultaneously provided in a peripheral region thereof. Since the source driving chip and the gate driving unit both occupy the peripheral area of the display panel, the peripheral area of the display panel occupies a large area, which affects the visual effect of the display screen.
  • an embodiment of the present disclosure provides a display panel, a driving method of the display panel, and The display device solves the problem that the peripheral area of the display panel existing in the prior art is large and affects the visual effect of the display screen.
  • inventions of the present disclosure provide a display panel.
  • the display panel includes a display area and a peripheral area surrounding the display area; the display area is provided with: a plurality of gate lines extending along the first direction and a plurality of data lines extending along the second direction;
  • a multiplexer is disposed in the peripheral area pointed by the second direction; a signal input end of the multiplexer is connected in one-to-one correspondence with each output end of the source driving unit, and the first of the multiplexers
  • the output terminal of the class is connected in one-to-one correspondence with each of the data lines
  • the output terminal of the second type of the multiplexer is connected in one-to-one correspondence with each of the gate lines
  • the first type of control end of the multiplexer is
  • Each of the data line switch control lines is connected in one-to-one correspondence
  • the second type of control end of the multiplexer is connected to the gate line switch control line;
  • the multiplexer is configured to time-division the gate line signal output by the source driving unit to a corresponding gate line under control of a gate line turn-on signal input from the gate line switch control line;
  • the data signal output by the source driving unit is time-divisionally input to the corresponding data line under the control of the data line on signal input from the data line switch control line.
  • the multiplexer may include: a first type of switching transistor corresponding to the data line, and the gate line One-to-one correspondence of the second type of switching transistor;
  • the drains of the first type of switching transistors are respectively connected to the data lines, the sources are connected to the output ends of the source driving units, and the gates are connected to the data line switch control lines;
  • the drains of the second type of switching transistors are respectively connected to the gate lines, the sources are respectively connected to the output ends of the source driving units, and the gates are connected to the gate line switch control lines.
  • the number of the first type of control ends of the multiplexer is the same as the number of sub-pixels included in each pixel in the display area;
  • the number of signal input ends of the multiplexer is the same as the number of columns of pixels included in the display area.
  • the number of signal input ends of the multiplexer is equal to the number of the gate lines.
  • the multiplexer includes a plurality of sub-selectors, and the plurality of sub-selectors and the column of pixels included in the display area One correspondence
  • Each of the sub-selectors includes: a first-type switching transistor having the same number of sub-pixel columns as each column of pixels, and a second-type switching transistor.
  • the display area is further disposed between: connecting the second type of output end of the multiplexer and the corresponding gate line The gate voltage storage capacitor.
  • the gate voltage storage capacitor is composed of interconnected gate lines and a common sub-electrode, and the common sub-electrode and the common in each pixel
  • the electrodes are arranged in the same layer and are independent of each other.
  • the first direction is perpendicular to the second direction.
  • the first type of transistor and the second type of transistor are thin film transistors or metal oxide semiconductor field effect transistors.
  • Embodiments of the present disclosure provide a display device including the above display panel.
  • An embodiment of the present disclosure provides a driving method for driving the above display panel, including:
  • the second type of control terminals of the multiplexer are sequentially loaded with the gate line conduction signals of the same number of gate lines through the gate switch control line, and the gate conduction is performed every time the gate line is loaded.
  • a gate line signal is applied to a signal input end of the multiplexer through an output end of the source driving unit, and a low level signal is applied to other signal input ends of the multiplexer, so that
  • the second type of control end of the path selector sequentially loads the gate line turn-on signal
  • the second type of output end of the multiplexer sequentially outputs the gate line signals to the respective gate lines connected to the second type of output terminals;
  • the first type of control end of the multiplexer is sequentially turned on by each data line switch control line during a period between two times when the second type of control terminal of the multiplexer loads the gate-on signal Loading a data line turn-on signal, and simultaneously loading a data signal to each signal input end of the multiplexer through an output end of the source driving unit, so that the first type of output ends of the multiplexer are sequentially The data lines connected to the first type of output end output data signals.
  • the second type of control terminal of the multiplexer loads the data of the first type of control end of the multiplexer in turn through the data line switch control lines every time period between the gate turn-on signals After the line turns on the signal, it also includes:
  • a low level signal is applied to each signal input of the multiplexer through an output of the source drive unit.
  • the display panel provided by the embodiment of the present disclosure does not need to separately set the gate driving unit, and the gate driving function is integrated in the source driving unit and implemented by the multiplexer, and the corresponding gate line conduction and the pair are controlled in a time sharing manner.
  • the function of inputting the data signal of the data line can reduce the peripheral area of the display panel, and is beneficial to realize the narrow bezel design of the display panel and improve the visual effect of the display screen of the display panel.
  • FIG. 1 is a schematic structural view of a display panel in the related art
  • FIG. 2 to FIG. 3 are schematic structural diagrams of a display panel according to an embodiment of the present disclosure.
  • FIG. 4 is a timing diagram of input and output of a display panel according to an embodiment of the present disclosure.
  • the source driving chip is generally disposed at one of the upper and lower ends of the display panel, and the gate driving unit is disposed at one of the left and right ends of the display panel.
  • the source driving chip 1 is located at the upper end of the display panel
  • the gate driving unit 2 is located at the left end of the display panel
  • the data lines 3 and the gate lines 4 are vertically distributed to each other in the display area of the display panel. Since both the source driving chip 1 and the gate driving unit 2 occupy the peripheral area of the display panel, the peripheral area of the display panel occupies a large area, which affects the visual effect of the display screen.
  • the display panel includes a display area 01 and a peripheral area 02 surrounding the display area 01.
  • the display area 01 is provided with a plurality of gate lines extending along the first direction. 03 and a plurality of data lines 04 extending in the second direction.
  • a multiplexer 05 is disposed in the peripheral area 02 pointed by the second direction; multiple selection
  • the signal input terminals p1 and p2 of the device 05 are connected in one-to-one correspondence with the output terminals Data m1 and Data m2 of the source driving unit, and the first type of output terminals M1(a), M1(b), M1 of the multiplexer 05 ( c), M2 (a), M2 (b) and M2 (c) are connected one-to-one with each data line 04, and the second type of output terminals N1 and N2 of the multiplexer 05 are connected one-to-one with the respective gate lines 03.
  • the first type of control terminals o1, o2 and o3 of the multiplexer 05 are connected in one-to-one correspondence with the respective data line switch control lines SW B, SW G, SW R, and the second type of control terminal Q of the multiplexer 05 Connected to the gate line switch control line SW gate.
  • the multiplexer 05 is configured to input the gate line signal outputted by the source driving unit to the corresponding gate line 03 under the control of the gate line on signal input from the gate line switch control line SW gate;
  • the data signal output from the source driving unit is time-divisionally input to the corresponding data line 04 under the control of the data line ON signal input from the data line switch control lines SW B, SW G, and SW R .
  • the display panel provided by the embodiment of the present disclosure does not need to separately set the gate driving unit, and the gate driving function is integrated in the source driving unit and implemented by the multiplexer, and the corresponding gate line conduction is controlled in a time sharing manner.
  • the function of inputting a data signal to the data line can reduce the peripheral area of the display panel, thereby facilitating the design of the narrow frame of the display panel and improving the visual effect of the display screen of the display panel.
  • the gate of the source driving unit is output.
  • the gate line signal on the gate line 03 can be continuously supplied until the charging of each pixel connected to the row gate line 03 is completed.
  • the display area can generally also be provided with:
  • the gate voltage storage capacitors Cn1 and Cn2 connected between the second type of output terminals N1 and N2 of the multiplexer 05 and the corresponding gate line 03 are independent of each other.
  • the capacitance values of the gate voltage storage capacitors Cn1 and Cn2 are between several pF and several hundred pF.
  • the gate voltage storage capacitors Cn1 and Cn2 may be composed of interconnected gate lines 03 and common sub-electrodes, which are disposed in the same layer as the common electrodes in each pixel and are independent of each other. In some display panel manufacturing processes, it is not necessary to add a new process step to complete the fabrication of the gate voltage storage capacitor, and the aperture ratio of each pixel is not lowered. Of course, in a specific implementation, a new film layer may be added to the display panel, and the gate voltage storage capacitor structure is formed by using the newly added film layer and the gate line, which will not be described in detail herein.
  • the multiplexer 05 may specifically include: first-type switching transistors T R1 and T R2 corresponding to the data line 04. And T G1 , T G2 , T B1 and T B2 , and the second type of switching transistors Tn1 and Tn2 corresponding to the gate line 03 one by one.
  • the drains of the first type of switching transistors T R1 , T R2 , T G1 , T G2 , T B1 , and T B2 are respectively connected to the data line 04 , and the output terminals of the source and source driving units are Data m1 and Data.
  • M2 is connected, and the gate is connected to the data line switch control lines SW B, SW G, SW R ;
  • the drains of the second type of switching transistors Tn1 and Tn2 are respectively connected to the gate line 03, the sources are respectively connected to the output terminals Data m1 and Data m2 of the source driving unit, and the gate is connected to the gate line switching control line SW gate.
  • the first type of switching transistors T R1 , T R2 , T G1 , T G2 , T B1 , and T B2 are at the time when the connected data line switch control lines SW B, SW G, SW R are loaded with the data line turn-on signal.
  • the data signals currently outputted by the output terminals Data m1 and Data m2 of the source driving unit connected to the source of the first type of switching transistor can pass through the first type of switching transistors T R1 , T R2 , T G1 , T G2 , T B1 and T B2 are loaded onto the corresponding data line 04, thereby completing the function of charging the data line 04.
  • the second type of switching transistors Tn1 and Tn2 are in an on state when the connected gate line switch control line SW gate is loaded with the gate line turn-on signal, and the output of the source driving unit connected to the source of the second type of switching transistor can be
  • the gate line signals currently outputted by the terminals Data m1 and Data m2 are loaded onto the corresponding gate lines 03 through the second type of switching transistors Tn1 and Tn2, thereby completing the function of charging the gate lines 03.
  • the first type of switching transistor T is known.
  • the sources of R1 , T R2 , T G1 , T G2 , T B1 and T B2 and the second type of switching transistors Tn1 and Tn2 are both connected to the output terminals Data m1 and Data m2 of the source driving unit, in order to ensure the source driving unit
  • the output signals of Data m1 and Data m2 can be accurately loaded onto the corresponding gate line 03 or data line 04.
  • the data line switch control lines SW B, SW G, SW R and the gate line are generally used.
  • the switch control line SW gate time-divisionally loads the data line turn-on signal and the gate line turn-on signal to turn on the first type of switching transistors T R1 , T R2 , T G1 , T G2 , T B1 and T B2 and the second Class switching transistors Tn1 and Tn2.
  • FIG. 3 only two columns of pixels, two gate lines, two output ends of the source driving unit and two input ends of the multiplexer are shown in FIG. 3; in practical applications, the display panel is shown. There may be a plurality of columns of pixels provided with a plurality of gate lines, the source drive unit may have a plurality of outputs, and the multiplexer may have a plurality of inputs, and the specific number thereof is not limited in the present disclosure.
  • the number of interfaces of the multiplexer 05 disposed in the peripheral area of the display panel is proportional to the complexity of the display panel fabrication, in order to minimize the number of output terminals of the source driving unit, that is, to reduce the multipath
  • the number of signal inputs of the selector 05 is simplified to simplify the circuit complexity.
  • the number of signal input terminals of the multiplexer 05 is set to be the same as the number of columns of pixels included in the display area, so that the source drive unit
  • the data signal outputted by one output terminal can be time-divisionally loaded onto the data line corresponding to each sub-pixel included in a column of pixels.
  • the number of the first type of control terminals of the multiplexer 05 that is, the number of data line switch control lines, should be set to be the same as the number of sub-pixels included in each pixel in the display area.
  • one column of pixels is composed of three columns of sub-pixels R, G, and B. Therefore, the display panel is provided with three data line switch control lines SW B, SW G, and SW R through the data.
  • the line switch control lines SW B, SW G, SW R time-divisionally load the data line turn-on signal, and the data signal outputted from one output end of the source drive unit can be loaded into the three columns of sub-pixels by the multiplexer 05.
  • Data line Data line.
  • the number of signal input terminals of the multiplexer 05 can be set to be the same as the number of the gate lines 03, so that the second type of switching transistors connected to the gate lines 03 can be connected one-to-one.
  • the source is connected in one-to-one correspondence with the output end of the source driving unit, and the gate line signal outputted by the output end of each source driving unit is selected when the gate line conducting signal is loaded on the gate line conducting control line SW gate
  • the gate line 03 required for conduction is turned on.
  • the number of signal input ends of the multiplexer 05 may also be greater than the number of the gate lines 03, and details are not described herein.
  • the multiplexer 05 in the above display panel provided by the embodiment of the present disclosure may be divided into multiple sub-selectors, for example, may be divided in such a manner that one sub-selector includes an input of one multiplexer.
  • the multiplexer 05 when one input terminal of the multiplexer 05 is time-divided to provide data signals for a column of sub-pixels, the multiplexer 05 can be divided into one-to-one correspondence with the plurality of columns of pixels included in the display area. Multiple sub-selectors. For example, as shown in FIG.
  • each sub-selector includes: the number is the same as the number of sub-pixel columns included in each pixel column.
  • the first type of switching transistor and the second type of switching transistor.
  • Each of the sub-selectors in Figure 3 includes three first-type switching transistors and one second
  • the source of the class switching transistor is connected to an output terminal of the source driving unit, so that the signal output from the output terminal can be loaded to the corresponding gate line and data line through the sub selector.
  • the switching transistor mentioned in the above embodiments of the present disclosure may be a thin film transistor (TFT) or a metal oxide semiconductor field effect transistor (MOS), which is not limited herein. .
  • TFT thin film transistor
  • MOS metal oxide semiconductor field effect transistor
  • the sources and drains of these transistors can be interchanged without specific distinction.
  • a thin film transistor will be described as an example in describing a specific embodiment.
  • an embodiment of the present disclosure further provides a driving method of the foregoing display panel, including:
  • the second type of control terminal of the multiplexer is sequentially loaded with the same gate line on-line signal by the gate switch control line, and the gate-on signal is loaded each time the gate-on signal is loaded.
  • the gate line signal is loaded to a signal input end of the multiplexer through the output end of the source driving unit, and the low level signal is loaded to the other signal input end of the multiplexer, so that the second type of the multiplexer is
  • the control terminal sequentially loads the gate line turn-on signal
  • the second type of output terminal of the multiplexer sequentially outputs the gate line signals to the respective gate lines connected to the second type of output terminals;
  • the control lines are sequentially passed through the data lines. After loading the data line turn-on signal on the first type of control end of the multiplexer, the following steps may also be included:
  • a low level signal is applied to each signal input end of the multiplexer through the output terminal of the source driving unit to ensure that the signal on the gate line can be reset.
  • a high voltage is applied to the gate line conduction control line SW gate, and the second type of switching transistors Tn1 and Tn2 are controlled to be in an on state; at this time, the high voltage Vgh of the output terminal Data m1 of the source driving unit is gated.
  • the pole voltage storage capacitor Cn1 is charged to increase the voltage of the gate line GLn1, and at the end of the first phase, the voltage of the gate line GLn1 reaches a peak value.
  • the gate line GLn1 voltage enters the hold phase due to the action of the gate voltage storage capacitor Cn1.
  • the signal of the output terminal Data m2 other than the output terminal Data m1 of the source driving unit is at a low level. Therefore, although the second type switching transistor Tn2 is in an on state, the gate line GLn2 is in the pull state. Low reset state.
  • a low voltage is applied to the gate line conduction control line SW gate to control the second type of switching transistor Tn1 to be in an off state; a high voltage is applied to the data line conduction control line SW R to control the data line
  • the first type of switching transistors T R1 and T R2 connected to the conduction control line SW R are in an on state, so that the signals of the output terminals Data m1 and Data m2 of the source driving unit are loaded to the corresponding data lines Dm1(R) and Dm2 ( R).
  • the gate line GLn1 since the gate line GLn1 is kept in an on state, the sub-pixels connected to the data lines Dm1(R) and Dm2(R) can be charged, and the row of GLn1, the row of Dm1(R), Dm2(R) The red sub-pixels reach the LR (m1n1) and LR (m2n1) gray levels, respectively.
  • a high voltage is applied to the data line conduction control line SW G, and the first type of switching transistors T G1 and T G2 connected to the data line conduction control line SW G are controlled to be in an on state, so that the source is driven.
  • the signals of the output terminals Data m1 and Data m2 of the unit are loaded onto the corresponding data lines Dm1(G) and Dm2(G).
  • the gate line GLn1 since the gate line GLn1 is kept in the on state, the sub-pixels connected to the data lines Dm1(G) and Dm2(G) can be charged, and the row of GLn1, the row of Dm1(G), Dm2(G) The green sub-pixels reach the LG (m1n1) and LG (m2n1) gray levels, respectively.
  • a high voltage is applied to the data line conduction control line SW B, and the first type of switching transistors T B1 and T B2 connected to the data line conduction control line SW B are controlled to be in an on state, so that the source is driven.
  • the signals of the output terminals Data m1 and Data m2 of the unit are loaded onto the corresponding data lines Dm1(B) and Dm2(B).
  • the sub-pixels connected to the data lines Dm1(B) and Dm2(B) can be charged, and the row of GLn1, the row of Dm1(B), Dm2(B)
  • the blue sub-pixels reach the LB (m1n1) and LB (m2n1) gray levels, respectively.
  • the gate line conduction control line SW gate and the data line conduction control lines SW R, SW G, and SW B are both applied with a low voltage, and the output terminals of the source driving unit are outputted by Data m1 and Data m2.
  • the signal is also low voltage, so that the charge on the gate voltage storage capacitor Cn1 can be released, so that the gate line GLn1 voltage is further lowered.
  • the fifth phase is shorter.
  • the time occupied by the fifth stage may be zero.
  • a high voltage is applied to the gate line conduction control line SW gate, and the second type of switching transistors Tn1 and Tn2 are controlled to be in an on state; at this time, the low voltage Vg1 loaded by the output terminal Data m1 of the source driving unit makes the gate The pole voltage storage capacitor Cn1 discharges, pulling down the voltage of the gate line GLn1; the high voltage Vgh loaded by the output terminal Data m2 of the source driving unit charges the gate voltage storage capacitor Cn2, so that the voltage of the gate line GLn2 rises, at the sixth At the end of the phase, the voltage of the gate line GLn2 reaches a peak. After the sixth stage, the gate line GLn2 voltage enters the hold phase due to the action of the gate voltage storage capacitor Cn2.
  • a low voltage is applied to the gate line conduction control line SW gate to control the second type of switching transistor Tn2 to be in an off state; a high voltage is applied to the data line conduction control line SW R to control the data line
  • the first type of switching transistors T R1 and T R2 connected to the conduction control line SW R are in an on state, so that the signals of the output terminals Data m1 and Data m2 of the source driving unit are loaded to the corresponding data lines Dm1(R) and Dm2 ( R).
  • the gate line GLn2 since the gate line GLn2 is kept in an on state, the sub-pixels connected to the data lines Dm1(R) and Dm2(R) can be charged, and the row of GLn2, the row of Dm1(R), Dm2(R) The red sub-pixels reach the LR (m1n2) and LR (m2n2) gray levels, respectively.
  • a high voltage is applied to the data line conduction control line SW G, and the first type of switching transistors T G1 and T G2 connected to the data line conduction control line SW G are controlled to be in an on state, so that the source is driven.
  • the signals of the output terminals Data m1 and Data m2 of the unit are loaded to the corresponding data lines Dm1(G) and Dm2(G).
  • the gate line GLn2 since the gate line GLn2 is kept in the on state, the sub-pixels connected to the data lines Dm1(G) and Dm2(G) can be charged, and the row of GLn2, Dm1(G), Dm2(G) can be seated.
  • the green sub-pixels of the column reach the LG (m1n2) and LG (m2n2) gray levels, respectively.
  • a high voltage is applied to the data line conduction control line SW B, and the first type of switching transistors T B1 and T B2 connected to the data line conduction control line SW B are controlled to be in an on state, so that the source is driven.
  • the signals of the output terminals Data m1 and Data m2 of the unit are loaded onto the corresponding data lines Dm1(B) and Dm2(B).
  • the gate line GLn2 since the gate line GLn2 is kept in the on state, the sub-pixels connected to the data lines Dm1(B) and Dm2(B) can be charged, and the row of GLn2, the row of Dm1(B), Dm2(B) The blue sub-pixels reach the LB (m1n2) and LB (m2n2) gray levels, respectively.
  • the switching transistor is active as an active level as an example. In practical applications, the switching transistors may all be active low, or Part of the active low part is active high and will not be described here.
  • an embodiment of the present disclosure further provides a display device including the display panel provided by the above embodiment of the present disclosure.
  • the display device can be any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • a display function such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • a display panel, a driving method of the display panel, and a display device are provided by the embodiments of the present disclosure.
  • the display panel includes a display area and a peripheral area surrounding the display area; the display area is provided with a plurality of gate lines extending in the first direction and a plurality of data lines extending in the second direction.
  • a multiplexer is disposed in the peripheral area pointed by the second direction, and the signal input end of the multiplexer is connected to the output ends of the source driving unit in a one-to-one correspondence, and the multiplexer
  • a type of output end is connected to each of the data lines in one-to-one correspondence
  • a second type of output end of the multiplexer is connected to each gate line in one-to-one correspondence
  • the first type of control end of the multiplexer and each The data line switch control lines are connected one-to-one
  • the second type of control end of the multiplexer is connected to the gate line switch control line.
  • the multiplexer is configured to input the gate line signal outputted by the source driving unit to the corresponding gate line in time under the control of the gate line on signal input from the gate line switch control line; and control at the slave data line switch Under the control of the data line conduction signal of the line input, the data signal output by the source driving unit is time-divisionally input to the corresponding data line.
  • the display panel provided by the embodiment of the present disclosure does not need to separately set the gate driving unit, and the gate driving function is integrated in the source driving unit and implemented by the multiplexer, and the corresponding gate line conduction and the pair are controlled in a time sharing manner.
  • the function of inputting the data signal of the data line can reduce the peripheral area of the display panel, and is beneficial to realize the narrow bezel design of the display panel and improve the visual effect of the display screen of the display panel.

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Abstract

一种显示面板、显示面板的驱动方法及显示装置。该显示面板包括显示区域（01）和包围显示区域（01）的周边区域（02）。在显示区域（01）内设置有：沿第一方向延伸的多条栅线（03）和沿第二方向延伸的多条数据线（04）。在所述第二方向指向的周边区域（02）内设置有多路选择器（05）。多路选择器（05）在从栅线开关控制线(SW gate)输入的栅线导通信号的控制下，将源极驱动单元输出的栅线信号分时输入到对应的栅线（03）；在从数据线开关控制线（SW B、SW G、SW R）输入的数据线导通信号的控制下，将源极驱动单元输出的数据信号分时输入到对应的数据线（04）。

Description

显示面板、显示面板驱动方法及显示装置
相关申请的交叉参考
本申请主张在2015年4月8日在中国提交的中国专利申请号No.201510163660.6的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示技术领域，尤其涉及一种显示面板、显示面板驱动方法及显示装置。
背景技术
目前，显示技术被广泛应用于电视、手机等用户专用电子产品以及公共信息的显示，用于显示画面的显示面板也多种多样，显示的画面丰富多彩。一般地，显示面板包括源驱动芯片和栅极驱动单元。其中，所述源驱动芯片负责接收图像数据并缓存图像数据，将数字信号转换为模拟信号，最终将转换得到的模拟信号通过输出缓冲器输送到显示面板的各条数据线；所述栅极驱动单元负责实现逐行扫描，根据时序控制产生对应各行栅线的栅线扫描信号，将所述栅线扫描信号依次加载到对应的栅线以控制对应各行栅线的像素开关逐行打开，使图像数据进入每行像素的存储电容，最终实现图像的正常显示。
相关技术中的显示面板的结构，在其周边区域中会同时设置有源极驱动芯片和栅极驱动单元。由于源极驱动芯片和栅极驱动单元都占用了显示面板的周边区域，显示面板的周边区域占用面积较大，影响了显示画面的视觉效果。
由上可知，如何实现显示面板的窄边框设计，从而提高显示画面的视觉效果，是本领域技术人员亟待解决的技术问题。
发明内容
有鉴于此，本公开实施例提供了一种显示面板、显示面板的驱动方法及 显示装置，用以解决现有技术中存在的显示面板的周边区域较大，影响显示画面的视觉效果的问题。
因此，本公开实施例提供了一种显示面板。所述显示面板包括显示区域和包围所述显示区域的周边区域；所述显示区域中设置有：沿第一方向延伸的多条栅线和沿第二方向延伸的多条数据线；
所述第二方向指向的周边区域内设置有多路选择器；所述多路选择器的信号输入端与源极驱动单元的各输出端一一对应连接，所述多路选择器的第一类输出端与各所述数据线一一对应连接，所述多路选择器的第二类输出端与各所述栅线一一对应连接，所述多路选择器的第一类控制端与各数据线开关控制线一一对应连接，并且所述多路选择器的第二类控制端与栅线开关控制线连接；
所述多路选择器用于，在从所述栅线开关控制线输入的栅线导通信号的控制下，将所述源极驱动单元输出的栅线信号分时输入到对应的栅线；以及在从所述数据线开关控制线输入的数据线导通信号的控制下，将所述源极驱动单元输出的数据信号分时输入到对应的数据线。
在一种可能的实施方式中，本公开实施例提供的上述显示面板中，所述多路选择器可包括：与所述数据线一一对应的第一类开关晶体管，以及与所述栅线一一对应的第二类开关晶体管；
所述第一类开关晶体管的漏极分别与所述数据线连接，源极与所述源极驱动单元的输出端连接，栅极与所述数据线开关控制线连接；
所述第二类开关晶体管的漏极分别与所述栅线连接，源极分别与所述源极驱动单元的输出端连接，栅极与所述栅线开关控制线连接。
在一种可能的实施方式中，本公开实施例提供的上述显示面板中，所述多路选择器的第一类控制端的个数与所述显示区域内各像素包含的亚像素个数相同；
所述多路选择器的信号输入端的个数与所述显示区域内所包含像素的列数相同。
在一种可能的实施方式中，本公开实施例提供的上述显示面板中，所述多路选择器的信号输入端的个数等于所述栅线的个数。
在一种可能的实施方式中，本公开实施例提供的上述显示面板中，所述多路选择器包含多个子选择器，所述多个子选择器与所述显示区域内所包含各列像素一一对应；
每个所述子选择器包括：与每列像素包含的亚像素列数相同的第一类开关晶体管，以及一个第二类开关晶体管。
在一种可能的实施方式中，本公开实施例提供的上述显示面板中，所述显示区域中还设置有：连接于所述多路选择器的第二类输出端与对应的栅线之间的栅极电压存储电容。
在一种可能的实施方式中，本公开实施例提供的上述显示面板中，所述栅极电压存储电容由互相连接的栅线与公共子电极组成，所述公共子电极与各像素中的公共电极同层设置且相互独立。
在一种可能的实施方式中，本公开实施例提供的上述显示面板中，所述第一方向垂直于所述第二方向。
在一种可能的实施方式中，本公开实施例提供的上述显示面板中，所述第一类晶体管和第二类晶体管是薄膜晶体管或金属氧化物半导体场效应管。
本公开实施例提供了一种显示装置，包括上述显示面板。
本公开实施例提供了一种本用于驱动上述显示面板的驱动方法，包括：
在每帧的显示时间内，通过栅极开关控制线对多路选择器的第二类控制端依次加载与栅线个数相同的栅线导通信号，在每次加载所述栅极导通信号的同时，通过源极驱动单元的输出端对所述多路选择器的一信号输入端加载栅线信号，对所述多路选择器的其他信号输入端加载低电平信号，使得对多路选择器的第二类控制端依次加载栅线导通信号时，所述多路选择器的第二类输出端依次对与所述第二类输出端连接的各栅线输出栅线信号；
在所述多路选择器的第二类控制端每两次加载栅极导通信号之间的时间段内，通过各数据线开关控制线依次对所述多路选择器的第一类控制端加载数据线导通信号，同时通过所述源极驱动单元的输出端对所述多路选择器的各信号输入端加载数据信号，使所述多路选择器的第一类输出端依次对与所述第一类输出端连接的数据线输出数据信号。
在一种可能的实现方式中，本公开实施例提供的上述驱动方法中，在所 述多路选择器的第二类控制端每两次加载栅极导通信号之间的时间段内，通过各数据线开关控制线依次对所述多路选择器的第一类控制端加载数据线导通信号之后，还包括：
通过所述源极驱动单元的输出端对所述多路选择器的各信号输入端加载低电平信号。
本公开实施例提供的显示面板中无需单独设置栅极驱动单元，栅极驱动功能集成在源极驱动单元中并通过多路选择器实现，采用分时的方式实现控制对应栅线导通和对数据线输入数据信号的功能，这样可以减小显示面板的周边区域，有利于实现显示面板的窄边框设计，提高显示面板显示画面的视觉效果。
附图说明
图1为相关技术中显示面板的结构示意图；
图2-图3为本公开实施例提供的显示面板的结构示意图；
图4为本公开实施例提供的显示面板的输入输出时序图。
具体实施方式
相关技术中的显示面板中，一般将源极驱动芯片设置在显示面板的上下两端中的一端，将栅极驱动单元设置在显示面板左右两端中的一端。如图1所示，源极驱动芯片1位于显示面板的上端，栅极驱动单元2位于显示面板的左端，数据线3与栅线4彼此垂直分布于显示面板的显示区域。由于源极驱动芯片1和栅极驱动单元2都占用了显示面板的周边区域，显示面板的周边区域占用面积较大，影响了显示画面的视觉效果。
下面结合附图，对本公开实施例提供的显示面板、其驱动方法及显示装置的具体实施方式进行详细地说明。
本公开一实施例提供了一种显示面板，如图2所示，显示面板包括显示区域01和包围显示区域01的周边区域02，显示区域01中设置有沿第一方向延伸的多条栅线03和沿第二方向延伸的多条数据线04。
在所述第二方向指向的周边区域02内设置有多路选择器05；多路选择 器05的信号输入端p1和p2与源极驱动单元的输出端Data m1和Data m2一一对应连接，多路选择器05的第一类输出端M1(a)、M1(b)、M1(c)、M2(a)、M2(b)和M2(c)与各数据线04一一对应连接，多路选择器05的第二类输出端N1和N2与各栅线03一一对应连接，多路选择器05的第一类控制端o1、o2和o3与各数据线开关控制线SW B、SW G、SW R一一对应连接，并且多路选择器05的第二类控制端Q与栅线开关控制线SW gate连接。
多路选择器05用于，在从栅线开关控制线SW gate输入的栅线导通信号的控制下，将源极驱动单元输出的栅线信号分时输入到对应的栅线03；在从数据线开关控制线SW B、SW G、SW R输入的数据线导通信号的控制下，将源极驱动单元输出的数据信号分时输入到对应的数据线04。
本公开实施例提供的上述显示面板中无需单独设置栅极驱动单元，栅极驱动功能集成在源极驱动单元中并通过多路选择器实现，采用分时的方式实现控制对应栅线导通和对数据线输入数据信号的功能，这样可以减小显示面板的周边区域，有利于实现显示面板的窄边框设计，提高显示面板显示画面的视觉效果。
进一步地，在本公开实施例提供的上述显示面板中，为了保证多路选择器05在从栅线开关控制线SW gate输入的栅线导通信号的控制下，将源极驱动单元输出的栅线信号输入到对应的栅线03之后，栅线03上的栅线信号可以持续提供直到与该行栅线03连接的各像素充电完成，如图2所示，显示区域一般还可以设置有：连接于多路选择器05的第二类输出端N1和N2与对应的栅线03之间的栅极电压存储电容Cn1和Cn2，这些栅极电压存储电容相互独立。可选的，所述栅极电压存储电容Cn1和Cn2的电容值在几pF到几百pF之间。
在具体实施时，所述栅极电压存储电容Cn1和Cn2可以由相互连接的栅线03与公共子电极组成，所述公共子电极与各像素中的公共电极同层设置且相互独立，这样在原有的显示面板制作工艺中无需增加新的工艺步骤完成栅极电压存储电容的制作，并且也不会降低各像素的开口率。当然，在具体实施时，也可以在显示面板中增加新的膜层，利用所述新增膜层与栅线形成上述栅极电压存储电容结构，在此不作详述。
在具体实施时，本公开实施例提供的上述显示面板中，多路选择器05，如图3所示，可以具体包括：与数据线04一一对应的第一类开关晶体管TR1、TR2、TG1、TG2、TB1和TB2，以及与栅线03一一对应的第二类开关晶体管Tn1和Tn2。
其中，所述第一类开关晶体管TR1、TR2、TG1、TG2、TB1和TB2的漏极分别与数据线04连接，源极与源极驱动单元的输出端Data m1和Data m2连接，栅极与数据线开关控制线SW B、SW G、SW R连接；
第二类开关晶体管Tn1和Tn2的漏极分别与栅线03连接，源极分别与源极驱动单元的输出端Data m1和Data m2连接，栅极与栅线开关控制线SW gate连接。
具体地，第一类开关晶体管TR1、TR2、TG1、TG2、TB1和TB2在连接的数据线开关控制线SW B、SW G、SW R加载有数据线导通信号时处于导通状态，可以将与第一类开关晶体管的源极连接的源极驱动单元的输出端Data m1和Data m2当前输出的数据信号通过第一类开关晶体管TR1、TR2、TG1、TG2、TB1和TB2加载到对应的数据线04上，从而完成对数据线04进行充电的功能。第二类开关晶体管Tn1和Tn2在连接的栅线开关控制线SW gate加载有栅线导通信号时处于导通状态，可以将与第二类开关晶体管的源极连接的源极驱动单元的输出端Data m1和Data m2当前输出的栅线信号通过第二类开关晶体管Tn1和Tn2加载到对应的栅线03上，从而完成对栅线03进行充电的功能。
进一步地，从上述第一类开关晶体管TR1、TR2、TG1、TG2、TB1和TB2和第二类开关晶体管Tn1和Tn2的连接关系和工作原理可知，第一类开关晶体管TR1、TR2、TG1、TG2、TB1和TB2和第二类开关晶体管Tn1和Tn2的源极均与源极驱动单元的输出端Data m1和Data m2连接，为了保证源极驱动单元的输出端Data m1和Data m2输出的信号可以准确的加载到对应的栅线03或数据线04上，在具体实施时，一般采用数据线开关控制线SW B、SW G、SW R和栅线开关控制线SW gate分时加载数据线导通信号和栅线导通信号的方式以分时开启第一类开关晶体管TR1、TR2、TG1、TG2、TB1和TB2和第二类开关晶体管Tn1和Tn2。
需要说明的是，图3中仅仅示出了两列像素，两条栅线，源极驱动单元的两个输出端以及多路选择器的两个输入端；在实际应用中，所示显示面板 可包含多列像素，设置有多条栅线，所述源极驱动单元可具有多个输出端，所述多路选择器可具有多个输入端，本公开中不对其具体数量进行限制。
进一步地，由于显示面板的周边区域内设置的多路选择器05的接口数量与显示面板制作复杂程度成正比，在具体实施时，为了尽量减少源极驱动单元的输出端的数量，即减少多路选择器05的信号输入端的数量，以简化电路复杂程度，一般将多路选择器05的信号输入端的个数与显示区域内所包含的像素的列数设置为相同，这样，源极驱动单元的一个输出端输出的数据信号可以分时加载到一列像素中包含的各亚像素对应的数据线上。对应地，多路选择器05的第一类控制端的个数，即数据线开关控制线的个数，应设置为与显示区域内各像素包含的亚像素个数相同。
在如图3所示的显示面板中，一列像素由三列亚像素R、G、B组成，因此，所述显示面板设置有三条数据线开关控制线SW B、SW G、SW R，通过数据线开关控制线SW B、SW G、SW R分时加载数据线导通信号，源极驱动单元的一个输出端输出的数据信号可以通过多路选择器05分时加载到这三列亚像素对应的数据线上。
进一步地，在具体实施时，可以将多路选择器05的信号输入端的个数设置为与栅线03的个数相同，这样，可以将与栅线03一一对应连接的第二类开关晶体管的源极与源极驱动单元的输出端一一对应连接，通过在栅线导通控制线SW gate加载有栅线导通信号时，各源极驱动单元的输出端输出的栅线信号选择性地导通所需的栅线03。当然，在具体实施时，多路选择器05的信号输入端的个数也可以大于栅线03的个数，在此不作赘述。
在具体实施时，本公开实施例提供的上述显示面板中的多路选择器05可以划分为多个子选择器，例如可以按照一个子选择器包含一个多路选择器的输入端的方式进行划分。如图3所示，在多路选择器05的一个输入端分时为一列亚像素提供数据信号时，可以将多路选择器05划分为与显示区域内所包含的多列像素一一对应的多个子选择器。例如图3所示，将多路选择器05分为如虚线框所示的左右两个子选择器；这样，每个子选择器包括：个数与每个像素列中包含的亚像素列个数相同的第一类开关晶体管，以及一个第二类开关晶体管。图3中每个子选择器包含的三个第一类开关晶体管和一个第二 类开关晶体管的源极均与源极驱动单元的一个输出端连接，这样可以通过所述子选择器将该输出端输出的信号加载到对应的栅线和数据线上。
需要说明的是本公开上述实施例中提到的开关晶体管可以是薄膜晶体管(TFT，Thin Film Transistor)，也可以是金属氧化物半导体场效应管(MOS，Metal Oxide Semiconductor)，在此不做限定。在具体实施中，这些晶体管的源极和漏极可以互换，不做具体区分。在描述具体实施例时以薄膜晶体管为例进行说明。
基于同一构思，本公开一实施例还提供了上述显示面板的驱动方法，包括：
在每帧显示时间内，通过栅极开关控制线对多路选择器的第二类控制端依次加载与栅线个数相同的栅线导通信号，在每次加载栅极导通信号的同时，通过源极驱动单元的输出端对多路选择器的一信号输入端加载栅线信号，对多路选择器的其他信号输入端加载低电平信号，使得对多路选择器的第二类控制端依次加载栅线导通信号时，多路选择器的第二类输出端依次对与所述第二类输出端连接的各栅线输出栅线信号；
在多路选择器的第二类控制端每两次加载栅极导通信号之间的时间段内，通过各数据线开关控制线依次对多路选择器的第一类控制端加载数据线导通信号，同时通过源极驱动单元的输出端对所述多路选择器的各信号输入端加载数据信号，使多路选择器的第一类输出端依次对与所述第一类输出端连接的数据线输出数据信号。
进一步地，在本公开实施例提供的上述驱动方法中，在多路选择器的第二类控制端每两次加载栅极导通信号之间的时间段内，通过各数据线开关控制线依次对多路选择器的第一类控制端加载数据线导通信号之后，还可以包括以下步骤：
通过源极驱动单元的输出端对多路选择器的各信号输入端加载低电平信号，以保证栅线上的信号可以进行复位。
下面结合图3所示的显示面板的结构以及图4所示的图3中显示面板的输入输出时序图，对本公开实施例提供的显示面板的驱动方法的工作过程作以描述。
第1阶段，栅线导通控制线SW gate上施加有一高电压，控制第二类开关晶体管Tn1和Tn2处于开启状态；此时，源极驱动单元的输出端Data m1加载的高电压Vgh对栅极电压存储电容Cn1充电，使栅线GLn1的电压升高，在第1阶段结束时，栅线GLn1的电压达到峰值。在第1阶段后，栅线GLn1电压由于栅极电压存储电容Cn1的作用进入保持阶段。在所述第1阶段，除源极驱动单元的输出端Data m1以外的其输出端Data m2的信号为低电平，因此，虽然第二类开关晶体管Tn2处于开启状态，但栅线GLn2处于拉低复位状态。
第2阶段，栅线导通控制线SW gate上施加有一低电压，控制第二类开关晶体管Tn1处于断开状态；数据线导通控制线SW R上施加有一高电压，控制与所述数据线导通控制线SW R连接的第一类开关晶体管TR1和TR2处于开启状态，使得源极驱动单元的输出端Data m1和Data m2的信号加载到对应的数据线Dm1(R)和Dm2(R)上。此时，由于栅线GLn1保持导通状态，因此，可以对与数据线Dm1(R)和Dm2(R)连接的亚像素充电，GLn1所在行，Dm1(R)、Dm2(R)所在列的红色亚像素分别达到LR(m1n1)、LR(m2n1)灰阶。
第3阶段，数据线导通控制线SW G上施加有一高电压，控制与所述数据线导通控制线SW G连接的第一类开关晶体管TG1和TG2处于开启状态，使得源极驱动单元的输出端Data m1和Data m2的信号加载到对应的数据线Dm1(G)和Dm2(G)上。此时，由于栅线GLn1保持导通状态，因此，可以对与数据线Dm1(G)和Dm2(G)连接的亚像素充电，GLn1所在行，Dm1(G)、Dm2(G)所在列的绿色亚像素分别达到LG(m1n1)、LG(m2n1)灰阶。
第4阶段，数据线导通控制线SW B上施加有一高电压，控制与所述数据线导通控制线SW B连接的第一类开关晶体管TB1和TB2处于开启状态，使得源极驱动单元的输出端Data m1和Data m2的信号加载到对应的数据线Dm1(B)和Dm2(B)上。此时，由于栅线GLn1保持导通状态，因此，可以对与数据线Dm1(B)和Dm2(B)连接的亚像素充电，GLn1所在行，Dm1(B)、Dm2(B)所在列的蓝色亚像素分别达到LB(m1n1)、LB(m2n1)灰阶。
第5阶段，栅线导通控制线SW gate和数据线导通控制线SW R、SW G、SW B上均施加有低电压，源极驱动单元的输出端Data m1和Data m2输出的 信号也为低电压，这样可以释放栅极电压存储电容Cn1上电荷，使得栅线GLn1电压进一步降低。此处需要说明的是，第5阶段时间较短。可选的，第5阶段所占时间可为0。
第6阶段，栅线导通控制线SW gate上施加有一高电压，控制第二类开关晶体管Tn1和Tn2处于开启状态；此时，源极驱动单元的输出端Data m1加载的低电压Vg1使得栅极电压存储电容Cn1放电，拉低栅线GLn1的电压；源极驱动单元的输出端Data m2加载的高电压Vgh对栅极电压存储电容Cn2充电，使栅线GLn2的电压升高，在第6阶段结束时，栅线GLn2的电压达到峰值。在第6阶段后，栅线GLn2电压由于栅极电压存储电容Cn2的作用进入保持阶段。
第7阶段，栅线导通控制线SW gate上施加有一低电压，控制第二类开关晶体管Tn2处于断开状态；数据线导通控制线SW R上施加有一高电压，控制与所述数据线导通控制线SW R连接的第一类开关晶体管TR1和TR2处于开启状态，使得源极驱动单元的输出端Data m1和Data m2的信号加载到对应的数据线Dm1(R)和Dm2(R)上。此时，由于栅线GLn2保持导通状态，因此，可以对与数据线Dm1(R)和Dm2(R)连接的亚像素充电，GLn2所在行，Dm1(R)、Dm2(R)所在列的红色亚像素分别达到LR(m1n2)、LR(m2n2)灰阶。
第8阶段，数据线导通控制线SW G上施加有一高电压，控制与所述数据线导通控制线SW G连接的第一类开关晶体管TG1和TG2处于开启状态，使得源极驱动单元的输出端Data m1和Data m2的信号加载到对应的数据线Dm1(G)和Dm2(G)。，此时，由于栅线GLn2保持导通状态，因此，可以对与数据线Dm1(G)和Dm2(G)连接的亚像素充电，GLn2所在行，Dm1(G)、Dm2(G)坐在列的绿色亚像素分别达到LG(m1n2)、LG(m2n2)灰阶。
第9阶段，数据线导通控制线SW B上施加有一高电压，控制与所述数据线导通控制线SW B连接的第一类开关晶体管TB1和TB2处于开启状态，使得源极驱动单元的输出端Data m1和Data m2的信号加载到对应的数据线Dm1(B)和Dm2(B)上。此时，由于栅线GLn2保持导通状态，因此，可以对与数据线Dm1(B)和Dm2(B)连接的亚像素充电，GLn2所在行，Dm1(B)、Dm2(B)所在列的蓝色亚像素分别达到LB(m1n2)、LB(m2n2)灰阶。
之后针对其他各行像素，重复针对上述两行像素的各个阶段，此处不再叙述。需要说明的是，在上述第1阶段至第9阶段的描述中仅仅以开关晶体管为高电平有效为例进行说明，在实际运用中，所述开关晶体管还可以全部为低电平有效，或者部分为低电平有效部分为高电平有效，在此不做赘述。
基于同一构思，本公开一实施例还提供了一种显示装置，包括本公开上述实施例提供的显示面板。该显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。该显示装置的实施可以参见上述显示面板的实施例，重复之处不再赘述。
本公开实施例提供的一种显示面板、显示面板的驱动方法及显示装置。该显示面板包括显示区域和包围显示区域的周边区域；显示区域中设置有沿第一方向延伸的多条栅线和沿第二方向延伸的多条数据线。在所述第二方向指向的周边区域内设置有多路选择器，所述多路选择器的信号输入端与源极驱动单元的各输出端一一对应连接，所述多路选择器的第一类输出端与各所述数据线一一对应连接，所述多路选择器的第二类输出端与各栅线一一对应连接，所述多路选择器的第一类控制端与各数据线开关控制线一一对应连接，并且所述多路选择器的第二类控制端与栅线开关控制线连接。所述多路选择器用于在从栅线开关控制线输入的栅线导通信号的控制下，将源极驱动单元输出的栅线信号分时输入到对应的栅线；在从数据线开关控制线输入的数据线导通信号的控制下，将源极驱动单元输出的数据信号分时输入到对应的数据线。本公开实施例提供的显示面板中无需单独设置栅极驱动单元，栅极驱动功能集成在源极驱动单元中并通过多路选择器实现，采用分时的方式实现控制对应栅线导通和对数据线输入数据信号的功能，这样可以减小显示面板的周边区域，有利于实现显示面板的窄边框设计，提高显示面板显示画面的视觉效果。
显然，本领域的技术人员可以对本公开进行各种改动和变型而不脱离本公开的精神和范围。这样，倘若本公开的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (12)

  1. 一种显示面板，包括显示区域和包围所述显示区域的周边区域；所述显示区域中设置有沿第一方向延伸的多条栅线和沿第二方向延伸的多条数据线；
    其中，所述第二方向指向的周边区域内设置有多路选择器；所述多路选择器的信号输入端与源极驱动单元的各输出端一一对应连接，所述多路选择器的第一类输出端与各所述数据线一一对应连接，所述多路选择器的第二类输出端与各所述栅线一一对应连接，所述多路选择器的第一类控制端与各数据线开关控制线一一对应连接，并且所述多路选择器的第二类控制端与栅线开关控制线连接；
    所述多路选择器用于，在从所述栅线开关控制线输入的栅线导通信号的控制下，将所述源极驱动单元输出的栅线信号分时输入到对应的栅线；以及在从所述数据线开关控制线输入的数据线导通信号的控制下，将所述源极驱动单元输出的数据信号分时输入到对应的数据线。
  2. 如权利要求1所述的显示面板，其中，所述多路选择器包括：与所述数据线一一对应的第一类开关晶体管，以及与所述栅线一一对应的第二类开关晶体管；
    所述第一类开关晶体管的漏极分别与所述数据线连接，源极与所述源极驱动单元的输出端连接，栅极与所述数据线开关控制线连接；
    所述第二类开关晶体管的漏极分别与所述栅线连接，源极分别与所述源极驱动单元的输出端连接，栅极与所述栅线开关控制线连接。
  3. 如权利要求2所述的显示面板，其中，所述多路选择器的第一类控制端的个数与所述显示区域内各像素包含的亚像素个数相同；
    所述多路选择器的信号输入端的个数与所述显示区域内所包含像素的列数相同。
  4. 如权利要求3所述的显示面板，其中，所述多路选择器的信号输入端的个数等于所述栅线的个数。
  5. 如权利要求4所述的显示面板，其中，所述多路选择器包含多个子选 择器，所述多个子选择器与所述显示区域内所包含各列像素一一对应；
    每个所述子选择器包括：与每列像素包含的亚像素列数相同的第一类开关晶体管，以及一个第二类开关晶体管。
  6. 如权利要求1-5任一项所述的显示面板，其中，所述显示区域中还设置有：连接于所述多路选择器的第二类输出端与对应的栅线之间的栅极电压存储电容。
  7. 如权利要求6所述的显示面板，其中，所述栅极电压存储电容由相互连接的栅线与公共子电极组成，所述公共子电极与各像素中的公共电极同层设置且相互独立。
  8. 如权利要求1-5所述的显示面板，其中，所述第一方向垂直于所述第二方向。
  9. 如权利要求2-5所述的显示面板，其中，所述第一类晶体管和第二类晶体管是薄膜晶体管或金属氧化物半导体场效应管。
  10. 一种显示装置，包括如权利要求1-9任一项所述的显示面板。
  11. 一种用于驱动如权利要求1-9任一项所述的显示面板的驱动方法，所述驱动方法包括：
    在每帧显示时间内，通过栅极开关控制线对多路选择器的第二类控制端依次加载与栅线个数相同的栅线导通信号，在每次加载所述栅极导通信号的同时，通过源极驱动单元的输出端对所述多路选择器的一信号输入端加载栅线信号，对所述多路选择器的其他信号输入端加载低电平信号，使得对多路选择器的第二类控制端依次加载栅线导通信号时，所述多路选择器的第二类输出端依次对与所述第二类输出端连接的各栅线输出栅线信号；
    在所述多路选择器的第二类控制端每两次加载栅极导通信号之间的时间段内，通过各数据线开关控制线依次对所述多路选择器的第一类控制端加载数据线导通信号，同时通过所述源极驱动单元的输出端对所述多路选择器的各信号输入端加载数据信号，使所述多路选择器的第一类输出端依次对与所述第一类输出端连接的数据线输出数据信号。
  12. 如权利要求11所述的驱动方法，其中，在所述多路选择器的第二类控制端每两次加载栅极导通信号之间的时间段内，通过各数据线开关控制线 依次对所述多路选择器的第一类控制端加载数据线导通信号之后，还包括：
    通过所述源极驱动单元的输出端对所述多路选择器的各信号输入端加载低电平信号。
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